An FPGA-based high-speed incremental photoelectric encoder simulation device

Abstract

The application provides a high-speed incremental photoelectric encoder simulation device based on FPGA, which is arranged on an FPGA platform and comprises a parameter calculation unit, which continuously calculates and stores phase parameters and whole-turn counting parameters in a while loop mode with an indefinite period based on the resolution of the simulated incremental photoelectric encoder and the clock frequency of the FPGA platform; and a high-speed signal generation unit, which continuously accumulates the motor speed output by a motor model in a single-period timing loop mode, and generates each phase pulse signal of the simulated incremental photoelectric encoder based on the accumulation result, the phase parameters and the whole-turn counting parameters, and each accumulation and pulse signal generation operation is completed within one clock cycle of the FPGA platform. The device provided by the application can accurately simulate the output signal of a real incremental photoelectric encoder under high-speed working conditions.

Description

Technical Field

[0001] This application belongs to the field of motor simulator technology, and relates to photoelectric encoder simulation technology adapted to motor simulators, specifically providing a high-speed incremental photoelectric encoder simulation device based on FPGA. Background Technology

[0002] In the research and development of electric drive systems for new energy vehicles, motor controllers need to undergo extensive operating condition verification. To this end, it is usually necessary to build a hardware-in-the-loop (HIL) test platform for motor simulators. The motor simulator generates feedback signals that match the behavior of real motors to replace real motors in completing the testing and verification of the motor controller's functions.

[0003] Since the motor simulator does not have a real mechanical shaft, it is not possible to use a conventional physical photoelectric encoder to measure the output motor shaft rotation angle signal. Instead, it is necessary to use a photoelectric encoder simulation device to generate A / B / Z three-phase signals that conform to the output characteristics of a real encoder based on the operating state of the motor model.

[0004] Existing photoelectric encoder simulation schemes typically generate corresponding photoelectric encoder output pulses by receiving the position values ​​periodically output by the motor model and calculating the displacement changes in adjacent update cycles. Although this method can reflect the position change trend, it cannot accurately simulate the output results of photoelectric encoders under high-speed conditions due to the limitation of the parameter transmission update frequency from the motor model to the encoder model. Summary of the Invention

[0005] This application provides a high-speed incremental photoelectric encoder simulation device based on FPGA, deployed on an FPGA platform, comprising: The parameter calculation unit continuously calculates and stores the phase parameters and the full-cycle count parameters in a while loop with an indefinite period, based on the resolution of the simulated incremental photoelectric encoder and the clock frequency of the FPGA platform. The high-speed signal generation unit continuously accumulates the motor speed output by the motor model in a single-cycle timed loop, and generates the pulse signals of each phase of the simulated incremental photoelectric encoder based on the accumulation result, phase parameters and full-cycle count parameters. Each accumulation and pulse signal generation operation is completed within one clock cycle of the FPGA platform.

[0006] In the FPGA-based high-speed incremental photoelectric encoder simulation device provided in this application, the phase parameters and full-cycle count parameters generated by the parameter calculation unit are independent of the motor speed and are only related to the inherent performance of the simulated incremental photoelectric encoder and the deployed FPGA. Therefore, a low-frequency while loop is used, and there is no need to consider the real-time changes in motor speed. The real-time accumulation and pulse signal generation operations, which are directly related to the motor speed, are completed by the high-speed signal generation unit in a high-speed single-cycle timing loop within a single clock cycle, thereby ensuring the real-time performance and accuracy of pulse signal generation.

[0007] By dividing two types of operations with different real-time requirements and computational complexity into different functional units and executing them cyclically at different frequencies, the problem of optical encoder pulse signal output delay caused by high-frequency execution of computational operations with long logical paths but low real-time requirements can be effectively avoided. Attached Figure Description

[0008] Figure 1 This is a schematic diagram illustrating the structure and working principle of an incremental photoelectric encoder. Figure 2 This is a schematic diagram of the output signal of an incremental photoelectric encoder. Figure 3 A schematic diagram illustrating the working principle of using a photoelectric encoder simulation device to simulate the output motor angle signal in a motor simulator. Figure 4 This is a schematic diagram of the architecture of an FPGA-based high-speed incremental photoelectric encoder analog device provided according to an embodiment of this application; Figure 5 This is a schematic diagram of the architecture of the parameter calculation unit provided according to an embodiment of this application; Figure 6 This is a schematic diagram of the operation flow of the parameter calculation unit provided in each while loop according to the embodiments of this application; Figure 7 This is a schematic diagram of the architecture of a high-speed signal generation unit provided according to an embodiment of this application; Figure 8 This is a flowchart illustrating the cyclic accumulation of rotational speed and generation of pulse signals by the high-speed signal generation unit according to an embodiment of this application. Figure 9 This is a schematic diagram illustrating the workflow of a rotation speed accumulation value storage module, an accumulation module, a back-up module, a comparison module, and a gating module, which are based on FPGA platform hardware logic circuits in some embodiments. Figure 10 This is a schematic diagram of the workflow of an AB phase four-step state machine based on hardware logic circuits on an FPGA platform in some embodiments. Figure 11This is a schematic diagram of the workflow of a Z-phase state machine based on hardware logic circuits on an FPGA platform in some optional embodiments. Figure 12 This is a schematic diagram showing the measured results of the phase pulse signals generated by the FPGA-based high-speed incremental photoelectric encoder simulation device provided in the embodiments of this application under low clock frequency and low speed conditions. Figure 13 This is a schematic diagram showing the measured results of the phase pulse signals generated by the FPGA-based high-speed incremental photoelectric encoder simulation device according to the embodiments of this application under low clock frequency and high speed conditions. Figure 14 This is a schematic diagram of the measured results of the phase pulse signals generated by the FPGA-based high-speed incremental photoelectric encoder simulation device according to the embodiments of this application under high clock frequency and low speed conditions. Figure 15 This is a schematic diagram showing the measured results of the phase pulse signals generated by the FPGA-based high-speed incremental photoelectric encoder simulation device provided in the embodiments of this application under high clock frequency and high speed conditions.

[0009] Numbers in the diagram 1: FPGA platform; 2: FPGA-based high-speed incremental photoelectric encoder simulation device; 21: Parameter calculation unit; 211: Phase parameter generation module; 212: Full-cycle counting parameter generation module; 213: Parameter storage module; 22: High-speed signal generation unit. Detailed Implementation

[0010] The present application will now be further described based on preferred embodiments and with reference to the accompanying drawings.

[0011] Incremental encoders convert the rotation of a mechanical shaft into corresponding electrical pulse signals or digital coded signals through photoelectric conversion. They are one of the most widely used angle sensors in position detection and motion control systems.

[0012] like Figure 1As shown, the basic structure of an incremental photoelectric encoder typically includes a light-emitting element, a code disk, a photosensitive element, a lens system, and a signal processing circuit. The light-emitting element usually uses a light-emitting diode (LED) or an infrared light source as the light source for photoelectric conversion. The code disk is the core component of the encoder, rigidly connected to the rotating shaft being measured and rotating synchronously with the shaft. The photosensitive element detects the light signal modulated by the code disk and converts it into an electrical signal. The lens system focuses the light emitted by the light source onto the etched area of ​​the code disk to improve the signal-to-noise ratio of the photoelectric conversion. The signal processing circuit amplifies, shapes, and filters the original analog signal output from the photosensitive element, ultimately outputting a standard digital pulse signal or coded signal.

[0013] like Figure 2 As shown, the code disk of the incremental photoelectric encoder is engraved with uniformly distributed grid lines. When the code disk rotates with the shaft, the light beam emitted by the light source is alternately transmitted and blocked, causing the output signal of the photosensitive element to exhibit periodic high and low level changes. Correspondingly, the detection circuit outputs two pulse signals with a 90° phase difference, which are the A-phase signal and B-phase signal output by the encoder. For each revolution of the code disk, the circuit outputs a Z-phase index pulse signal.

[0014] Generally, the number of pulses generated by one rotation of the code disk is called PPR (Pulses Per Revolution). Since the A / B two-phase signals will experience four state combinations in sequence within one pulse period, namely 00, 10, 11, and 01, counting can be performed using these four state change edges to achieve quadruple frequency decoding, thereby increasing the effective counting resolution to 4×PPR.

[0015] In practical applications, the rotation angle or displacement can be calculated by accumulating the number of A / B phase pulses. At the same time, the rotation direction can be determined by the order in which the edges of the A and B phase signals appear. Since the Z phase index pulse signal is only output once when the code disk rotates to a certain fixed mechanical position, it is used as a marker for the mechanical zero position or reference position.

[0016] Figure 3 An architecture for a drag-and-drop test platform for hardware-in-the-loop testing of motor drive units (MDUs) is shown, such as... Figure 3 As shown, a motor simulator (EME) can be used to replace the real motor and connected to the motor drive unit under test. The motor simulator uses the voltage output by the MDU inverter as the reference voltage and simulates the electrical characteristics (current-voltage conversion relationship) of the real motor through a motor model (mathematical model) to generate the target current. Combined with the current feedback signal collected by the sampling unit, the control module generates a PWM signal to control the EME inverter controller, so that the EME inverter controller can output a three-phase signal to simulate the real motor.

[0017] In this in-loop test architecture, since the motor simulator replaces the real motor, a device capable of simulating a real angle sensor is needed to convert the speed information calculated by the motor model into the output signal of the real angle sensor and provide it to the drive controller of the motor drive unit. For example, using... Figure 3 The photoelectric encoder simulation device in the system outputs A-phase, B-phase, and Z-phase pulse signals to the drive controller, simulating those of a real photoelectric encoder. Simultaneously, because the in-loop test needs to cover the high-speed rotation of the motor, the photoelectric encoder simulation device must accurately generate high-frequency pulse signals within extremely short time intervals, placing extremely high demands on the real-time performance of signal generation. Therefore, the photoelectric encoder simulation device is typically deployed on an FPGA platform with high-speed parallel processing capabilities.

[0018] However, the photoelectric encoder simulation module that comes with the existing motor simulator usually calculates the angle change between adjacent update cycles by receiving the angle value periodically output by the motor model and outputting the corresponding encoder pulse. This method can reflect the position change trend, but under high-speed conditions, due to the limitation of the update frequency of parameter transmission from the motor model to the encoder simulation module, it cannot achieve accurate simulation of the output pulse of the photoelectric encoder under high-speed conditions.

[0019] One possible improvement is to obtain constant or slowly varying speed values ​​from the motor model side, and then calculate angle values ​​at high frequency based on the speed values ​​on the encoder simulation side. The relationship between the real-time angle values ​​and the angles corresponding to each grid line is determined in a global angle space from 0 to 360°, thereby directly determining the high or low level of each phase pulse signal. Since the rate of change of speed is much lower than the rate of change of angle, this method can overcome the update frequency limitation of the motor model parameters being transmitted to the encoder simulation device under high-speed conditions. However, performing high-frequency speed-angle conversion to optical encoder pulse signal generation on the encoder simulation side requires sequentially executing the following steps: Step 1: Determine the current angle based on the accumulated rotation speed. ; ; Step 2, for and Perform the remainder operation to map to the interval [0°, 360°); ; Step 3, determine which grid interval the current angle is in: .

[0020] This process inevitably involves multiple floating-point division operations in each angle update cycle. The excessive amount of computation will cause a complete pulse signal to require multiple clock cycles of the FPGA to complete. Therefore, under high-speed rotation conditions, the lag of the photoelectric encoder analog signal will inevitably occur.

[0021] Therefore, in order to solve the above problems, this application provides a high-speed incremental photoelectric encoder simulation device 2 based on FPGA through embodiments, such as... Figure 4 As shown, the high-speed incremental photoelectric encoder simulation device 2 is deployed on the FPGA platform 1 and includes a parameter calculation unit 21 and a high-speed signal generation unit 22.

[0022] Specifically, refer to Figure 4 The parameter calculation unit 21 continuously calculates and stores the phase parameters and the full-revolution count parameters in a while loop with an indefinite period, based on the resolution of the simulated incremental photoelectric encoder and the clock frequency of the FPGA platform 1. Each parameter calculation operation takes multiple clock cycles. The high-speed signal generation unit 22 continuously accumulates the motor speed output by the motor model in a single-cycle timed loop (SCTL) manner, and generates the pulse signals of each phase of the simulated incremental photoelectric encoder based on the accumulation result, phase parameters and full-revolution count parameters. Each accumulation and pulse signal generation operation is completed within one clock cycle of the FPGA platform.

[0023] In the FPGA-based high-speed incremental photoelectric encoder simulation device 2 provided in this application, the parameter calculation unit 21 is used to cyclically generate the phase parameter step and the full-revolution count parameter count. Both of these parameters are independent of the motor speed and are only related to the inherent performance of the simulated incremental photoelectric encoder and the deployed FPGA. Therefore, when the parameter calculation unit 21 performs cyclic calculations, it does not need to consider the real-time changes in the motor speed. Even if the frequency of the while loop is low and each loop takes a long time (experiencing multiple clock cycles), it will not affect the calculation accuracy of the phase parameter and the full-revolution count parameter. The real-time accumulation and pulse signal generation operations, which are directly related to the motor speed, are completed by the high-speed signal generation unit 22 in a high-speed timing manner within a single clock cycle, thereby ensuring the real-time performance and accuracy of the pulse signal generation.

[0024] By dividing two types of operations with different real-time requirements and computational complexity into different functional units and executing them cyclically at different frequencies, the problem of optical encoder pulse signal output delay caused by high-frequency execution of computational operations with long logical paths but low real-time requirements can be effectively avoided.

[0025] The specific implementation methods of the parameter calculation unit 21 and the high-speed signal generation unit 22 will be described in detail below with reference to the accompanying drawings.

[0026] Figure 5 The figure shows a schematic diagram of the architecture of the parameter calculation unit 21 in some specific embodiments. As shown, the parameter calculation unit includes a phase parameter generation module 211, a full-cycle count parameter generation module 212, and a parameter storage module 213, wherein: In each slow while loop, the phase parameter generation module 211 calculates the phase parameter based on the resolution of the simulated incremental photoelectric encoder. and the clock frequency of the deployed FPGA platform. The following calculations are performed to generate the phase parameters required for the high-speed signal generation unit. : (1), in, This is the equivalent coefficient corresponding to one revolution of the motor, used to unify the physical dimensions of different speed unit systems to revolutions per second (rpm), ensuring that subsequent speed accumulation operations are independent of the speed unit. For example, when the motor model outputs speed in rpm (revolutions per minute), When the value is 60, and the unit of the motor model's output speed is rad / s (radians per second), Pick When the motor model outputs a speed in degrees per second (° / s), Get 360.

[0027] The full-cycle counting parameter is adjusted in each slow while loop according to the resolution of the simulated incremental photoelectric encoder. The following calculations are performed to generate the full-cycle count parameters required for the high-speed signal generation unit. : (2).

[0028] The phase parameter generation module 211 and the full-cycle count parameter generation module 212 calculate the parameters. and The signals are stored in the parameter storage module for the high-speed signal generation unit to read and execute the pulse signal generation operations for each phase. It is understood that the parameter storage module consists of registers from the FPGA platform, and its bit depth is determined by the analog accuracy requirements of the photoelectric encoder. For example, optionally, the calculated... If the value is a 32-bit or 64-bit floating-point number, then the parameter storage module will store the corresponding value. The register bit width is set to 32 bits or 64 bits.

[0029] Figure 6The diagram illustrates the operation flow executed by the parameter calculation unit 21 in each while loop. In some specific embodiments, the calculation and storage operations performed by each while loop can be described in graphical code within the LabVIEW FPGA, and automatically translated into a hardware netlist by the LabVIEW FPGA compiler. This netlist is then passed to a third-party FPGA synthesis tool such as Xilinx Vivado (or Intel Quartus). After logic synthesis, placement and routing, timing optimization, and other steps, a bitfile is finally generated. After downloading / burning the bitfile to the FPGA chip, the functions of each module in the parameter calculation unit can be realized.

[0030] It is understandable that, since the above phase parameter calculation includes division operations, it is usually impossible to complete in one clock cycle in an FPGA. Therefore, the LabVIEW FPGA compiler will automatically insert multi-stage pipeline registers in the division path to split the calculation into multiple clock cycles to complete sequentially. This is also the reason why the parameter calculation operation containing division is placed in a while loop in the embodiments of this application.

[0031] In some specific embodiments, the registers of each module in the parameter calculation unit 21 are uniformly timed using the system clock of the deployed FPGA platform, thereby ensuring that the trigger signal CLK of the register in the parameter storage module 213 is strictly synchronized with the trigger signal used by the high-speed signal generation unit described later, so as to ensure that the parameter values ​​read by the high-speed signal generation unit in any clock cycle are stable and complete values.

[0032] Figure 7 The diagram shows the architecture of the high-speed signal generation unit 22 in some specific embodiments. Figure 8 The flowchart shows the process of each module cyclically accumulating rotational speed and generating pulse signals.

[0033] like Figure 7 , Figure 8 As shown, the high-speed signal generation unit 22 further includes an accumulation value storage module, an accumulation module, a back-off module, a comparison module, a gating module, an AB phase four-step state machine, and a Z phase state machine.

[0034] The high-speed signal generation unit 22 performs high-speed single-cycle timing loop (SCTL) operation according to the clock frequency ticks of the FPGA platform 1. In each single-cycle timing loop operation: The accumulation module, rollback module, comparison module, and gating module work together to accumulate the accumulated speed value s stored in the speed accumulation value storage module and the motor speed value n passed from the motor model, and then compare it with the phase parameter step. Based on the comparison result, the pulse trigger signal trig_s and the accumulated speed value s are updated.

[0035] Specifically, the accumulation module uses the motor speed n passed from the motor model to accumulate the accumulated speed value s stored in the speed accumulation value storage module, obtaining s+n; the comparison module compares s+n with the phase parameter step and outputs a pulse trigger signal trig_s based on the comparison result, where the pulse trigger signal trig_s is invalid when s+n is less than step, and valid otherwise; the rollback module calculates the difference between s+n and step, i.e., s+n-step; the gating module uses the calculation result of the accumulation module when the pulse trigger signal trig_s is invalid, i.e., s+n to update the accumulated speed value s stored in the speed accumulation value storage module, and vice versa.

[0036] In each single-cycle timed loop (SCTL) operation: The AB phase four-step state machine maintains the current level of the A-phase and B-phase pulse signals when the pulse trigger signal trig_s is invalid, and otherwise changes the level of the A-phase and B-phase pulse signals according to the preset four-step state transition sequence.

[0037] Specifically, the AB phase four-step state machine has four discrete state values: 0, 1, 2, and 3. These represent the four states that the simulated incremental photoelectric encoder sequentially experiences between adjacent pulses. Specifically, state=0 corresponds to a level of 10 for both phases A and B; state=1 corresponds to a level of 11 for both phases A and B; state=2 corresponds to a level of 01 for both phases A and B; and state=3 corresponds to a level of 00 for both phases A and B. In each single-cycle timing loop operation, the AB phase four-step state machine determines whether to sequentially transition between the four states based on the validity or invalidity of the pulse trigger signal trig_s. When the pulse trigger signal trig_s received in a single-cycle timing loop is invalid, the AB phase four-step state machine maintains its current state, thus keeping the levels of the A-phase and B-phase pulse signals unchanged. When the pulse trigger signal trig_s received in a single-cycle timing loop is valid, the AB phase four-step state machine changes sequentially from the current state to the next state. Assuming the motor speed n is positive, i.e., the rotation direction is positive, the state value of the AB phase four-step state machine increases by 1, such as changing from 0 to 1, from 1 to 2, from 2 to 3, or from 3 to 0. Correspondingly, the levels of the A-phase and B-phase pulse signals change according to the changed state, thereby realizing the analog output of the A-phase and B-phase pulse signals of the real incremental photoelectric encoder.

[0038] In each single-cycle timed loop operation: The Z-phase state machine performs pulse counting accumulation based on the pulse trigger signal trig_s, updates the pulse count value based on the comparison result of the pulse count accumulation with the full-cycle count parameter count, and maintains or changes the level of the Z-phase pulse signal based on the pulse count value.

[0039] Specifically, when the pulse trigger signal trig_s received in a single-cycle timing loop operation is invalid, the Z-phase state machine keeps the pulse count value c unchanged; when the pulse trigger signal trig_s received in a single-cycle timing loop operation is valid, it means that a photoelectric encoder pulse has been generated. The Z-phase state machine increments the pulse count value by 1, that is, the pulse count value c+1. ​​Then, the result of incrementing the pulse count by 1 is compared with the full-revolution count parameter count. If the pulse count value after incrementing by 1 is less than the full-revolution count parameter count, it means that the motor has not rotated one revolution since the full-revolution count pulse was generated from the previous Z-phase pulse signal. At this time, the pulse count value c is updated using the result of incrementing the pulse count value. If the result of incrementing the pulse count value is equal to the full-revolution count parameter count, it means that the motor has rotated one revolution since the last full-revolution count pulse was generated. At this time, the pulse count value c is cleared. In addition, the Z-phase state machine sets the Z-phase pulse signal to high level only when the pulse count value is 0, and sets the Z-phase pulse signal to low level when the pulse count value is other values.

[0040] It should be noted that when trig_s is valid in a single-cycle timing loop and triggers the full-cycle counting pulse, the pulse count value c remains at 0 until the next trig_s is valid. Therefore, the duration for which the Z-phase pulse signal remains high in each cycle is the interval between two pulses, which is 1 / 4 of a complete A-phase or B-phase cycle.

[0041] pass Figure 7 , Figure 8As can be seen, the high-speed signal generation unit provided in this application only uses calculation operations such as addition, subtraction, and comparison triggering, without any division or complex table lookup (such as multi-interval table lookup in the full-angle space from 0 to 360°). Each calculation operation can be performed in parallel, thereby ensuring that it can be implemented in the framework of Single-Cycle Timed Loop (SCTL), which greatly shortens the calculation path, reduces the output delay, and ensures the simulation accuracy of the real photoelectric encoder under high-speed conditions.

[0042] Meanwhile, the triggering condition of the pulse trigger signal trig_s is a comparison between the accumulated result of the rotational speed n and the phase parameter. This comparison significantly improves the processing speed compared to triggering based on the count value. The advantages of this triggering method are explained in detail below, in conjunction with the meaning of the phase parameter step: Without loss of generality, let the unit of the motor speed n be rpm, i.e., k = 60. Then the time for one revolution is 60 / n seconds. Correspondingly, since the clock frequency of the FPGA platform is ticks, the motor takes 60 × ticks / n clock cycles to complete one revolution. Considering that the motor generates 4 × ppr pulses per revolution, the number of clock cycles required to trigger one pulse can be obtained. : (3).

[0043] According to equation (3), one possible triggering method is to calculate... Then, it is used as the threshold parameter to trigger trig_s. At this time, in the high-speed signal calculation unit, the accumulation object will become the cumulative clock cycle number, which is incremented by 1 in each single-cycle timer loop.

[0044] While the aforementioned triggering method is relatively simple in terms of counting, it will significantly cause instability in the output results. The specific reason is that the rotational speed n is a time-varying variable. If the calculation is performed in the parameter calculation unit, although it avoids the calculation delay caused by the long path of division, once n changes, the threshold signal transmitted to the high-speed signal generation unit will be affected. This will change, at which point the accumulated number of clock cycles will be affected. The uncertainty of the comparison results leads to unstable output results.

[0045] Therefore, in the embodiments of this application, the rotational speed n is moved from the denominator to the numerator, and the comparison threshold generated by the parameter calculation unit for triggering the pulse is changed to: (4), Step represents how many angle changes (phase changes) are needed to trigger two adjacent pulses when the rotation speed is accumulated at the clock frequency ticks during the motor rotation process. As can be seen from equation (4), this value is determined only by the inherent parameters of the FPGA and the photoelectric encoder, thus ensuring that the threshold parameters of the high-speed signal generation unit remain stable.

[0046] Meanwhile, in the high-speed signal generation unit, the accumulated amount is changed from the clock cycle count value to the real-time rotational speed n. The larger n is, the faster the accumulation speed of s in each single-cycle timing loop, and the fewer the clock cycles between two pulse triggers, and the shorter the time interval. Conversely, the slower the accumulation speed of s in each single-cycle timing loop, the more the clock cycles between two pulse triggers, and the longer the time interval. In this process, the threshold used for comparison remains unchanged, so the interval of the output pulse signal can be made to change smoothly with the rotational speed.

[0047] Meanwhile, this triggering method also only includes addition operations, thus maintaining extremely low latency. Furthermore, after each trigger, a rollback module is used to backtrack s+n by one step instead of directly resetting it to zero, ensuring that the next accumulation starts from the correct position to avoid error accumulation.

[0048] The above analysis is based on the motor speed unit of rpm. It can be understood that when using other units of speed expression, as shown in equation (1), the corresponding equivalent coefficient can be used to replace 60 in equation (4) when calculating step.

[0049] In some specific embodiments, the computational and storage operations performed by each module in the high-speed signal generation unit in each single-cycle timing loop can be described in a graphical code manner within LabVIEW FPGA. The LabVIEW FPGA compiler automatically translates this into a hardware netlist, which is then passed to a third-party FPGA synthesis tool such as Xilinx Vivado (or Intel Quartus). After steps such as logic synthesis, placement and routing, and timing optimization, a bitfile is finally generated. After downloading / programming the bitfile to the FPGA chip, the functions of each module in the high-speed signal generation unit can be realized.

[0050] The following schematic description, in conjunction with optional embodiments, illustrates the logic circuit architecture of each functional module in the high-speed signal generation unit.

[0051] Figure 9The figure illustrates the workflow of a speed accumulation value storage module, an accumulation module, a backoff module, a comparison module, and a gating module based on FPGA platform hardware logic circuits in some optional embodiments. As shown in the figure, the speed accumulation value storage module can be constructed using a first multi-bit register. The number of bits in the multi-bit register can be determined according to the analog precision, such as 16 bits, 32 bits, etc. Alternatively, it can be consistent with the number of bits in the register storing the phase parameter step in the parameter storage module 213 to adapt to the precision requirements for the speed accumulation value s. In each SCTL cycle, the first multi-bit register is triggered by the rising or falling edge of the clock signal clk to store data. The accumulation module and the backoff module can be constructed using a first adder and a first subtractor, respectively. The comparison module can be constructed using a first comparator, and the gating module can be constructed using a first multiplexer.

[0052] The workflow of each module in the SCTL loop has been described in detail above. It is understood that the specific implementation of each adder, subtractor, comparator, and multiplexer (MUX) in the diagram is not unique on the FPGA platform architecture. For example, the modules can be constructed using a lookup table (LUT) + carry chain, or they can be implemented using the DSP hard core in the FPGA platform.

[0053] Figure 10 The figure shows a schematic diagram of the working process of an AB phase four-step state machine based on FPGA platform hardware logic circuits in some optional embodiments. As shown in the figure, the AB phase four-step state machine includes a second multiplexer, a second adder, a two-bit register, a first lookup table and a second lookup table. It can drive the state value state to change sequentially according to the pulse trigger signal trig_s and output the corresponding A phase pulse signal and B phase pulse signal.

[0054] Specifically, the second multiplexer selects to output 0 when the pulse trigger signal trig_s is invalid and outputs 1 when the pulse trigger signal trig_s is valid. The selected output result is then output to the second adder. The second adder adds the output result of the second multiplexer to the current state value state stored in the two-bit register, resulting in state+0 (i.e., state remains unchanged) or state+1 (i.e., state increments by one bit). Driven by the clock signal clk, the two-bit register updates the calculation result of the second adder to the new state value state. Since the two-bit register only has a storage width of 2 bits, it only stores the lowest two bits of the calculation result of the second adder each time the state value is updated. When state increments from 3 to 4, it will naturally overflow and wrap back to 0, thus realizing the cycle of state between the four states 0, 1, 2, and 3: 0->1->2->3->0->….

[0055] The first lookup table and the second lookup table take the state value output by the two-bit register as input. According to the pre-set state-level mapping relationship, they output the level values ​​corresponding to the A-phase pulse signal and the B-phase pulse signal, respectively. Since the state-level mapping relationship is a fixed constant in each state, there is no calculation error during the operation of the mapping, which ensures that the A and B phase signals maintain a constant 90° phase difference.

[0056] Figure 11 The figure shows a schematic diagram of the operation of a Z-phase state machine based on FPGA platform hardware logic circuits in some optional embodiments. As shown, the Z-phase state machine includes a third multiplexer, a third adder, a second comparator, a fourth multiplexer, a second multi-bit register, and a zero detector, which are used to accumulate pulse counts according to the pulse trigger signal trig_s, and control the level state of the Z-phase pulse signal based on the comparison result of the pulse count value and the full-cycle count parameter count.

[0057] Specifically, the third multiplexer outputs 0 when the pulse trigger signal trig_s is invalid and outputs 1 when the pulse trigger signal trig_s is valid, and outputs the selection result to the third adder. The third adder adds the output result of the third multiplexer to the current pulse count value c stored in the second multi-bit register to obtain c+0 (i.e., the count value remains unchanged) or c+1 (i.e., the count value is incremented once). The number of bits in the second multi-bit register can be determined according to the full-cycle counting parameters, for example, the same as the number of bits in the register storing the full-cycle counting parameters in the parameter storage module 213.

[0058] The second comparator compares the calculation result of the third adder with the full-cycle count parameter count and outputs the comparison result trig_z. The comparison result trig_z is invalid if the calculation result of the third adder is less than count, and valid otherwise.

[0059] The fourth multiplexer selects the calculation result of the third adder (i.e., the accumulated count value) when the comparison result trig_z is invalid, and selects the output 0 when the comparison result trig_z is valid, and outputs the selected output result to the second multi-bit register; the second multi-bit register updates the output result of the fourth multiplexer to the new pulse count value c under the drive of the clock signal clk.

[0060] The zero-value detector takes the pulse count value c output from the second multi-bit register as input and detects whether the pulse count value c is 0. If c is 0, it outputs a high-level Z-phase pulse signal; otherwise, it outputs a low-level Z-phase pulse signal.

[0061] As can be seen, when `trig_s` is invalid in a single-cycle timing loop, the third multiplexer outputs 0, and the pulse count value `c` remains unchanged after being incremented by 0. If `c` is not 0 at this time, the Z-phase pulse signal remains at a low level. When `trig_s` is valid in a single-cycle timing loop but the pulse count accumulation result has not yet reached `count`, the pulse count value `c` completes one increment but is still not 0, and the Z-phase pulse signal remains at a low level. Only when the pulse count accumulation result reaches `count` (i.e., the comparison result `trig_z` is valid) is the second multi-bit register cleared to 0, and the zero-value detector immediately outputs the Z-phase pulse signal at a high level. This continues until the next `trig_s` is valid, causing the pulse count value `c` to increment again to a non-zero value, at which point the Z-phase pulse signal falls back to a low level. Therefore, the duration for which the Z-phase pulse signal remains at a high level is exactly the duration for which the pulse count value `c` remains 0, that is, one pulse interval between the last trigger of a full-cycle counting pulse and the next valid `trig_s`, which is 1 / 4 of a complete A-phase or B-phase cycle.

[0062] Understandable, Figure 10 , Figure 11 The specific implementation methods of various adders, multiplexers, comparators, zero detectors, and other modules are not unique on the FPGA platform architecture. For example, the above modules can be constructed by using a lookup table (LUT) + carry chain, or they can be implemented using the DSP hard core in the FPGA platform.

[0063] In some preferred embodiments, when the FPGA-based high-speed incremental photoelectric encoder simulation device is powered on or reset on the FPGA platform 1, an initialization operation can be performed to uniformly clear each storage element. For example, the step, count, etc. stored in the parameter storage device are set to default values ​​to avoid the high-speed signal generation unit being unable to read valid values ​​in the first SCTL loop; the speed accumulation value s stored in the speed accumulation value storage module is initialized to 0, the state value state stored in the two-bit register is initialized to 0 (corresponding to the initial level combination of A=1 and B=0), the pulse count value c stored in the second multi-bit register is initialized to 0, and the intermediate signals such as the pulse trigger signal trig_s and the comparison result trig_z are reset to invalid states.

[0064] By performing the above initialization operations, it can be ensured that each register has been cleared and its default parameters loaded before entering the high-speed timing loop operation, thereby ensuring that the high-speed signal generation unit has a definite and consistent initial state when it starts working.

[0065] It is understood that the above initialization, reset and clearing operations are conventional power-on reset settings in the field. The specific implementation method (such as synchronous reset or asynchronous reset, triggering by the global reset signal provided by the FPGA platform or a dedicated initialization module) can be flexibly selected according to the actual engineering needs, and does not affect the core operation logic of the high-speed signal generation unit under normal working conditions.

[0066] Figure 12 The diagram shows the measured results of the phase pulse signals generated by the FPGA-based high-speed incremental photoelectric encoder simulation device under low clock frequency and low speed conditions in a specific embodiment. In this embodiment, the clock frequency of the FPGA platform is 40MHz, the ppr of the simulated incremental photoelectric encoder is 2048, and the motor speed output by the motor model is 2000rpm. Figure 13 The diagram shows the measured results of the phase pulse signals generated by the FPGA-based high-speed incremental photoelectric encoder simulation device under low clock frequency and high speed conditions in a specific embodiment. In this embodiment, the clock frequency of the FPGA platform is 40MHz, the ppr of the simulated incremental photoelectric encoder is 2048, and the motor speed output by the motor model is 60000rpm. Figure 14The diagram shows the measured results of the phase pulse signals generated by the FPGA-based high-speed incremental photoelectric encoder simulation device under high clock frequency and low speed conditions in a specific embodiment. In this embodiment, the clock frequency of the FPGA platform is 180MHz, the ppr of the simulated incremental photoelectric encoder is 2048, and the motor speed output by the motor model is 2000rpm. Figure 15 The diagram shows the measured results of the phase pulse signals generated by the FPGA-based high-speed incremental photoelectric encoder simulation device under high clock frequency and high speed conditions in a specific embodiment. In this embodiment, the clock frequency of the FPGA platform is 180MHz, the ppr of the simulated incremental photoelectric encoder is 2048, and the motor speed output by the motor model is 60000rpm.

[0067] Figures 12 to 15 In the illustrated embodiments, the high-speed incremental photoelectric encoder simulation devices are all deployed on NI PXIe-7846R reconfigurable I / O modules. This module is based on the PXI Express bus standard and integrates a Xilinx Kintex-7 series FPGA chip. It interacts with the embedded controller via the PXI Express bus. The embedded controller is responsible for compiling, downloading, and controlling the execution of the FPGA program, as well as setting parameters and displaying data, thereby enabling the loading and real-time monitoring of the device's operational logic. During development, the LabVIEW FPGA development environment running on the embedded controller is used for graphical programming. After compilation, the program automatically generates a bitstream file that can be downloaded to the FPGA chip.

[0068] pass Figures 12 to 15 As can be seen, the FPGA-based high-speed incremental photoelectric encoder simulation device provided in this application can accurately simulate the output of the photoelectric encoder under various FPGA clock frequencies and motor speeds.

[0069] The specific embodiments of this application have been described in detail above. For those skilled in the art, several improvements and modifications can be made to this application without departing from the principle of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A high-speed incremental photoelectric encoder analog device based on FPGA, deployed on an FPGA platform, characterized in that, include: The parameter calculation unit continuously calculates and stores the phase parameters and the full-cycle count parameters in a while loop with an indefinite period, based on the resolution of the simulated incremental photoelectric encoder and the clock frequency of the FPGA platform. The high-speed signal generation unit continuously accumulates the motor speed output by the motor model in a single-cycle timed loop, and generates the pulse signals of each phase of the simulated incremental photoelectric encoder based on the accumulation result, phase parameters and full-cycle count parameters. Each accumulation and pulse signal generation operation is completed within one clock cycle of the FPGA platform.

2. The FPGA-based high-speed incremental photoelectric encoder analog device according to claim 1, characterized in that, The parameter calculation unit includes: The phase parameter generation module calculates the phase parameters in each while loop based on the resolution of the simulated incremental photoelectric encoder and the clock frequency of the deployed FPGA platform. The whole circle count parameter generation module calculates the whole circle count parameter based on the resolution of the simulated incremental photoelectric encoder in each while loop; The parameter storage module is used to store the phase parameters and the full-cycle count parameters; Both the phase parameter and the full revolution count parameter are independent of the motor speed.

3. The FPGA-based high-speed incremental photoelectric encoder analog device according to claim 2, characterized in that, The phase parameter is calculated based on the following formula: ， in, For phase parameters, The resolution of the simulated incremental photoelectric encoder is given by [reference to a specific parameter]. The clock frequency of the deployed FPGA platform. This is the equivalent coefficient corresponding to one revolution of the motor; The full-circle counting parameter is calculated based on the following formula: ， in, This is the parameter for counting the entire revolution.

4. The FPGA-based high-speed incremental photoelectric encoder analog device according to claim 2, characterized in that, The high-speed signal generation unit includes a speed accumulation value storage module, an accumulation module, a back-up module, a comparison module, a gating module, an AB phase four-step state machine, and a Z phase state machine; In each single-cycle timed loop operation: The accumulation module, rollback module, comparison module, and gating module work together to accumulate the accumulated speed value stored in the speed accumulation value storage module and the motor speed value passed from the motor model, and then compare it with the phase parameter. Based on the comparison result, the pulse trigger signal and the accumulated speed value are updated. The AB phase four-step state machine maintains the current level of the A-phase and B-phase pulse signals when the pulse trigger signal is invalid, and otherwise changes the level of the A-phase and B-phase pulse signals according to the preset four-step state transition sequence. The Z-phase state machine performs pulse counting accumulation based on the pulse trigger signal, updates the pulse count value based on the comparison result of the pulse count accumulation with the full-cycle counting parameter, and maintains or changes the level of the Z-phase pulse signal based on the pulse count value.

5. The FPGA-based high-speed incremental photoelectric encoder analog device according to claim 4, characterized in that, The accumulation module, backoff module, comparison module, and gating module work together, including: The accumulation module uses the motor speed n passed in from the motor model to accumulate the speed accumulation value s stored in the speed accumulation value storage module, and obtains s+n; The comparison module compares s+n with the phase parameter step and outputs a pulse trigger signal trig_s based on the comparison result. The pulse trigger signal trig_s is invalid when s+n is less than step, and valid otherwise. The rollback module calculates the difference between s+n and step, s+n-step; When the pulse trigger signal trig_s is invalid, the gating module uses the calculation result s+n from the accumulator module to update the accumulated speed value s stored in the speed accumulation value storage module; otherwise, it uses the calculation result s+n-step from the rollback module to update the accumulated speed value s stored in the speed accumulation value storage module.

6. The FPGA-based high-speed incremental photoelectric encoder analog device according to claim 5, characterized in that, The speed accumulation value storage module, accumulation module, rollback module, comparison module, and gating module are respectively constructed from a first multi-bit register, a first adder, a first subtractor, a first comparator, and a first multiplexer.

7. The FPGA-based high-speed incremental photoelectric encoder analog device according to claim 4, characterized in that, The AB phase four-step state machine has four discrete state values, which represent the four states that the simulated incremental photoelectric encoder goes through sequentially between adjacent pulses. In each single-cycle timing operation, the AB-phase four-step state machine determines whether to sequentially transition between the four states based on whether the pulse trigger signal is valid or invalid. Specifically, when the received pulse trigger signal is invalid, the AB-phase four-step state machine maintains its current state, and the levels of the A-phase and B-phase pulse signals remain unchanged. When the received pulse trigger signal is valid in the single-cycle timing operation, the AB-phase four-step state machine changes from the current state to the next state sequentially, and the levels of the A-phase and B-phase pulse signals change according to the changed state.

8. The FPGA-based high-speed incremental photoelectric encoder analog device according to claim 7, characterized in that, The AB phase four-step state machine includes a second multiplexer, a second adder, a two-bit register, a first lookup table, and a second lookup table; The second multiplexer selects to output 0 when the pulse trigger signal is invalid and outputs 1 when the pulse trigger signal is valid. The second adder adds the output of the second multiplexer to the current state value stored in the two-bit register; The two-bit register stores only the lowest two bits of the calculation result of the second adder each time the state value is updated, and the four discrete state values ​​are 0, 1, 2, and 3 respectively; The first lookup table and the second lookup table take the state value output by the two-bit register as input and output the level values ​​corresponding to the A-phase pulse signal and the B-phase pulse signal respectively according to the preset state-level mapping relationship.

9. The FPGA-based high-speed incremental photoelectric encoder analog device according to claim 4, characterized in that, In each single-cycle timed loop operation: When the received pulse trigger signal is invalid, the pulse count value of the Z-phase state machine remains unchanged; When the received pulse trigger signal is valid, the Z-phase state machine increments the pulse count value by 1, and then compares the result of incrementing the pulse count by 1 with the full-cycle counting parameter. If the pulse count value after incrementing by 1 is less than the full-cycle counting parameter, the pulse count value is updated using the result of incrementing the pulse count value. If the pulse count value after incrementing by 1 is equal to the full-cycle counting parameter, the pulse count value is cleared to zero. Furthermore, the Z-phase state machine sets the Z-phase pulse signal to a high level only when the pulse count value is 0.

10. The FPGA-based high-speed incremental photoelectric encoder analog device according to claim 6, characterized in that, The Z-phase state machine includes a third multiplexer, a third adder, a second comparator, a fourth multiplexer, a second multi-bit register, and a zero-value detector; The third multiplexer outputs 0 when the pulse trigger signal is invalid and outputs 1 when the pulse trigger signal is valid. The third adder adds the output of the third multiplexer to the current pulse count value stored in the second multi-bit register; The second comparator compares the calculation result of the third adder with the full-cycle count parameter and outputs the comparison result trig_z. The comparison result trig_z is invalid when the calculation result of the third adder is less than the full-cycle count parameter, and valid otherwise. The fourth multiplexer selects the output of the calculation result of the third adder when the comparison result trig_z is invalid, and selects the output of 0 when the comparison result trig_z is valid. The second multi-bit register updates the pulse count value based on the output of the fourth multiplexer; The zero-value detector takes the pulse count value output by the second multi-bit register as input and detects whether the pulse count value is 0. If it is 0, it outputs a high-level Z-phase pulse signal; otherwise, it outputs a low-level Z-phase pulse signal.

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