A preparation process of a car-grade high-precision anti-leakage current piezoresistive pressure sensor chip

Abstract

The application relates to a preparation process of a car-gauge high-precision anti-leakage current piezoresistive pressure sensor chip. The application comprises the following steps: preparing an SOI substrate structure of a supporting silicon wafer, a buried oxygen insulating layer and top silicon; growing a thin oxide layer on the front surface and the back surface of the SOI substrate structure; forming a low-range pressure-sensitive zone and a high-range pressure-sensitive zone in the top silicon through zoned boron ion implantation and gradient annealing; forming an N-type heavily doped shielding layer surrounding the pressure-sensitive zone through phosphorus ion implantation and annealing; depositing and patterning an electrically connected metal layer, a dielectric film, a platinum resistance thin film structure, an electrically isolated layer and an external connecting PAD structure; etching from the back surface to form a back surface release cavity, and forming an embedded nanodiamond high-heat-dissipation structure in the supporting silicon area below the buried oxygen insulating layer. The application can simultaneously consider wide-range pressure detection, efficient heat dissipation, electromagnetic shielding, temperature compensation and surface dehumidification and dust removal on a single chip, and improves the pressure detection precision and long-term stability under complex working conditions.

Description

Technical Field

[0001] This invention relates to the field of piezoresistive pressure sensor technology, and in particular to the fabrication process of an automotive-grade, high-precision, leakage-proof piezoresistive pressure sensor chip. Background Technology

[0002] Piezoresistive pressure sensors typically utilize the characteristic that the resistance of a piezoresistive membrane changes when it is deformed under pressure, converting pressure signals into electrical signals. These chips offer advantages such as small size, fast response, and mature manufacturing processes, and are widely used in industrial high-pressure fluid detection, precision measurement and control, environmental monitoring, and sensing scenarios in harsh working conditions.

[0003] Automotive applications place high demands on the overall performance of piezoresistive pressure sensors. The pressure detection targets vary significantly across different parts of a vehicle; for example, the pressure ranges corresponding to fuel vapor pressure, intake air pressure, engine oil pressure, and brake pressure differ. Therefore, piezoresistive pressure sensors must possess good range adaptability to reduce the adaptation costs and packaging complexity associated with repeatedly replacing different chip specifications for different scenarios. The automotive environment experiences a wide temperature range, requiring pressure sensors to exhibit excellent high and low temperature resistance, and to minimize the impact of temperature drift and internal heat buildup on detection accuracy, ensuring stable pressure signal output under high, low, and alternating temperature conditions. Vibration and shock during vehicle operation, as well as electromagnetic interference from motors, controllers, wiring harnesses, and other electronic components, can easily affect the stability and accuracy of weak pressure signals. Therefore, it is necessary to suppress external interference signals and substrate leakage interference. The detection sensitivity of a piezoresistive pressure sensor mainly depends on the piezoresistive structure and its stress response capability. If the piezoresistive structure experiences stress concentration, lattice distortion, or leakage loss during compression deformation, it can easily lead to signal attenuation and limit the improvement of detection sensitivity. Therefore, it is necessary to optimize the piezoresistive structure to improve signal output quality. Moisture and microparticles can easily accumulate on the sensor surface under temperature changes or humid environments, leading to decreased insulation performance, signal drift, or reduced long-term reliability.

[0004] However, existing piezoresistive pressure sensor chips still have the following shortcomings: Firstly, the measurement range is relatively limited. A single chip can usually only be adapted to a fixed pressure range, making it difficult to be compatible with high-pressure and low-pressure conditions. Different chips need to be configured for multi-scenario detection, which increases the adaptation cost and packaging complexity.

[0005] Secondly, during chip operation, pressure deformation and Joule heat from the circuit can easily accumulate in the silicon substrate. Traditional silicon substrates have limited heat dissipation efficiency, which can easily lead to thermal drift, zero-point shift, sensitivity decay, or even thermal failure.

[0006] Third, the chip lacks a dedicated electromagnetic shielding structure, and external electromagnetic interference and the base leakage electrode are easily superimposed on the weak pressure signal, resulting in increased signal noise and decreased detection accuracy.

[0007] Fourth, conventional serpentine varistors are prone to lattice distortion at bends, generating large Schottky barriers that lead to leakage and signal loss, and the sensitivity improvement of conventional serpentine varistors is limited.

[0008] Fifth, traditional temperature compensation methods are limited and lack active dehumidification and dust removal structures, making it easy for moisture and microparticles to adhere to the chip surface, resulting in poor long-term operational stability.

[0009] Therefore, it is necessary to provide a piezoresistive pressure sensor chip fabrication process that can simultaneously achieve multi-range pressure detection, efficient heat dissipation, electromagnetic interference resistance, temperature detection compensation, and surface dehumidification and dust removal on a single chip, so as to improve the detection accuracy, stability, and batch manufacturing consistency of the chip under complex working conditions in automotive applications. Summary of the Invention

[0010] Therefore, the technical problem to be solved by the present invention is to overcome the problems of the existing piezoresistive pressure sensor, such as single range, insufficient heat dissipation capacity, weak electromagnetic interference resistance, large temperature drift error, significant leakage loss of serpentine piezoresistor, and easy contamination and moisture on the chip surface.

[0011] To address the aforementioned technical problems, this invention provides a fabrication process for an automotive-grade, high-precision, leakage-proof piezoresistive pressure sensor chip, comprising: An SOI substrate structure is provided, the SOI substrate structure comprising a supporting silicon wafer, a buried oxide insulating layer and a top silicon wafer arranged sequentially from bottom to top; A top thin oxide layer and a bottom thin oxide layer are grown on the front and back sides of the SOI substrate structure, respectively. A low-range varistor region and a high-range varistor region are formed in the top silicon partition. The low-range varistor region includes a connected low-range varistor region heavily doped P+ structure and a low-range varistor region lightly doped P- type varistor. The high-range varistor region includes a connected high-range varistor region heavily doped P+ structure and a high-range varistor region lightly doped P- type varistor. A shielding layer is formed within the top silicon. The shielding layer is a heavily doped N-type polycrystalline silicon shielding closed loop and is located above the low-range varistor region and the high-range varistor region respectively, and forms a reverse isolation junction with the top silicon. Low-range varistor electrical connection metal and high-range varistor electrical connection metal are formed on the surface of the top thin oxide layer, respectively. The low-range varistor electrical connection metal is in contact with the shielding layer and the heavily doped P+ structure of the low-range varistor, respectively. The high-range varistor electrical connection metal is in contact with the shielding layer and the heavily doped P+ structure of the high-range varistor, respectively. A dielectric film is formed on the surface of the top thin oxide layer, and a platinum resistance thin film structure is formed on the surface of the dielectric film. The platinum resistance thin film structure is used for chip surface heating and chip operating temperature detection. An electrical isolation layer is formed on the surface of the dielectric film, and an external connection PAD structure is formed on the surface of the electrical isolation layer, which respectively connects the low-range varistor electrical connection metal, the high-range varistor electrical connection metal and the platinum resistance thin film structure. The SOI substrate structure is patterned and etched from the back side, with the buried oxide insulating layer as the etching stop layer, to release the varistor region in the top silicon and form a back-side release cavity, and an embedded nanodiamond high heat dissipation structure is formed in the supporting silicon wafer below the buried oxide insulating layer.

[0012] In one embodiment of the present invention, an SOI substrate structure is provided, comprising: The donor silicon wafer and the support silicon wafer are polished and cleaned. The supporting silicon wafer is thermally oxidized to form the buried oxide insulating layer on the surface of the supporting silicon wafer; The donor silicon wafer is thinned and polished to form the top silicon, and the donor silicon wafer is bonded to the support silicon wafer on which the buried oxide insulating layer is formed; The bonded SOI silicon wafer is cleaned, dried, and thinned to obtain the SOI substrate structure.

[0013] In one embodiment of the present invention, a top thin oxide layer and a bottom thin oxide layer are grown on the front and back sides of the SOI substrate structure, respectively, including: The SOI substrate structure is placed in an oxidation furnace, and a dry oxidation process is used to form the top thin oxide layer on the front side of the top silicon and the bottom thin oxide layer on the back side of the supporting silicon wafer. The top thin oxide layer and the bottom thin oxide layer are both silicon oxide layers with a thickness of 10nm~100nm; the oxidation temperature of the dry oxidation process is 700℃~1200℃ and the oxidation time is 30min~90min.

[0014] In one embodiment of the present invention, a low-range varistor region and a high-range varistor region are formed within the top silicon, including: A low-range varistor region is formed in the top silicon near the chip edge, and a heavily doped P+ structure and a lightly doped P- type varistor are formed in the low-range varistor region, so that the heavily doped P+ structure in the low-range varistor region is electrically connected to multiple lightly doped P- type varistors in the low-range varistor region. The lightly doped P-type varistor in the low-range varistor region is formed by boron ion implantation, with an implantation energy of 50 keV to 130 keV and an implantation dose of 0.5 × 10⁻⁶. 14 cm -2 ~1.8×10 14 cm -2 The low-range varistor region heavily doped P+ structure is formed by boron ion implantation at an implantation energy of 30 keV to 80 keV and an implantation dose of 3 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 The annealing temperature corresponding to the low-range pressure-sensitive region is 1050℃~1150℃, and the annealing time is 120min~240min. A high-range varistor region is formed in the top silicon near the center of the chip. A heavily doped P+ structure and a lightly doped P- type varistor are formed in the high-range varistor region, so that the heavily doped P+ structure in the high-range varistor region is electrically connected to multiple lightly doped P- type varistors in the high-range varistor region.

[0015] The high-range varistor region, lightly doped P-type varistor, is formed by boron ion implantation with an implantation energy of 50 keV to 90 keV and an implantation dose of 0.5 × 10⁻⁶. 15 cm -2 ~2×10 15 cm -2 The high-range varistor region heavily doped P+ structure is formed by boron ion implantation at an implantation energy of 20 keV to 60 keV and an implantation dose of 1 × 10⁻⁶. 16 cm -2 ~3×10 16 cm -2 The annealing temperature corresponding to the high-range pressure-sensitive region is 900℃~1050℃, and the annealing time is 60min~100min.

[0016] In one embodiment of the present invention, the lightly doped P-type varistor in the low-range varistor region and / or the lightly doped P-type varistor in the high-range varistor region have a serpentine structure and include multiple straight piezoresistive segments and bends connecting adjacent straight piezoresistive segments. The bending corner connection section adopts a multi-layer metal stacked structure, which includes at least two layers selected from titanium, platinum and gold. The piezoresistive straight section is a silicon piezoresistive structure, and the piezoresistive straight section at the beginning and end is respectively connected to the corresponding low-range piezoresistive region heavily doped P+ structure or the high-range piezoresistive region heavily doped P+ structure.

[0017] In one embodiment of the present invention, a shielding layer is formed within the top silicon, comprising: An injection window corresponding to the low-range varistor region and the high-range varistor region is formed in the top silicon by photolithography; The top silicon is implanted with N-type heavily doped ions through the implantation window, and the wafer after ion implantation is annealed to form the shielding layer. The shielding layer and the P-type silicon region located on the periphery of the shielding layer in the top silicon form a reverse isolation junction. The N-type heavily doped ion implantation uses phosphorus ion implantation with an implantation energy of 80 keV to 150 keV and an implantation dose of 1 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 The annealing temperature is 900℃~1200℃, and the annealing time is 30min~90min.

[0018] In one embodiment of the present invention, low-range varistor electrical connection metals and high-range varistor electrical connection metals are respectively formed on the surface of the top thin oxide layer, including: A first electrical connection hole corresponding to the heavily doped P+ structure in the low-range varistor region, the heavily doped P+ structure in the high-range varistor region, and the shielding layer is formed on the top thin oxide layer. A metal layer is deposited on the surface of the top thin oxide layer where the first electrical connection hole is formed using a magnetron sputtering process, and the metal layer is patterned to form the low-range varistor region electrical connection metal and the high-range varistor region electrical connection metal. The low-range varistor region electrical connection metal is electrically connected to the heavily doped P+ structure of the low-range varistor region and the shielding layer, respectively, and the high-range varistor region electrical connection metal is electrically connected to the heavily doped P+ structure of the high-range varistor region and the shielding layer, respectively. The background vacuum level before magnetron sputtering is 5×10⁻⁶. -7 Torr, the process gas is high-purity Ar, the gas flow rate is 30sccm~60sccm, the chamber pressure is 3mTorr~8mTorr, the RF / DC power supply is turned on, the pre-sputtering time is 5min~10min to clean the surface of the aluminum target and remove the oxide layer and impurities; then the wafer is moved to the process position, the DC power of the formal sputtering is 800W~1200W, the substrate temperature is 25℃~80℃, the deposition rate is 300Å / min~500Å / min, the target film thickness is 0.1μm~5μm, and the deposition time is 1min~30min; after deposition, the power supply and argon gas are turned off, and high-purity nitrogen gas is introduced to purge the chamber to remove residual plasma and dust.

[0019] In one embodiment of the present invention, a dielectric film is formed on the surface of the top thin oxide layer, and a platinum resistance thin film structure is formed on the surface of the dielectric film, including: A dielectric film is deposited on the surface of the top thin oxide layer via plasma reaction, covering the electrical connection metals of the low-range varistor region and the high-range varistor region; wherein the dielectric film is a SiO film, and the dielectric film is formed using a PECVD process; the chamber vacuum degree of the PECVD process is 10. -6 The process involves using a Torr-level chamber temperature of 350℃~400℃, introducing a mixed gas consisting of SiH4, NH3, and O2 at flow rates of 20 sccm~40 sccm for SiH4, 30 sccm~50 sccm for NH3, and 50 sccm~80 sccm for O2. The chamber pressure is controlled at 2 Torr~5 Torr, the radio frequency power is 200W~400W, and SiO films are deposited via plasma reactive deposition at a deposition rate of 100 Å / min~200 Å / min, with a target film thickness of 0.1 μm~5 μm. The dielectric film is subjected to chemical mechanical polishing to achieve surface planarization; A platinum thin film is deposited in the central region of the planarized dielectric film surface by magnetron sputtering, and the platinum thin film is patterned and etched to form a platinum resistance thin film structure; wherein the sputtering power of the magnetron sputtering process is 20W~200W, the argon flow rate is 20sccm~100sccm, the deposition thickness is 50nm~200nm, and the photolithographic patterning etching forms a temperature-sensing heating thin film resistor. The platinum resistance film structure is annealed to stabilize the temperature drift coefficient of the resistance film structure; wherein the annealing temperature of the platinum resistance film structure is 450℃~800℃ and the annealing time is 30min~90min.

[0020] In one embodiment of the present invention, an electrical isolation layer is formed on the surface of the dielectric film, and an external connection PAD structure is formed on the surface of the silicon oxide electrical isolation layer, respectively connecting the low-range varistor electrical connection metal, the high-range varistor electrical connection metal, and the platinum resistance thin film structure, including: An electrical isolation layer covering the platinum resistance thin film structure is deposited on the surface of the dielectric film using a low-pressure chemical vapor deposition process. The electrical isolation layer is patterned to form second electrical connection holes in the electrical isolation layer, corresponding to the low-range varistor region electrical connection metal, the high-range varistor region electrical connection metal, and the platinum resistance thin film structure, respectively. A metal layer for connecting the via is deposited on the surface of the electrically insulating layer on which the second electrical connection hole is formed by magnetron sputtering, and the metal layer is patterned to form the external connection PAD structure. The electrically insulating layer is a silicon oxide layer with a thickness of 0.05 μm to 0.5 μm. The low-pressure chemical vapor deposition process includes: after the wafer is pre-cleaned and dried, it is fed into a low-pressure chemical vapor deposition equipment, the chamber is evacuated to a low-pressure environment, the temperature is raised to the deposition process temperature, silicon source gas and oxidation source gas are introduced, and the thickness of the electrically insulating layer is controlled by adjusting the gas flow rate, chamber pressure and deposition time, so as to uniformly grow a silicon oxide thin film with a thickness of 0.05 μm to 0.5 μm on the wafer surface; after the electrically insulating layer is deposited, it is subjected to low-temperature densification annealing.

[0021] In one embodiment of the present invention, the SOI substrate structure is patterned and etched from the back side, with the buried oxide insulating layer serving as the etching stop layer to release the varistor region in the top silicon and form a back-side release cavity. An embedded nanodiamond high-heat-dissipation structure is formed within the supporting silicon wafer below the buried oxide insulating layer, including: After patterning and etching the SOI substrate structure from the back side, the SOI silicon wafer with the back release cavity formed thereon is cleaned and dried. An embedding trench is formed in the supporting silicon wafer below the buried oxide insulating layer and corresponding to the varistor region; wherein the embedding trench is formed using a low-power RIE process and the trench depth is 50nm~150nm. A nanodiamond film is deposited in the embedding groove, and the nanodiamond film is chemically and mechanically polished to form the embedded nanodiamond high heat dissipation structure. The nanodiamond film is deposited using a PECVD process with a cavity pressure of 1 Torr to 3 Torr, a radio frequency power of 200 W to 350 W, a total flow rate of methane and hydrogen of 20 sccm to 80 sccm, and a deposition rate of 5 nm / min to 15 nm / min. After chemically and mechanically polishing, the underlying silicon structure under the buried oxide layer in the pressure-sensitive region is reconstructed to form the embedded nanodiamond high heat dissipation structure.

[0022] The technical solution of the present invention has the following advantages compared with the prior art: The fabrication process of the automotive-grade high-precision piezoresistive pressure sensor chip described in this invention can address the problems of large differences in pressure detection range, wide temperature variation range, strong electromagnetic interference, easy adhesion of moisture, and easy attenuation of weak pressure signals in automotive application scenarios. It can achieve integrated single-chip wide-range adaptive detection, efficient heat diffusion, full-domain electromagnetic shielding, active dehumidification, dynamic temperature compensation, and high-sensitivity low-leakage detection.

[0023] The pressure detection requirements vary significantly across different parts of a vehicle. Addressing the challenge that a single chip cannot simultaneously handle micro-pressure, low-pressure, and high-pressure detection, this invention employs a zoned, differentiated ion doping and gradient high-temperature annealing process to divide the chip's sensitive film into two range regions: low and high. The low-range, high-sensitivity region utilizes low doping concentration and prolonged high-temperature deep annealing, resulting in a deeper junction and higher piezoresistive coefficient, suitable for high-precision micro-pressure detection. The high-range, high-pressure-resistant region employs high doping concentration and short-time low-temperature shallow annealing, resulting in a shallower junction and stronger structural pressure resistance, suitable for high-pressure conditions. This dual-zone sensitivity gradient distribution enables adaptive multi-range detection with a single chip, reducing reliance on different sensor chip specifications in various automotive applications.

[0024] During vehicle operation, electromagnetic interference arises from motors, controllers, wiring harnesses, and other electronic components. Simultaneously, leakage current in the chip substrate can easily be superimposed on the weak pressure detection signal, leading to increased signal noise and decreased detection accuracy. To address this issue, this invention utilizes high-energy ion implantation to form a heavily doped N-type polycrystalline silicon shielded closed loop, positioned above all piezoresistive sensing units. The heavily doped polycrystalline silicon forms an equipotential shielding layer and simultaneously forms a reverse isolation PN junction with the underlying silicon substrate, completely blocking substrate leakage current and external electromagnetic coupling interference. This achieves full-domain electrical isolation and electromagnetic shielding, improving the stability and accuracy of pressure detection signals in the complex electromagnetic environment of a vehicle.

[0025] The temperature range in automotive environments varies greatly, requiring pressure sensors to withstand not only high and low temperatures but also to suppress temperature drift, zero-point shift, and sensitivity decay caused by internal heat buildup. To address the limited heat dissipation efficiency of traditional silicon substrates, this invention embeds a high-heat-dissipation structure of embedded nanodiamonds within the silicon substrate under a buried oxide insulating layer. Due to the ultra-high thermal conductivity of nanodiamonds, localized heat accumulation on the chip can be rapidly and evenly distributed laterally, and deformation heat and Joule heat can be quickly dissipated longitudinally. This eliminates hotspot accumulation, suppresses thermal stress deformation and temperature drift errors, and significantly improves the stability of the chip under high voltage and long-term continuous operation.

[0026] Sensor surfaces are prone to moisture and microparticle adhesion under varying temperature conditions, humid environments, or oil / dust environments, leading to decreased insulation performance, signal drift, and reduced long-term reliability. To address this issue, this invention integrates a precision platinum resistance thin film structure on the chip surface, providing dual functionality: when powered by a low-power microcurrent, the platinum resistance slightly heats up, removing moisture and microparticles from the chip surface and eliminating signal drift caused by dielectric adhesion; when not powered, the chip's operating temperature is collected in real-time, and a matching algorithm performs dynamic temperature compensation for the pressure signal, significantly reducing temperature drift errors.

[0027] The detection sensitivity of a piezoresistive pressure sensor primarily depends on the stress response capability of the piezoresistive structure and the quality of electrical signal transmission. Traditional silicon-based serpentine piezoresistive resistors are prone to stress concentration and lattice distortion at bends, forming a significant Schottky barrier. This leads to increased leakage current and signal loss, limiting further improvements in sensing sensitivity and signal-to-noise ratio. To address this issue, this invention employs a multi-metal stacked corner connection process. This allows the straight sections of the piezoresistive resistor to retain the high-sensitivity silicon piezoresistive structure, while the bends utilize a multi-layered titanium, platinum, and gold metal stacked structure for conductive connection, completely eliminating the Schottky barrier leakage problem. Simultaneously, the serpentine piezoresistive structure extends the piezoresistive sensing path, significantly improving sensing sensitivity.

[0028] In summary, this invention, through the synergistic design of a multi-range piezoresistive region, an embedded nanodiamond high heat dissipation structure, a closed-loop heavily doped polycrystalline silicon shielding and isolation structure, a precision platinum resistance thin film temperature-pressure composite structure, and a multi-metal stacked corner connection structure, enables the piezoresistive pressure sensor chip to better adapt to high and low temperature alternation, strong electromagnetic interference, humid pollution, and high reliability pressure detection scenarios in the automotive field, and has high automotive-grade application value. Attached Figure Description

[0029] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0030] Figure 1 This is a process flow diagram of the fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to the present invention.

[0031] Figure 2 This is a cross-sectional schematic diagram of the SOI substrate structure prepared by the present invention.

[0032] Figure 3 This is a cross-sectional schematic diagram of the top and bottom thin oxide layers formed according to the present invention.

[0033] Figure 4 This is a cross-sectional schematic diagram of the low-range and high-range piezoresistive regions formed by the present invention.

[0034] Figure 5 This is a schematic diagram of the planar layout after the low-range and high-range pressure-sensitive areas are formed according to the present invention.

[0035] Figure 6 This is a schematic diagram of the planar layout of the serpentine structure formed by the present invention.

[0036] Figure 7 This is a cross-sectional schematic diagram showing the low-range and high-range piezoresistive regions formed by the present invention.

[0037] Figure 8This is a cross-sectional schematic diagram of the shielding layer formed according to the present invention.

[0038] Figure 9 This is a cross-sectional schematic diagram of the electrically connected metal layer formed according to the present invention.

[0039] Figure 10 This is a cross-sectional schematic diagram of the dielectric film and platinum resistance thin film structure formed according to the present invention.

[0040] Figure 11 This is a cross-sectional schematic diagram of the present invention after the formation of the electrical isolation layer and the external connection PAD structure.

[0041] Figure 12 This is a cross-sectional schematic diagram of the nanodiamond high heat dissipation structure and the back release cavity formed by the present invention.

[0042] Figure 13 This is a schematic diagram of the planar layout of the low-range varistor region, high-range varistor region, back-side release cavity, shielding layer, platinum resistance thin film structure, and embedded nanodiamond high heat dissipation structure formed by the present invention.

[0043] Figure 14 This is a schematic diagram of the planar layout of the low-range pressure-sensitive area, the high-range pressure-sensitive area, and the back release cavity formed by the present invention.

[0044] Figure 15 This is a longitudinal cross-sectional schematic diagram of the low-range pressure-sensitive area, high-range pressure-sensitive area, back-side release cavity, shielding layer, and embedded nanodiamond high heat dissipation structure of the present invention.

[0045] Explanation of reference numerals on the accompanying drawings: 1. Supporting silicon wafer; 2. Buried oxide insulating layer; 3. Top silicon; 4. Top thin oxide layer; 41. Low-range varistor region; 42. High-range varistor region; 5. Heavily doped P+ structure in the low-range varistor region; 6. Lightly doped P-type varistor in the low-range varistor region; 7. Heavily doped P+ structure in the high-range varistor region; 8. Lightly doped P-type varistor in the high-range varistor region; 9. Dielectric film; 10. Platinum resistance thin film structure; 11. Electrically insulating layer; 12. Bottom thin oxide layer; 13. Shielding layer; 131. First shielding unit; 132. Second shielding unit; 41. Electrical connection metal for low-range varistor region; 142. Electrical connection metal for high-range varistor region; 15. External connection PAD structure; 151. First platinum resistance film PAD; 152. Second platinum resistance film PAD; 16. Embedded nanodiamond high heat dissipation structure; 161. First nanodiamond heat dissipation part; 162. Second nanodiamond heat dissipation part; 17. Back release cavity; 171. First release area; 172. Second release area; 173. Third release area; 181. Piezoresistive straight section; 182. Bend corner connection section. Detailed Implementation

[0046] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0047] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0048] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0049] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0050] Reference Figure 1 As shown in this embodiment, the fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications includes: S1. Provide an SOI substrate structure, wherein the SOI substrate structure includes a supporting silicon wafer 1, a buried oxide insulating layer 2, and a top silicon wafer 3 arranged sequentially from bottom to top. The supporting silicon wafer 1 provides mechanical support, the buried oxide insulating layer 2 improves longitudinal insulation capability, and the top silicon wafer 3 is used to arrange the varistor region and shielding structure. (Refer to...) Figure 2 As shown.

[0051] Specifically, an SOI substrate structure is provided, including: The donor silicon wafer and the support silicon wafer 1 are polished and cleaned; the surface of the donor silicon wafer achieves atomic-level polishing precision. The supporting silicon wafer 1 is thermally oxidized to form the buried oxide insulating layer 2 on the surface of the supporting silicon wafer 1; The donor silicon wafer is thinned and polished to form the top silicon 3. The voltage withstand capability of the chip is adjusted by regulating the thickness of the top silicon 3. The thicker the top silicon 3, the greater the voltage withstand capability of the chip. The thickness of the top silicon 3 is 5μm~80μm. The donor silicon wafer and the supporting silicon wafer 1 with the buried oxide insulating layer 2 are cleaned using standard processes to thoroughly remove surface particles, metal impurities, and organic contaminants, ensuring a clean and defect-free bonding interface. Then, the donor silicon wafer and the supporting silicon wafer 1 with the buried oxide insulating layer 2 are bonded. The buried oxide insulating layer 2 is a silicon oxide layer. The growth thickness of the buried oxide insulating layer 2 can be adjusted as needed. In this embodiment, the thickness of the buried oxide insulating layer 2 is 2μm~30μm. At the same time, the buried oxide insulating layer 2 serves as a stop layer for subsequent backside ICP etching. The bonded SOI silicon wafer was cleaned, dried, and thinned to obtain an SOI substrate structure. The SOI silicon wafer was ultrasonically treated in anhydrous ethanol, acetone, and deionized water for 30-60 minutes respectively, and then heated at 100°C for 30 minutes on a hot plate. The thickness of the SOI silicon wafer after overall thinning was 350 μm-450 μm.

[0052] S2. A top thin oxide layer 4 and a bottom thin oxide layer 12 are grown on the front and back sides of the SOI substrate structure, respectively. (Refer to...) Figure 3 As shown. This step specifically includes: The SOI substrate structure is placed in an oxidation furnace, and the top thin oxide layer 4 is formed on the front side of the top silicon 3 using a dry oxidation process, and the bottom thin oxide layer 12 is formed on the back side of the supporting silicon wafer 1. The top thin oxide layer 4 and the bottom thin oxide layer 12 are both silicon oxide layers with a thickness of 10nm~100nm; the oxidation temperature of the dry oxidation process is 700℃~1200℃ and the oxidation time is 30min~90min.

[0053] The top thin oxide layer 4 suppresses the channeling effect during subsequent ion implantation, and the bottom thin oxide layer 12 serves as an etching barrier layer during the backside ICP etching process.

[0054] S3. Within the top silicon 3, a low-range varistor region 41 and a high-range varistor region 42 are formed. The low-range varistor region 41 includes a connected heavily doped P+ structure 5 and a lightly doped P-type varistor 6. The high-range varistor region 42 includes a connected heavily doped P+ structure 7 and a lightly doped P-type varistor 8. (Refer to...) Figure 4 As shown. This step specifically includes: A low-range varistor region 41 is formed in the top silicon 3 near the chip edge. A heavily doped P+ structure 5 and a lightly doped P-type varistor 6 are formed in the low-range varistor region 41. The heavily doped P+ structure 5 is electrically connected to multiple lightly doped P-type varistors 6 and connected to the subsequently fabricated low-range varistor region electrical connection metal 141 to form a Wheatstone bridge. In order to reduce the resistance error in the circuit, the resistance value of the internal interconnection structure should be as small as possible. The low-range varistor region lightly doped P-type varistor 6 is formed by boron ion implantation, with an implantation energy of 50 keV~130 keV and an implantation dose of 0.5 × 10⁻⁶. 14 cm -2 ~1.8×10 14 cm -2 The low-range varistor region heavily doped P+ structure 5 is formed by boron ion implantation at an implantation energy of 30 keV to 80 keV and an implantation dose of 3 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 The annealing temperature for the low-range varistor region 41 is 1050℃~1150℃, and the annealing time is 120min~240min. Because the low-range varistor region 41 is close to the chip edge, it has the strongest pressure sensitivity and is most sensitive to pressure changes. Low-doping concentration and long-term high-temperature deep annealing are used to achieve a larger junction depth and a higher piezoresistive coefficient. The target range of the low-range varistor region 41 can reach 0~500kPa. A high-range varistor region 42 is formed in the top silicon 3 near the center of the chip. A heavily doped P+ structure 7 and a lightly doped P-type varistor 8 are formed in the high-range varistor region 42. The heavily doped P+ structure 7 is electrically connected to multiple lightly doped P-type varistors 8. It is then connected to the subsequently fabricated high-range varistor electrical connection metal 142 to form a Wheatstone bridge. In order to reduce the resistance error in the circuit, the resistance value of the internal interconnect structure should be as small as possible.

[0055] The high-range varistor region, lightly doped P-type varistor 8, is formed by boron ion implantation with an implantation energy of 50 keV to 90 keV and an implantation dose of 0.5 × 10⁻⁶. 15 cm -2 ~2×10 15 cm -2 The high-range varistor region heavily doped P+ structure 7 is formed by boron ion implantation at an implantation energy of 20 keV to 60 keV and an implantation dose of 1 × 10⁻⁶. 16 cm -2 ~3×10 16 cm-2 The high-range varistor region 42 has an annealing temperature of 900℃~1050℃ and an annealing time of 60min~100min, which can accurately form gradient junction depth and sensitivity partitioning. The high-range varistor region 42 is located close to the chip center, resulting in the strongest voltage withstand capability. High doping concentration and short-time low-temperature shallow annealing are employed, resulting in a shallower junction depth and stronger structural voltage withstand capability, making it suitable for high-voltage operating conditions. The target range of the high-range varistor region 42 can reach 1~5MPa. The low-range pressure-sensitive region 41 forms a deep junction high-sensitivity pressure detection area, and the high-range pressure-sensitive region 42 forms a shallow junction withstand pressure detection area, enabling the same chip to be compatible with both low-range and high-range pressure detection.

[0056] In this embodiment, refer to Figure 5 As shown, four high-range pressure-sensitive areas 42 are provided, which are centrally symmetrically distributed around the center of the chip and located close to the center of the chip; four low-range pressure-sensitive areas 41 are provided, which are centrally symmetrically distributed around the center of the chip and located outside the four high-range pressure-sensitive areas 42 respectively.

[0057] Specifically, the two high-range varistor regions 42 located on the upper and lower sides of the chip are arranged opposite each other along the Y-axis of the chip plane, and the two high-range varistor regions 42 located on the left and right sides of the chip are arranged opposite each other along the X-axis of the chip plane; the two low-range varistor regions 41 located on the upper and lower sides of the chip are arranged opposite each other along the Y-axis of the chip plane, and the two low-range varistor regions 41 located on the left and right sides of the chip are arranged opposite each other along the X-axis of the chip plane.

[0058] Specifically, refer to Figure 6 As shown, the lightly doped P-type varistor 6 in the low-range varistor region and / or the lightly doped P-type varistor 8 in the high-range varistor region have a serpentine structure and include multiple straight varistor segments 181 and bend corner connecting segments 182 connecting adjacent straight varistor segments 181. The bending corner connection segment 182 adopts a multi-layer metal stacked structure, which includes at least two layers selected from titanium, platinum and gold. The piezoresistive straight segment 181 is a silicon piezoresistive structure, and the piezoresistive straight segment 181 located at the beginning and end is respectively connected to the corresponding low-range piezoresistive region heavily doped P+ structure 5 or the high-range piezoresistive region heavily doped P+ structure 7.

[0059] Figure 7The high-range varistor region lightly doped P-type varistor 8 adopts a serpentine structure, while the low-range varistor region lightly doped P-type varistor 6 adopts a non-serpentine structure (single-segment connection structure). In this embodiment, both the high-range varistor region lightly doped P-type varistor 8 and the low-range varistor region lightly doped P-type varistor 6 adopt a serpentine structure.

[0060] By setting the P-type varistor to a serpentine structure, the piezoresistive sensing path can be extended within a limited chip area; by connecting the adjacent piezoresistive straight segment 181 through the bend corner connection segment 182, the continuity of electrical connection at the bend can be improved, the risk of leakage and signal loss can be reduced, and the pressure detection sensitivity can be improved.

[0061] S4. A shielding layer 13 is formed within the top silicon 3. The shielding layer 13 is a heavily doped N-type polycrystalline silicon shielding closed loop and is located above the low-range varistor region 41 and the high-range varistor region 42, respectively, and forms a reverse isolation junction with the top silicon 3. (Refer to...) Figure 8 As shown, this step specifically includes: An injection window corresponding to the low-range varistor region 41 and the high-range varistor region 42 is formed in the top silicon 3 by photolithography; The top silicon 3 is implanted with N-type heavily doped ions through the implantation window, and the wafer after ion implantation is annealed to form the shielding layer 13. The shielding layer 13 and the P-type silicon region located on the periphery of the shielding layer 13 in the top silicon 3 form a reverse isolation junction. The N-type heavily doped ion implantation uses phosphorus ion implantation with an implantation energy of 80 keV to 150 keV and an implantation dose of 1 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 High-energy doping enables heavy N-type doping of the polycrystalline silicon in the window region, laying the doping foundation for the shielding structure. The annealing treatment is carried out at a temperature of 900℃~1200℃ for 30min~90min. This process repairs lattice damage caused by ion implantation and activates the doped phosphorus impurities, enabling the doped region to form a stable, heavily doped N-type polycrystalline silicon shielding loop. The final shielding ring naturally forms a reverse PN junction with the bottom silicon substrate. Utilizing the isolation characteristics of the reverse junction, electrical shielding and insulation isolation are achieved throughout the device.

[0062] In this embodiment, the shielding layer 13 includes a first shielding unit 131 corresponding to the high-range pressure-sensitive region 42 and a second shielding unit 132 corresponding to the low-range pressure-sensitive region 41. The projection of the first shielding unit 131 toward the high-range pressure-sensitive region 42 covers the corresponding high-range pressure-sensitive region 42, and the projection of the second shielding unit 132 toward the low-range pressure-sensitive region 41 covers the corresponding low-range pressure-sensitive region 41.

[0063] S5. Low-range varistor electrical connection metal 141 and high-range varistor electrical connection metal 142 are formed on the surface of the top thin oxide layer 4. The low-range varistor electrical connection metal 141 contacts the shielding layer 13 and the heavily doped P+ structure 5 of the low-range varistor, respectively. The high-range varistor electrical connection metal 142 contacts the shielding layer 13 and the heavily doped P+ structure 7 of the high-range varistor, respectively. (Refer to...) Figure 9 As shown, this step specifically includes: A first electrical connection hole is formed on the top thin oxide layer 4, corresponding to the heavily doped P+ structure 5 in the low-range varistor region, the heavily doped P+ structure 7 in the high-range varistor region, and the shielding layer 13. A metal layer is deposited on the surface of the top thin oxide layer 4 where the first electrical connection hole is formed using a magnetron sputtering process, and the metal layer is patterned to form the low-range varistor region electrical connection metal 141 and the high-range varistor region electrical connection metal 142. The low-range varistor region electrical connection metal 141 is electrically connected to the low-range varistor region heavily doped P+ structure 5 and the shielding layer 13, respectively. The high-range varistor region electrical connection metal 142 is electrically connected to the high-range varistor region heavily doped P+ structure 7 and the shielding layer 13, respectively. The background vacuum level before magnetron sputtering is 5×10⁻⁶. -7 Torr, the process gas is high-purity Ar, the gas flow rate is 30sccm~60sccm, the chamber pressure is 3mTorr~8mTorr, the RF / DC power supply is turned on, and the pre-sputtering time is 5min~10min to clean the surface of the aluminum target and remove the oxide layer and impurities; then the wafer is moved to the process position, the DC power of the formal sputtering is 800W~1200W, the substrate temperature is 25℃~80℃, the deposition rate is 300Å / min~500Å / min, and the deposition time is set according to the target film thickness, the target film thickness is 0.1μm~5μm, and the deposition time is 1min~30min; after deposition, the power supply and argon gas are turned off, and high-purity nitrogen gas is introduced to purge the chamber to remove residual plasma and dust.

[0064] The internal interconnection resistance of the varistor is reduced by the low-range varistor electrical connection metal 141 and the high-range varistor electrical connection metal 142, and a stable varistor signal lead-out path and shielding potential connection path are formed.

[0065] S6. A dielectric film 9 is formed on the surface of the top thin oxide layer 4, and a platinum resistance thin film structure 10 is formed on the surface of the dielectric film 9. The platinum resistance thin film structure 10 is used for chip surface heating and chip operating temperature detection. (Refer to...) Figure 10 As shown. This step specifically includes: A dielectric film 9 is deposited on the surface of the top thin oxide layer 4 via plasma reaction, covering the low-range varistor electrical connection metal 141 and the high-range varistor electrical connection metal 142; wherein, the dielectric film 9 is a SiO film, and the dielectric film 9 is formed by PECVD process; the cavity vacuum degree of the PECVD process is 10. -6 The process involves using a Torr-level chamber temperature of 350℃~400℃, introducing a mixed gas consisting of SiH4, NH3, and O2 at flow rates of 20 sccm~40 sccm for SiH4, 30 sccm~50 sccm for NH3, and 50 sccm~80 sccm for O2. The chamber pressure is controlled at 2 Torr~5 Torr, the radio frequency power is 200W~400W, and SiO films are deposited via plasma reactive deposition at a deposition rate of 100 Å / min~200 Å / min, with a target film thickness of 0.1 μm~5 μm. The dielectric film 9 is subjected to chemical mechanical polishing to achieve surface planarization; wherein the chemical mechanical polishing uses silica polishing slurry, the polishing pressure is 2psi~4psi, and the polishing disc speed is 50rpm~80rpm, so as to accurately remove excess film layer and achieve global planarization.

[0066] A temperature measurement structure in a thermo-pressure composite structure is fabricated. A platinum thin film is deposited in the central region of the planarized dielectric film 9 using a magnetron sputtering process, and the platinum thin film is patterned and etched to form a platinum resistance thin film structure 10. The magnetron sputtering process has a sputtering power of 20W~200W, an argon flow rate of 20sccm~100sccm, and a deposition thickness of 50nm~200nm. The circular temperature-measuring heating thin film resistor is formed by photolithographic patterning and etching. The platinum resistance thin film structure 10 is annealed to stabilize the resistance temperature drift coefficient of the platinum resistance thin film structure 10; wherein, the annealing temperature of the platinum resistance thin film structure 10 is 450℃~800℃ and the annealing time is 30min~90min. The dielectric film 9 provides electrical isolation between the pressure-sensitive electrical connection structure and the platinum resistance film structure 10. Furthermore, the platinum resistance film structure 10 is used for chip surface heating and chip operating temperature detection. In heating mode, the platinum resistance film structure 10 can micro-heat the central region of the chip to remove moisture and particulate contaminants from the chip surface. In temperature measurement mode, the platinum resistance film structure 10 can acquire the chip surface operating temperature to provide temperature compensation parameters for the pressure detection signal output from the corresponding pressure-sensitive area.

[0067] S7. An electrical isolation layer 11 is formed on the surface of the dielectric film 9, and an external connection PAD structure 15 is formed on the surface of the electrical isolation layer 11, which respectively connects the low-range varistor electrical connection metal 141, the high-range varistor electrical connection metal 142, and the platinum resistance thin film structure 10. (Refer to...) Figure 11 As shown. This step specifically includes: An electrical isolation layer 11 covering the platinum resistance thin film structure 10 is deposited on the surface of the dielectric film 9 using a low-pressure chemical vapor deposition process. The electrical isolation layer 11 is patterned to form second electrical connection holes in the electrical isolation layer 11, corresponding to the low-range varistor electrical connection metal 141, the high-range varistor electrical connection metal 142, and the platinum resistance thin film structure 10, respectively. A metal layer for connecting the via is deposited on the surface of the electrically insulating layer 11 on which the second electrical connection hole is formed by magnetron sputtering, and the metal layer is patterned to form the external connection PAD structure 15. The electrically insulating layer 11 is a silicon oxide layer with a thickness of 0.05 μm to 0.5 μm. The low-pressure chemical vapor deposition process includes: after pre-process cleaning and drying, the wafer is fed into a low-pressure chemical vapor deposition equipment. The chamber is evacuated to a low-pressure environment, heated to the deposition process temperature, and silicon source gas and oxide source gas are introduced. The thickness of the electrically insulating layer 11 is controlled by adjusting the gas flow rate, chamber pressure, and deposition time to uniformly grow a silicon oxide film with a thickness of 0.05 μm to 0.5 μm on the wafer surface. The low-pressure environment can improve step coverage and ensure uniform film thickness in trenches and pattern sidewalls. After the electrically insulating layer 11 is deposited, it undergoes low-temperature densification annealing to release internal stress in the film, reduce pinhole and defect density, improve insulation withstand voltage performance, and ensure the electrical stability of the device. The metal layer is an Al layer; The electrical isolation layer 11 improves the insulation withstand voltage performance of the chip surface, and the external electrical connection terminals of the platinum resistance thin film structure 10, the low-range varistor region electrical connection metal 141, and the high-range varistor region electrical connection metal 142 are formed by the external connection PAD structure 15.

[0068] S8. Pattern the SOI substrate structure from the back side, using the buried oxide insulating layer 2 as the etching stop layer to release the varistor region in the top silicon 3 and form a back-side release cavity 17. An embedded nanodiamond high heat dissipation structure 16 is formed within the supporting silicon wafer 1 below the buried oxide insulating layer 2. (Refer to...) Figure 12 As shown. This step specifically includes: After patterning the SOI substrate structure from the back side, the SOI silicon wafer with the back release cavity 17 formed thereon is cleaned and dried. During patterning etching, KOH alkaline etchant wet etching or ICP etching is used. The etching temperature of KOH alkaline etchant wet etching is 75℃~85℃. Cleaning is carried out using SC1 and SC2 standard cleaning, and the drying temperature is 120℃. An embedding groove is formed in the supporting silicon wafer 1 below the buried oxide insulating layer 2 and corresponding to the varistor region; wherein the embedding groove is formed using a low-power RIE process and the groove depth is 50nm~150nm. A nanodiamond film is deposited in the embedding groove, and the nanodiamond film is chemically and mechanically polished to form the embedded nanodiamond high heat dissipation structure 16. The nanodiamond film is deposited using a PECVD process with a cavity pressure of 1 Torr to 3 Torr, a radio frequency power of 200 W to 350 W, a total flow rate of methane and hydrogen of 20 sccm to 80 sccm, and a deposition rate of 5 nm / min to 15 nm / min. After chemically and mechanically polishing, the underlying silicon structure under the buried oxide layer in the pressure-sensitive region is reconstructed to form the embedded nanodiamond high heat dissipation structure 16.

[0069] Furthermore, an embedded nanodiamond high heat dissipation structure 16 is embedded within the supporting silicon wafer 1. The back side of the embedded nanodiamond high heat dissipation structure 16 extends to the back release cavity 17, and the front side of the embedded nanodiamond high heat dissipation structure 16 extends to the back side of the buried oxide insulating layer 2. The projection of the embedded nanodiamond high heat dissipation structure 16 toward the high-range varistor region 42 covers the high-range varistor region 42. (Refer to...) Figure 13 , Figure 15 As shown, the embedded nanodiamond high heat dissipation structure 16 includes a first nanodiamond heat dissipation part 161 corresponding to the high-range pressure-sensitive region 42 and a second nanodiamond heat dissipation part 162 corresponding to the low-range pressure-sensitive region 41. The back sides of the first nanodiamond heat dissipation part 161 and the second nanodiamond heat dissipation part 162 both extend to the back release cavity 17, and the front sides both extend to the back side of the buried oxygen insulating layer 2.

[0070] The pressure-sensitive membrane structure that can be deformed under pressure is formed by the back release cavity 17, and the local heat of the pressure-sensitive area is discharged in the lateral and longitudinal directions by the embedded nanodiamond high heat dissipation structure 16, so as to reduce thermal drift and improve the long-term stability of the chip.

[0071] In this embodiment, refer to Figure 13 As shown, the platinum resistance film structure 10 is circular and located in the central region of the chip between the four high-range pressure-sensitive regions 42. The external connection PAD structure 15 includes a first platinum resistance film PAD151 and a second platinum resistance film PAD152. The leads of the first platinum resistance film PAD151 and the second platinum resistance film PAD152 extend radially along the platinum resistance film structure 10 and are respectively arranged in the 45° axial direction and the 135° axial direction passing through the center of the chip.

[0072] Furthermore, referring to Figure 14 As shown, the back release cavity 17 includes a first release region 171 located in the central region of the chip, a second release region 172 extending from the first release region 171 to each of the high-range pressure-sensitive regions 42, and a third release region 173 extending from the first release region 171 to each of the low-range pressure-sensitive regions 41. The projection of each second release region 172 onto the corresponding high-range pressure-sensitive region 42 covers the corresponding high-range pressure-sensitive region 42, and the projection of each third release region 173 onto the corresponding low-range pressure-sensitive region 41 covers the corresponding low-range pressure-sensitive region 41.

[0073] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A fabrication process for an automotive-grade, high-precision, leakage-proof piezoresistive pressure sensor chip, characterized in that, include: An SOI substrate structure is provided, the SOI substrate structure comprising a supporting silicon wafer (1), a buried oxide insulating layer (2) and a top silicon wafer (3) arranged sequentially from bottom to top; A top thin oxide layer (4) and a bottom thin oxide layer (12) are grown on the front and back sides of the SOI substrate structure, respectively. A low-range varistor region (41) and a high-range varistor region (42) are formed in the top silicon (3). The low-range varistor region (41) includes a connected low-range varistor region heavily doped P+ structure (5) and a low-range varistor region lightly doped P-type varistor (6). The high-range varistor region (42) includes a connected high-range varistor region heavily doped P+ structure (7) and a high-range varistor region lightly doped P-type varistor (8). A shielding layer (13) is formed in the top silicon (3). The shielding layer (13) is a heavily doped N-type polycrystalline silicon shielding closed loop and is located above the low-range varistor region (41) and the high-range varistor region (42) respectively, and forms a reverse isolation junction with the top silicon (3). A low-range varistor electrical connection metal (141) and a high-range varistor electrical connection metal (142) are formed on the surface of the top thin oxide layer (4). The low-range varistor electrical connection metal (141) is in contact with the shielding layer (13) and the heavily doped P+ structure (5) of the low-range varistor, respectively. The high-range varistor electrical connection metal (142) is in contact with the shielding layer (13) and the heavily doped P+ structure (7) of the high-range varistor, respectively. A dielectric film (9) is formed on the surface of the top thin oxide layer (4), and a platinum resistance film structure (10) is formed on the surface of the dielectric film (9). The platinum resistance film structure (10) is used for chip surface heating and chip operating temperature detection. An electrical isolation layer (11) is formed on the surface of the dielectric film (9), and an external connection PAD structure (15) is formed on the surface of the electrical isolation layer (11) to connect the low-range varistor electrical connection metal (141), the high-range varistor electrical connection metal (142) and the platinum resistance thin film structure (10). The SOI substrate structure is patterned and etched from the back side, and the buried oxide insulating layer (2) is used as the etching stop layer to release the pressure-sensitive area in the top silicon (3) and form a back release cavity (17), and an embedded nanodiamond high heat dissipation structure (16) is formed in the supporting silicon wafer (1) below the buried oxide insulating layer (2).

2. The fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to claim 1, characterized in that, Provide SOI substrate structures, including: The donor silicon wafer and the support silicon wafer (1) are polished and cleaned. The supporting silicon wafer (1) is thermally oxidized to form the buried oxide insulating layer (2) on the surface of the supporting silicon wafer (1). The donor silicon wafer is thinned and polished to form the top silicon (3), and the donor silicon wafer is bonded to the support silicon wafer (1) on which the buried oxide insulating layer (2) is formed; The bonded SOI silicon wafer is cleaned, dried, and thinned to obtain the SOI substrate structure.

3. The fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to claim 1, characterized in that, A top thin oxide layer (4) and a bottom thin oxide layer (12) are grown on the front and back sides of the SOI substrate structure, respectively, including: The SOI substrate structure is placed in an oxidation furnace, and the top thin oxide layer (4) is formed on the front side of the top silicon (3) using a dry oxidation process, and the bottom thin oxide layer (12) is formed on the back side of the supporting silicon wafer (1). The top thin oxide layer (4) and the bottom thin oxide layer (12) are both silicon oxide layers with a thickness of 10nm~100nm; the oxidation temperature of the dry oxidation process is 700℃~1200℃ and the oxidation time is 30min~90min.

4. The fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to claim 1, characterized in that, Within the top silicon (3), a low-range varistor region (41) and a high-range varistor region (42) are formed, including: A low-range varistor region (41) is formed in the top silicon (3) near the chip edge, and a heavily doped P+ structure (5) and a lightly doped P-type varistor (6) are formed in the low-range varistor region (41), so that the heavily doped P+ structure (5) and multiple lightly doped P-type varistors (6) are electrically connected; The lightly doped P-type varistor (6) in the low-range varistor region is formed by boron ion implantation, with an implantation energy of 50 keV to 130 keV and an implantation dose of 0.5 × 10⁻⁶. 14 cm -2 ~1.8×10 14 cm -2 The low-range varistor region heavily doped P+ structure (5) is formed by boron ion implantation, with an implantation energy of 30 keV~80 keV and an implantation dose of 3×10⁻⁶. 15 cm -2 ~5×10 15 cm -2 The annealing temperature corresponding to the low-range pressure-sensitive region (41) is 1050℃~1150℃, and the annealing time is 120min~240min. A high-range varistor region (42) is formed in the top silicon (3) near the center of the chip, and a heavily doped P+ structure (7) and a lightly doped P-type varistor (8) are formed in the high-range varistor region (42), so that the heavily doped P+ structure (7) and multiple lightly doped P-type varistors (8) are electrically connected; The high-range varistor region lightly doped P-type varistor (8) is formed by boron ion implantation, with an implantation energy of 50 keV~90 keV and an implantation dose of 0.5 × 10⁻⁶. 15 cm -2 ~2×10 15 cm -2 The high-range varistor region heavily doped P+ structure (7) is formed by boron ion implantation, with an implantation energy of 20 keV~60 keV and an implantation dose of 1×10⁻⁶. 16 cm -2 ~3×10 16 cm -2 The annealing temperature corresponding to the high-range pressure-sensitive region (42) is 900℃~1050℃, and the annealing time is 60min~100min.

5. The fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to claim 1, characterized in that, The low-range varistor region lightly doped P-type varistor (6) and / or the high-range varistor region lightly doped P-type varistor (8) have a serpentine structure and include multiple piezoresistive straight segments (181) and bend corner connecting segments (182) connecting adjacent piezoresistive straight segments (181). The bend and corner connection section (182) adopts a multi-layer metal stacked structure, which includes at least two of the titanium layer, platinum layer and gold layer; the piezoresistive straight section (181) is a silicon piezoresistive structure, and the piezoresistive straight section (181) located at the beginning and end is respectively connected to the corresponding low-range piezoresistive region heavily doped P+ structure (5) or the high-range piezoresistive region heavily doped P+ structure (7).

6. The fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to claim 1, characterized in that, A shielding layer (13) is formed within the top silicon (3), comprising: An injection window corresponding to the low-range varistor region (41) and the high-range varistor region (42) is formed in the top silicon (3) by photolithography; The top silicon (3) is implanted with N-type heavily doped ions through the implantation window, and the wafer after ion implantation is annealed to form the shielding layer (13). The shielding layer (13) and the P-type silicon region located on the periphery of the shielding layer (13) in the top silicon (3) form a reverse isolation junction. The N-type heavily doped ion implantation uses phosphorus ion implantation with an implantation energy of 80 keV to 150 keV and an implantation dose of 1 × 10⁻⁶. 15 cm -2 ~5×10 15 cm -2 The annealing temperature is 900℃~1200℃, and the annealing time is 30min~90min.

7. The fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to claim 1, characterized in that, Low-range varistor electrical connection metal (141) and high-range varistor electrical connection metal (142) are respectively formed on the surface of the top thin oxide layer (4), including: A first electrical connection hole corresponding to the heavily doped P+ structure (5) of the low-range varistor region, the heavily doped P+ structure (7) of the high-range varistor region, and the shielding layer (13) is formed on the top thin oxide layer (4); A metal layer is deposited on the surface of the top thin oxide layer (4) on which the first electrical connection hole is formed by magnetron sputtering, and the metal layer is patterned to form the low-range varistor electrical connection metal (141) and the high-range varistor electrical connection metal (142). The low-range varistor electrical connection metal (141) is electrically connected to the low-range varistor heavily doped P+ structure (5) and the shielding layer (13) respectively, and the high-range varistor electrical connection metal (142) is electrically connected to the high-range varistor heavily doped P+ structure (7) and the shielding layer (13) respectively. The background vacuum level before magnetron sputtering is 5×10⁻⁶. -7 Torr, the process gas is high-purity Ar, the gas flow rate is 30sccm~60sccm, the chamber pressure is 3mTorr~8mTorr, the RF / DC power supply is turned on, the pre-sputtering time is 5min~10min to clean the surface of the aluminum target and remove the oxide layer and impurities; then the wafer is moved to the process position, the DC power of the formal sputtering is 800W~1200W, the substrate temperature is 25℃~80℃, the deposition rate is 300Å / min~500Å / min, the target film thickness is 0.1μm~5μm, and the deposition time is 1min~30min; after deposition, the power supply and argon gas are turned off, and high-purity nitrogen gas is introduced to purge the chamber to remove residual plasma and dust.

8. The fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to claim 1, characterized in that, A dielectric film (9) is formed on the surface of the top thin oxide layer (4), and a platinum resistance thin film structure (10) is formed on the surface of the dielectric film (9), comprising: A dielectric film (9) is deposited on the surface of the top thin oxide layer (4) via plasma reaction, covering the low-range varistor electrical connection metal (141) and the high-range varistor electrical connection metal (142). The dielectric film (9) is a SiO film, formed using a PECVD process. The cavity vacuum degree of the PECVD process is 10. -6 The process involves using a Torr-level chamber temperature of 350℃~400℃, introducing a mixed gas consisting of SiH4, NH3, and O2 at flow rates of 20 sccm~40 sccm for SiH4, 30 sccm~50 sccm for NH3, and 50 sccm~80 sccm for O2. The chamber pressure is controlled at 2 Torr~5 Torr, the radio frequency power is 200W~400W, and SiO films are deposited via plasma reactive deposition at a deposition rate of 100 Å / min~200 Å / min, with a target film thickness of 0.1 μm~5 μm. The dielectric film (9) is subjected to chemical mechanical polishing to achieve surface planarization; A platinum thin film is deposited in the central region of the planarized dielectric film (9) by magnetron sputtering, and the platinum thin film is patterned and etched to form a platinum resistance thin film structure (10); wherein the sputtering power of the magnetron sputtering process is 20W~200W, the argon flow rate is 20sccm~100sccm, the deposition thickness is 50nm~200nm, and the photolithographic patterning is used to form a temperature-sensing heating thin film resistor; The platinum resistance film structure (10) is annealed to stabilize the resistance temperature drift coefficient of the platinum resistance film structure (10); wherein the annealing temperature of the platinum resistance film structure (10) is 450℃~800℃ and the annealing time is 30min~90min.

9. The fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to claim 1, characterized in that, An electrical isolation layer (11) is formed on the surface of the dielectric film (9), and an external connection PAD structure (15) is formed on the surface of the silicon oxide electrical isolation layer (11), which respectively connects the low-range varistor electrical connection metal (141), the high-range varistor electrical connection metal (142), and the platinum resistance thin film structure (10), including: An electrical isolation layer (11) covering the platinum resistance thin film structure (10) is deposited on the surface of the dielectric film (9) using a low-pressure chemical vapor deposition process. The electrical isolation layer (11) is patterned to form second electrical connection holes in the electrical isolation layer (11) corresponding to the low-range varistor electrical connection metal (141), the high-range varistor electrical connection metal (142), and the platinum resistance thin film structure (10), respectively. A metal layer for connecting the via is deposited on the surface of the electrical isolation layer (11) on which the second electrical connection hole is formed by magnetron sputtering, and the metal layer is patterned to form the external connection PAD structure (15). The electrically insulating layer (11) is a silicon oxide layer with a thickness of 0.05μm to 0.5μm. The low-pressure chemical vapor deposition process includes: after the wafer is pre-cleaned and dried, it is sent into a low-pressure chemical vapor deposition equipment, the cavity is pumped to a low-pressure environment, the temperature is raised to the deposition process temperature, silicon source gas and oxidation source gas are introduced, and the thickness of the electrically insulating layer (11) is controlled by adjusting the gas flow rate, cavity pressure and deposition time, and a silicon oxide thin film with a thickness of 0.05μm to 0.5μm is uniformly grown on the wafer surface; after the electrically insulating layer (11) is deposited, it is subjected to low-temperature densification annealing.

10. The fabrication process of a high-precision, leakage-proof piezoresistive pressure sensor chip for automotive applications according to claim 1, characterized in that, The SOI substrate structure is patterned and etched from the back side, with the buried oxide insulating layer (2) as the etching stop layer, to release the pressure-sensitive region in the top silicon (3) and form a back-side release cavity (17), and an embedded nanodiamond high heat dissipation structure (16) is formed in the supporting silicon wafer (1) below the buried oxide insulating layer (2), including: After patterning the SOI substrate structure from the back side, the SOI silicon wafer with the back release cavity (17) formed thereon is cleaned and dried. An embedding groove is formed in the supporting silicon wafer (1) below the buried oxide insulating layer (2) and corresponding to the varistor region; wherein the embedding groove is formed by a low-power RIE process and the groove depth is 50nm~150nm; A nanodiamond film is deposited in the embedding groove, and the nanodiamond film is chemically and mechanically polished to form the embedded nanodiamond high heat dissipation structure (16). The nanodiamond film is deposited by PECVD process, with a cavity pressure of 1 Torr~3 Torr, a radio frequency power of 200W~350W, a total flow rate of methane and hydrogen of 20sccm~80sccm, and a deposition rate of 5nm / min~15nm / min. After chemically and mechanically polishing, the underlying silicon structure under the buried oxide layer in the pressure-sensitive region is reconstructed to form the embedded nanodiamond high heat dissipation structure (16).

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