A device and method for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system.

Abstract

A device and method for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter (RDC) system, relating to the fields of motor control and sensor technology, is disclosed. The device includes: a dedicated resolver-to-digital converter chip (RDC), an excitation amplification module, a resolver, a signal conditioning module, an analog signal conversion module, and a microcontroller unit (MCU). This invention retains the original main RDC chip while introducing a microcontroller unit (MCU) to construct a completely independent software calculation channel. The MCU synchronously acquires the excitation signal and the conditioned sine and cosine differential signals, calculates position and velocity information in real time through software algorithms, and cross-validates the results with the output of the main RDC to achieve early anomaly detection. This invention achieves comprehensive health management of the RDC system from result verification to process monitoring and root cause tracing, significantly improving the system's reliability, security, and maintainability. It is suitable for high-reliability applications such as aerospace, industrial servo systems, and electric vehicle drives.

Description

Technical Field

[0001] This invention relates to the field of motor control and sensor technology, and in particular to a device and method for state monitoring, anomaly diagnosis and waveform quality monitoring of a resolver-to-digital converter system. Background Technology

[0002] Resolver transformers, as a type of absolute position sensor that is resistant to harsh environments and highly reliable, are widely used in aerospace, high-end industrial servo systems, electric vehicle drives, and other fields with stringent safety requirements. Dedicated resolver-to-digital converter (RDC) chips, such as Analog Devices' AD2S1210, can stably convert the analog sine and cosine signals (±SIN, ±COS) output by the resolver into digital angle and velocity values ​​by integrating excitation generation, signal demodulation, and a high-precision tracking loop, thus simplifying system design.

[0003] However, under prolonged exposure to high temperatures, vibrations, and electromagnetic interference, the entire RDC signal chain—including the RDC chip itself, peripheral excitation signal amplification and signal conditioning circuits, resolver sensors, and connecting cables—is at risk of performance degradation or even sudden failure. Currently, the system's health status assessment heavily relies on the limited fault flags provided by the RDC chip (such as signal loss or amplitude exceeding limits). This approach has significant drawbacks: First, it is a "post-event alarm," typically triggered only after a fault has affected signal integrity and caused calculation errors, failing to provide early warning of faults. Second, the fault flags are vaguely located, making it difficult to distinguish the root cause of the fault and complicating maintenance. Most importantly, the entire position sensing system completely relies on the output of a single chip, lacking an effective redundancy verification mechanism, posing a fatal risk of "single point of failure" in applications with high functional safety requirements.

[0004] Furthermore, traditional monitoring methods only focus on whether the final output is correct, neglecting the quality of the source of that result—the analog signal waveform. Signal distortion caused by transient electromagnetic interference (EMI), power fluctuations, loose wiring, etc., may be partially suppressed within the RDC chip or not captured by the fault logic, but the calculated position information may already contain imperceptible errors or jumps, posing potential risks to the upper-level control system.

[0005] Some existing technologies, such as patent CN202610075258.0 "Fault Diagnosis Method and Fault Diagnosis Device for Redundant Rotary Transformers," utilize the abrupt change characteristics of the low-pass filtering result of the voltage induced signal product to quickly diagnose excitation winding open-circuit faults, and utilize the sampling amplitude monitoring of the voltage induced signal to diagnose output winding open-circuit faults. Patent CN202511846301.0 "Multi-parameter Analysis and Fault Diagnosis Method Based on Rotary Transformer Output Signals" assesses the fault status of the rotary transformer itself and its application equipment through in-depth analysis of the rotary transformer's output signals. These existing technologies, to varying degrees, suffer from the aforementioned shortcomings.

[0006] Therefore, the industry urgently needs a forward-looking technology that can perform real-time, online, and in-depth health management of RDC systems. This technology should not only detect potential faults before performance becomes apparent, but also monitor signal quality, assess data reliability, and provide sufficient detailed information to support root cause analysis when a fault occurs. Summary of the Invention

[0007] Based on the above problems, the purpose of this invention is to overcome the shortcomings of the prior art and provide a device and method for state monitoring, anomaly diagnosis and waveform quality monitoring of a resolver-to-digital converter system. By constructing a dual-core redundant parallel architecture and deep signal analysis capabilities, it can solve the problems of delayed early warning, difficulty in fault location, lack of signal quality assessment and single-point dependence in the prior art, and realize the full-link, forward-looking health management of the RDC system.

[0008] The technical solution adopted by this invention to achieve its objective is a device for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system, comprising:

[0009] A dedicated resolver-to-digital converter chip RDC is used to generate the original excitation signal ±EXC and calculate the first position and velocity information;

[0010] The excitation amplification module is used to amplify the original excitation signal ±EXC and output the resolver excitation signal R. 12 ;

[0011] A resolver, used to generate a resolver excitation signal R. 12 Drive and output feedback signal S 13 S 24 ;

[0012] The signal conditioning module is used to condition the feedback signal S. 13 S 24 It outputs sine and cosine differential signals ±SIN and ±COS that conform to the electrical specifications of the dedicated resolver-to-digital converter chip RDC.

[0013] The analog signal conversion module is used to convert the original excitation signal ±EXC, the sine and cosine differential signals ±SIN and ±COS, and the resolver excitation signal R. 12 Feedback signal S 13 S 24 The signal is conditioned to conform to the electrical specifications of the microcontroller unit (MCU);

[0014] Microcontroller unit (MCU), the microcontroller unit (MCU) includes:

[0015] High-speed synchronous sampling analog-to-digital converter (ADC) is used to synchronously acquire the output signal of the analog signal conversion module;

[0016] The software calculation module is used to process the acquired digital signals and calculate the second position and velocity information in real time.

[0017] A communication interface is used to communicate with a dedicated resolver-to-digital converter chip (RDC) to obtain initial position and speed information;

[0018] The cross-validation and diagnostic module is used to compare the first position and velocity information with the second position and velocity information, and to determine the health status of the system based on the comparison results.

[0019] The waveform quality monitoring module is used to perform real-time analysis of the original sampled waveform, calculate quality parameters including transient noise level, total harmonic distortion (THD), and dynamic amplitude, and dynamically classify the reliability of the system output data based on the quality parameters.

[0020] The fault data recording module is used to trigger and save a complete context data snapshot containing the original waveform data before and after the fault, the calculation results, and the quality parameters when the dedicated resolver-to-digital converter chip RDC reports a fault or the waveform quality monitoring module detects a serious anomaly.

[0021] Furthermore, the cross-validation and diagnostic module is specifically configured as follows:

[0022] Calculate the real-time deviation between the first location information and the second location information;

[0023] Establish a dynamic confidence interval for the deviation value under a healthy system condition;

[0024] When the deviation value continues to exceed the dynamic confidence interval, it is determined to be an inconsistency anomaly and the root cause diagnosis process is triggered.

[0025] Furthermore, the root cause diagnosis process includes:

[0026] Analyze the amplitude and total harmonic distortion (THD) characteristics of the sinusoidal and cosine differential signals ±SIN and ±COS, and the phase difference between the sinusoidal and cosine differential signals ±SIN and ±COS and the original excitation signal ±EXC.

[0027] Analysis of the resolver excitation signal R 12 and feedback signal S 13 S 24 Amplitude and frequency;

[0028] Based on the pattern of the aforementioned deviation values, it is determined that the root cause of the fault originates from within the dedicated resolver-to-digital converter chip (RDC), the excitation amplification module, the signal conditioning module, the connecting cables, or the resolver itself.

[0029] Furthermore, the dynamic reliability grading implemented by the waveform quality monitoring module includes:

[0030] High reliability level, excellent waveform quality and cross-validated;

[0031] The level of concern is that a tolerable transient waveform degradation was detected, but the cross-validation did not exceed the limit.

[0032] Untrusted level: Severe waveform distortion or cross-validation exceeding limits is detected. At the untrusted level, the device outputs an invalid data flag and triggers a security handling strategy.

[0033] Furthermore, the waveform quality monitoring module monitors the gradual decay trend of the ±SIN and ±COS envelope amplitudes of the sine and cosine differential signals, and generates a predictive maintenance warning before the amplitude drops to the signal loss fault threshold of the dedicated resolver-to-digital converter chip RDC.

[0034] Furthermore, the data snapshots saved by the fault data recording module have a time window covering a specific period before and after the fault trigger point, which is used for offline in-depth analysis to distinguish between real faults and transient interference, and to accurately locate the specific link of the fault in the signal chain.

[0035] This invention also provides a method for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system, applied to the aforementioned device, comprising the following steps:

[0036] S1. System initialization and synchronization: Configure the dedicated resolver-to-digital converter chip RDC and establish time base synchronization with the microcontroller unit MCU;

[0037] S2. Dual-channel parallel data acquisition: The dedicated resolver-to-digital converter chip RDC normally calculates and outputs the first position and speed information, while the microcontroller unit MCU synchronously samples the original waveform and software calculates and outputs the second position and speed information.

[0038] S3. Cross-validation and consistency judgment: Real-time comparison of the first position and velocity information and the second position and velocity information, and comparison with the dynamic confidence interval;

[0039] S4. Real-time waveform quality monitoring and reliability grading: Analyze the quality parameters of the original sampled waveform and dynamically evaluate the reliability level of the output data;

[0040] S5. Anomaly Diagnosis and Fault Data Recording: When consistency judgment fails or waveform quality is severely degraded, perform the root cause diagnosis process and save a complete context data snapshot.

[0041] Furthermore, the real-time waveform quality monitoring and reliability grading steps specifically include:

[0042] Monitor for sudden increases in signal noise caused by sudden electromagnetic interference; when noise increases but the fundamental amplitude of the signal does not exceed the limit and cross-validation is not lost, mark the current data as reliability downgraded; when severe waveform distortion is detected that causes cross-validation to fail, determine that the data is unreliable and activate the safety fault tolerance mechanism.

[0043] Furthermore, the abnormal diagnosis and fault data recording steps also include: when the internal fault register flag bit of the dedicated resolver-to-digital converter chip RDC is set through the communication interface, a data snapshot is immediately triggered; the data snapshot includes at least the fault register value, the original ADC data before and after the fault time, the software calculation result sequence, and the waveform quality parameter sequence.

[0044] Furthermore, it also includes predictive maintenance steps: by recording and analyzing the statistical characteristics of the signal amplitude trend, THD baseline change and cross-validation deviation output by the waveform quality monitoring module over a long period of time, the aging status of key components of the resolver-to-digital converter system is assessed and early warning is given.

[0045] The beneficial effects of this invention are as follows:

[0046] (i) Achieving predictive maintenance and early warning: Through highly sensitive dual-core cross-validation and millisecond-level waveform quality monitoring, it can keenly capture early signs such as chip aging, circuit parameter drift, and slight signal degradation before the main RDC's own fault flag is triggered, thus achieving a fundamental shift from "post-event alarm" to "pre-event warning".

[0047] (ii) Provides data reliability awareness and intelligent fault tolerance: The unique real-time waveform quality monitoring and dynamic grading mechanism enables the system to recognize the reliability of its own output data. When faced with transient interference, it can automatically downgrade the reliability of data or shield unreliable data, avoiding misleading the upper-level controller with erroneous information, and significantly improving the system's resilience and intelligent fault tolerance level in complex electromagnetic environments.

[0048] (III) Achieving refined fault location and isolation: By combining deviation analysis, multi-dimensional waveform feature analysis and main RDC fault register, the fault can be effectively isolated to specific links such as RDC chip, excitation drive, conditioning circuit, cable connection or resolver sensor, which greatly improves the testability and maintainability of the system.

[0049] (iv) Building enhanced fault tracing and diagnosis support: The "fault snapshot" mechanism fully preserves the original waveforms and system states before and after the fault occurred, providing engineers with powerful data support for offline in-depth analysis, problem reproduction, and design optimization, and solving the industry problem of difficult on-site fault reproduction and diagnosis.

[0050] (v) A highly reliable redundant safety architecture has been established: The independent dual-core design constitutes dual redundancy at both the physical and logical levels. This not only provides data verification, but also ensures that in the extreme case of complete failure of the main RDC, the MCU channel can still provide degraded location information to support safe system shutdown or switching, meeting the requirements of high-level functional safety (such as ISO26262) for avoiding single points of failure. Attached Figure Description

[0051] Figure 1 This is a block diagram of the overall structure of the device in Embodiment 1 of the present invention.

[0052] Figure 2 This is a flowchart of the MCU internal software processing and diagnostic logic in Embodiment 2 of the present invention;

[0053] Figure 3 This is a logical diagram illustrating waveform quality monitoring and data reliability grading in Embodiment 2 of the present invention;

[0054] Figure 4 This is a schematic diagram of the fault snapshot record content in Embodiment 2 of the present invention. Detailed Implementation

[0055] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] Example 1

[0057] Figure 1 This invention illustrates a specific embodiment of the status monitoring, anomaly diagnosis, and waveform quality monitoring device for the resolver-to-digital converter system, comprising:

[0058] The dedicated resolver-to-digital converter chip RDC is used to generate the original excitation signal ±EXC, receive and process the sine and cosine differential signals ±SIN and ±COS, and output a high-precision first position through an internal closed-loop tracking circuit. and speed information.

[0059] The excitation amplification module is used to amplify the original excitation signal ±EXC and output the resolver excitation signal R. 12 .

[0060] A resolver, used to generate a resolver excitation signal R. 12 Drive and output feedback signal S 13 S 24 .

[0061] The signal conditioning module connects between the resolver output and the dedicated resolver-to-digital converter (RDC) chip. It includes at least two symmetrical conditioning channels to process the feedback signal S. 13 S 24 Each channel includes a differential receiver, an anti-aliasing filter, and level adjustment circuitry to ensure that the differential feedback signal from the resolver is converted without distortion into a single-ended signal suitable for RDC sampling.

[0062] The analog signal conversion module is used to convert the original excitation signal ±EXC, the sine and cosine differential signals ±SIN and ±COS, and the resolver excitation signal R. 12 Feedback signal S 13 S 24 The signal is conditioned to conform to the electrical specifications of the microcontroller unit (MCU).

[0063] Microcontroller unit (MCU), the microcontroller unit (MCU) includes:

[0064] High-speed synchronous sampling analog-to-digital converter (ADC) is used to synchronously acquire the output signal of analog signal conversion module. It has multi-channel synchronous sampling capability, or can achieve strict synchronization through the cooperation of multiple ADC modules to synchronously digitize the output signal of analog signal conversion module at high frequency.

[0065] The software processing module processes the acquired digital signals, runs digital demodulation and position calculation algorithms, and calculates the second position in real time from the synchronously sampled data. With speed Information. This process typically includes steps such as digital phase-locked loop (DPLL), synchronous demodulation, filtering, and arctangent (arctan2) calculation.

[0066] The communication interface is used to communicate with the dedicated resolver-to-digital converter chip RDC, configure its operating parameters, and read the first position in real time. and speed information.

[0067] The cross-validation and diagnostic module is used to compare the first position and velocity information with the second position and velocity information, and to determine the system health status based on the comparison results. Specifically, this module is configured to calculate the real-time deviation between the first position information and the second position information.

[0068]

[0069]

[0070] Establish a dynamic confidence interval for the deviation value under a healthy system condition; when the deviation value continuously exceeds the dynamic confidence interval, it is determined to be an inconsistency anomaly and the root cause diagnosis process is triggered.

[0071] The waveform quality monitoring module is used to perform real-time analysis of the original sampled waveform, calculate quality parameters including transient noise level, total harmonic distortion (THD), and dynamic amplitude, and dynamically classify the reliability of the system output data based on the quality parameters. It also assigns confidence labels or triggers corresponding control strategies (such as data disabling or alarms) to data of different levels. The dynamic reliability classification implemented by the waveform quality monitoring module includes:

[0072] High reliability level, excellent waveform quality and cross-validated;

[0073] The level of concern is that a tolerable transient waveform degradation was detected, but the cross-validation did not exceed the limit.

[0074] Untrusted level: Severe waveform distortion or cross-validation exceeding limits is detected. At the untrusted level, the device outputs an invalid data flag and triggers a security handling strategy.

[0075] The waveform quality monitoring module monitors the gradual decay trend of the ±SIN and ±COS envelope amplitudes of the sine and cosine differential signals, and generates a predictive maintenance warning before the amplitude drops to the signal loss fault threshold of the dedicated resolver-digital converter chip RDC.

[0076] The fault data recording module is used to trigger and save a complete context data snapshot containing the original waveform data before and after the fault, the calculation results, and quality parameters when the dedicated resolver-to-digital converter chip RDC reports a fault or the waveform quality monitoring module detects a serious anomaly. The data snapshot's time window covers a specific period before and after the fault trigger point, and is used for offline in-depth analysis to distinguish between real faults and transient interference, and to accurately locate the specific link of the fault in the signal chain.

[0077] In this embodiment, the root cause diagnosis process includes:

[0078] Analyze the amplitude and total harmonic distortion (THD) characteristics of the sinusoidal and cosine differential signals ±SIN and ±COS, and the phase difference between the sinusoidal and cosine differential signals ±SIN and ±COS and the original excitation signal ±EXC.

[0079] Analysis of the resolver excitation signal R 12 and feedback signal S 13 S 24 Amplitude and frequency;

[0080] Based on the pattern of the aforementioned deviation values, it is determined that the root cause of the fault originates from within the dedicated resolver-to-digital converter chip (RDC), the excitation amplification module, the signal conditioning module, the connecting cables, or the resolver itself.

[0081] This embodiment applies to a motor controller for a new energy vehicle. The main RDC chip is the AD2S1210, which outputs a 16-bit absolute angle and has an excitation frequency of 10kHz.

[0082] MCU Selection: STMicroelectronics STM32H743 is selected, with a main frequency of 480MHz, three built-in 16-bit ADCs, and support for timer-triggered alternating sampling mode to achieve three-channel quasi-synchronous sampling, with a sampling rate set to 250kHz (25 times the excitation frequency). Its powerful floating-point unit (FPU) and DSP instructions can meet the requirements of real-time software computation.

[0083] Signal conditioning module:

[0084] Differential reception: Two high common-mode rejection ratio instrumentation amplifiers INA188 are used to receive the S_13 and S_24 signals of the resolver, respectively.

[0085] Anti-aliasing filter: Design a Butterworth low-pass filter with a cutoff frequency of 50kHz.

[0086] Level adjustment circuit: After adjusting the signal to the 0-3.3V range, it sends it to the input pin of AD2S1210 and the ADC pin of STM32H743 respectively.

[0087] The STM32H743 communicates with the AD2S1210 via the SPI interface, and ADC sampling is triggered by the advanced timer TIM8.

[0088] Example 2

[0089] A specific implementation of the method for state monitoring, anomaly diagnosis, and waveform quality monitoring of the resolver-to-digital converter system of the present invention, applied to the test system described in Example 1, includes the following steps:

[0090] S1. System initialization and synchronization: Configure the dedicated resolver-to-digital converter chip RDC and establish time base synchronization with the microcontroller unit MCU;

[0091] S2. Dual-channel parallel data acquisition: The dedicated resolver-to-digital converter chip RDC normally calculates and outputs the first position and speed information, while the microcontroller unit MCU synchronously samples the original waveform and software calculates and outputs the second position and speed information.

[0092] S3. Cross-validation and consistency judgment: Real-time comparison of the first position and velocity information and the second position and velocity information, and comparison with the dynamic confidence interval;

[0093] S4. Real-time waveform quality monitoring and reliability grading: Analyze the quality parameters of the original sampled waveform and dynamically evaluate the reliability level of the output data. Specifically, this includes: monitoring for short-term sudden increases in signal noise caused by sudden electromagnetic interference; marking the current data as reliability downgraded when noise increases but the fundamental amplitude of the signal does not exceed the limit and cross-validation is not lost; and determining that the data is unreliable and activating the safety fault tolerance mechanism when severe waveform distortion is detected that causes cross-validation to fail.

[0094] S5. Anomaly Diagnosis and Fault Data Recording: When consistency judgment fails or waveform quality is severely degraded, a fault root cause diagnosis process is performed and a complete context data snapshot is saved. When the internal fault register flag bit of the dedicated resolver-to-digital converter chip RDC is set through the communication interface, data snapshot recording is immediately triggered; the data snapshot includes at least the fault register value, the original ADC data before and after the fault, the software calculation result sequence, and the waveform quality parameter sequence.

[0095] S6. Predictive maintenance steps: By recording and analyzing the statistical characteristics of the signal amplitude trend, THD baseline change, and cross-validation deviation output by the waveform quality monitoring module over a long period of time, the aging status of key components of the resolver-to-digital converter system is assessed and an early warning is given.

[0096] Specifically, the process of MCU internal software processing and diagnostic logic is as follows: Figure 2 As shown;

[0097] 1. High-speed sampling task: The timer interrupt triggers the ADC to synchronously sample three signals, and the data is cyclically stored into the buffer through DMA.

[0098] 2. Software calculation and quality monitoring tasks (high priority):

[0099] - Digital phase-locked loop is applied to the EXC signal to generate a synchronization reference signal.

[0100] - Digital quadrature demodulation and low-pass filtering are performed on the SIN and COS signals to obtain the envelope A. sin(t) and A cos(t) .

[0101] - Calculated using the CORDIC algorithm = arctan2(A sin(t) A cos(t) ).

[0102] - In parallel, calculate the effective value, peak-to-peak noise, and THD approximation within the current 200 sampling point window for the original SIN / COS sampling data.

[0103] 3. Data reading, comparison, and classification tasks (medium priority):

[0104] - Read the angle value of AD2S1210 via SPI at a frequency of 1kHz .

[0105] - calculate And update its running statistics (μ, σ).

[0106] - Comprehensive decision-making: combining Whether it exceeds the range of μ±5σ, and waveform quality parameters (such as whether THD exceeds 2%, whether noise surges), according to Figure 3 The logic performs a final reliability classification (A / B / C level) on the output data at the current moment.

[0107] 4. Fault logging task (event triggered):

[0108] This task is triggered when data is classified as C or when the AD2S1210 fault register is read as set.

[0109] - like Figure 4 As shown, the task packages all relevant data (raw ADC buffer data, calculation results, quality parameters, and fault codes) within a 100ms time window before and after the current moment, adds a timestamp, and stores it in an external FLASH.

[0110] Examples of specific problems solved by this invention:

[0111] Scenario 1: The vehicle encounters strong electromagnetic interference while driving.

[0112] - Traditional systems: Strong common-mode noise couples into the signal lines, causing numerous glitches in the SIN / COS waveform. The AD2S1210's internal filter may not completely eliminate these glitches, resulting in random jumps in the angle output, even though the signal amplitude may not exceed limits, and the fault flag may not trigger. The controller receiving incorrect position information may cause torque fluctuations.

[0113] - This invention: The waveform quality monitoring module detects a sharp increase in transient noise energy in the SIN / COS signal in real time, exceeding the THD limit. Although at this time... The system may not immediately exceed limits due to interference affecting both cores, but it has already downgraded the data reliability to level B or C. If the interference persists, the data will be marked as level C (unreliable). The MCU can report "low data reliability" to the upper-level controller and suggest that the controller use inertial estimation or trigger safety limits to avoid control actions based on erroneous data and ensure driving safety.

[0114] Scenario 2: Intermittent poor contact occurs at the resolver terminals due to vibration.

[0115] - Traditional systems: Changes in contact resistance cause signal amplitude fluctuations, which may intermittently trigger "LOS / DOS" faults. However, there are no traces after the fault is reset, making the problem difficult to reproduce and locate.

[0116] - This invention: Once a "LOS / DOS" fault is triggered, a fault snapshot mechanism immediately records the complete waveform for hundreds of milliseconds before and after the fault. Offline analysis of the snapshot clearly shows that before the fault indicator is generated, the signal amplitude has already shown a regular decrease or fluctuation, thus accurately pinpointing the problem to a "connector contact problem," rather than a fault in the resolver or the chip itself.

[0117] In summary, this invention provides an unprecedented comprehensive health management solution for high-reliability RDC systems by organically combining dual-core redundancy, waveform quality monitoring and intelligent grading, and enhanced fault tracing, significantly improving the system's security, reliability, and maintainability.

Claims

1. A device for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system, characterized in that, include: A dedicated resolver-to-digital converter chip RDC is used to generate the original excitation signal ±EXC and calculate the first position and velocity information; The excitation amplification module is used to amplify the original excitation signal ±EXC and output the resolver excitation signal R. 12 ; A resolver, used to generate a resolver excitation signal R. 12 Drive and output feedback signal S 13 S 24 ; The signal conditioning module is used to condition the feedback signal S. 13 S 24 It outputs sine and cosine differential signals ±SIN and ±COS that conform to the electrical specifications of the dedicated resolver-to-digital converter chip RDC. The analog signal conversion module is used to convert the original excitation signal ±EXC, the sine and cosine differential signals ±SIN and ±COS, and the resolver excitation signal R. 12 Feedback signal S 13 S 24 The signal is conditioned to conform to the electrical specifications of the microcontroller unit (MCU); Microcontroller unit (MCU), the microcontroller unit (MCU) includes: High-speed synchronous sampling analog-to-digital converter (ADC) is used to synchronously acquire the output signal of the analog signal conversion module; The software calculation module is used to process the acquired digital signals and calculate the second position and velocity information in real time. A communication interface is used to communicate with a dedicated resolver-to-digital converter chip (RDC) to obtain initial position and speed information; The cross-validation and diagnostic module is used to compare the first position and velocity information with the second position and velocity information, and to determine the health status of the system based on the comparison results. The waveform quality monitoring module is used to perform real-time analysis of the original sampled waveform, calculate quality parameters including transient noise level, total harmonic distortion (THD), and dynamic amplitude, and dynamically classify the reliability of the system output data based on the quality parameters. The fault data recording module is used to trigger and save a complete context data snapshot containing the original waveform data before and after the fault, the calculation results, and the quality parameters when the dedicated resolver-to-digital converter chip RDC reports a fault or the waveform quality monitoring module detects a serious anomaly.

2. The device for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system according to claim 1, characterized in that, The cross-validation and diagnostic module is specifically configured as follows: Calculate the real-time deviation between the first location information and the second location information; Establish a dynamic confidence interval for the deviation value under a healthy system condition; When the deviation value continues to exceed the dynamic confidence interval, it is determined to be an inconsistency anomaly and the root cause diagnosis process is triggered.

3. The device for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system according to claim 2, characterized in that, The root cause diagnosis process includes: Analyze the amplitude and total harmonic distortion (THD) characteristics of the sinusoidal and cosine differential signals ±SIN and ±COS, and the phase difference between the sinusoidal and cosine differential signals ±SIN and ±COS and the original excitation signal ±EXC. Analysis of the resolver excitation signal R 12 and feedback signal S 13 S 24 Amplitude and frequency; Based on the pattern of the aforementioned deviation values, it is determined that the root cause of the fault originates from within the dedicated resolver-to-digital converter chip (RDC), the excitation amplification module, the signal conditioning module, the connecting cables, or the resolver itself.

4. The device for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system according to claim 1, characterized in that, The dynamic reliability grading implemented by the waveform quality monitoring module includes: High reliability level, excellent waveform quality and cross-validated; The level of concern is that a tolerable transient waveform degradation was detected, but the cross-validation did not exceed the limit. Untrusted level: Severe waveform distortion or cross-validation exceeding limits is detected. At the untrusted level, the device outputs an invalid data flag and triggers a security handling strategy.

5. The device for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system according to claim 1, characterized in that: The waveform quality monitoring module monitors the gradual decay trend of the ±SIN and ±COS envelope amplitudes of the sine and cosine differential signals, and generates a predictive maintenance warning before the amplitude drops to the signal loss fault threshold of the dedicated resolver-digital converter chip RDC.

6. The device for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system according to claim 1, characterized in that: The data snapshots saved by the fault data recording module have a time window covering a specific period before and after the fault trigger point. They are used for offline in-depth analysis to distinguish between real faults and transient interference, and to accurately locate the specific link of the fault in the signal chain.

7. A method for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system, applied to the apparatus described in any one of claims 1 to 6, characterized in that, Includes the following steps: S1. System initialization and synchronization: Configure the dedicated resolver-to-digital converter chip RDC and establish time base synchronization with the microcontroller unit MCU; S2. Dual-channel parallel data acquisition: The dedicated resolver-to-digital converter chip RDC normally calculates and outputs the first position and speed information, while the microcontroller unit MCU synchronously samples the original waveform and software calculates and outputs the second position and speed information. S3. Cross-validation and consistency judgment: Real-time comparison of the first position and velocity information and the second position and velocity information, and comparison with the dynamic confidence interval; S4. Real-time waveform quality monitoring and reliability grading: Analyze the quality parameters of the original sampled waveform and dynamically evaluate the reliability level of the output data; S5. Anomaly Diagnosis and Fault Data Recording: When consistency judgment fails or waveform quality is severely degraded, perform the root cause diagnosis process and save a complete context data snapshot.

8. The method for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system according to claim 7, characterized in that, The real-time waveform quality monitoring and reliability grading steps specifically include: Monitor for sudden increases in signal noise caused by sudden electromagnetic interference; when noise increases but the fundamental amplitude of the signal does not exceed the limit and cross-validation is not lost, mark the current data as reliability downgraded; when severe waveform distortion is detected that causes cross-validation to fail, determine that the data is unreliable and activate the safety fault tolerance mechanism.

9. The method for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system according to claim 7, characterized in that, The abnormal diagnosis and fault data recording steps further include: when the internal fault register flag bit of the dedicated resolver-to-digital converter chip RDC is set through the communication interface, a data snapshot is immediately triggered; the data snapshot includes at least the fault register value, the original ADC data before and after the fault time, the software calculation result sequence, and the waveform quality parameter sequence.

10. The method for state monitoring, anomaly diagnosis, and waveform quality monitoring of a resolver-to-digital converter system according to claim 7, characterized in that, It also includes predictive maintenance steps: by recording and analyzing the statistical characteristics of the signal amplitude trend, THD baseline change and cross-validation deviation output by the waveform quality monitoring module over a long period of time, the aging status of key components of the resolver-to-digital converter system is assessed and early warning is given.

Images