A power tube gate leakage current defect detection device and method

Abstract

The application discloses a kind of power tube gate leakage current defect detection device and method, including pre-drive circuit, test trigger circuit, leakage threshold detection module, gate leakage test logic module and pull-down transistor MN2;Test trigger circuit and pre-drive circuit are connected in series after with the gate of the power tube MN1 to be detected MN1 connection, MN1 is detected trigger control;Test trigger circuit, leakage threshold detection module and gate leakage test logic module are connected with test enable input signal TST;Leakage threshold detection module is connected with the gate of MN1, and the gate leakage of MN1 is detected and the corresponding logic output signal is output;Gate leakage test logic module is connected with leakage threshold detection module and the gate of MN2, when input signal TST is high level, MN1 drain electrode is pulled down to ground by MN2;When being detected, gate leakage test logic module inputs high level to leakage threshold detection module, MN1 gate leakage detection result is latched, simultaneously input low level to MN2 gate and shut down MN2.

Description

Technical Field

[0001] This invention relates to the field of analog chips and mixed-signal chips, and in particular to a device and method for detecting gate leakage current defects in power transistors. Background Technology

[0002] Gate oxide defects in power transistors refer to any microscopic imperfections in their core insulating layer—the gate oxide. These defects weaken the insulating ability of the oxide layer and are one of the most critical factors leading to performance degradation, reduced reliability, and premature failure in power devices (especially SiC MOSFETs). Gate oxide defects pose a serious threat to the performance of power transistors, specifically manifesting as a series of cascading problems such as inducing further breakdown of the gate oxide layer, causing threshold voltage drift, and significantly increasing switching losses. Such defects reduce the insulating strength of the oxide layer, and under the action of electric field stress, local conductive channels are easily formed at the defect sites, accelerating the dielectric breakdown process over time and ultimately leading to permanent device failure. At the same time, threshold voltage drift changes the conduction and turn-off characteristics of the device, affecting the accuracy of drive control, while increased switching losses mean decreased energy conversion efficiency, accompanied by higher heat generation, further exacerbating thermal stress damage to the oxide layer. Under long-term operation in the presence of gate oxide defects, these degradation effects will accumulate continuously, accelerating the aging of the internal materials of the power transistor, ultimately significantly shortening its actual service life and severely reducing the overall reliability and safety of the system.

[0003] To mitigate the risks posed by gate oxide defects, the industry typically employs two strategies: First, process optimization: reducing defects introduced during manufacturing from the outset and monitoring them through WAT (Wafer Acceptance Test). For example, the disclosed technology, "Test Circuit, Method, and Test System for Gate Leakage Current of MOS Transistor" (CN121741431A), uses the WAT testing method, which requires external hardware and has a long measurement time, making it unsuitable for FT testing. FT often requires completing all chip parameter tests within 1-2 seconds. Second, defect screening: measuring the gate leakage current during the FT testing phase before chip delivery to filter out chips with substandard leakage current. For example, the technology disclosed in "Patent Publication No. CN114545183A, entitled A Power Transistor, Power Switch Chip and Leakage Detection Method" monitors gate oxide defects by directly applying voltage to the gate of the power transistor under test and measuring its leakage current during FT testing. However, due to the influence of measurement error and accuracy of the automatic testing machine itself, the current measurement error is often on the nA level. Therefore, if the leakage current is measured by directly applying bias voltage to the gate of the power transistor, it is impossible to accurately detect leakage defects on the nA level.

[0004] Therefore, there is an urgent need to propose an FT test method that can detect tiny gate oxide defects and quickly and accurately screen out chips with gate oxide defects. Summary of the Invention

[0005] To address the above problems, the present invention aims to provide a device and method for detecting gate leakage current defects in power transistors. The technical solution adopted by the present invention is as follows: The first part of this technology provides a power transistor gate leakage current defect detection device for detecting a power transistor MN1 under test. The device includes: a pre-drive circuit, a test trigger circuit, a leakage current threshold detection module, a gate leakage current test logic module, and a pull-down transistor MN2. The test trigger circuit and the pre-drive circuit are connected in series to the gate of the power transistor MN1 and perform detection trigger control on the power transistor MN1. The test trigger circuit, the leakage current threshold detection module, and the gate leakage current test logic module are externally connected to a test enable signal. The leakage current threshold detection module is connected to the gate of the power transistor MN1 and performs detection trigger control on the power transistor MN1. The gate leakage current detection module outputs a corresponding logic output signal; the drain of the pull-down transistor MN2 is connected to the drain of the power transistor MN1, and its source is grounded; the gate leakage current test logic module is connected to the leakage current threshold detection module and the gate of the pull-down transistor MN2. When the external test enable signal is high, the output of the power transistor MN1 is pulled down to ground through the pull-down transistor MN2; when the gate leakage current test logic module inputs a low level to the gate of the pull-down transistor MN2 and inputs a high level to the leakage current threshold detection module, the detection output result of the power transistor MN1 is latched.

[0006] Furthermore, the test trigger circuit includes a NOR gate I2, an inverter I3, and an inverter I4 connected in series; the output of the inverter I4 is connected to the pre-drive circuit; and the NOR gate I2 is externally connected to a test enable signal.

[0007] Furthermore, the transistor includes transistors MP1, MP2, and MN3; the gate of transistor MP2 is externally connected to a test enable signal; the gates of transistors MP1 and MN3 are connected to the output of inverter I4; the drain of transistor MP1 is connected to the source of transistor MP2; and the gate of power transistor MN1 is connected to the drain of transistor MP2 and the drain of transistor MN3.

[0008] Furthermore, the leakage threshold detection module includes a transistor MP3, a resistor R1, a transistor MP4, a resistor R2, and a latch output module; the gate of the transistor MP3 is externally connected to a test enable signal via an inverter I1; the drain of the transistor MP3 is connected to the gate of the power transistor MN1 via a resistor R1; the gate of the transistor MP4 is connected between the resistor R1 and the gate of the power transistor MN1, and detects the voltage drop across the resistor R1. If the voltage drop across the resistor R1 is greater than or equal to the gate drive threshold of the transistor MP4, a high level is output through the latch output module; the latch output module is connected between the drain of the transistor MP4 and the resistor R2.

[0009] Furthermore, the latch output module includes inverters I5, I6, I7, NOR gate I8, NOR gate I10, and inverter I12 connected in sequence; a NOR gate I9 with one input connected between inverters I6 and I7 and another input connected to NOR gate I8; and a NOR gate I11 with one input connected to the output of NOR gate I9 and another input connected between NOR gate I10 and inverter I12; the output of NOR gate I11 is connected to the input of NOR gate I10; and NOR gates I8 and I9 are connected to the gate leakage current test logic module.

[0010] Furthermore, the gate leakage test logic module includes a NOR gate I25, an inverter I26, a counter, an SR latch, a NAND gate I21, and an inverter I22 connected in sequence, as well as inverters I23 and I24 connected in series between the counter and the SR latch; the output of inverter I24 is connected between NOR gate I8 and NOR gate I9; and an external test enable signal is connected to NAND gate I21.

[0011] Furthermore, the counter includes D flip-flops I13, I14, I15, I16, I17, and I18 connected in sequence.

[0012] Furthermore, the SR latch includes a NOR gate I20 and a NOR gate I19; one input of the NOR gate I19 is connected to an external test enable signal via an inverter I27, and the other input is connected between the NOR gate I20 and the NAND gate I21.

[0013] The second part of this technology provides a detection method using a power transistor gate leakage current defect detection device, which includes the following steps: When an external test enable signal is input at a high level, the gate of the power transistor MN1 under test is triggered to a high-impedance state by the test trigger circuit and the pre-drive circuit. When the test enable signal is at a high level, the drain output of the power transistor MN1 is pulled down to ground through the pull-down transistor MN2. The leakage current threshold detection module is used to detect the gate leakage current of the power transistor MN1 under test and outputs the corresponding logic output signal. When the gate leakage test logic module pulls down the gate input of transistor MN2 to a low level and inputs a high level to the leakage threshold detection module, the detection output result of power transistor MN1 is latched.

[0014] Furthermore, the leakage current threshold detection module is used to detect gate leakage current in the power transistor MN1 under test, and outputs a corresponding logic output signal, including: The voltage drop across resistor R1 is detected by the transistor MP4; if the voltage drop across resistor R1 is greater than or equal to the gate drive threshold of transistor MP4, a high level is output through the latch output module.

[0015] Compared with the prior art, the present invention has the following beneficial effects: This invention employs a pre-drive circuit and a test trigger circuit. The test trigger circuit is externally connected to the drive logic signal IN and the test enable signal TST of the power transistor. When the test enable signal goes high, it causes the gate (PG node) of the power transistor MN1 under test to be in a high-impedance state, facilitating gate leakage detection by the leakage threshold detection module and the gate leakage test logic module. When the test enable signal goes low, the test is turned off, ensuring that the drive logic signal can properly control the switching of the power transistor MN1.

[0016] This invention sets up a transistor MP4 and detects the voltage drop across resistor R1. If the voltage drop across resistor R1 is greater than or equal to the gate drive threshold of transistor MP4, a high-level output is generated (representing that the gate leakage current of MN1 is unqualified). A larger resistance value of R1 makes it easier to detect even small gate leakage currents. This invention eliminates the need to apply a bias voltage to the PG node to directly measure the leakage current. Instead, it sets the gate leakage current detection threshold using the pull-up resistor R1 at the PG node and the VSG4 drive voltage of MP4, and converts it into a test logic output TST_OUT. This invention utilizes NOR gates I11 and I10 to form a latched output module and latches the detection results, ensuring accurate and reliable data.

[0017] This invention employs a gate leakage current testing logic module, which consists of a counter composed of D flip-flops I13, I14, I15, I16, I17, and I18, and an SR latch composed of NOR gates I20 and I19. The advantages are as follows: An EN_PD signal is generated and input to the gate of transistor MN2. During testing, transistor MN2 is turned on while the drain of power transistor MN1 remains grounded. This prevents voltage changes at the drain of power transistor MN1 from interfering with gate detection through its gate-drain parasitic capacitance CGD. At the end of the test, the gate leakage current testing logic module outputs a low-level EN_PD signal to the gate of transistor MN2, turning it off. Turning off transistor MN2 prevents pulling down the drain of power transistor MN1 during normal operation, which would affect circuit function. Simultaneously, the gate leakage current testing logic module outputs a high-level TST_LAT signal to the leakage threshold detection module, latching the test result from the leakage threshold detection module. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope of protection. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of the present invention.

[0020] Figure 2 for Figure 1 Waveform diagram of the key node.

[0021] Figure 3 This is a schematic diagram of the leakage current threshold detection module in this invention.

[0022] Figure 4 This is a schematic diagram of the gate leakage current test logic module in this invention.

[0023] Figure 5 This is a waveform diagram of a key node in the gate leakage detection logic module of this invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0025] In this embodiment, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0026] The terms "first" and "second," etc., used in the specification and claims of this embodiment are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0027] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0028] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0029] like Figure 1 As shown, this embodiment provides a power transistor gate leakage current defect detection device, which includes a pre-drive circuit, a test trigger circuit, a leakage current threshold detection module, a gate leakage current test logic module, and a pull-down transistor MN2.

[0030] The input signal IN is the drive logic signal for power transistor MN1. A high level IN indicates that power transistor MN1 is turned on, and a low level IN indicates that power transistor MN1 is turned off. The input signal TST is the test enable signal; a change from low to high TST indicates the start of testing. The input signal VCC is the module power supply. The output signal OUT is connected to the drive load. The output signal TST_OUT is the output of the gate leakage current test result for power transistor MN1. A high level TST_OUT indicates that the gate leakage current of power transistor MN1 is too large and fails to meet the standard, while a low level TST_OUT indicates that the gate leakage current of power transistor MN1 is small and the test is passed.

[0031] In this embodiment, power transistor MN1 is the gate leakage current device under test, and transistor MN2 is the pull-down MOSFET of the drain of power transistor MN1. The gate terminal PG of the power transistor is connected to the pre-drive circuit composed of transistors MP1, MP2, and MN3. When the input TST is high, the output of NOR gate I2 is low, which is output to the gates of transistors MP1 and MN3 via inverters I3 and I4, making transistor MP1 turn on and transistor MN3 turn off. The input signal TST is connected to the gate of transistor MP2. When the input signal TST is high, transistor MP2 will be in the off state.

[0032] At this time, transistors MP2 and MN3 will be in the off state simultaneously. The gate terminal PG of power transistor MN1 will be input to the leakage threshold detection module. The leakage threshold detection module is responsible for detecting the gate leakage of power transistor MN1 and outputting the corresponding logic output signal TST_OUT. For example, if the output signal TST_OUT is high, it means that the gate leakage test of power transistor MN1 is unqualified, and if the output signal is low, it means that the gate leakage test of power transistor MN1 is qualified.

[0033] Simultaneously, when the input signal TST changes from low to high, the gate leakage current test logic module outputs a high pulse signal EN_PD. EN_PD is input to the gate of transistor MN2, causing it to conduct and pull down the drain OUT terminal of power transistor MN1 to ground. When the output signal EN_PD of the gate leakage current test logic module changes from high to low, the gate leakage current test logic module outputs the TST_LAT signal, which changes from low to high and is output to the leakage current threshold detection module to latch the detection result.

[0034] Figure 2 correspond Figure 1 The key waveforms are as follows: the rising edge of the input signal TST indicates the start of gate leakage current detection; the output signal EN_PD will change from low to high, turning on transistor MN2 and pulling down the drain OUT terminal of power transistor MN1 to ground. This is to ensure that the drain and source of power transistor MN1 are grounded together, preventing changes in the drain voltage of power transistor MN1 from affecting the gate leakage current detection through its gate-drain parasitic capacitance CGD; the output signal TST_LAT will change from low to high, latching the detection result of the leakage threshold detection module.

[0035] Figure 3This is a complete gate leakage current detection circuit. At the start of detection, after the input test signal TST changes from low to high, the inverter I1 outputs TST_N as low, turning on transistor MP3 and pulling up the power transistor MN1's gate PG node to the power supply voltage through resistor R1. Transistor MP4 will detect the voltage drop across resistor R1. The gate leakage current of power transistor MN1 will flow through resistor R1 and generate a voltage difference across it. If the voltage difference in resistor R1 exceeds the conduction threshold voltage of transistor MP4, transistor MP4 will conduct, causing the upper end of resistor R2 to change from low level to high level. After passing through inverters I5 and I6, the output is high level, and the output of inverter I7 is low level. Since the gate leakage test logic module outputs the TST_LAT signal as low level, one input of NOR gate I8 is connected to TST_LAT, and the other input is connected to the output of inverter I7. Therefore, NOR gate I8 outputs a high level. Similarly, NOR gate I9 outputs a high level. After passing through NOR gates I10 and I11, inverter I12 outputs TST_OUT as high level.

[0036] At the end of the test, the gate leakage current test logic module output signal TST_LAT will change from low to high, causing NOR gates I8 and I9 to output low. NOR gates I10 and I11 then form a latch to latch the output signal TST_OUT. Therefore, the gate leakage current pass threshold for power transistor MN1 to have its gate leakage current trigger output signal TST_OUT high is: I_leak=VSG4 / R1 Here, I_leak represents the gate leakage current acceptance threshold of power transistor MN1. VSG4 is the source-gate on-state voltage of transistor MP4, and R1 is the resistance value of resistor R1. It is evident that the larger the resistance value of R1, the smaller the gate leakage current acceptance threshold of the power transistor. This method avoids applying a bias voltage to the PG node of the power transistor MN1 to directly measure its leakage current. Instead, it sets the gate leakage current acceptance threshold through the pull-up resistor R1 of PG and the source-gate on-state voltage VSG4 of transistor MP4, and converts it into the test logic output signal TST_OUT. Therefore, during FT testing, the value of TST_OUT can be directly read to determine whether the gate leakage current of power transistor MN1 exceeds the acceptable threshold point set by I_leak. This avoids the problem that FT testing machines cannot accurately detect nA-level leakage currents due to measurement errors and inaccuracies.

[0037] Figure 4The gate leakage current test logic module uses D flip-flops I13, I14, I15, I16, I17, and I18 cascaded to form a counter structure. NOR gates I20 and I19 form an SR latch. When the input signal TST is low, inverter I27 outputs a high level, causing the R terminal of the D flip-flops to be high, resetting them, and all D flip-flops output a low level at their Q terminals. The Q terminal of D flip-flop I18 is connected to the input of inverter I23. Through inverter I23, inverter I24 outputs the TST_LAT signal, which is low. NOR gate I19 outputs a low level, and NOR gate I20 outputs a high level. The input signal TST is connected to one end of NAND gate I21. Through NAND gate I21, inverter I22 outputs the EN_PD signal, which is low, and inverter I24 outputs the TST_LAT signal, which is low. When the input signal TST goes high, the counter formed by the cascaded D flip-flops I13, I14, I15, I16, I17, and I18 begins counting. Simultaneously, when the input signal TST goes high, the output of NOR gate I20 is high, and the output of NAND gate I21 and inverter I22 changes from low to high. When the count reaches the Q terminal of D flip-flop I18, the output of inverter I26 goes high, and the output of NOR gate I25 and inverter I26 remains high at the input CLK terminal of D flip-flop I13, stopping the count. Conversely, when the output of NOR gate I20 is low, the output of NAND gate I21 and inverter I22 changes the output of EN_PD to low, and the output of inverter I23 and inverter I24 changes the output of TST_LAT to high. The waveforms of key nodes in the gate leakage test logic module can be found in [reference needed]. Figure 5 As shown.

[0038] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any changes made based on the design principles of the present invention, or any non-creative modifications made thereon, shall fall within the scope of protection of the present invention.

Claims

1. A power transistor gate leakage current defect detection device, used to detect the power transistor MN1 under test, characterized in that, include: Test trigger circuit, pre-drive circuit, leakage threshold detection module, gate leakage test logic module and pull-down transistor MN2; The test trigger circuit and the pre-drive circuit are connected in series to the gate of the power transistor MN1, and the power transistor MN1 is controlled for detection and triggering. The test trigger circuit, the leakage threshold detection module, and the gate leakage test logic module are connected to an external test enable signal. The leakage threshold detection module is connected to the gate of the power transistor MN1, performs gate leakage detection on the power transistor MN1, and outputs a corresponding logic output signal. The drain of the pull-down transistor MN2 is connected to the drain of the power transistor MN1, and its source is grounded. The gate leakage test logic module is connected to the gate of the leakage threshold detection module and the gate of the pull-down transistor MN2. When the external test enable signal is high, the output of the power transistor MN1 is pulled down to ground through the pull-down transistor MN2. When the gate leakage test logic module inputs a low level to the gate of the pull-down transistor MN2 and inputs a high level to the leakage threshold detection module, the detection output result of the power transistor MN1 is latched.

2. The power transistor gate leakage current defect detection device according to claim 1, characterized in that, The test trigger circuit includes a NOR gate I2, an inverter I3, and an inverter I4 connected in series; the output of the inverter I4 is connected to the pre-drive circuit; and the NOR gate I2 is externally connected to a test enable signal.

3. The power transistor gate leakage current defect detection device according to claim 2, characterized in that, The transistor includes transistors MP1, MP2, and MN3; the gate of transistor MP2 is externally connected to a test enable signal; the gates of transistors MP1 and MN3 are connected to the output of inverter I4; the drain of transistor MP1 is connected to the source of transistor MP2; the gate of power transistor MN1 is connected to the drain of transistor MP2 and the drain of transistor MN3.

4. A power transistor gate leakage current defect detection device according to claim 1, 2, or 3, characterized in that, The leakage current threshold detection module includes a transistor MP3, a resistor R1, a transistor MP4, a resistor R2, and a latch output module. The gate of the transistor MP3 is externally connected to a test enable signal via an inverter I1. The drain of the transistor MP3 is connected to the gate of the power transistor MN1 via a resistor R1. The gate of the transistor MP4 is connected between the resistor R1 and the gate of the power transistor MN1, and detects the voltage drop across the resistor R1. If the voltage drop across the resistor R1 is greater than or equal to the gate drive threshold of the transistor MP4, a high level is output through the latch output module. The latch output module is connected between the drain of the transistor MP4 and the resistor R2.

5. The power transistor gate leakage current defect detection device according to claim 4, characterized in that, The latch output module includes inverters I5, I6, I7, NOR gate I8, NOR gate I10, and inverter I12 connected in sequence; a NOR gate I9 with one input connected between inverters I6 and I7 and another input connected to NOR gate I8; and a NOR gate I11 with one input connected to the output of NOR gate I9 and another input connected between NOR gate I10 and inverter I12; the output of NOR gate I11 is connected to the input of NOR gate I10; and NOR gates I8 and I9 are connected to the gate leakage test logic module.

6. The power transistor gate leakage current defect detection device according to claim 5, characterized in that, The gate leakage current test logic module includes NOR gate I25, inverter I26, counter, SR latch, NAND gate I21 and inverter I22 connected in sequence, and inverters I23 and I24 connected in series between the counter and the SR latch; the output of inverter I24 is connected between NOR gate I8 and NOR gate I9; the NAND gate I21 is externally connected to a test enable signal.

7. The power transistor gate leakage current defect detection device according to claim 6, characterized in that, The counter includes D flip-flops I13, I14, I15, I16, I17, and I18 connected in sequence.

8. The power transistor gate leakage current defect detection device according to claim 7, characterized in that, The SR latch includes a NOR gate I20 and a NOR gate I19; one input of the NOR gate I19 is connected to an external test enable signal via an inverter I27, and the other input is connected between the NOR gate I20 and the NAND gate I21.

9. A detection method using the power transistor gate leakage current defect detection device according to any one of claims 1 to 8, characterized in that, Includes the following steps: When an external test enable signal is input at a high level, the gate of the power transistor MN1 under test is triggered to a high-impedance state by the test trigger circuit and the pre-drive circuit. When the test enable signal is at a high level, the drain output of the power transistor MN1 is pulled down to ground through the pull-down transistor MN2. The leakage current threshold detection module is used to detect the gate leakage current of the power transistor MN1 under test and outputs the corresponding logic output signal. When the gate leakage test logic module pulls down the gate input of transistor MN2 to a low level and inputs a high level to the leakage threshold detection module, the detection output result of power transistor MN1 is latched.

10. The detection method according to claim 9, characterized in that, The leakage threshold detection module is used to detect the gate leakage of the power transistor MN1 under test and output the corresponding logic output signal, including: using the transistor MP4 to detect the voltage drop across the resistor R1; if the voltage drop across the resistor R1 is greater than or equal to the gate drive threshold of the transistor MP4, a high level is output through the latch output module.

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