A chip testing device, a chip testing system and a chip testing method
Patent Information
- Application Number
- CN202611208216.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-10
- Publication Date
- 2026-10-27
AI Technical Summary
[0014]本申请提供的芯片测试装置、芯片测试系统和芯片测试方法，通过在测试载板布设与待测芯片引脚阵列对应的过孔阵列并划分测试分区，进而利用测试载板顶底两面的电路走线分别按列、按行对奇偶序号过孔分组互连，以在每个测试分区形成相互独立的四路测试通道，同时各过孔与周围过孔之间保持电气绝缘，进一步的，由顶针实现过孔与待测芯片引脚的可靠电连接，再由单片机依次向各测试通道输入测试信号并同步监测其余测试通道的信号，这样，能够依托测试通道间的信号串扰检测逻辑，快速识别待测芯片引脚间的焊接桥连现象，无需额外复杂检测设备，可快速、精准定位待测芯片的焊接桥连情况。
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Figure CN122983641A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip testing technology, and in particular to a chip testing device, a chip testing system, and a chip testing method. Background Technology
[0002] With the rapid iteration of integrated circuit technology and surface mount technology, printed circuit board (PCB) manufacturing processes are evolving towards miniaturization and thinning. Traditional in-circuit testers are no longer adequate for the testing needs of all types of electronic products. For example, unlike traditional pin-based packaging structures, the solder joints of Ball Grid Array (BGA) chips are all located on the bottom of the chip, relying on an array of solder balls to achieve electrical interconnection with the printed circuit board (PCB). In this packaging structure, the solder balls are hidden on the bottom of the chip and are opaque, making it impossible to directly observe the soldering quality with the naked eye, which easily leads to solder bridging and other soldering defects.
[0003] In recent years, BGA chips have primarily relied on manual observation using optical magnifying glasses and industrial microscopes, combined with two-dimensional X-ray inspection to check the solder joint condition, and power-on testing to determine faults. However, BGA chips typically have hundreds of solder joints, making the above inspection methods insufficient to meet the practical application requirements of rapid quality inspection and efficient repair. Summary of the Invention
[0004] In view of this, this application provides a chip testing apparatus, a chip testing system, and a chip testing method to quickly and accurately identify solder bridging problems in the chip under test.
[0005] The first aspect of this application provides a chip testing apparatus, which includes a test carrier board and a microcontroller; wherein...
[0006] The test substrate is provided with a via array corresponding to the pin array of the chip under test; the via array forms at least one test partition; wherein, within each test partition, the odd-numbered vias in each column are electrically connected through circuit traces on a first surface of the test substrate, the even-numbered vias in each column are electrically connected through circuit traces on the first surface, the odd-numbered vias in each row are electrically connected through circuit traces on a second surface of the test substrate, and the even-numbered vias in each row are connected through circuit traces on the second surface, so as to form four independent test channels in the test partition; within each test partition, each via is insulated from other vias around it;
[0007] The first surface has a pin at the position corresponding to each via for electrically connecting each via to the corresponding pin of the chip under test;
[0008] The microcontroller is used to sequentially provide test signals to each of the four test channels in each test partition, and to detect the signals of the remaining test channels while providing test signals to the current test channel, so as to obtain the detection results;
[0009] The microcontroller is also used to determine whether the chip under test is abnormal based on the detection results.
[0010] The second aspect of this application provides a chip testing system, which includes a chip under test and a chip testing device as described in any one of the first aspects of this application.
[0011] A third aspect of this application provides a chip testing method, wherein the chip testing method is applied to a microcontroller in any of the chip testing devices provided in the first aspect of this application; the chip testing method includes:
[0012] Test signals are sequentially provided to each of the four test channels in each test partition, and while providing test signals to the current test channel, the signals of the other test channels are detected to obtain the detection results;
[0013] The test results will determine whether the chip under test is abnormal.
[0014] The chip testing apparatus, chip testing system, and chip testing method provided in this application utilize a via array corresponding to the pin array of the chip under test (DUT) on a test carrier board and divide it into test zones. Then, the circuit traces on the top and bottom sides of the test carrier board are used to interconnect the odd and even numbered vias by column and row, forming four independent test channels in each test zone. Simultaneously, each via maintains electrical insulation from surrounding vias. Furthermore, a pin ensures reliable electrical connection between the vias and the pins of the DUT. A microcontroller sequentially inputs test signals to each test channel and simultaneously monitors the signals of the remaining test channels. This allows for rapid identification of solder bridging phenomena between the pins of the DUT based on signal crosstalk detection logic between test channels, eliminating the need for additional complex testing equipment and enabling rapid and accurate location of solder bridging conditions in the DUT.
[0015] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description
[0016] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0017] Figure 1 This is a schematic diagram illustrating BGA chip solder bridging as an exemplary embodiment of this application;
[0018] Figure 2 This is a schematic diagram of a chip testing apparatus shown in an exemplary embodiment of this application;
[0019] Figure 3 This diagram illustrates the interaction between a chip testing apparatus and a chip under test, as shown in an exemplary embodiment of this application.
[0020] Figure 4 This is a schematic diagram illustrating the implementation principle of the electrical connection of the test carrier board in a chip testing apparatus according to an exemplary embodiment of this application;
[0021] Figure 5 A schematic diagram illustrating the implementation principle of electrical connections of a test carrier board in a chip testing apparatus, as shown in another exemplary embodiment of this application;
[0022] Figure 6 for Figure 5 A schematic diagram of the test channel formed by the chip testing device shown;
[0023] Figure 7 for Figure 5 A schematic diagram of the signals transmitted through each via in the chip testing device shown.
[0024] Figure 8 This is a flowchart illustrating a chip testing method as an exemplary embodiment of this application.
[0025] Explanation of reference numerals in the attached figures:
[0026] 1: Test carrier board;
[0027] 11: Via array;
[0028] 111: Test partition;
[0029] 12: First surface;
[0030] 13: Second surface;
[0031] 14: Threshold;
[0032] 2: Microcontroller. Detailed Implementation
[0033] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.
[0034] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.
[0035] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."
[0036] Figure 1 This is a schematic diagram illustrating BGA chip solder bridging as shown in an exemplary embodiment of this application. Please refer to... Figure 1 Solder bridging occurs when multiple solder balls that were originally insulated from each other become conductive due to excessive solder melting and uneven reflow, forming a low-impedance abnormal path. It is a common type of failure in BGA chip assembly processes.
[0037] The chip testing apparatus, chip testing system, and chip testing method provided in this application are used to quickly and accurately identify solder bridging phenomena in the chip under test.
[0038] The following specific embodiments are given to illustrate the technical solution of this application in detail.
[0039] Figure 2 This is a schematic diagram of a chip testing apparatus shown in an exemplary embodiment of this application. Figure 3 This is a diagram illustrating the mating relationship between a chip testing apparatus and a chip under test, as shown in an exemplary embodiment of this application. Figure 4 This is a schematic diagram illustrating the implementation principle of the electrical connection of the test carrier board in a chip testing apparatus, as shown in an exemplary embodiment of this application. Figure 5 This is a schematic diagram illustrating the implementation of the electrical connections of a test substrate in a chip testing apparatus, as shown in another exemplary embodiment of this application. Please also refer to... Figures 2 to 5 The chip testing apparatus provided in this embodiment includes a test carrier board 1 and a microcontroller 2; wherein,
[0040] The test substrate 1 is provided with a via array 11 corresponding to the pin array of the chip under test; the via array 11 forms at least one test partition 111; wherein, in each test partition 111, the odd-numbered vias in each column are electrically connected through circuit traces provided on the first surface 12 of the test substrate 1, the even-numbered vias in each column are electrically connected through circuit traces provided on the first surface 12, the odd-numbered vias in each row are electrically connected through circuit traces provided on the second surface 13 of the test substrate, and the even-numbered vias in each row are connected through circuit traces provided on the second surface 13, so as to form four independent test channels in the test partition 111; in each test partition 111, each via is insulated from other vias around it;
[0041] The first surface 12 is provided with a pin 14 at the position of each via for electrically connecting each via to the corresponding pin of the chip under test;
[0042] The microcontroller 2 is used to sequentially provide test signals to each of the four test channels in each of the test partitions 111, and to detect the signals of the remaining test channels during the process of providing test signals to each test channel, so as to obtain the detection results.
[0043] The microcontroller 2 is also used to determine whether the chip under test is abnormal based on the detection results.
[0044] For details, please refer to Figure 3 The chip under test includes a BGA chip and a PCB board; the PGB is provided with an array of vias;
[0045] The BGA chip has a solder ball array corresponding to the via array; each via in the via array is electrically connected to the corresponding solder ball in the solder ball array, forming the pins of the chip under test.
[0046] It's understandable that BGA chips refer to Ball Grid Array packaged chips, where the entire bottom surface of the chip is covered with rows and columns of spherical solder balls. (See reference...) Figure 3 This means that the BGA chip has a solder ball array. Furthermore, the PCB board has a via array, and the positions of the via array and the solder ball array on the BGA chip correspond. Finally, the solder balls are aligned with the vias and soldered together to form the pins of the chip under test.
[0047] Please continue to refer to Figure 2The test substrate 1 has a first surface 12 (top layer) and a second surface 13 (bottom layer), which are two opposing surfaces. Furthermore, the test substrate 1 is provided with a via array 11, which matches the pin array of the chip under test (DUT). For example, if the pin array of the DUT is a row A, column B pin array, the via array 11 is also a row A, column B via array, comprising A×B vias. A via refers to a small metal hole perpendicularly drilled through the test substrate 1, used to connect the circuit traces on the first surface 12 and the circuit traces on the second surface 13 of the test substrate 1, so that electrical signals can be transmitted from the first surface 12 to the second surface 13 of the test substrate 1.
[0048] Optionally, in one possible implementation, the thickness of the test substrate 1 along the direction perpendicular to the first surface is 0.5 mm to 3 mm. In practice, the thickness of the test substrate 1 is set according to actual needs, and is not limited in this application.
[0049] Please continue to refer to Figure 4 and Figure 5 The via array 11 forms at least one test partition 111. Specifically, each test partition 111 consists of M rows and N columns of vias; wherein M is greater than or equal to 3 and N is greater than or equal to 3.
[0050] For example, see Figure 4 ,exist Figure 4 In the example shown, the via array 11 can form four test partitions, each of which is a 3×3 array; for another example, see Figure 5 In another possible implementation, the via array 11 can form a test partition. Of course, each test partition can also be a 4×4 array, a 3×5 array, etc., and this embodiment does not limit it.
[0051] For further details, please refer to [link / reference]. Figure 4 For example, in one possible implementation, the pin array of the chip under test includes 6 rows and 6 columns of pins. Correspondingly, the test carrier board 1 is provided with a via array 11 consisting of 6 rows and 6 columns of pins. The via array 11 forms four test partitions, each test partition consisting of 3×3 vias.
[0052] Further, see Figure 5 ,exist Figure 5 In the example shown, in one possible implementation, the pin array of the chip under test includes 5 rows and 5 columns of pins. Correspondingly, the test carrier board 1 is provided with a via array 11 consisting of 5 rows and 5 columns of pins, which forms a test partition.
[0053] Please refer to the following at the same time Figure 4and Figure 5 It should be noted that the green circuit traces in the figure are circuit traces set on the first surface 12 (top layer) of the test carrier board 1, the red circuit traces are circuit traces set on the second surface 13 (bottom layer) of the test carrier board 1, and the yellow circles represent vias that connect the circuit traces on the first surface 12 and the circuit traces on the second surface 13.
[0054] Within each test partition 111, in the column direction, odd-numbered vias in each column are electrically connected via circuit traces on the first surface of the test substrate, and even-numbered vias in each column are electrically connected via circuit traces on the first surface. Furthermore, in the row direction, odd-numbered vias in each row are electrically connected via circuit traces on the second surface of the test substrate, and even-numbered vias in each row are connected via circuit traces on the second surface. This allows for the formation of four independent test channels within the test partition 111.
[0055] Specifically, for example, when the via array has m rows and n columns, each column of vias is numbered according to the column direction, and the specific numbers can be H1, H2, H3, H4, H5, ..., Hm; furthermore, each row of vias is numbered according to the row direction, and the specific numbers can be L1, L2, L3, L4, L5, ..., Ln.
[0056] Within each test partition 111, electrical connections in the column direction are implemented on the first surface 12. Specifically, in the column direction, odd-numbered vias in each column are electrically connected via circuit traces provided on the first surface 12 of the test carrier board 1, and even-numbered vias in each column are electrically connected via circuit traces provided on the first surface 12. See also Figure 4 For example, for the first test partition in the upper left corner, H1 and H3 are routed on the first surface 12 via circuit traces set on the first surface 12 (specifically... Figure 4 (The green circuit trace shown is an electrical connection.) Furthermore, in this test partition, each column has only one even-numbered via on the first surface 12, which is not electrically connected to other vias. It can be understood that when each column contains multiple even-numbered vias, on the first surface 12, the multiple even-numbered vias are connected by a single circuit trace.
[0057] For example, see Figure 5 On the first surface 12, H1, H3, and H5 are electrically connected through a circuit trace (specifically...) Figure 5 (The green circuit trace shown) H2 and H4 are electrically connected through another circuit trace (specifically...) Figure 5 The green circuit traces are shown.
[0058] Furthermore, on the second surface 13, in the row direction, the odd-numbered vias in each row are electrically connected via circuit traces disposed on the second surface 13 of the test carrier board 1. See also Figure 4 For example, in Figure 4 In the example shown, for the first test partition in the upper left corner, L1 and L3 are connected to circuit traces on the second surface 13 (specifically...). Figure 4 (The red circuit traces shown are for electrical connections.) Furthermore, in this test zone, each row contains only one even-numbered via, which is not electrically connected to other vias on the second surface 13. It should be noted that when each row contains multiple even-numbered vias, these vias are connected by a single circuit trace on the second surface 13.
[0059] See Figure 5 On the second surface 13, L1, L3, and L5 are electrically connected through a circuit trace (specifically...) Figure 5 (As shown in red, the circuit traces) L2 and L4 are electrically connected through another circuit trace (specifically...) Figure 5 The green circuit traces are shown.
[0060] Please continue to refer to Figure 4 and Figure 5 Through the aforementioned electrical connections, four independent test channels can be formed in each test zone 111. For example, in Figure 4 In the example shown, in the first test partition 111 in the upper left corner, the first via in the first column, the third via in the first column, the first via in the third column, and the third via in the third column form the first test channel; the second via in the first column and the second via in the third column form the second test channel; the first via in the second column and the third via in the second column form the third test channel; and the second via in the second column forms the fourth test channel.
[0061] Furthermore, Figure 6 for Figure 5 A schematic diagram of the test channel formed by the chip testing device shown; Figure 7 for Figure 5 The diagram shows the signal transmission through each via in the chip testing setup. Please also refer to... Figure 5 , Figure 6 and Figure 7 ,exist Figure 5 In the example shown, the first via in the first column, the third via in the first column, the fifth via in the first column, the first via in the third column, the third via in the third column, the fifth via in the third column, and the first via in the fifth column, the third via in the fifth column, and the fifth via in the fifth column are electrically connected to form... Figure 6 The first test channel shown ( Figure 6 The pink circuit trace in the image shows test channel A. Further, as... Figure 7 As shown, these vias transmit the same signal during signal transmission.
[0062] Similarly, the second via in the first column, the fourth via in the first column, the second via in the third column, the fourth via in the third column, and the second via in the fifth column and the fourth via in the fifth column are electrically connected to form... Figure 6 The second test channel shown ( Figure 6 The yellow circuit trace in the image indicates the B test channel. Further, as... Figure 7 As shown, these vias transmit the same signal during signal transmission.
[0063] Similarly, the first via in the second column, the third via in the second column, the fifth via in the second column, and the first via in the fourth column, the third via in the fourth column, and the fifth via in the fourth column are electrically connected to form... Figure 6 The third test channel shown ( Figure 6 The blue circuit trace in the image shows the C test channel. Further, as... Figure 7 As shown, these vias transmit the same signal during signal transmission.
[0064] Similarly, the second via in the second column, the fourth via in the second column, and the second via in the fourth column and the fourth via in the fourth column are electrically connected to form... Figure 6 The fourth test channel shown ( Figure 6 The gray circuit traces in the diagram show the D test channel. Further, as... Figure 7 As shown, these vias transmit the same signal during signal transmission.
[0065] See Figure 4 and Figure 5 It is understood that the four independent test channels include a first test channel formed by electrically connecting odd-numbered vias in each column and odd-numbered vias in each row (e.g., Figure 6 The A test channel is formed by electrically connecting the even-numbered vias in each column and the odd-numbered vias in each row (e.g., the A test channel). Figure 6 The B test channel in the middle), and the third test channel formed by electrically connecting the odd-numbered vias in each column and the even-numbered vias in each row (such as the B test channel in the middle), are all part of the test channel. Figure 6 The C test channel), and a fourth test channel formed by the electrical connection of even-numbered vias in each column and even-numbered vias in each row (e.g., the C test channel), and the C test channel formed by the electrical connection of even-numbered vias in each column and even-numbered vias in each row. Figure 6 (D test channel in the middle).
[0066] Please refer to the following at the same time Figure 4 and Figure 5 It is understandable that, through the above-mentioned wiring connections, each via is insulated from other vias around it within each test zone, and electrical connection only occurs when solder bridging occurs.
[0067] For further details, please refer to [link / reference]. Figure 2 It is understood that the first surface 12 is provided with pads, and pins 14 are soldered onto the pads. Specifically, a pin 14 is provided at the position of each via for electrically connecting each via to the corresponding pin of the chip under test.
[0068] Optionally, in one possible implementation, the pin 14 is a flexible probe used to form a detachable electrical connection with the pins of the chip under test.
[0069] Specifically, a flexible probe is used as a pin, which adheres to the pins of the chip under test by elastic pressure, and can be repeatedly assembled and disassembled. For details on the specific structure of the flexible pin, please refer to the descriptions in related technologies; they will not be repeated here.
[0070] Furthermore, during the actual testing process, the microcontroller 2 sequentially provides test signals to each of the four test channels in each test partition, and while providing test signals to each test channel, it detects the signals of the remaining test channels to obtain the detection results, and determines whether the chip under test has any abnormalities based on the detection results.
[0071] Specifically, in one possible implementation, the microcontroller 2 is used to sequentially provide a high-level test signal to each of the four test channels in each test partition, and while providing a high-level test signal to the current test channel, monitor whether there is a high-level detection signal in the other test channels;
[0072] The microcontroller 2 is also used to determine that the chip under test is abnormal when a high-level detection signal is present in the target test channel among the other test channels.
[0073] In practice, to shorten the testing time, Figure 5 In the example shown, the microcontroller first provides a high-level test signal to test channel A, and then checks whether there are high-level detection signals in test channels B, C, and D. If a high-level detection signal is detected in at least one of the test channels B, C, and D, it is determined that the chip under test is abnormal.
[0074] Furthermore, a high-level test signal is continuously provided to test channel B to detect whether there is a high-level detection signal in test channels C and D. If at least one of test channels C and D detects a high-level detection signal, it is determined that the chip under test has an abnormality.
[0075] Furthermore, a high-level test signal is continuously provided to the C test channel to detect whether a high-level detection signal exists in the D test channel. If a high-level detection signal is detected in the D test channel, it is determined that the chip under test has an abnormality.
[0076] Referring to the preceding description, it should be noted that if a high-level test signal is provided to test channel A, and no high-level detection signal is detected in any of the test channels B, C, and D; and if a high-level test signal is provided to test channel B, and no high-level detection signal is detected in any of the test channels C and D; and if a high-level test signal is provided to test channel C, and no high-level detection signal is detected in test channel D, then the chip under test is determined to be normal.
[0077] It should be noted that, in practice, an oscilloscope or multimeter is also used to display the test results. When only one test zone is included, a maximum of 5 rounds of testing are required to complete the testing process, which can quickly detect solder bridging.
[0078] The chip testing device provided in this embodiment lays out an array of vias corresponding to the pin array of the chip under test on a test carrier board and divides it into test zones. Then, the circuit traces on the top and bottom sides of the test carrier board are used to interconnect the odd and even numbered vias by column and row, so as to form four independent test channels in each test zone. At the same time, each via is electrically isolated from the surrounding vias. Furthermore, a pin is used to achieve a reliable electrical connection between the vias and the pins of the chip under test. Then, a microcontroller sequentially inputs test signals to each test channel and simultaneously monitors the signals of the other test channels. In this way, the solder bridging phenomenon between the pins of the chip under test can be quickly identified by relying on the signal crosstalk detection logic between the test channels. No additional complex testing equipment is required, and the solder bridging situation of the chip under test can be quickly and accurately located.
[0079] Optionally, in one possible implementation, the microcontroller 2 is specifically used to determine, when a high-level detection signal exists in the target test channel among the other test channels, that there is a solder bridge between the pin of the chip under test corresponding to the current test channel and the pin of the chip under test corresponding to the target test channel.
[0080] Specifically, for example, in Figure 5In the example shown, when a high-level test signal is provided to the C test channel, if a high-level detection signal is detected in the D test channel, it is determined that the chip under test is abnormal, and it is determined that there is a solder bridging between the pins of the chip under test corresponding to the C test channel and the pins of the chip under test corresponding to the D test channel.
[0081] For example, in Figure 4 In the example shown, it is possible not only to determine whether there is an anomaly in the chip under test, but also to determine which test partition the anomaly occurred in by dividing the test partitions and testing each test partition one by one. Furthermore, it is possible to further determine which two channels in the test partition the anomaly occurred in, so as to accurately locate the location of the anomaly.
[0082] The chip testing device provided in this embodiment monitors the signals of each test channel in real time using a microcontroller. When a high-level test signal is input to the current test channel and a high-level detection signal is simultaneously detected in the other target test channels, it can accurately determine whether there is a solder bridging short circuit between the pins of the corresponding two channels of the chip under test. At the same time, by dividing the via array into sections and testing each section sequentially, it can not only quickly identify whether there is an abnormality in the chip under test, but also narrow down the fault range section by section, accurately locate the test section to which the abnormality belongs and the specific location of the bridging, effectively identify the location of the solder bridging, greatly improve the fault detection efficiency and accuracy, and reduce manual detection errors and troubleshooting costs.
[0083] Corresponding to the aforementioned embodiment of a chip testing device, this application also provides a chip testing system and a chip testing method, which are described below.
[0084] For details, please continue to refer to... Figure 3 This application also provides a chip testing system, which includes a chip under test and a chip testing device as described in any of the first aspects of this application.
[0085] Specifically, the chip under test includes a BGA chip and a PCB board; the PGB is provided with an array of vias;
[0086] The BGA chip has a solder ball array corresponding to the via array; each via in the via array is electrically connected to the corresponding solder ball in the solder ball array, forming the pins of the chip under test.
[0087] Figure 8 A flowchart illustrating a chip testing method as shown in an exemplary embodiment of this application is provided below. Figure 8The chip testing method provided in this application is applied to the microcontroller in any of the chip testing devices described in the first aspect of this application, and the chip testing method includes:
[0088] S801. Test signals are sequentially provided to each of the four test channels in each test partition, and while providing test signals to the current test channel, the signals of the other test channels are detected to obtain the detection results.
[0089] S802. Determine whether the chip under test is abnormal based on the test results.
[0090] For details on the specific implementation principles and processes of S801 and S802, please refer to the descriptions in the previous embodiments, which will not be repeated here.
[0091] The chip testing method provided in this embodiment can quickly and accurately test whether solder bridging exists in the chip.
[0092] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A chip testing device, characterized in that, The chip testing device includes a test carrier board and a microcontroller; wherein... The test substrate is provided with a via array corresponding to the pin array of the chip under test; the via array forms at least one test partition; wherein, within each test partition, the odd-numbered vias in each column are electrically connected through circuit traces on a first surface of the test substrate, the even-numbered vias in each column are electrically connected through circuit traces on the first surface, the odd-numbered vias in each row are electrically connected through circuit traces on a second surface of the test substrate, and the even-numbered vias in each row are connected through circuit traces on the second surface, so as to form four independent test channels in the test partition; within each test partition, each via is insulated from other vias around it; The first surface has a pin at the position corresponding to each via for electrically connecting each via to the corresponding pin of the chip under test; The microcontroller is used to sequentially provide test signals to each of the four test channels in each test partition, and to detect the signals of the remaining test channels while providing test signals to the current test channel, so as to obtain the detection results; The microcontroller is also used to determine whether the chip under test is abnormal based on the detection results.
2. The chip testing apparatus according to claim 1, characterized in that, The microcontroller is specifically used to sequentially provide a high-level test signal to each of the four test channels in each test partition, and while providing a high-level test signal to the current test channel, monitor whether there is a high-level detection signal in the other test channels; The microcontroller is also used to determine that the chip under test is abnormal when a high-level detection signal is present in the target test channel among the other test channels.
3. The chip testing apparatus according to claim 2, characterized in that, Specifically, the microcontroller is used to determine, when a high-level detection signal exists in the target test channel among the other test channels, that there is a solder bridge between the pin of the chip under test corresponding to the current test channel and the pin of the chip under test corresponding to the target test channel.
4. The chip testing apparatus according to claim 1, characterized in that, The pin is a flexible probe used to form a detachable electrical connection with the pins of the chip under test.
5. The chip testing apparatus according to claim 1, characterized in that, Each test partition consists of M rows and N columns of vias; wherein M is greater than or equal to 3 and N is greater than or equal to 3.
6. The chip testing apparatus according to claim 1, characterized in that, The four test channels include a first test channel formed by electrically connecting odd-numbered vias in each column and odd-numbered vias in each row; a second test channel formed by electrically connecting even-numbered vias in each column and odd-numbered vias in each row; a third test channel formed by electrically connecting odd-numbered vias in each column and even-numbered vias in each row; and a fourth test channel formed by electrically connecting even-numbered vias in each column and even-numbered vias in each row.
7. The chip testing apparatus according to claim 1, characterized in that, The thickness of the test substrate along the direction perpendicular to the first surface is 0.5 mm to 3 mm.
8. A chip testing system, characterized in that, The chip testing system includes the chip under test and the chip testing apparatus according to any one of claims 1 to 7.
9. The chip testing system according to claim 8, characterized in that, The chip under test includes a BGA chip and a PCB board; the PCB board is provided with an array of vias. The BGA chip has a solder ball array corresponding to the via array; each via in the via array is electrically connected to the corresponding solder ball in the solder ball array, forming the pins of the chip under test.
10. A chip testing method, characterized in that, The chip testing method is applied to the microcontroller in the chip testing apparatus according to any one of claims 1 to 7; the chip testing method includes: Test signals are sequentially provided to each of the four test channels in each test partition, and while providing test signals to the current test channel, the signals of the other test channels are detected to obtain the detection results; The test results will determine whether the chip under test is abnormal.