A chip test optimization method and system based on sampling pre-checking

Abstract

The application relates to the chip testing technical field, in particular to a chip testing optimization method and system based on sampling pre-inspection, which comprises the following steps: stratified sampling is performed on chips to be tested to obtain a pre-inspection chip set; initial test items are executed on the pre-inspection chip set, and failure correlation rules between the initial test items are determined according to test results; based on the failure correlation rules, a test item pair with a one-way failure accompanying relationship is extracted from the initial test items; and according to the test item pair, a full-amount test optimization scheme of the chips to be tested is generated. The application can obviously reduce test process repetition, reduce test machine time consumption, and thus improve the throughput of large-scale mass production testing. Compared with the rigid execution of all test items in the prior art, the application can efficiently complete chip testing, and realizes the optimized allocation of test resources under the premise of ensuring product quality.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, specifically to a chip testing optimization method and system based on sampling pre-inspection. Background Technology

[0002] In the mass production of semiconductor chips, batch testing is a core process for controlling factory quality and screening out defective products. With the rapid increase in chip integration, the number of test items for a single chip can easily reach hundreds, and the machine time consumption at the testing end has become a key bottleneck restricting the economic benefits of mass production.

[0003] Currently, mainstream batch testing in the industry generally adopts fixed and standardized test templates. This means that a fixed full-scale test program is preset for chips of the same model, and all benchmark tests are executed sequentially and without differentiation for all chips within the batch. However, in actual mass production scenarios, due to factors such as equipment status fluctuations and process drift in specific batches, the failure modes of chips in the same batch are usually not absolutely random, but rather exhibit strong batch clustering and fault linkage characteristics. For example, the failure of a certain underlying electrical parameter often inevitably leads to the failure of specific functional modules in a physical sense.

[0004] Based on this, the existing fixed testing mode has the following technical defects: On the one hand, the existing technology fails to deeply explore and utilize the sampling data in the early stage of testing. Conventional sampling is only used for batch yield qualification, and the common fault characteristics contained in the data are wasted. On the other hand, the existing test scheme lacks a coordination mechanism based on physical failure logic in the generation and scheduling stage, which makes each test item in the test program in a rigid and isolated execution state. This may directly lead to the test end mechanically applying stimuli and executing meaningless derivative related tests when facing pre-faults with strong causal relationships. This not only causes a large amount of redundant test steps and consumes test resources and machine time, but also seriously limits the improvement of large-scale mass production test throughput. Summary of the Invention

[0005] In view of the aforementioned problems, this application is proposed to provide a chip testing optimization method and system based on sampling pre-inspection to overcome or at least partially solve the aforementioned problems, comprising: The above-mentioned objective of this application is achieved through the following technical solution: A chip testing optimization method based on sampling pre-inspection includes the following steps: The chips to be tested are sampled in layers to obtain a pre-test chip set; Initial test items are performed on the pre-test chip set, and failure association rules between the initial test items are determined based on the test results; Based on the failure association rules, test item pairs with a one-way failure association relationship are extracted from the initial test items; Based on the test items, a full-scale test optimization scheme for the chip under test is generated.

[0006] The second objective of this invention is achieved through the following technical solution: A chip testing optimization system based on sampling pre-inspection includes: The stratified sampling module is used to perform stratified sampling of the chips to be tested to obtain a pre-inspection chip set. The rule determination module is used to perform initial test items on the pre-inspection chip set and determine the failure association rules between the initial test items based on the test results; The association determination module is used to extract test item pairs with a one-way failure association relationship from the initial test items based on the failure association rules. The test generation module is used to generate a full-scale test optimization scheme for the chip under test based on the test item pairs.

[0007] This application has the following advantages: In the embodiments of this application, addressing the technical shortcomings of existing technologies where chip batch testing commonly employs fixed, linear, and standardized test templates, resulting in the lack of in-depth mining of latent defect data during the sampling phase and isolated, rigid test scheduling, leading to massive time waste and limited throughput during physical machine execution, this application provides a chip testing optimization method based on sampling pre-inspection, comprising the steps of: performing stratified sampling of the chips to be tested to obtain a pre-inspection chip set; executing initial test items on the pre-inspection chip set, and determining failure association rules between the initial test items based on the test results; extracting test item pairs with unidirectional failure association relationships from the initial test items based on the failure association rules; and generating a full-scale test optimization scheme for the chips to be tested based on the test item pairs. By introducing a stratified sampling pre-inspection mechanism in the early stages of batch testing and dynamically mining failure correlation rules between initial test items based on the pre-inspection data, the problem of conventional sampling in existing technologies being used only for simple batch yield interception, resulting in the complete waste of the common characteristics and spatial clustering characteristics of physical defects hidden in early data, can be solved. This achieves the technical effect of transforming static and rigid yield judgment into data-driven dynamic rule mining, thereby providing underlying physical logic support for the topology reconstruction of subsequent test flows. By extracting test item pairs with unidirectional failure association relationships based on failure correlation rules, the problem of existing technologies often remaining at the level of bidirectional symmetric pure mathematical statistics in the analysis of test item correlations, ignoring the strict precondition causal physical hierarchy of defect propagation inside semiconductor devices, such as front-end power supply short circuit inevitably leading to back-end logic failure, but the converse is not true, thus failing to safely guide test scheduling, can be solved. This achieves the technical effect of extracting test nodes with real physical causal dependencies from massive amounts of data and providing test equipment with high-confidence "interception / detour" intervention anchor points. Based on this, this full-scale test optimization scheme breaks the traditional mechanical sequential test logic at the underlying compiler scheduling level. When the test end loads this optimization scheme, it has the ability to directly block and avoid downstream derivative test steps when upstream core failures are triggered. This reduces the invalid machine time consumption of a single chip and the entire batch without reducing the actual physical test coverage and factory quality. By deeply integrating the sampling pre-inspection mechanism with the scheme generation method based on unidirectional physical failure logic, the full-scale test optimization scheme generated for the same chip model can adapt to the specific dynamic failure modes exhibited by different mass production batches due to wafer fab process drift or wear of physical probes on test equipment. This solves the technical defect that the existing rigid test scheduling cannot flexibly cope with the complex and ever-changing physical defect evolution trend in the mass production environment. It achieves the technical effect of maximizing the optimization of test instrument resource allocation, reducing the depreciation cost of reactive switching of physical hardware such as high-frequency relays, and ultimately breaking the bottleneck of mass production economic benefits and substantially improving the throughput of large-scale chip mass production testing. Attached Figure Description

[0008] To more clearly illustrate the technical solution of this application, the drawings used in the description of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0009] Figure 1 This is a flowchart illustrating the steps of a chip testing optimization method based on sampling pre-inspection, provided in one embodiment of this application. Figure 2 This is a structural block diagram of a chip testing optimization system based on sampling pre-inspection provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structural block of a computer electronic device provided in an embodiment of the present invention.

[0010] 1. Computer electronic device; 2. External device; 3. Processing unit; 4. Bus; 5. Network adapter; 6. I / O interface; 7. Display; 8. Memory; 9. Random access memory; 10. Cache memory; 11. Storage system; 12. Program / utility; 13. Program module. Detailed Implementation

[0011] To make the objectives, features, and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0012] The inventors, through analysis of existing technologies, discovered that in traditional semiconductor chip mass production testing, testing methods typically employ fixed, standardized test templates, performing full-scale testing procedures indiscriminately on chips of the same model. Initial sampling data is used only for batch yield assessment, not for uncovering failure correlation rules, leading to the neglect of physical failure logic relationships between test items. Furthermore, failure modes within the same batch of chips are affected by equipment status fluctuations and process drift, exhibiting batch clustering and fault linkage characteristics; that is, failure of specific underlying electrical parameters inevitably triggers cascading failures of related functional modules. However, existing testing procedures typically execute each test item in isolation, lacking a coordinated mechanism based on failure logic. This results in the testing system mechanically executing subsequent related test items even after a failure is detected in a preceding test item, causing redundancy in testing steps, inefficient use of testing resources and time, and limiting test throughput.

[0013] Reference Figure 1 This illustration shows a chip testing optimization method based on sampling pre-inspection according to an embodiment of this application, including the following steps: S110. Perform stratified sampling of the chips to be tested to obtain a pre-inspection chip set; S120. Perform initial test items on the pre-test chip set, and determine the failure association rules between the initial test items based on the test results; S130. Based on the failure association rules, extract test item pairs with unidirectional failure association relationships from the initial test items; S140. Based on the test item pair, generate a full-scale test optimization scheme for the chip under test.

[0014] First, some nouns or terms that appear in the description of this embodiment shall be interpreted as follows: Chips under test: These are integrated circuit products that require verification of various indicators such as functionality, performance, and reliability during the semiconductor manufacturing process. They are usually produced and tested in batches.

[0015] Stratified sampling is a statistical sampling method that divides the population into several non-overlapping subgroups and then draws samples independently from each subgroup, aiming to ensure that the samples can represent different characteristics or regions of the population.

[0016] Pre-test chip set: This refers to a sample of chips extracted from the chips to be tested through stratified sampling. This pre-test chip set is used for preliminary targeted testing before full-scale testing to identify common batch issues and establish failure modes.

[0017] Initial test items: These are the basic test items performed on the pre-test chip set. They typically cover the chip's key functions and parameters, and the test results are used to analyze the chip's failure modes and correlations.

[0018] Failure association rules: These rules analyze the test results of initial test items to reveal the interdependencies or causal relationships between failure modes of different test items. For example, the failure of one test item may lead to the failure of another test item.

[0019] Unidirectional failure association: This refers to a specific failure association rule where the failure of one test item necessarily or highly likely to cause the failure of another specific test item, but the converse is not necessarily true. This relationship indicates a clear causal or strong correlation between the test items.

[0020] Test item pair: refers to a combination of two test items that have a one-way failure relationship. It usually includes a prerequisite test item and an associated test item, where the failure of the prerequisite test item will be accompanied by the failure of the associated test item.

[0021] Full-scale test optimization solution: refers to a solution that adjusts and optimizes the traditional full-scale test procedure based on the pre-inspection results and failure association rules for the batch of chips to be tested. It aims to reduce duplicate testing, improve testing efficiency, and at the same time ensure test coverage and product quality.

[0022] In the embodiments of this application, stratified sampling of the chips to be tested is performed to obtain a pre-test chip set. This aims to select samples representative of the overall characteristics from a large number of chips to be tested for preliminary analysis. For example, random sampling can be used to randomly select a certain proportion of chips from the entire batch as the pre-test chip set. Alternatively, the batch can be divided into several sub-batches based on classification criteria such as production time and equipment number, and samples can be randomly selected from each sub-batch. This method allows for the acquisition of the overall condition of the chips within a batch in the early stages, laying the foundation for subsequent analysis.

[0023] Furthermore, after obtaining the pre-tested chip set, a set of pre-defined basic tests needs to be performed on these sample chips. These basic tests can cover the chip's key electrical parameters, functional modules, etc. After the tests are completed, the collected test results are analyzed. For example, the failure status of each test item can be statistically analyzed, and whether there is a trend of common failures among different test items can be observed. Through preliminary analysis of the failure data, possible connections between the failures of some test items and the failures of other test items can be identified, thereby establishing failure correlation rules.

[0024] Furthermore, after determining the failure association rules among the initial test items, these rules need to be clarified to identify combinations of test items with clear causal relationships or high correlation. For example, established failure association rules can be reviewed, and engineers can use their experience to determine which associations are unidirectional and strongly correlated. Alternatively, a statistical threshold can be set; if the probability of test item B failing when test item A fails exceeds this threshold, then a unidirectional failure correlation between A and B is considered to exist. In this way, test item pairs with optimization potential can be screened out, providing a basis for subsequent test optimization.

[0025] Finally, after identifying test item pairs with a unidirectional failure relationship, the full test program for the entire batch of chips under test can be optimized based on this. For example, for each test item pair, the test result of one of the test items can be used as a judgment condition. If the preceding test item fails, the execution of the other test item associated with it can be skipped or simplified. This optimization can be achieved by modifying the execution flow of the test program; for example, conditional statements can be inserted into the test program to dynamically adjust the execution of subsequent test items based on the test results of the preceding test item. In this way, unnecessary test steps can be reduced, thereby improving overall test efficiency.

[0026] For example, as a specific implementation, suppose a chip manufacturing plant is conducting mass production testing on a batch of microcontroller chips, designated "Batch X," which contains 10,000 chips to be tested.

[0027] First, stratified sampling is performed on the chips to be tested to obtain a pre-inspection chip set. 100 chips can be selected from "batch X" as the pre-inspection chip set. For example, one chip can be selected from every 100 chips on the production line, or the chips can be evenly selected based on information such as production date and wafer number, to ensure that the sample represents the overall characteristics. In this case, the 100 selected chips constitute the pre-inspection chip set.

[0028] Based on this, initial test items are performed on the pre-test chip set, and failure correlation rules between these initial test items are determined according to the test results. Specifically, a test program containing 200 initial test items is performed on these 100 pre-test chips. After the test is completed, the pass / fail results for each chip on each test item are collected. For example, data analysis may reveal that when the "Power Management Module Voltage Test" item (test item A) fails, the "ADC Conversion Accuracy Test" item (test item B) has a 90% probability of also failing; while when test item B fails, the probability of test item A failing is only 30%. Through this statistical analysis, failure correlation rules between test item A and test item B can be established.

[0029] Furthermore, based on failure association rules, test item pairs with a unidirectional failure association relationship are extracted from the initial test items. According to the above analysis, a unidirectional failure association relationship can be identified between "Power Management Module Voltage Test" and "ADC Conversion Accuracy Test," meaning that the failure of test item A is highly likely to be accompanied by the failure of test item B. Therefore, test item A and test item B are extracted as a test item pair, where test item A is the preceding test item and test item B is the associated test item.

[0030] Finally, based on this test item pair, a full-scale test optimization scheme for the chip under test is generated, and the extracted test item pair is applied to the full-scale test program of "batch X". Specifically, in the full-scale test program, when test item A is executed, its test result is judged in real time. If test item A is determined to be a failure, the test program will not execute test item B, but will directly skip that test item and infer that test item B is also a failure based on preset logic. If test item A passes, test item B is executed normally. In this way, for all chips in "batch X" where test item A fails, the repeated execution of test item B can be avoided, thereby optimizing the test process.

[0031] As can be seen from the above examples, the solution in this embodiment first performs stratified sampling and initial testing on a small portion of the chips to uncover common failure characteristics within the batch, thus addressing the problem of insufficient utilization of sampling data in existing technologies. Subsequently, failure association rules are established based on these failure characteristics, and test item pairs with unidirectional failure association relationships are extracted. This provides a basis for judging physical failure logic for subsequent test optimization, overcoming the deficiency of independent execution of test items in existing technologies. Finally, a full-scale test optimization scheme is generated based on these test item pairs, enabling the test program to dynamically adjust subsequent tests according to the failure status of preceding test items. This effectively avoids performing derivative association tests that do not generate useful information, reduces repetitive testing steps, and improves work efficiency.

[0032] Existing technologies generally use fixed and standardized test templates, performing all benchmark tests on all chips indiscriminately. This results in rigidly executing derivative correlation tests that do not produce effective information when faced with faults with clear causal relationships, leading to a waste of test resources and time.

[0033] Based on the above examples, the solution in this embodiment first performs stratified sampling of the chips to be tested and performs initial tests on the pre-inspection chip set to make full use of the sampling data in the early stage of testing. Unlike the existing technology that only uses sampling for batch yield qualification, the solution in this embodiment provides a data basis for subsequent optimization by mining the common fault characteristics contained in the sampling data. For example, in the example of "batch X" above, by testing 100 pre-inspection chips, a clear correlation between "power management module voltage test" and "ADC conversion accuracy test" can be found, without having to perform indiscriminate testing on all 10,000 chips.

[0034] Secondly, this embodiment determines the failure association rules between initial test items based on the test results, and extracts test item pairs with unidirectional failure association relationships, which contrasts with the lack of a coordination mechanism based on physical failure logic in existing technologies. In existing solutions, test items are executed independently and cannot be dynamically adjusted according to preceding faults. However, the solution in this embodiment establishes test item pairs, clarifying the causal or strong correlation between test items, and providing a basis for decision-making in the test program.

[0035] Therefore, by generating a full-scale test optimization scheme for the chip under test based on the test items, the test program can dynamically adjust the subsequent test process according to the test results of the preceding test items. In the example above, when test item A fails, test item B will be skipped, thus avoiding unnecessary tests. Through this dynamic optimization mechanism, the repetition of test steps can be significantly reduced, test time consumption can be lowered, and the throughput of large-scale mass production testing can be improved. Compared with the rigid execution of all test items in the prior art, the solution in this embodiment can complete chip testing efficiently and achieve optimized allocation of test resources while ensuring product quality.

[0036] The following will further explain a chip testing optimization method based on sampling pre-inspection in this exemplary embodiment.

[0037] In one embodiment of this application, the specific process of "performing stratified sampling of the chip to be tested to obtain a pre-inspection chip set" described in step S110 can be further explained in conjunction with the following description.

[0038] As described in the following steps Obtain the batch parameters of the chip to be tested, including the total batch quantity, the number of wafers, and the wafer area distribution; The sampling quantity is determined based on the total quantity of the batch, and each wafer containing the chip to be tested is used as an independent sampling layer. Based on the wafer region distribution, sample chips are uniformly extracted from the central region, intermediate region and edge region of each wafer to obtain the pre-detection chip set.

[0039] It should be noted that obtaining the batch parameters of the chip under test is intended to provide basic data for the subsequent sampling process. Batch parameters are key information describing the scale and structure of the entire chip production batch. For example, batch parameters can be automatically obtained from a manufacturing execution system or product lifecycle management system, or obtained by manually inputting data from production documents. These batch parameters include the total batch quantity, the number of wafers, and the wafer region distribution. The total batch quantity refers to the total number of chips in the batch under test, serving as an important basis for determining the statistically valid sampling quantity. For example, it can be obtained based on the final chip sorting count or initial design specifications. The number of wafers refers to the total number of semiconductor wafers that make up the batch of chips, used to divide the entire batch into independent sampling units. For example, the number of wafers is usually recorded in the wafer batch tracking system during the wafer manufacturing and assembly stages. The wafer region distribution describes the distribution of chips in different regions on a single wafer, such as the center, middle, and edges. It is crucial for identifying and addressing internal wafer process differences. For example, the wafer region distribution can be extracted from wafer maps generated by electrical testing or probe testing, or preset based on known wafer process characteristics within the industry.

[0040] Furthermore, determining the sampling quantity based on the total batch size translates the overall batch size into specific sample requirements. The sampling quantity can be determined based on statistical principles, for example, by setting a desired confidence level and error range, or by using a preset sampling ratio, such as 0.5% or 1% of the total. Treating each wafer containing the chip under test as an independent sampling layer establishes a stratified sampling framework. By considering each wafer as an independent sampling layer, it ensures that the pre-tested chip set includes samples from all wafers within the batch, effectively avoiding sample bias caused by differences between wafers. Specifically, this can be achieved by logically dividing the entire batch into independent wafer units in the data management system, ensuring that samples are extracted from each wafer layer during subsequent sampling.

[0041] Finally, based on the wafer region distribution, sample chips are uniformly extracted from the central, intermediate, and edge regions of each wafer to further refine the stratified sampling and capture the spatial variability within the wafer. Chip performance and failure modes may differ in different regions of the wafer, for example, due to inhomogeneities in process parameters such as temperature, etching, or deposition. Uniform sampling within specific regions ensures that the pre-inspected chip set comprehensively reflects these spatial differences. Specifically, software algorithms can divide the digital wafer map into predefined central, intermediate, and edge regions, and then uniformly sample within each region using random or systematic selection methods, for example, selecting one chip every N chips.

[0042] For example, as one specific implementation, suppose a chip batch contains 100,000 chips, which are distributed across 100 wafers.

[0043] First, the system retrieves batch parameters for this batch of chips from the production database, including the total batch size of 100,000, the number of wafers of 100, and the typical regional distribution of each wafer, such as 30% in the central area, 40% in the middle area, and 30% in the edge area. Based on the total batch size, for example, using a sampling ratio of 0.5%, it determines that 500 chips need to be sampled as a pre-inspection sample. Next, each of these 100 wafers is identified as an independent sampling layer. Then, for each wafer, since the total sample size is 500 chips and there are 100 wafers, an average of 5 chips need to be sampled from each wafer.

[0044] Based on this, and according to the wafer region distribution, 1-2 chips can be extracted from the central region of each wafer, 2 chips from the middle region, and 1-2 chips from the edge region. The specific extraction operation can be performed by selecting the physical coordinates of the chips within each region using a random number generator, or by selecting chips at preset uniform intervals to ensure a uniform distribution of samples.

[0045] Ultimately, all the chips extracted from different wafers and regions are brought together to form a highly representative pre-test chip set.

[0046] The above technical solution effectively addresses the issue of insufficient sample representativeness that may arise from traditional sampling methods when performing stratified sampling of chips under test. By acquiring detailed batch parameters and using the wafer as an independent sampling layer, combined with uniform sampling based on the regional distribution within the wafer, it ensures that the obtained pre-test chip set is not only statistically significant in quantity but also comprehensively covers various potential sources of variation in the chip batch in terms of spatial distribution. This allows the pre-test chip set to more accurately reflect the true failure modes and characteristics of the entire batch of chips, thus providing a data foundation for the subsequent generation of failure association rules. Based on this, the solution in this embodiment helps to construct a more targeted and efficient full-scale testing optimization scheme, effectively improving the accuracy and efficiency of chip testing while reducing testing costs.

[0047] In an optional embodiment of this application, considering that the failure modes of chips during mass production testing are not only affected by wafer-level process drift, but also by thermal stress, mechanical stress, and parasitic parameter fluctuations during the subsequent packaging process, these are also important factors inducing functional failure. Therefore, to further improve the fidelity of sampling pre-inspection and the accuracy of test optimization, based on the above scheme, packaging-related multidimensional parameters can be used as combination variables for chip sampling. Specific implementation details are as follows: Furthermore, in the step of obtaining the batch parameters of the chip under test, the batch parameters include not only the number of wafers and the wafer area distribution at the wafer manufacturing front end, but also the chip's packaging traceability parameters. Specifically, the packaging traceability parameters include the packaging manufacturer's identifier, the packaging process type (e.g., flip-chip, wafer-level chip-scale packaging (WLCSP), wire bonding, etc.), the packaging batch number, and optional packaging cavity / carrier reference number. The purpose of introducing packaging traceability parameters is that, for adjacent bare dies on the same wafer, if they are assigned to different packaging manufacturers or different packaging batches, after experiencing small fluctuations in thermosetting temperature or differences in mechanical stress, the final electrical parameter drift and failure performance may also show significant differences. Therefore, obtaining packaging traceability parameters is a prerequisite for constructing a high-fidelity sampling model.

[0048] Based on the packaging traceability parameters obtained above, the specific process of "performing tiered sampling of the chip under test to obtain a pre-inspection chip set" can be configured as cross-tiered sampling of wafer manufacturing and packaging processes. That is, each wafer containing the chip under test is used as the first-dimensional spatial sampling layer, and different packaging plants, packaging processes, or packaging batches are used as the second-dimensional process sampling layer. Within the cross subset formed by the orthogonal intersection of the two dimensions, for example, a chip set specifically defined as the "edge region of wafer A" and belonging to "packaging batch X of packaging plant B," sample chips are uniformly extracted according to a preset ratio and fused to obtain the pre-inspection chip set. This cross-tiered sampling mechanism effectively prevents excessive concentration of sampled samples under specific packaging stress conditions, ensuring that the pre-inspection chip set can cover the dual-variable coupling scenario of "wafer manufacturing process drift" and "packaging thermomechanical stress fluctuations," thereby laying a data foundation for capturing more hidden packaging-induced fault linkage characteristics.

[0049] Furthermore, after acquiring the two-dimensional sampling data, the step of "generating the failure association rules based on the conditional failure probability" can further include a rule clustering verification mechanism based on packaging variables. Specifically, the packaging traceability parameters of the intersection chips in the pre-inspection chip set are extracted, and the conditional failure probability distribution of the same test item pair under different packaging batches or packaging processes is compared. If the conditional failure probability of a certain test item pair under a specific packaging process or a specific packaging batch exceeds a preset significance threshold, but does not exceed the significance threshold under other packaging conditions, a local failure association rule with packaging constraints is generated. Through this identification mechanism, the blind spot of the one-size-fits-all approach to global rules in the prior art can be overcome. For example, a defect with a slightly high leakage current in a certain front-end pin may not cause subsequent test failures under wire bonding processes due to the small parasitic inductance; however, in a specific batch of flip-chip packaging, due to the small deformation caused by the curing stress of the bottom filler adhesive, this slight leakage will inevitably lead to the failure of the associated high-speed interface test. Through the above mechanism, the system generates unidirectional failure association rules only for specific packaging batches, thereby realizing dynamic rule loading based on the underlying physical mechanism.

[0050] Finally, in the step of "generating a full-scale test optimization scheme for the chip under test based on the test item pair," when the failure association rule used is a local failure association rule with packaging constraints, an additional pre-judgment threshold can be configured in the conditional bypass path constructed between the pre-test node and the derived test node in the test program. This pre-judgment threshold is used to: first, read the device identification register or batch tracking code stored in the chip under test to parse its corresponding current packaging parameters when performing full-scale testing at the test end; only when the current packaging parameters match the constraints of the local failure association rule, and the pre-test item test result is a failure, is a conditional jump instruction triggered to bypass the derived test node. This mechanism not only avoids invalid test steps but also effectively prevents physical omissions caused by incorrect application of failure rules when different packaging plants or packaging batches are tested on the same testing line. This improves test throughput while ensuring the safety of mass production testing and the confidence of factory yield data.

[0051] In one embodiment of this application, the specific process of step S120, "performing initial test items on the pre-test chip set and determining the failure association rules between the initial test items based on the test results," can be further explained in conjunction with the following description.

[0052] As described in the following steps An initial test item is performed on the pre-detection chip set, and the test results of each chip in the pre-detection chip set on each initial test item are collected. The number of failed chips for each initial test item in the statistical test results is determined, and the ratio of the number of failed chips to the total number of chips in the pre-inspection chip set is determined as the failure distribution characteristic. The initial test items whose failure distribution characteristics exceed a preset probability threshold are selected as candidate correlation test items; For any two candidate association test items, the number of failed chips in one of the candidate association test items is used as the condition base to calculate the proportion of failed chips in the other candidate association test item, thus obtaining the conditional failure probability. The failure association rule is generated based on the failure probability of the condition.

[0053] It should be noted that initial tests are performed on the pre-test chip set, and the test results of each chip in the pre-test chip set are collected for each initial test. The aim is to obtain actual performance data of the chips in each test, providing original evidence for failure analysis. For example, the pre-test chip set can be batch-tested using automated testing equipment, and the pass or failure status of each chip in each initial test, as well as the relevant test parameter values, can be recorded in real time. Alternatively, tests can be performed manually or using a semi-automated testing platform, and the test results can be entered into a data management system.

[0054] Furthermore, the number of failed chips for each initial test item in the statistical test results is determined, and the ratio of the number of failed chips to the total number of chips in the pre-inspection chip set is defined as the failure distribution characteristic. This aims to quantify the failure frequency of each initial test item, thereby providing a preliminary assessment of its failure prevalence in the pre-inspection chip set. For example, statistical analysis of the collected test results can be performed using a data processing program to calculate the number of failed chips for each initial test item, and then divide it by the total number of chips in the pre-inspection chip set to obtain a ratio between 0 and 1, which represents the failure distribution characteristic.

[0055] Furthermore, initial test items whose failure distribution characteristics exceed a preset probability threshold are selected as candidate association test items. This aims to exclude test items with excessively low failure frequencies, focusing the analysis on test items with higher failure risk or prevalence, thereby improving the efficiency and accuracy of association rule mining. For example, a probability threshold, such as 0.05, can be set. Any initial test item with failure distribution characteristics below this threshold will be excluded, while test items with characteristics above or equal to this threshold will be considered as candidate association test items.

[0056] Finally, by calculating conditional probabilities, the likelihood that one test item will fail when the other fails can be quantified. For example, all candidate combinations of associated test items can be iterated. For each pair of test items (A, B), first, all chips that fail on test item A are identified, and the number of these chips is used as the conditional base. Then, among these chips, the number that also fails on test item B is counted, and the ratio of this number to the conditional base is used as the conditional failure probability P(B failure|A failure). Finally, the failure association rules are generated based on the conditional failure probabilities, aiming to transform the quantified conditional failure probabilities into actionable rules to guide subsequent test optimization. For example, a conditional probability threshold can be set. When P(B failure|A failure) exceeds this threshold, a rule is generated: "If test item A fails, then test item B is very likely to fail." Furthermore, these generated rules can be further refined, for example, by assigning different confidence levels based on the probability.

[0057] For example, as a specific implementation, suppose there is a pre-test chip set containing 100 chips, and 5 initial test items T1, T2, T3, T4, and T5.

[0058] First, perform tests T1 through T5 on these 100 chips and record the pass / fail result for each chip on each test item. For example, the test results show that: 30 chips failed in T1; 5 chips failed in T2; 25 chips failed in T3; 4 chips failed in T4; and 28 chips failed in T5.

[0059] Based on this, the number of failed chips for each initial test item was counted, and the failure distribution characteristics were calculated: failure distribution characteristic of T1 = 30 / 100 = 0.3; failure distribution characteristic of T2 = 5 / 100 = 0.05; failure distribution characteristic of T3 = 25 / 100 = 0.25; failure distribution characteristic of T4 = 4 / 100 = 0.04; failure distribution characteristic of T5 = 28 / 100 = 0.28.

[0060] Then, using a preset probability threshold, such as 0.1, initial test items with failure distribution characteristics exceeding 0.1 are selected as candidate association test items. In this example, the failure distribution characteristics of T1, T3, and T5 are 0.3, 0.25, and 0.28, respectively, all exceeding 0.1. Therefore, T1, T3, and T5 are selected as candidate association test items, while T2 and T4 are excluded because they are below the threshold. Subsequently, for the selected candidate association test items (T1, T3, T5), the conditional failure probability between any two test items can be calculated. For example, consider test items T1 and T3: using the number of failed chips in T1 as the conditional base, among the 30 chips that failed in T1, how many chips also failed in T3? Assume that 20 chips fail simultaneously in both T1 and T3. Then, the conditional failure probability P(T3 failure|T1 failure) = 20 / 30 ≈ 0.67. Furthermore, consider test items T3 and T5: using the number of failed chips in T3 as the conditional base, among these 25 chips that failed in T3, count how many chips also failed in T5. Assume that 18 chips failed in both T3 and T5. Then, the conditional failure probability P(T5 failure|T3 failure) = 18 / 25 = 0.72.

[0061] Finally, failure association rules are generated based on the conditional failure probabilities. For example, a conditional probability threshold, such as 0.6, can be set. Since P(T3 failure | T1 failure) ≈ 0.67 > 0.6, the rule "If T1 fails, then T3 is very likely to fail" can be generated. Since P(T5 failure | T3 failure) = 0.72 > 0.6, the rule "If T3 fails, then T5 is very likely to fail" can be generated. Based on this, these generated rules can provide clear guidance for subsequent test optimization. For example, when T1 fails, the test for T3 can be skipped, and its failure can be directly inferred.

[0062] Through the above technical solution, this application provides a data-driven method to determine failure association rules between initial test items. Specifically, by statistically analyzing and filtering the test results of the pre-test chip set, statistically significant failure modes can be effectively identified, avoiding analytical biases caused by random or low-frequency failure data. In particular, by calculating the conditional failure probability, the dependencies between test items can be accurately quantified, making the generated failure association rules more precise and reliable, thereby improving the quality of the failure association rules. This provides a foundation for subsequently extracting test item pairs with unidirectional failure association relationships from the initial test items, and thus enables more effective generation of full-scale test optimization schemes for the chip under test, reducing testing costs and shortening the testing cycle.

[0063] In one embodiment of this application, the specific process of "for any two candidate associated test items, using the number of failed chips in one of the candidate associated test items as the condition base, calculating the proportion of failed chips in the other candidate associated test item, and obtaining the conditional failure probability" can be further explained in conjunction with the following description.

[0064] As described in the following steps Use any two of the candidate association test items as the first test item and the second test item, respectively. The pre-detection chips that fail based on the test results of the first test item constitute a condition sample set, and the number of chips in the condition sample set is used as the condition base. In the statistical sample set under the given conditions, the intersection chips whose test results for the second test item are invalid; Obtain the measured parameter offset of the intersection chip on the second test item, and set the association weight for the intersection chip based on the measured parameter offset; The association weights of each intersection chip are summed to obtain a weighted intersection value, and the ratio of the weighted intersection value to the condition base is determined as the condition failure probability.

[0065] It should be noted that the first and second test items are arbitrarily selected from the screened candidate related test items, used to analyze the failure correlation between them. The first test item serves as a condition, and the second test item as a result, to explore the probability that the second test item will fail when the first test item fails. For example, the first test item could be a static power consumption test of the chip, and the second test item could be a performance test of a functional module.

[0066] Furthermore, the conditional sample set refers to the set of pre-detection chips that were determined to be faulty in the first test item. It serves as the basis for subsequently calculating the conditional failure probability and limits the scope of the system's focus, namely, the failure scenario of the second test item given that the first test item has already failed. The conditional sample set can be constructed by iterating through the test results of all pre-detection chips and filtering out chips that failed in the first test item. The conditional cardinality is the total number of chips in the conditional sample set, representing the total number of samples in all cases of failure in the first test item. The conditional cardinality serves as the denominator in calculating the conditional failure probability, used to standardize the frequency of failure occurrence. Intersection chips refer to chips in the conditional sample set that are also determined to be faulty in the second test item. These intersection chips are samples that failed in both the first and second test items and are a key component in calculating the conditional failure probability. Specifically, they can be obtained by re-evaluating the chips in the conditional sample set for failure in the second test item.

[0067] Furthermore, the measured parameter offset refers to the deviation between the actual measured parameter value of the chip in the second test item and the nominal value or the upper and lower limits of the good product for that parameter. For example, if the good product range for a certain voltage parameter is 1.0V ± 0.1V, while the measured value is 0.8V, then its offset is 0.2V. This measured parameter offset can quantify the severity of the failure, rather than simply a binary judgment of "failure" or "pass". The measured parameter offset can be directly measured and recorded by the testing equipment, or calculated through post-processing. The correlation weight is a value assigned to each intersecting chip based on the measured parameter offset, used to reflect the severity of the chip's failure in the second test item. The larger the offset, the more severe the failure usually is, and the corresponding correlation weight should also be higher. The correlation weight can be a linear function, for example, the weight increases by a fixed value for every unit increase in offset; or it can be a non-linear function, for example, the weight increases exponentially when the offset exceeds a certain threshold.

[0068] Finally, the weighted intersection value is the sum of the association weights of all intersection chips. This value is not simply the number of failed chips, but a total value that comprehensively considers the severity of failure of each failed chip. As the numerator for calculating the conditional failure probability, it can more accurately reflect the weighted failure degree of the second test item under the condition of failure in the first test item. The conditional failure probability is the ratio of the weighted intersection value to the conditional cardinality. This probability value not only considers the frequency of failure occurrence, but also further incorporates information on the severity of failure, thus providing a more comprehensive and accurate measure of failure association strength.

[0069] For example, as a specific implementation, suppose that during the pre-inspection of a batch of chips to be tested, "leakage current test" and "functional module A test" are selected as candidate associated test items. In this case, suppose "leakage current test" is set as the first test item and "functional module A test" is set as the second test item.

[0070] First, the system identifies all pre-test chips that failed in the "leakage current test," for example, 100 chips, forming a conditional sample set, with the number of chips (100) serving as the conditional base. Based on this, the system counts how many of these 100 chips also failed in the "functional module A test," say 20. For these 20 overlapping chips, the system further obtains their measured parameter offsets in the "functional module A test." For example, for a certain overlapping chip, the acceptable yield limit for a key timing parameter in the "functional module A test" is 10ns, but the measured value is 12ns, then the offset is 2ns. The system can preset a mapping function, for example, a weight of 1 for offsets between 0-1ns, 1.5 for offsets between 1-2ns, and 2 for offsets above 2ns. Based on this function, the associated weight of this chip is set to 1.5.

[0071] Based on this, similar offset acquisition and association weight settings are performed on all 20 intersecting chips, and then these association weights are accumulated to obtain a weighted intersection value, for example, 25.

[0072] Ultimately, the calculated conditional failure probability is 25 / 100 = 0.25. In this way, even with the same number of failed chips, a more severe failure will result in a higher conditional failure probability, thus more accurately reflecting the correlation strength between test items.

[0073] The above technical solution determines the failure association rules between initial test items by no longer relying solely on the number of failed chips, but also by considering the severity of the failures. Specifically, by obtaining the measured parameter offsets of the intersection chips and setting association weights, the intensity of the failures can be quantified, resulting in a weighted intersection value. This allows the calculated conditional failure probability to more accurately reflect the true correlation strength and potential causal relationship between the failures of the test items, helping to avoid misjudgments or omissions caused by simple counting, and making the generated failure association rules more accurate and reliable. Finally, based on the generated failure association rules, more instructive test item pairs can be extracted, leading to a more efficient and optimized full-scale test optimization scheme, effectively improving the efficiency and quality of chip testing.

[0074] In one embodiment of this application, the specific process of "generating the failure association rule based on the conditional failure probability" can be further explained in conjunction with the following description.

[0075] As described in the following steps Extract the wafer coordinate data of each pre-detection chip in the pre-detection chip set, and divide the conditional failure probability into the central region conditional probability, the middle region conditional probability, and the edge region conditional probability based on the wafer coordinate data. Compare the numerical dispersion of the conditional probabilities of the central region, the intermediate region, and the edge region. If the numerical dispersion is greater than the preset regional drift threshold, then a regional failure association rule is generated.

[0076] It should be noted that extracting the wafer coordinate data of each pre-test chip in the pre-test chip set aims to obtain the physical location information of each pre-test chip on the wafer, providing basic data for subsequent area division. In practice, the test equipment typically records the wafer ID and its XY coordinates on the wafer for each chip under test. This data can be obtained directly from test logs or a database. Alternatively, the physical location of each chip can be identified and recorded by scanning markers on the wafer or using image recognition technology, and then converted into standardized wafer coordinate data. Based on the wafer coordinate data, the conditional failure probability is divided into central region conditional probability, intermediate region conditional probability, and edge region conditional probability. The purpose is to refine the previously calculated overall conditional failure probability to different wafer regions based on the chip's physical location on the wafer, facilitating the analysis of regional failure modes. Specifically, this can be achieved by pre-defining the coordinate ranges of the central, intermediate, and edge regions of the wafer. For example, the central region could be 0-20% of the wafer radius, the intermediate region 20%-80%, and the edge region 80%-100%. Then, each pre-inspection chip is categorized into its corresponding region based on its wafer coordinates, and the conditional failure probability of the chip within that region is calculated. Alternatively, a clustering algorithm can be used to spatially cluster the pre-inspection chips based on the wafer coordinate data, forming several region clusters. Then, the conditional failure probability within each cluster is calculated, and the cluster is named the central, intermediate, or edge region conditional probability based on its physical location.

[0077] Furthermore, comparing the numerical dispersion of the conditional probabilities of the central region, the intermediate region, and the edge region aims to assess the degree of difference in conditional failure probabilities between different wafer regions, in order to determine whether there are regional failure modes. Specifically, this can be achieved by calculating the standard deviation or variance of the conditional probabilities of the three regions. The larger the standard deviation or variance, the higher the numerical dispersion. Alternatively, the difference between the maximum and minimum values ​​of the conditional probabilities of the three regions can be calculated to measure their degree of dispersion.

[0078] Finally, the preset region drift threshold is a pre-defined value used to determine whether the difference in conditional failure probabilities between different wafer regions is significant enough to indicate the existence of a regional failure mode. This region drift threshold can be set as an empirical value based on historical test data or process experience. For example, if the difference in conditional failure probabilities between different regions exceeds 10%, then region drift is considered to exist. Alternatively, a statistical significance level can be determined through statistical analysis methods, such as hypothesis testing, and then converted into a region drift threshold. The generation of region-level failure association rules serves to generate failure association rules for specific wafer regions when a significant regional failure mode is detected, guiding subsequent test optimization. Specifically, region information can be added as a limiting condition to the existing failure association rules. For example, if the rule "Test A failure leads to Test B failure" shows a higher conditional probability in edge regions, then a region-level rule "In edge regions, Test A failure leads to Test B failure" can be generated. Alternatively, a separate set of failure association rules can be generated for each region with significant region drift, and these failure association rules are only applicable to the chip in that specific region.

[0079] As an example, in one specific implementation, after performing initial tests on the pre-inspection chip set and obtaining the conditional failure probability, further processing is performed. For example, for each pre-inspection chip, its wafer coordinate data can be represented as (X,Y) coordinate pairs. In this case, the system can pre-define the wafer's central region as a circular region with a radius less than R1, the middle region as an annular region with a radius between R1 and R2, and the edge region as an annular region with a radius greater than R2. Then, each pre-inspection chip is classified into the corresponding region according to its (X,Y) coordinates.

[0080] Based on this, the conditional failure probability within each chip region is recalculated, resulting in conditional probabilities for the central region, intermediate region, and edge region. For example, if the overall conditional failure probability of "test A failure causing test B failure" is 80%, it might be 70% in the central region, 85% in the intermediate region, and 95% in the edge region. Subsequently, the system calculates the numerical dispersion of the conditional probabilities for these three regions, such as calculating their standard deviation. If the calculated standard deviation is greater than a preset region drift threshold, a region-level failure association rule is generated. For example, a rule could be generated stating, "In the edge region, if test A fails, the probability of test B failing is 95%", or an independent set of failure association rules could be generated for each region.

[0081] Through the above technical solution, this embodiment, when generating failure association rules based on conditional failure probabilities, no longer relies solely on overall statistical data, but specifically analyzes the differences in failure modes of chips in different wafer regions. Specifically, by extracting wafer coordinate data, dividing regional conditional probabilities, and further comparing their numerical dispersion, localized failure modes caused by differences in wafer manufacturing processes or physical locations can be effectively identified. When significant regional differences are detected, regional-level failure association rules are generated, making subsequent test optimization schemes more targeted and avoiding low testing efficiency or missed detections due to ignoring regional differences, thereby improving the accuracy and practicality of the failure association rules.

[0082] In one embodiment of this application, the test item pair includes pre-test items and associated test items. The specific process of "generating a full-scale test optimization scheme for the chip under test based on the test item pair" in step S140 can be further explained in conjunction with the following description.

[0083] As described in the following steps The preceding test items and the associated test items are mapped to preceding test nodes and derived test nodes in the test program, respectively, and a conditional bypass path from the preceding test node to the derived test node is constructed in the test program. In the test program, a status monitoring instruction is configured for the pre-test node. The status monitoring instruction is used to capture the test results of the pre-test item in real time when the test is executed at the test end. The test program configured with the state monitoring instructions and the conditional detour path is encapsulated into the full-scale test optimization scheme.

[0084] It should be noted that a test item pair refers to a specific failure correlation between two or more test items during chip testing. A preceding test item is one whose failure result can predict or accompany the failure of another test item in the testing process. A related test item is one whose failure has a one-way correlation with the failure of a preceding test item. In this embodiment, a test item pair typically indicates that when a preceding test item fails, a related test item is also likely to fail. Mapping refers to transforming the abstract concept of a test item into an operable entity in the test program. A test program is a sequence of software code or instructions used to control the test equipment to perform chip testing. Pre-test nodes and derived test nodes are specific execution points or modules in the test program, corresponding to preceding test items and related test items, respectively. This mapping can be achieved by defining specific functions, subroutines, code blocks, or tags in the test program. For example, "power consumption test" can be mapped to a function named Power_Consumption_Test_Node, and "simulated performance test" can be mapped to a function named Analog_Performance_Test_Node. Conditional bypass paths refer to the logical path of test execution flow that can be skipped when certain conditions are met in a test program. The purpose of this is to skip the corresponding derived test nodes directly when the result of the current test node meets the preset conditions, without executing the associated test items it represents. Specifically, this can be achieved by using conditional jump instructions in the test program, such as IF-THEN-ELSE statements, GOTO instructions, or function pointer jumps, or by configuring the flow control logic in the test sequence management tool.

[0085] Furthermore, a status monitoring instruction is a special instruction or code segment embedded in the test program. Its function is to monitor and capture the test results or status of the preceding test nodes in real time during test execution. This status monitoring instruction can be a flag check, an interrupt service routine, a callback function, or a mechanism that continuously polls specific registers or memory addresses. Its purpose is to ensure that once the preceding test item is completed, its result can be immediately perceived by the system and used for subsequent process judgments. Real-time capture means that during the execution of the test program by the test equipment, the status monitoring instruction can immediately obtain the test results of the preceding test items without waiting for the entire test sequence to complete or performing additional result queries. The test end typically refers to automated test equipment or dedicated test instruments used to apply stimuli to the chip under test and measure the response. The real-time capture mechanism ensures that the test process can quickly make decisions based on the immediate results of the preceding test items, thereby achieving dynamic test path adjustments.

[0086] Finally, encapsulation refers to packaging the modified and configured test program, along with its internal state monitoring instructions and conditional bypass paths, into a complete deployable unit. A full-scale test optimization scheme refers to the optimized test program ultimately used for comprehensive testing of the chip under test. This encapsulation can involve compiling the modified source code into an executable file, or packaging configuration information and script files into a deployment package for loading and execution on the test server.

[0087] For example, as a specific implementation method, suppose that during the testing of a batch of chips, a sampling pre-inspection reveals a one-way failure relationship between the "power consumption test" (pre-test item) and the "simulation performance test" (related test item), that is, a chip that fails the power consumption test will almost certainly fail the simulation performance test as well.

[0088] To optimize the full-scale testing process, the following steps can be implemented: First, in the chip's test program, define "Power Consumption Test" as a function or code block named Test_Power_Consumption as a pre-test node. Simultaneously, define "Simulated Performance Test" as a function or code block named Test_Analog_Performance as a derived test node. Based on this, immediately after the Test_Power_Consumption function completes execution, configure a status monitoring instruction. This status monitoring instruction can be a conditional statement, such as IF (Power_Consumption_Result==FAIL). Then, construct a conditional bypass path. If Power_Consumption_Result is FAIL, the test program will execute a jump instruction, such as GOTO End_Analog_Performance_Test, directly skipping the execution of the Test_Analog_Performance function. If Power_Consumption_Result is PASS, the Test_Analog_Performance function continues to execute sequentially.

[0089] Finally, the entire test program, including the aforementioned mappings, state monitoring instructions, and conditional jump logic, is compiled or packaged to form the final full-scale test optimization scheme, which is then sent to the automated test equipment for execution. When the automated test equipment executes this scheme, if the chip fails in Test_Power_Consumption, Test_Analog_Performance will be automatically skipped, thus saving test time.

[0090] Through the above technical solution, this application can concretize the abstract test optimization scheme into an executable test program, thereby solving the problem of how to dynamically adjust the test process to improve efficiency in actual testing. By mapping pre-test items and related test items to test nodes and constructing conditional bypass paths, combined with the real-time capture capability of status monitoring instructions, the test system can skip subsequent related test items that will inevitably fail based on the immediate results of pre-test items, thereby reducing unnecessary test steps and test time, improving test efficiency while reducing test costs. Furthermore, since the optimization is based on failure association rules established from pre-test data, it ensures that test coverage and accuracy are not sacrificed while shortening test time, thus ensuring the test quality of the chip.

[0091] In one embodiment of this application, the specific process following step S140, "generating a full-scale test optimization scheme for the chip under test based on the test item pair," can be further explained in conjunction with the following description.

[0092] As described in the following steps Extract the initial execution order of the pre-test items and the associated test items in the initial test program; If the initial execution order of the pre-test item lags behind the associated test item, then the execution order of the pre-test item is reconstructed to precede the associated test item to construct a timing interception path; Based on the timing interception path, conditional jump instructions are configured between the pre-test item and the associated test item to form an interception linkage relationship.

[0093] It should be noted that extracting the initial execution order of the pre-test items and related test items in the initial test program aims to obtain the original execution order of the test items before optimization. This can be achieved by parsing the script file of the test program, reading the test sequence configuration file, or querying the test item metadata in the test management system. By clarifying the original position of each test item, an accurate basis can be provided for subsequent order adjustments, ensuring the precision of the optimization operation.

[0094] Furthermore, the execution order of the pre-test items is restructured before the associated test items to construct a timing interception path. This aims to adjust the execution order of test items, ensuring that causally related test items are executed in a logical causal order. The restructured execution order can be achieved by modifying the test item call order in the test script, adjusting the execution list in the test sequence configuration file, or dynamically adjusting the test queue in the test control software. Constructing a timing interception path logically establishes an execution flow from the pre-test items to the associated test items, allowing the test results of the pre-test items to directly influence the execution of the associated test items.

[0095] Finally, conditional jump instructions are configured to form an interception linkage, aiming to establish a mechanism that allows the execution of related test items to be skipped immediately when the test result of the preceding test item meets specific conditions. By configuring conditional jump instructions, linkage between preceding and related test items can be achieved. When the preceding test item fails, the test flow can skip the related test item, thereby avoiding unnecessary test execution.

[0096] For example, as a specific implementation, suppose that in the initial test program there are test items TestA and TestB, where TestA is a prerequisite test item and TestB is an associated test item, and the initial execution order is TestB first, followed by TestA.

[0097] First, the system will detect that TestA's initial execution order lags behind TestB. Based on this, the test optimization system will restructure the execution order of TestA to precede TestB. For example, by modifying the test script to adjust the execution order to TestA, TestB, a timing interception path from TestA to TestB can be constructed.

[0098] Furthermore, a conditional jump instruction is configured between TestA and TestB along this timing interception path. For example, after TestA completes execution, a pseudocode instruction can be inserted: IF TestA_Result == FAIL THEN JUMP_TO_NEXT_TEST_AFTER_TestB. Based on this, when the test server executes TestA and detects that its result is invalid, the conditional jump instruction will be triggered, and the test flow will directly skip the execution of TestB, thus forming an effective interception linkage.

[0099] Through the above technical solution, this application can effectively solve the test redundancy problem caused by the unreasonable initial execution order of pre-test items and related test items. By reconstructing the execution order of test items and configuring conditional jump instructions, it is ensured that when a pre-test item fails, its related test items can be intercepted in a timely manner, avoiding unnecessary test execution. Based on this, the solution of this embodiment can significantly improve the efficiency of chip testing, reduce testing time, and lower testing costs.

[0100] In one embodiment of this application, the specific process following "configuring conditional jump instructions between the pre-test item and the associated test item based on the timing interception path to form an interception linkage relationship" can be further described in conjunction with the following description.

[0101] As described in the following steps The full-scale test optimization scheme is distributed to the test terminal to perform tests on the chip under test sequentially; When the test terminal determines that the test result of the pre-test item is invalid, the conditional jump instruction is triggered; In response to the triggering of the conditional jump instruction, the corresponding associated test item is bypassed along the timing interception path in the test control flow to block the transmission of the physical test signal corresponding to the associated test item to the chip under test; Based on the interception linkage relationship, inferred failure data is generated for the bypassed associated test items, and the inferred failure data is filled into the test log.

[0102] It should be noted that distributing the full-scale test optimization scheme to the testing end to sequentially perform tests on the chip under test refers to deploying the pre-optimized test program onto the actual testing equipment and initiating automated testing of the chip. This full-scale test optimization scheme can be transmitted to the controller of the testing equipment via a network interface or dedicated data bus in the form of a compiled binary file; alternatively, the full-scale test optimization scheme can also be a script file or configuration file, loaded and executed by the interpreter or configuration engine on the testing end device, thereby driving the testing hardware to test the chip.

[0103] Furthermore, when the test terminal determines that the test result of the pre-test item is a failure, it triggers the conditional jump instruction, which is a key triggering mechanism for dynamically adjusting the test process. The test terminal monitors the test results of the pre-test items in real time, and immediately activates the preset jump logic once a failure is detected. Specifically, after executing the pre-test item, the test control unit inside the test terminal immediately reads its test result. If the result matches the preset failure condition, the test control unit generates an internal signal or sets a flag, thereby triggering the conditional jump instruction. In addition, conditional judgment statements can be embedded in the test program. When the pre-test item is completed and returns to a failure state, the condition of the judgment statement is true, and the program flow automatically jumps to the logic branch pointed to by the conditional jump instruction.

[0104] Furthermore, in response to the triggering of the conditional jump instruction, the corresponding associated test item is skipped along the timing interception path in the test control flow to block the transmission of the physical test signal corresponding to the associated test item to the chip under test. This is an actual test skip operation, ensuring that the associated test item will not be executed under specific conditions, thereby saving test time. After receiving the trigger signal of the conditional jump instruction, the test control flow modifies the program counter or instruction pointer to directly skip the code segment of the associated test item and execute subsequent test items or data processing logic. At the same time, the signal generator and measurement unit of the test hardware are kept inactive to avoid applying voltage, current, or clock signals related to the associated test item to the chip. As another implementation, the test end can maintain a test item execution queue. When the conditional jump instruction is triggered, the test control software removes or marks the corresponding associated test item from the test item execution queue so that it is no longer scheduled for execution. The blocking of physical test signals is achieved by controlling the relays, switch matrices, or digital I / O ports of the test instrument to ensure that the test probes or pins do not make electrical connections or signal interactions with the chip.

[0105] Finally, generating deduced failure data for the skipped associated test items based on the interception linkage relationship and filling the test log with this deduced failure data is key to solving the problem of missing test log data. Even if a test item is skipped, a reasonable failure record must be generated for it to maintain the integrity and accuracy of the test log. The interception linkage relationship can be predefined as a mapping rule, such as "if the preceding test item A fails, then the associated test item B is also considered to have failed, and a specific failure code or default failure parameter value is recorded." After skipping an associated test item, the test control system will generate corresponding failure data according to this mapping rule and write it to the test log file. In addition, the deduced failure data can be calculated or inferred based on the actual failure parameters of the preceding test item. For example, if the voltage test result of the preceding test item is lower than the lower limit, the system can infer that the current test result of the associated test item will also be lower than a certain threshold according to the preset linkage model, and generate corresponding virtual failure data. Similarly, these virtual failure data will also be formatted and added to the test log to ensure the continuity and traceability of the log.

[0106] For example, as a specific implementation, suppose that when testing a batch of chips, the full-scale test plan has been optimized based on the interception linkage between the pre-test item "Power Supply Voltage Test" and the associated test item "Power Consumption Test," and this optimized plan has been sent to the test terminal. When the test terminal performs the "Power Supply Voltage Test" on a chip under test, if the test result is determined to be below a preset lower limit, it is considered a failure. At this time, the test control unit inside the test terminal will immediately trigger a preset conditional jump instruction. In response to this trigger, the test control flow will skip the execution code segment of the "Power Consumption Test" directly along the pre-built timing interception path. At the same time, the power module and current measurement unit of the test instrument will not apply excitation signals related to the "Power Consumption Test" or perform current measurements on the chip, thereby blocking the transmission of physical test signals.

[0107] During this process, the system generates deduced failure data for the bypassed "power consumption test" based on preset interception linkage relationships, such as "if the power supply voltage test fails, the power consumption test is also considered a failure and recorded as a high power consumption failure." This deduced failure data may include a specific failure code and a virtual power consumption value. Subsequently, this deduced failure data is formatted and filled into the chip's test log, ensuring that even if the "power consumption test" is not actually performed, its potential failure information can be fully recorded for subsequent analysis.

[0108] Through the above technical solution, this application not only optimizes the chip testing process and improves testing efficiency, but also effectively solves the problem of incomplete test log data that may result from skipping test items. When the testing end determines that a preceding test item has failed and triggers a conditional jump instruction to skip the associated test item, it no longer simply skips it. Instead, it generates deduced failure data for the skipped associated test item based on the interception linkage relationship and fills it into the test log. This ensures the continuity, integrity, and traceability of the test log, enabling subsequent failure analysis, yield management, and quality traceability to be based on comprehensive data, avoiding misjudgments or analysis blind spots caused by missing data. Based on this, the solution in this embodiment improves testing efficiency while also ensuring the quality and availability of test data.

[0109] In one embodiment of this application, the specific process of "generating deduced failure data for the bypassed associated test item based on the interception linkage relationship and filling the deduced failure data into the test log" can be further explained in conjunction with the following description.

[0110] As described in the following steps Obtain the parameter recording specifications of the bypassed associated test items in the standard test data format, wherein the parameter recording specifications include the corresponding preset parameters for good quality upper and lower limits; Extract the measured parameter offset of the pre-test item corresponding to the conditional jump instruction, and convert the measured parameter offset into an associated deviation value according to a preset mapping conversion function; Based on the preset parameters for good products and the associated deviation value, calculate the virtual failure parameter value that exceeds the preset parameters for good products. The virtual failure parameter values ​​and the derived failure data are encapsulated into a fake test record according to the standard test data format, and the fake test record is written to the corresponding data stream node of the test log.

[0111] It should be noted that obtaining the parameter recording specifications for skipped related test items in the standard test data format aims to obtain the data structure and range definition that the skipped related test items should have in the test log. The parameter recording specifications can be a predefined XML file, a JSON schema, a database table structure definition, or a configuration file containing information such as field names, data types, units, and yield limits. Its purpose is to provide a benchmark and format constraints for subsequently generating virtual failure parameter values, ensuring consistency between the derived data and the actual test data.

[0112] Furthermore, the measured parameter offset of the preceding test item corresponding to the conditional jump instruction is extracted to obtain the direct cause of the skipped associated test item, i.e., the degree of failure of the preceding test item. The measured parameter offset refers to the deviation between the actual measured value of the preceding test item and its acceptable range, such as the nominal value or the lower / upper limit of the acceptable range. For example, if the preceding test item is a voltage measurement with an acceptable upper limit of 1.8V and a measured value of 1.9V, the offset is 0.1V. This measured parameter offset is a key input for assessing the potential failure degree of the associated test item. The measured parameter offset is converted into an associated deviation value according to a preset mapping transformation function, aiming to establish a quantitative relationship between the degree of failure of the preceding test item and the potential failure degree of the associated test item. The mapping transformation function can be a linear function, a non-linear function, a lookup table, or an algorithm based on a machine learning model. For example, the voltage offset of the preceding test item can be multiplied by a preset coefficient to obtain the resistance deviation value of the associated test item. This associated deviation value reflects the degree of influence of the failure of the preceding test item on the parameters of the associated test item.

[0113] Furthermore, the virtual failure parameter value can be calculated based on the yield limits of the associated test item and the associated deviation value derived from the failure of the preceding test item. For example, if the yield limit of the associated test item is 100 ohms and the associated deviation value is +10 ohms, then the virtual failure parameter value can be calculated as 110 ohms, indicating that the virtual failure parameter value exceeds the yield limit, which simulates the failure result that may occur if the associated test item is actually tested.

[0114] Finally, the virtual failure parameter values ​​and the derived failure data are encapsulated into a dummy test record according to the standard test data format. This aims to integrate the generated virtual failure parameter values ​​and other derived failure information (e.g., failure type, failure time, associated test item ID, etc.) into a data packet conforming to the standard test data format. The standard test data format can be STDF, ATDF, or other custom industry-standard data structures. Encapsulation ensures that the dummy test record can be seamlessly processed by subsequent data analysis tools and systems. Writing the dummy test record to the corresponding data stream node of the test log means storing the encapsulated dummy test record in the test log. The test log is typically a file, database, or data stream used to record all test processes and results. The corresponding data stream node refers to the storage location reserved or logically corresponding to the associated test item in the test log. By writing the dummy test record to the correct location, the integrity and consistency of the test log can be ensured, enabling subsequent failure analysis and yield management to process the derived data and actual test data together.

[0115] For example, as a specific implementation, suppose that when testing a chip under test, the measured parameter offset of the pre-test item "Power Supply Voltage Stability Test" is +0.2V, that is, the actual voltage is 0.2V higher than the upper limit, causing the associated test item "Output Drive Capability Test" to be skipped.

[0116] To generate deduced failure data for the "Output Drive Capability Test," the system first obtains the parameter recording specifications for the "Output Drive Capability Test" in the standard test data format. For example, this parameter recording specification might define the acceptable range of output current as 90mA to 110mA. Further, the system extracts the measured parameter offset of +0.2V from the "Power Supply Voltage Stability Test." Then, based on a preset mapping conversion function, +0.2V is converted into an associated deviation value of +1.0mA, indicating that a 0.2V offset in the power supply voltage may cause a 1.0mA deviation in the output current.

[0117] Based on this, according to the preset parameters of the "output drive capability test" (good product upper limit 110mA and associated deviation value +1.0mA), the virtual failure parameter value can be calculated to be 111.0mA, and this virtual failure parameter value exceeds the good product upper limit.

[0118] Finally, the virtual failure parameter value of 111.0mA and other derived failure data, such as the failure type "power-related failure" and failure timestamp, are encapsulated into a fake test record according to the STDF standard format and written into the STDF record node corresponding to "output drive capability test" in the test log.

[0119] Through the above technical solution, this application can generate structurally complete and reasonably deduced failure data for skipped related test items and integrate it into the test log. This solves the problem of incomplete test log data or incompatibility with standard formats that may occur during test optimization due to skipping some test items. Specifically, by obtaining parameter recording specifications, extracting the measured parameter offsets of preceding test items, performing mapping transformations, and calculating virtual failure parameter values, the solution in this embodiment can ensure that the deduced failure data not only has quantitative basis but also accurately simulates actual failure situations. Encapsulating this data as fake test records and writing it into the test log enables subsequent failure analysis, yield management, and quality traceability systems to uniformly process actual test data and deduced failure data, thereby improving the efficiency and accuracy of test data analysis, avoiding misjudgments or analysis blind spots caused by missing data, and ultimately enhancing the overall optimization effect and data value of chip testing.

[0120] As the system implementation is basically similar to the method implementation, it is described in a relatively simple way. For relevant details, please refer to the description of the method implementation.

[0121] Reference Figure 2 This illustration shows a chip testing optimization system based on sampling pre-inspection according to an embodiment of this application, which specifically includes the following modules: The stratified sampling module is used to perform stratified sampling of the chips to be tested to obtain a pre-inspection chip set. The rule determination module is used to perform initial test items on the pre-inspection chip set and determine the failure association rules between the initial test items based on the test results; The association determination module is used to extract test item pairs with a one-way failure association relationship from the initial test items based on the failure association rules. The test generation module is used to generate a full-scale test optimization scheme for the chip under test based on the test item pairs.

[0122] Reference Figure 3 The illustration shows a computer electronic device for implementing a chip testing optimization method based on sampling pre-inspection according to this application, which may specifically include the following: The aforementioned computer electronic device 1 is manifested in the form of a general-purpose computing device. The components of the computer electronic device 1 may include, but are not limited to: one or more processors or processing units 3, memory 8, and a bus 4 connecting different system components (including memory 8 and processing unit 3).

[0123] Bus 4 represents one or more of several bus architectures, including memory buses or memory controllers, peripheral buses, graphics acceleration ports, processors, or local buses using any of the various bus architectures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Audio / Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0124] Computer electronic device 1 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by computer electronic device 1, including volatile and non-volatile media, removable and non-removable media.

[0125] Memory 8 may include computer system readable media in the form of volatile memory, such as random access memory 9 and / or cache memory 10. Computer electronic device 1 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 11 may be used to read and write non-removable, non-volatile magnetic media (commonly referred to as a "hard disk drive"). Although Figure 3 As not shown, a disk drive for reading and writing to a removable non-volatile disk (such as a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (such as a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 4 via one or more data media interfaces. The memory may include at least one program product having a set (e.g., at least one) of program modules 13 configured to perform the functions of the embodiments of this application.

[0126] A program / utility 12 having a set (at least one) of program modules 13 may be stored, for example, in memory. Such program modules 13 include—but are not limited to—an operating system, one or more application programs, other program modules 13, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 13 typically perform the functions and / or methods described in the embodiments of this application.

[0127] The computer electronic device 1 can also communicate with one or more external devices 2 (e.g., keyboard, pointing device, display 7, camera, etc.), and with one or more devices that enable an operator to interact with the computer electronic device 1, and / or with any device that enables the computer electronic device 1 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed through the I / O interface 6. Furthermore, the computer electronic device 1 can also communicate with one or more networks (e.g., local area network (LAN)), wide area network (WAN), and / or public networks (e.g., the Internet) through the network adapter 5. Figure 3 As shown, network adapter 5 communicates with other modules of computer electronic device 1 via bus 4. It should be understood that, although... Figure 3 Not shown, it may be combined with other hardware and / or software modules, including but not limited to: microcode, device drivers, redundant processing unit 3, external disk drive array, RAID system, tape drive and data backup storage system 11, etc.

[0128] The processing unit 3 executes various functional applications and data processing by running programs stored in memory 8, such as implementing the steps of a chip testing optimization method based on sampling pre-inspection provided in the embodiments of this application.

[0129] That is, when the processing unit 3 executes the above program, it performs the following: performing stratified sampling of the chip to be tested to obtain a pre-inspection chip set; performing initial test items on the pre-inspection chip set, and determining the failure association rules between the initial test items based on the test results; extracting test item pairs with unidirectional failure association relationships from the initial test items based on the failure association rules; and generating a full-scale test optimization scheme for the chip to be tested based on the test item pairs.

[0130] In this application embodiment, the present application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of a chip testing optimization method based on sampling pre-inspection as provided in all embodiments of the present application.

[0131] That is, when the program is executed by the processor, it performs the following: performing stratified sampling of the chip to be tested to obtain a pre-inspection chip set; performing initial test items on the pre-inspection chip set, and determining the failure association rules between the initial test items based on the test results; extracting test item pairs with unidirectional failure association relationships from the initial test items based on the failure association rules; and generating a full-scale test optimization scheme for the chip to be tested based on the test item pairs.

[0132] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that includes or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0133] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including—but not limited to—electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0134] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the operator's computer, partially on the operator's computer, as a standalone software package, partially on the operator's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the operator's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider). The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably.

[0135] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0136] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0137] The foregoing has provided a detailed description of the methods and implementations of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A chip testing optimization method based on sampling pre-inspection, characterized in that, Including the following steps: The chips to be tested are sampled in layers to obtain a pre-test chip set; Initial test items are performed on the pre-test chip set, and failure association rules between the initial test items are determined based on the test results; Based on the failure association rules, test item pairs with a one-way failure association relationship are extracted from the initial test items; Based on the test items, a full-scale test optimization scheme for the chip under test is generated.

2. The chip testing optimization method based on sampling pre-inspection according to claim 1, characterized in that, The step of performing stratified sampling of the chips to be tested to obtain a pre-inspection chip set specifically includes: Obtain the batch parameters of the chip to be tested, including the total batch quantity, the number of wafers, and the wafer area distribution; The sampling quantity is determined based on the total quantity of the batch, and each wafer containing the chip to be tested is used as an independent sampling layer. Based on the wafer region distribution, sample chips are uniformly extracted from the central region, intermediate region and edge region of each wafer to obtain the pre-detection chip set.

3. The chip testing optimization method based on sampling pre-inspection according to claim 1, characterized in that, The step of performing initial tests on the pre-detection chip set and determining the failure association rules between the initial test items based on the test results specifically includes: An initial test item is performed on the pre-detection chip set, and the test results of each chip in the pre-detection chip set on each initial test item are collected. The number of failed chips for each initial test item in the statistical test results is determined, and the ratio of the number of failed chips to the total number of chips in the pre-inspection chip set is determined as the failure distribution characteristic. The initial test items whose failure distribution characteristics exceed a preset probability threshold are selected as candidate correlation test items; For any two candidate association test items, the number of failed chips in one of the candidate association test items is used as the condition base to calculate the proportion of failed chips in the other candidate association test item, thus obtaining the conditional failure probability. The failure association rule is generated based on the failure probability of the condition.

4. The chip testing optimization method based on sampling pre-inspection according to claim 3, characterized in that, The step of calculating the proportion of failed chips in the other candidate test item for any two candidate related test items, using the number of failed chips in one candidate related test item as the conditional base, to obtain the conditional failure probability, specifically includes: Use any two of the candidate association test items as the first test item and the second test item, respectively. The pre-detection chips that fail based on the test results of the first test item constitute a condition sample set, and the number of chips in the condition sample set is used as the condition base. In the statistical sample set under the given conditions, the intersection chips whose test results for the second test item are invalid; Obtain the measured parameter offset of the intersection chip on the second test item, and set the association weight for the intersection chip based on the measured parameter offset; The association weights of each intersection chip are summed to obtain a weighted intersection value, and the ratio of the weighted intersection value to the condition base is determined as the condition failure probability.

5. The chip testing optimization method based on sampling pre-inspection according to claim 3, characterized in that, The step of generating the failure association rule based on the conditional failure probability specifically includes: Extract the wafer coordinate data of each pre-detection chip in the pre-detection chip set, and divide the conditional failure probability into the central region conditional probability, the middle region conditional probability, and the edge region conditional probability based on the wafer coordinate data. Compare the numerical dispersion of the conditional probabilities of the central region, the intermediate region, and the edge region. If the numerical dispersion is greater than the preset regional drift threshold, then a regional failure association rule is generated.

6. The chip testing optimization method based on sampling pre-inspection according to claim 1, characterized in that, The test item pair includes pre-test items and related test items. The step of generating a full-scale test optimization scheme for the chip under test based on the test item pair specifically includes: The preceding test items and the associated test items are mapped to preceding test nodes and derived test nodes in the test program, respectively, and a conditional bypass path from the preceding test node to the derived test node is constructed in the test program. In the test program, a status monitoring instruction is configured for the pre-test node. The status monitoring instruction is used to capture the test results of the pre-test item in real time when the test is executed at the test end. The test program configured with the state monitoring instructions and the conditional detour path is encapsulated into the full-scale test optimization scheme.

7. The chip testing optimization method based on sampling pre-inspection according to claim 6, characterized in that, After the step of generating a full-scale test optimization scheme for the chip under test based on the test item pair, the specific steps include: Extract the initial execution order of the pre-test items and the associated test items in the initial test program; If the initial execution order of the pre-test item lags behind the associated test item, then the execution order of the pre-test item is reconstructed to precede the associated test item to construct a timing interception path; Based on the timing interception path, conditional jump instructions are configured between the pre-test item and the associated test item to form an interception linkage relationship.

8. The chip testing optimization method based on sampling pre-inspection according to claim 7, characterized in that, After the step of configuring conditional jump instructions between the pre-test item and the associated test item based on the timing interception path to form an interception linkage relationship, the specific steps include: The full-scale test optimization scheme is distributed to the test terminal to perform tests on the chip under test sequentially; When the test terminal determines that the test result of the pre-test item is invalid, the conditional jump instruction is triggered; In response to the triggering of the conditional jump instruction, the corresponding associated test item is bypassed along the timing interception path in the test control flow to block the transmission of the physical test signal corresponding to the associated test item to the chip under test; Based on the interception linkage relationship, inferred failure data is generated for the bypassed associated test items, and the inferred failure data is filled into the test log.

9. The chip testing optimization method based on sampling pre-inspection according to claim 8, characterized in that, The step of generating deduced failure data for the bypassed associated test item based on the interception linkage relationship, and filling the deduced failure data into the test log, specifically includes: Obtain the parameter recording specifications of the bypassed associated test items in the standard test data format, wherein the parameter recording specifications include the corresponding preset parameters for good quality upper and lower limits; Extract the measured parameter offset of the pre-test item corresponding to the conditional jump instruction, and convert the measured parameter offset into an associated deviation value according to a preset mapping conversion function; Based on the preset parameters for good products and the associated deviation value, calculate the virtual failure parameter value that exceeds the preset parameters for good products. The virtual failure parameter values ​​and the derived failure data are encapsulated into a fake test record according to the standard test data format, and the fake test record is written to the corresponding data stream node of the test log.

10. A chip testing optimization system based on sampling pre-inspection, characterized in that, include: The stratified sampling module is used to perform stratified sampling of the chips to be tested to obtain a pre-inspection chip set. The rule determination module is used to perform initial test items on the pre-inspection chip set and determine the failure association rules between the initial test items based on the test results; The association determination module is used to extract test item pairs with a one-way failure association relationship from the initial test items based on the failure association rules. The test generation module is used to generate a full-scale test optimization scheme for the chip under test based on the test item pairs.

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