An integrated circuit chip testing system and testing method

Abstract

The application discloses an integrated circuit chip test system and a test method, and relates to the technical field of integrated circuit chip testing.The system comprises a logic built-in self-test controller, a scan chain circuit, a clock management module, a scan chain multiplexing time delay sampling unit, a path aging grading unit, a test vector subset mapping storage unit and a dynamic scheduling controller.The actual propagation time delay of a single key path is collected by multiplexing the existing scan chain circuit, the path aging grade division and aging trend calculation are completed, the pre-stored test vector subset mapping relationship is combined, and the execution frequency and period of corresponding tests are scheduled according to the path aging grade.The application can differentially allocate test resources according to the key paths with different aging degrees, balance the fault detection reliability and test resource overhead, and is suitable for online aging monitoring and logic fault self-test scenes of high-reliability chips.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit chip testing technology, specifically to an integrated circuit chip testing system and testing method. Background Technology

[0002] With the continuous evolution of integrated circuit process nodes, the requirements for chip reliability throughout its entire lifecycle are constantly increasing in fields such as automotive electronics, industrial control, and aerospace. During long-term service, chips are affected by degradation effects such as negative bias temperature instability and hot carrier injection, causing the threshold voltage of internal transistors to drift. This leads to increased logic path propagation delay, and in severe cases, timing violations, resulting in chip failure. Built-in logic self-test, as a core technology for ensuring chip online reliability, can autonomously complete logic fault detection during chip operation without relying on external testing equipment. It has become a standard design module for high-reliability chips. With the increasingly significant differences in path aging characteristics in advanced processes, the adaptive adaptation capability of the test scheme has become a key factor determining the effectiveness of chip reliability assurance.

[0003] Existing logic-integrated self-test solutions generally adopt an architecture with fixed test vector sets and fixed test cycles, executing a unified standard test process on all logic paths within the chip. Some optimization solutions introduce aging awareness mechanisms to improve test adaptability. For example, a processor and method for measuring aging compensation voltage (publication number CN121412172A) collects the overall operating parameters of the chip through a built-in self-test circuit, calculates the aging compensation voltage, and adjusts the power supply parameters to mitigate the impact of aging on chip performance from a global perspective. The above solutions can achieve aging status awareness and performance compensation at the overall chip level. However, their aging monitoring granularity and test adjustment granularity are limited to the module or chip level, which cannot distinguish the differentiated aging rates and degradation degrees of different critical paths. Consequently, it is impossible to match corresponding test resources to the actual aging degree of a single critical path. This results in high-risk paths with faster aging rates not receiving sufficient test coverage, leading to a higher risk of missed delay faults. At the same time, paths with lighter aging degrees continue to undergo redundant testing, generating unnecessary power consumption and time overhead. It is difficult to achieve a precise balance between test reliability assurance and test resource consumption. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide an integrated circuit chip testing system and testing method to solve the problem that existing logic-built-in self-test schemes cannot accurately allocate test resources for the differentiated aging degree of a single critical path, resulting in a high risk of missed detection of delay faults in high-risk aging paths and waste of redundant test resources.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In one aspect, an integrated circuit chip testing system includes a built-in self-test controller, a scan chain circuit, a clock management module, a scan chain multiplexing delay sampling unit, a path aging classification unit, a test vector subset mapping storage unit, and a dynamic scheduling controller. The built-in self-test controller is electrically connected to the scan chain circuit. The clock management module provides a working clock signal to the scan chain circuit. The scan chain multiplexing delay sampling unit is electrically connected to both the scan chain circuit and the clock management module, and is used to collect the actual propagation delay of each critical path inside the chip through the scan chain circuit. The path aging classification unit is electrically connected to the scan chain multiplexing delay sampling unit, and is used to complete the path aging level classification and aging trend calculation based on the collected delay data. The test vector subset mapping storage unit is electrically connected to the dynamic scheduling controller, and is used to store the corresponding mapping relationship between critical paths and test vector subsets. The dynamic scheduling controller is electrically connected to the built-in self-test controller, and is used to schedule the execution frequency and execution cycle of the corresponding test vector subset according to the path aging level.

[0006] Furthermore, the scan chain multiplexing delay sampling unit includes a phase adjustment submodule and a transition capture submodule. The phase adjustment submodule is connected to the clock management module and is used to adjust the clock phase of the capture end scan trigger. The transition capture submodule is connected to the output scan trigger of the scan chain circuit and is used to detect the transition signal output by the path and record the corresponding clock phase. The scan chain multiplexing delay sampling unit calculates the actual propagation delay of the target critical path using the following formula: In the formula, This represents the actual propagation delay of the target's critical path. This represents the transmit clock phase value of the test transition signal of the transmitter scan trigger. This indicates the phase offset relative to the transmit clock when the capture end scan trigger successfully acquires the transition signal.

[0007] Furthermore, the path aging grading unit includes a reference register, a drift calculation submodule, and a grade mapping submodule. The reference register is used to determine the initial reference latency of each critical path during the chip manufacturing process. The drift calculation submodule is connected to the reference register and the scan chain multiplexing latency sampling unit, respectively, and is used to calculate the latency drift rate of each critical path. The grade mapping submodule is connected to the drift calculation submodule and is used to match the corresponding aging level based on the latency drift rate. The latency drift rate is calculated using the following formula: In the formula, This represents the latency drift rate of the target critical path. This indicates the actual propagation delay of the target critical path currently collected. This represents the initial reference delay of the target critical path stored in the reference register.

[0008] Furthermore, the test vector subset mapping storage unit adopts an on-chip read-only memory structure, storing three sets of corresponding data: path number, vector subset number, and total number of vectors in a single subset. The mapping relationship within the test vector subset mapping storage unit is generated through fault simulation during the chip design phase and is permanently stored after tape-out. Each vector subset corresponds to and covers the delay fault detection of at least one critical path. The critical path ranges covered by different vector subsets do not overlap. The dynamic scheduling controller reads the corresponding relationship within the mapping storage unit, retrieves the corresponding test vector subset, and sends it to the logic-built-in self-test controller for execution.

[0009] Furthermore, the dynamic scheduling controller includes a level matching submodule and a fragmented execution submodule. The level matching submodule is connected to the path aging classification unit and is used to match the execution cycle and number of repetitions of the corresponding test vector subset according to the aging level of each critical path. The fragmented execution submodule is connected to the chip system bus and is used to identify the chip's idle time slots, split the test vector subset into multiple short segments, and insert them into the idle time slots for execution. The dynamic scheduling controller adjusts the scheduling parameters of the next round of testing in real time according to the updated aging level, thus completing closed-loop adaptive scheduling.

[0010] On the other hand, an integrated circuit chip testing method, applicable to an integrated circuit chip testing system, includes a reference delay calibration step and a global test execution step, a path delay sampling step, an aging grade calculation step, and a dynamic scheduling generation step. The path delay sampling step collects the actual propagation delay of each critical path inside the chip by reusing the chip's existing scan chain circuit. The aging grade calculation step calculates the delay drift rate of each critical path and matches the corresponding aging level based on the collected delay data. The dynamic scheduling generation step generates the execution frequency and execution cycle scheme of the corresponding test vector subset based on the path aging level, driving the built-in self-test controller to execute the corresponding test.

[0011] Furthermore, the aging grading calculation step also includes an aging trend prediction sub-step. This sub-step uses a sliding window mechanism to store multiple consecutive sets of time-delay sampling data, obtains the aging rate of the target critical path through least squares fitting, calculates the remaining time for the path to reach a preset aging level threshold based on the aging rate, and adjusts the aging level of the corresponding path based on the calculation results. The aging rate is calculated using the following formula: In the formula, This represents the aging rate of the target's critical path. This indicates the total number of delay samples included within the sliding window. This indicates the sampling sequence number within the sliding window. This represents the target critical path delay drift rate obtained from the i-th sampling.

[0012] Furthermore, the reference delay calibration step is performed during the chip factory testing phase. During the calibration process, the chip runs in a standard test environment and performs delay acquisition on all critical paths in sequence. The acquired delay data of each path is written into the reference storage unit as the initial reference value. After each complete global test, the reference value is automatically verified and updated to eliminate systematic measurement deviations caused by fluctuations in ambient temperature and power supply voltage, and to ensure the reference consistency of delay drift calculation.

[0013] Furthermore, the path delay sampling step is performed during the idle time slots of the chip's normal operation. The sampling process is carried out one by one along the path, and each single path sampling only occupies a few clock cycles. The sampling operation does not interrupt the execution of the chip's normal functions. The sampling process is uniformly managed by the dynamic scheduling controller, which dynamically adjusts the sampling progress according to the system's idle state, prioritizing the completion of delay acquisition for paths with high aging levels, and ensuring that the time overhead of the sampling operation is controllable.

[0014] Furthermore, the test scheme generated by the dynamic scheduling generation step adopts a fragmented execution mode. The complete subset of test vectors is split into multiple test segments of fixed length. Each test segment is executed within a single idle time slot. Different aging levels correspond to different test segment insertion densities. The higher the aging level of the path, the shorter the insertion interval of the corresponding test segment. The execution results of all test segments are uniformly sent to the feature comparison module for verification. When abnormal results occur, a system alarm is triggered.

[0015] Compared with existing technologies, this integrated circuit chip testing system and method have the following advantages:

[0016] I. This invention, by setting a path-level granular latency sampling and aging classification architecture, combined with a mapping and storage mechanism between critical paths and test vector subsets and a dynamic scheduling controller, can match the corresponding test resource investment to the actual aging degree of a single critical path. It increases the test execution frequency for high-risk paths with deeper aging and reduces redundant test execution for paths with lighter aging, thereby effectively improving the latency fault detection coverage of high-risk aging paths and reducing the risk of missed detection. At the same time, it controls the overall test operation time and power consumption, achieving a more precise balance between test reliability assurance and test resource consumption.

[0017] Second, this invention completes path delay sampling by reusing the existing scanning chain circuit of the chip. Combined with the idle time slot fragmented test execution mode and aging trend prediction mechanism, it can avoid inserting dedicated monitoring devices in the functional logic path, reduce hardware design modification costs and additional path delay overhead, and adapt to the chip online operation scenario. The test execution does not interfere with the normal operation of the main function. It can also predict the path degradation trend in advance and adjust the test strategy in advance, further enhancing the reliability assurance capability of the chip throughout its entire life cycle.

[0018] Other advantages, objectives and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination or study, or may be learned from the practice of the invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a block diagram of the overall system architecture of the present invention;

[0021] Figure 2 This is a flowchart of the method of the present invention;

[0022] Figure 3 This is a schematic diagram illustrating the scanning chain multiplexing delay sampling principle of the present invention. Detailed Implementation

[0023] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.

[0024] As attached Figure 1-3 As shown, an integrated circuit chip testing system is integrated inside a digital integrated circuit chip for online aging monitoring and adaptive fault testing throughout the chip's entire lifecycle.

[0025] Specifically, the integrated circuit chip testing system includes a built-in self-test controller, a scan chain circuit, a clock management module, a scan chain multiplexing delay sampling unit, a path aging and grading unit, a test vector subset mapping and storage unit, and a dynamic scheduling controller. The built-in self-test controller is electrically connected to the scan chain circuit and is used to generate test stimulus sequences. The scan chain circuit loads the stimuli onto the chip's internal logic nodes and collects the test responses output by the scan chain, completing fault feature comparison and result determination. The clock management module is electrically connected to the scan chain circuit and is used to output multi-phase clock signals, providing the scan chain circuit with the operating clock for both normal functional mode and test mode.

[0026] The scan chain multiplexing delay sampling unit is electrically connected to both the scan chain circuit and the clock management module. It is used to collect the actual propagation delay of each critical path within the chip using the transmit and capture nodes of the scan chain circuit. The path aging classification unit is electrically connected to the scan chain multiplexing delay sampling unit. It is used to classify the path aging level based on the real-time acquired delay data and calculate the path aging development trend. The test vector subset mapping storage unit is electrically connected to the dynamic scheduler controller. It is used to store the corresponding mapping relationship between critical paths and test vector subsets. The dynamic scheduler controller is electrically connected to the logic-built-in self-test controller. It is used to schedule the execution frequency and execution cycle of the corresponding test vector subset according to the current path aging level.

[0027] In some optional implementations, the scan chain multiplexing delay sampling unit includes a phase adjustment submodule and a transition capture submodule. The phase adjustment submodule is connected to the clock management module and is used to receive the reference clock signal and generate multiple sets of capture clocks with phase step offsets, which are then output to the clock port of the capture end scan trigger. The transition capture submodule is connected to the data output port of the output end scan trigger of the scan chain circuit and is used to detect level transitions in the path output signal and latch the clock phase value corresponding to the moment the transition occurs.

[0028] The delay sampling employs a transmit-capture mechanism. The transmitter's scan trigger outputs a test transition signal at the effective edge of the transmit clock. This transition signal propagates along the combinational logic of the target critical path, eventually reaching the data input of the capture trigger. The phase adjustment submodule starts with an initial value in phase with the transmit clock and gradually increases the phase offset of the capture clock in fixed steps. When the effective edge of the capture clock precisely captures the transition signal at the input, the transition capture submodule determines successful capture and records the phase offset at that moment.

[0029] The scan chain multiplexing delay sampling unit calculates the actual propagation delay of the target critical path using the following formula:

[0030]

[0031] In the formula, It represents the actual propagation delay of the target critical path, that is, the length of time it takes for the transition signal to propagate from the path input end to the path output end. This represents the phase value of the transmit clock for the test transition signal of the transmitter scan trigger, which is the phase scale corresponding to the effective transmit edge under the reference clock system. This indicates the phase offset of the capture clock relative to the transmit clock when the capture end scan trigger successfully acquires the transition signal. It is the phase difference value cumulatively adjusted by the phase adjustment submodule.

[0032] It is understandable that this sampling method fully reuses the standard scan triggers in the original scan chain of the chip as sampling nodes, without the need to insert dedicated monitoring devices in the functional path, and will not introduce additional path delay and hardware overhead. At the same time, it can realize delay measurement at the granularity of a single critical path, and the monitoring accuracy is better than the traditional module-level overall monitoring scheme.

[0033] In some optional implementations, the path aging and grading unit includes a reference register, a drift calculation submodule, and a grade mapping submodule. The reference register employs an on-chip non-volatile memory structure to store the initial reference latency of each critical path calibrated during the chip's manufacturing phase. The drift calculation submodule is connected to both the reference register and the scan chain multiplexed latency sampling unit, and is used to read the current sampled latency and corresponding initial reference latency of the target path to calculate the latency drift rate of that path. The grade mapping submodule is connected to the drift calculation submodule and has a pre-configured mapping table between latency drift rate ranges and aging grades, used to match and output the corresponding aging grade based on the calculated latency drift rate.

[0034] The time delay drift rate is calculated using the following formula:

[0035]

[0036] In the formula, This represents the latency drift rate of the target critical path, used to quantify the relative degradation of the path's current latency relative to the initial baseline. A larger value indicates a deeper level of path aging. This indicates the actual propagation delay of the target critical path currently collected, which is output in real time by the scan chain multiplexing delay sampling unit. This represents the initial reference delay of the target critical path stored in the reference register. It is the path delay reference value collected under standard conditions during the chip factory calibration stage.

[0037] For example, the aging level mapping submodule can be divided into multiple aging levels, with different levels corresponding to different drift rate ranges. A lower drift rate corresponds to a lower aging level, and as the drift rate increases during the aging process, the corresponding aging level increases accordingly. The threshold values ​​for the aging level division can be set during the chip design phase based on the process node, operating scenario, and reliability requirements, and remain a fixed configuration after tape-out.

[0038] In some optional implementations, the test vector subset mapping storage unit adopts an on-chip read-only memory structure, storing three sets of corresponding data: path number, vector subset number, and total number of vectors in a single subset. The mapping relationship within the test vector subset mapping storage unit is generated during the chip design phase using fault simulation tools, and after fault coverage verification, it is permanently stored and cannot be modified after tape-out. Each vector subset corresponds to and covers at least one critical path for delay fault detection; the critical path ranges covered by different vector subsets do not overlap, and there are no overlapping path sets. The dynamic scheduling controller reads the correspondence within the mapping storage unit, retrieves the corresponding test vector subset according to the path number, and sends it to the built-in self-test controller for execution.

[0039] It is understandable that adopting a subset partitioning and mapping storage architecture can achieve a one-to-one correspondence between test resources and path aging states, avoiding the redundant overhead caused by uniformly executing the full test vector. The independent design of different subsets also facilitates individual retrieval and execution during scheduling, without the need for real-time splitting and calculation of the entire test set, thus reducing the computational load on the scheduling controller.

[0040] In some optional implementations, the dynamic scheduling controller includes a level matching submodule and a fragmented execution submodule. The level matching submodule is connected to the path aging classification unit and is used to receive the real-time aging level of each critical path, and match and generate the execution cycle and number of repetitions for the corresponding test vector subset. The higher the aging level of the path, the shorter the execution cycle of the corresponding test vector subset and the more repetitions per unit time, ensuring that high-risk paths receive sufficient fault detection frequency.

[0041] The fragmented execution submodule connects to the chip's system bus and is used to identify idle time slots during chip operation in real time. It splits a subset of test vectors into multiple short test segments of fixed length and inserts them into the idle time slots for execution. The fragmented execution submodule determines the length of the currently available idle time slot by monitoring signals such as system bus load and functional module idle flags, and selects test segments of matching length for insertion and execution. The test execution process does not interrupt the normal operation of the chip.

[0042] The dynamic scheduling controller adjusts the scheduling parameters for the next round of testing in real time based on the updated aging levels, completing closed-loop adaptive scheduling. Whenever the path aging classification unit outputs updated aging level data, the level matching submodule immediately refreshes the scheduling parameters of the corresponding vector subset, and the fragmented execution submodule adjusts the insertion rhythm of subsequent test segments according to the updated parameters, realizing dynamic synchronization between the test strategy and the aging state.

[0043] The present invention also provides an integrated circuit chip testing method applicable to the aforementioned integrated circuit chip testing system, including a reference delay calibration step, a global test execution step, a path delay sampling step, an aging grade calculation step, and a dynamic scheduling generation step.

[0044] The baseline latency calibration step is performed during the chip's factory testing phase to establish initial latency baselines for each critical path. During calibration, the chip operates in a standard test environment, with ambient temperature and supply voltage maintained at their rated values. The system sequentially acquires latency data for all critical paths, and after multiple samplings for each path, a stable value is taken as the baseline latency for that path. The acquired latency data for each path is written to the baseline storage unit as the initial baseline value, completing the calibration process.

[0045] After each complete global test, the system automatically verifies and updates the baseline values ​​to eliminate systematic measurement deviations caused by fluctuations in ambient temperature and power supply voltage. The verification process selects a reference path with stable aging levels as the calibration benchmark. The overall benchmark dataset is corrected based on the delay fluctuations of the reference path to ensure the consistency of delay drift calculations and avoid interference from environmental factors in the aging determination results.

[0046] The global test execution step is used to perform full-scale testing at the initial stage of chip power-on or at a set long-cycle node, completing basic fault detection and benchmark calibration throughout the entire path. During execution, the logic's built-in self-test controller retrieves the complete test vector set, completes the traversal test of the entire chip logic path through the scan chain circuit, and outputs the overall fault detection results.

[0047] The path delay sampling step collects the actual propagation delay of each critical path within the chip by reusing the chip's existing scan chain circuit. This step is performed during the idle time slots of normal chip operation. The sampling process is carried out one by one along the path, with each single path sampling taking only a few clock cycles. The sampling operation does not interrupt the normal execution of the chip's functions.

[0048] The sampling process is centrally managed by a dynamic scheduling controller, which dynamically adjusts the sampling progress based on the system's idle status. The sampling rate is increased when system resources are plentiful and decreased when resources are scarce. The scheduling process prioritizes latency acquisition for high-aging-level paths to ensure timely monitoring of high-risk paths, guaranteeing that the sampling operation's time overhead is controllable and will not significantly impact the chip's main functional performance.

[0049] The aging grading calculation step calculates the latency drift rate of each critical path based on the collected latency data and matches it with the corresponding aging level. This step also includes an aging trend prediction sub-step, which is used to predict the aging trend of the path and adjust the testing strategy in advance.

[0050] The aging trend prediction sub-step employs a sliding window mechanism to store multiple consecutive sets of time delay sampling data. The window retains the latest sets of sampling results, and removes the oldest set of data each time new sampling data is added, maintaining a constant window size. The time delay drift rate data within the window is linearly fitted using the least squares method to obtain the aging rate of the target critical path, characterizing the increase in path time delay drift rate within a unit sampling period.

[0051] Based on the calculated aging rate, the remaining time before the path reaches the preset aging level threshold is estimated. If the estimated remaining time is less than the set threshold, the path is upgraded to the corresponding aging level in advance, thereby increasing the testing intensity and enabling early fault warning.

[0052] The aging rate is calculated using the following formula:

[0053]

[0054] In the formula, The aging rate of the target critical path is represented by the slope of the delay drift rate obtained by linear fitting as a function of the sampling sequence number. A positive value indicates that the path delay continues to increase with sampling and the aging process continues. This represents the total number of time delay samples included within the sliding window, which is the fixed capacity of the sliding window. i represents the sampling sequence number within the sliding window, increasing sequentially from 1 to n according to the sampling time. This represents the target critical path delay drift rate obtained from the i-th sampling, which is output by the drift calculation submodule for the corresponding sampling batch.

[0055] It is understandable that introducing aging trend prediction can increase the test coverage density in advance before the path actually reaches a high aging level, make up for the monitoring lag caused by periodic sampling, and further reduce the risk of missed detection of delayed faults.

[0056] The dynamic scheduling generation step generates an execution frequency and cycle scheme for the corresponding test vector subset based on the path aging level, and drives the built-in self-test controller to execute the corresponding tests. The test scheme generated in this step adopts a fragmented execution mode, where the complete test vector subset is split into multiple fixed-length test segments, and each test segment is executed within a single idle time slot.

[0057] Different aging levels correspond to different test segment insertion densities. The higher the aging level of the path, the shorter the insertion interval of the corresponding test segments, and the more test vectors are executed per unit time. The execution results of all test segments are uniformly sent to the feature comparison module for verification. The feature comparison module compares the test response with the preset standard feature values. When abnormal results are found, the system alarm is triggered, and the fault path number and abnormality type are reported.

[0058] Workflow: During the chip manufacturing process, a baseline latency calibration is first performed. Initial latency data is acquired for all critical paths under a standard testing environment, and the baseline values ​​are written to the baseline register. Simultaneously, the mapping relationship of the test vector subsets is fixed. After the chip powers on, a global test is first performed to complete initial fault detection and baseline value verification.

[0059] Once in normal operation, the system performs latency sampling of each critical path sequentially according to priority during chip idle time slots. After each sampling, the path aging classification unit calculates the latency drift rate of the corresponding path, matches the current aging level, updates the sliding window data, and calculates the aging rate to complete trend prediction and level pre-adjustment.

[0060] The dynamic scheduling controller adjusts the execution cycle and frequency of the corresponding test vector subset based on the updated aging level, and inserts test segments into idle time slots of the system through the fragmented execution submodule. The test execution results are sent to the feature comparison module in real time for verification, and an alarm is triggered when an anomaly is detected. The system cyclically executes the closed-loop process of sampling, grading, scheduling, and testing, and runs continuously throughout the entire life cycle of the chip.

[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. An integrated circuit chip testing system, characterized in that, The system includes a built-in self-test controller, a scan chain circuit, a clock management module, a scan chain multiplexing delay sampling unit, a path aging classification unit, a test vector subset mapping storage unit, and a dynamic scheduling controller. The built-in self-test controller is electrically connected to the scan chain circuit. The clock management module provides a working clock signal to the scan chain circuit. The scan chain multiplexing delay sampling unit is electrically connected to both the scan chain circuit and the clock management module, and is used to collect the actual propagation delay of each critical path inside the chip through the scan chain circuit. The path aging classification unit is electrically connected to the scan chain multiplexing delay sampling unit, and is used to complete the path aging level classification and aging trend calculation based on the collected delay data. The test vector subset mapping storage unit is electrically connected to the dynamic scheduling controller, and is used to store the corresponding mapping relationship between critical paths and test vector subsets. The dynamic scheduling controller is electrically connected to the built-in self-test controller, and is used to schedule the execution frequency and execution cycle of the corresponding test vector subset according to the path aging level.

2. The integrated circuit chip testing system according to claim 1, characterized in that, The scan chain multiplexing delay sampling unit includes a phase adjustment submodule and a transition capture submodule. The phase adjustment submodule is connected to the clock management module and is used to adjust the clock phase of the capture end scan trigger. The transition capture submodule is connected to the output scan trigger of the scan chain circuit and is used to detect the transition signal output by the path and record the corresponding clock phase. The scan chain multiplexing delay sampling unit calculates the actual propagation delay of the target critical path using the following formula: In the formula, This represents the actual propagation delay of the target's critical path. This represents the transmit clock phase value of the test transition signal of the transmitter scan trigger. This indicates the phase offset relative to the transmit clock when the capture end scan trigger successfully acquires the transition signal.

3. The integrated circuit chip testing system according to claim 2, characterized in that, The path aging and grading unit includes a reference register, a drift calculation submodule, and a grade mapping submodule. The reference register is used to determine the initial reference latency of each critical path during the chip manufacturing process. The drift calculation submodule is connected to the reference register and the scan chain multiplexing latency sampling unit, and is used to calculate the latency drift rate of each critical path. The grade mapping submodule is connected to the drift calculation submodule and is used to match the corresponding aging level based on the latency drift rate. The latency drift rate is calculated using the following formula: In the formula, This represents the latency drift rate of the target critical path. This indicates the actual propagation delay of the target critical path currently collected. This represents the initial reference delay of the target critical path stored in the reference register.

4. The integrated circuit chip testing system according to claim 1, characterized in that, The test vector subset mapping storage unit adopts an on-chip read-only memory structure, storing three sets of corresponding data: path number, vector subset number, and total number of vectors in a single subset. The mapping relationship within the test vector subset mapping storage unit is generated through fault simulation during the chip design phase and is permanently stored after tape-out. Each vector subset corresponds to and covers at least one critical path for delay fault detection. The critical path ranges covered by different vector subsets do not overlap. The dynamic scheduling controller reads the corresponding relationship within the mapping storage unit, retrieves the corresponding test vector subset, and sends it to the built-in self-test controller for execution.

5. The integrated circuit chip testing system according to claim 1, characterized in that, The dynamic scheduling controller includes a level matching submodule and a fragmented execution submodule. The level matching submodule is connected to the path aging classification unit and is used to match the execution cycle and number of repetitions of the corresponding test vector subset according to the aging level of each critical path. The fragmented execution submodule is connected to the chip system bus and is used to identify the chip's idle time slots, split the test vector subset into multiple short segments, and insert them into the idle time slots for execution. The dynamic scheduling controller adjusts the scheduling parameters of the next round of testing in real time according to the updated aging level, thus completing closed-loop adaptive scheduling.

6. A method for testing integrated circuit chips, applicable to the integrated circuit chip testing system according to any one of claims 1 to 5, characterized in that, The test includes a baseline latency calibration step, a global test execution step, a path latency sampling step, an aging grade calculation step, and a dynamic scheduling generation step. The path latency sampling step collects the actual propagation latency of each critical path within the chip by reusing the chip's existing scan chain circuit. The aging grade calculation step calculates the latency drift rate of each critical path and matches it with the corresponding aging grade based on the collected latency data. The dynamic scheduling generation step generates the execution frequency and execution cycle scheme of the corresponding test vector subset based on the path aging grade, and drives the built-in self-test controller to execute the corresponding test.

7. The integrated circuit chip testing method according to claim 6, characterized in that, The aging grading calculation step further includes an aging trend prediction sub-step. This sub-step uses a sliding window mechanism to store multiple consecutive sets of time-delay sampling data, obtains the aging rate of the target critical path through least squares fitting, calculates the remaining time for the path to reach a preset aging level threshold based on the aging rate, and adjusts the aging level of the corresponding path based on the calculation results. The aging rate is calculated using the following formula: In the formula, This represents the aging rate of the target's critical path. This indicates the total number of delay samples included within the sliding window. This indicates the sampling sequence number within the sliding window. This represents the target critical path delay drift rate obtained from the i-th sampling.

8. The integrated circuit chip testing method according to claim 6, characterized in that, The reference delay calibration step is performed during the chip factory testing phase. During the calibration process, the chip runs in a standard test environment and performs delay acquisition on all critical paths in sequence. The acquired delay data of each path is written into the reference storage unit as the initial reference value. After each complete global test, the reference value is automatically verified and updated to eliminate systematic measurement deviations caused by fluctuations in ambient temperature and power supply voltage, and to ensure the reference consistency of delay drift calculation.

9. The integrated circuit chip testing method according to claim 6, characterized in that, The path delay sampling step is performed during the idle time slots of the chip's normal operation. The sampling process is carried out one by one along the path, and each single path sampling only occupies a few clock cycles. The sampling operation does not interrupt the execution of the chip's normal functions. The sampling process is uniformly managed by the dynamic scheduling controller, which dynamically adjusts the sampling progress according to the system's idle state, prioritizing the completion of delay acquisition for paths with high aging levels, and ensuring that the time overhead of the sampling operation is controllable.

10. The integrated circuit chip testing method according to claim 6, characterized in that, The test scheme generated by the dynamic scheduling generation step adopts a fragmented execution mode. The complete subset of test vectors is split into multiple test segments of fixed length. Each test segment is executed in a single idle time slot. Different aging levels correspond to different test segment insertion densities. The higher the aging level of the path, the shorter the insertion interval of the corresponding test segment. The execution results of all test segments are uniformly sent to the feature comparison module for verification. When abnormal results occur, a system alarm is triggered.

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