A testability design system

Abstract

This application provides a design-for-testability system, relating to the field of integrated circuit testing technology. The system includes: a main test access port, used to generate multiple control signals for multiple state branches based on externally input test signals, wherein the multiple state branches are branches possessed by the state machine within the main test access port; a configuration register, used to address and distribute serial configuration data with address identifiers based on the multiple control signals, generating scan chain mode control signals, interface routing control signals, and flexible parallel port control signals; a segmented scan chain, used to select paths for register segments within the die based on the scan chain mode control signals input to the configuration register; and a secondary test access port interface circuit, used to switch the routing of test signals and test response signals based on the interface routing control signals input to the configuration register, outputting downlink test signals and selected uplink test response signals to each slave die.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to a testability design system. Background Technology

[0002] As integrated circuit manufacturing processes gradually approach their physical limits and the cost of single-chip design continues to rise, heterogeneous integration solutions that integrate multiple chips with different functions into the same system-in-package using advanced packaging technology have become an important technological path to sustain the growth of chip computing power and integration.

[0003] In related technologies, Design for Testability (DPT) typically builds a test access architecture for multi-chip integrated scenarios based on the IEEE 1838 standard. The test access port on the master chip receives externally input test signals, and each slave chip is connected in series to the test path in a serial daisy chain manner, thereby covering the test of the internal circuits of each chip and the interconnection relationship between chips.

[0004] However, in the 2.5D packaging scenario, since each chip is connected in a serial dependency relationship in the test path, once a chip or its corresponding interconnect fails and breaks the circuit, all chips after the failure point will lose testability because the test signal cannot be transmitted, leaving room for further optimization. Summary of the Invention

[0005] In view of the above problems, this application provides a design-testability system.

[0006] This application provides a design for testability system, comprising: a main test access port for generating multiple control signals for multiple state branches based on externally input test signals, wherein the multiple state branches are branches possessed by the state machine within the main test access port; a configuration register for addressing and distributing serial configuration data with address identifiers based on the multiple control signals input from the main test access port, and generating scan chain mode control signals, interface routing control signals, and flexible parallel port control signals; a segmented scan chain for selecting paths for register segments within a core based on the scan chain mode control signals input from the configuration register; and a secondary test access port interface circuit for routing and switching externally input test signals and test response signals returned from each slave core based on the interface routing control signals input from the configuration register, and outputting downlink test signals sent to each slave core and a summarized uplink test response signal.

[0007] Furthermore, the main test access port includes: a state machine, used to jump to the corresponding state branch based on the externally input test signal, and output control signals for the state branch to the configuration register; an instruction register, used to serially shift and update the externally input instruction data when the state machine jumps to the instruction register branch, and output it to the core logic inside the chip. The instruction set corresponding to the instruction data only includes function mode instructions, scan mode instructions, device identification instructions, and bypass instructions; wherein, the multiple state branches include mutually independent configuration register branches, data register branches, and instruction register branches.

[0008] Furthermore, the configuration register branch includes sequentially connected configuration register selection state, configuration register capture state, configuration register shift state, and configuration register update state; the configuration control signal generation unit includes: a shift enable subunit, used to output a shift enable signal to the configuration register when the state machine jumps to the configuration register shift state, so that the configuration register continuously receives serial configuration data with address identifiers from external input; an update enable subunit, used to output an update enable signal to the configuration register when the state machine jumps to the configuration register update state, so that the configuration register updates the shifted serial configuration data to the addressed target register in parallel; and a loop bootstrapping subunit, used to reboot the state machine back to the starting state of the configuration register branch after the update enable signal is valid, so as to perform cyclic configuration of multiple target registers based on different address identifiers.

[0009] Further, the configuration registers include: a shared shift register, used to serially shift externally input serial configuration data with address identifiers based on the configuration control signal input from the main test access port, and output parallel configuration data containing address and data segments; an address decoding unit, used to decode the address segments in the parallel configuration data input from the shared shift register, and output update strobe signals; and multiple update registers, used to update the data segments in the parallel configuration data input from the shared shift register to the selected update register based on the update strobe signals input from the address decoding unit, and output scan chain mode control signals, interface routing control signals, and flexible parallel port control signals through their respective output terminals; wherein, the multiple update registers include a flexible parallel port configuration register, a die package configuration register, and a three-dimensional configuration register, the bit width of the shared shift register is greater than the bit width of any one of the multiple update registers, and the high bits of the shared shift register are used to carry address identifiers, and the low bits are used to carry configuration data to be written to the corresponding update register.

[0010] Furthermore, the output of the die package configuration register is connected to the segmented scan chain to output scan chain mode control signals, which include internal test mode signals, inter-die interconnect test mode signals, and board-level interconnect test mode signals; the output of the three-dimensional configuration register is connected to the secondary test access port interface circuit to output interface routing control signals, which include die selection signals, serial-parallel mode switching signals, and non-test die idle state control signals.

[0011] Furthermore, the segmented scan chain includes: an input boundary scan register segment and an output boundary scan register segment for board-level interconnection; an input die package register segment and an output die package register segment for inter-die interconnection; multiple multiplexers and multiple tri-state gates, used to cut off or select at least one of the input boundary scan register segment, output boundary scan register segment, input die package register segment, output die package register segment, and intra-die scan chain based on the scan chain mode control signal input by the configuration register; wherein, the register units in the boundary scan register segment and the die package register segment have the same structure, and each register unit includes a shift unit, a capture unit, and an update unit.

[0012] Furthermore, multiple multiplexers and multiple tri-state gates include: an internal test mode subunit, used to shield all external functional pins when the scan chain mode control signal indicates the internal test mode, and to connect the input boundary scan register segment, output boundary scan register segment, input die package register segment, output die package register segment, and internal chip scan chain in series into a scan path; an inter-chip interconnect test mode subunit, used to bypass the input boundary scan register segment, output boundary scan register segment, and internal chip scan chain when the scan chain mode control signal indicates the inter-chip interconnect test mode, and to select the scan path formed by the input die package register segment and the output die package register segment; and a board-level interconnect test mode subunit, used to bypass the input die package register segment, output die package segment, and internal chip scan chain when the scan chain mode control signal indicates the board-level interconnect test mode, and to select the scan path formed by the input boundary scan register segment and the output boundary scan register segment.

[0013] Further, the secondary test access port interface circuit includes: a downlink data routing unit, used to select and route externally input test data signals and test response signals returned from each slave core based on the serial-to-parallel mode switching signal in the interface routing control signal input to the configuration register, and output downlink test data signals to each slave core; a control signal routing unit, used to select and output state machine control signals of each slave core based on the non-test core idle state control signal in the interface routing control signal input to the configuration register and the externally input test mode selection signal, and output downlink control signals to each slave core; a logic isolation unit, used to perform logic gating based on the slave core gating signal in the interface routing control signal input to the configuration register and the test response signals returned from each slave core, and output isolated uplink test response signals; and an uplink data aggregation unit, used to serially aggregate the isolated uplink test response signals input to the logic isolation unit and output them to the uplink test response output terminal of the secondary test access port interface circuit; wherein, the downlink test data signal and the downlink control signal together constitute the downlink test signal output by the secondary test access port interface circuit.

[0014] Further, the downlink data routing unit includes: a first multiplexer, used to select an externally input test data signal and a test response signal returned from a first slave core based on a serial-to-parallel mode switching signal, and output an intermediate routing signal; a first register, used to store the externally input test data signal and output a downlink test data signal sent to the first slave core; and a second register, used to store the intermediate routing signal input from the first multiplexer and output a downlink test data signal sent to the second slave core; wherein, when the serial-to-parallel mode switching signal indicates parallel mode, the externally input test data signal is output in parallel to the first slave core and the second slave core via the first register and the second register; when the serial-to-parallel mode switching signal indicates serial mode, the test response signal returned from the first slave core is output to the downlink test data input terminal of the second slave core via the first multiplexer and the second register.

[0015] Furthermore, the system also includes a silicon interposer and multiple chips; the multiple chips include a master chip and multiple slave chips, and the master chip and multiple slave chips are all disposed on the silicon interposer; the silicon interposer is used to lead out independent and parallel physical connections between the secondary test access port interface circuit of the master chip and the master test access port of each slave chip via microbumps, and output test signal paths between chips; the secondary test access port interface circuit in the master chip is also used to distribute downlink test signals to each slave chip in parallel based on the test signal paths between chips input by the silicon interposer, and to receive test response signals returned by each slave chip in parallel, and output a summarized uplink test response signal.

[0016] Compared with the prior art, the design testability system provided in this application has at least the following advantages:

[0017] (1) By constructing a hierarchical test access architecture in the main chip consisting of the main test access port, configuration register, segmented scan chain and secondary test access port interface circuit, and using the configuration register as the unified addressing and distribution node for mode and routing, the status control function of the test access port and the mode selection function of the test path are decoupled. Without increasing the number of external test pins, independent and flexible configuration of the test mode inside the chip and the test path between chips can be achieved, providing a unified control basis for subsequent multi-chip parallel testing.

[0018] (2) By setting up a shared shift register, an address decoding unit, and multiple update registers including a flexible parallel port configuration register, a die package configuration register, and a three-dimensional configuration register in the configuration register, and adopting a serial configuration data format of "high bits carrying address identifiers and low bits carrying configuration data", multiple configuration registers can be addressed, distributed, and cyclically updated by a single configuration data path. The configuration state has been added, so there is no need to switch between multiple state branches when configuring the configuration register, which reduces the test interface overhead and shortens the total time of the configuration stage.

[0019] (3) By setting up input and output boundary scan register segments for board-level interconnection, input and output die package register segments for inter-chip interconnection, and multiple multiplexers and tri-state gates in the segmented scan chain, and switching the scan path between internal test mode, inter-chip interconnection test mode and board-level interconnection test mode according to the scan chain mode control signal, the same set of register segments can be reused as different scan paths in different test modes, avoiding hardware redundancy and shifting overhead caused by building an independent scan chain for each test target, and shortening the overall execution time of various test tasks within a single chip.

[0020] (4) By setting up a downlink data routing unit, a control signal routing unit, a logic isolation unit and an uplink data aggregation unit in the secondary test access port interface circuit, and by performing routing switching and gating isolation on the downlink test signal and the uplink test response signal according to the slave core selection signal, the serial-parallel mode switching signal and the non-test core idle state control signal in the interface routing control signal, the master core can flexibly select each slave core to enter the test or remain idle, and switch between serial link and parallel link as needed, thereby avoiding the situation where the failure of the intermediate core in the traditional daisy chain method leads to the inability to test subsequent cores.

[0021] (5) By further integrating the system with a silicon interposer and multiple chips, and by using the microbumps in the silicon interposer to lead out independent and parallel physical connections between the secondary test access port interface circuit of the main chip and the main test access port of each slave chip, each slave chip can simultaneously receive the downlink test signal from the main chip and send back the test response signal in parallel mode. This significantly reduces the test time that increases linearly with the number of slave chips in the traditional serial daisy chain, effectively alleviating the overall test time problem caused by the expansion of the test scale in multi-chip heterogeneous integration. Attached Figure Description

[0022] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0023] Figure 1 This schematically illustrates the overall architecture of a testability design system according to an embodiment of this application;

[0024] Figure 2 This illustration schematically shows a structural diagram of the state machine in the main test access port according to an embodiment of this application;

[0025] Figure 3 This illustration schematically shows a timing comparison diagram of the standard IEEE 1838 architecture and the improved architecture according to embodiments of this application when configuring multiple configuration registers;

[0026] Figure 4 The schematic diagram illustrates the structure of a segmented scan chain according to an embodiment of this application;

[0027] Figure 5(A) schematically illustrates the working principle of the segmented scan chain in the internal test mode according to an embodiment of the present application; Figure 5(B) schematically illustrates the working principle of the segmented scan chain in the inter-chip interconnect test mode according to an embodiment of the present application; Figure 5(C) schematically illustrates the working principle of the segmented scan chain in the board-level interconnect test mode according to an embodiment of the present application.

[0028] Figure 6 This illustration schematically shows a structural diagram of a secondary test access port interface circuit according to an embodiment of the present application;

[0029] Figure 7(A) schematically illustrates the connection method of the secondary test access port interface circuit according to an embodiment of the present application when test core 0 and core 1 are interconnected; Figure 7(B) schematically illustrates the connection method of the secondary test access port interface circuit according to an embodiment of the present application when test core 0 and core 2 are interconnected; Figure 7(C) schematically illustrates the connection method of the secondary test access port interface circuit according to an embodiment of the present application when test core 1 and core 2 are interconnected. Detailed Implementation

[0030] The embodiments of this application will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of this application. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of this application for ease of explanation. However, it will be apparent that one or more embodiments may be implemented without these specific details. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of this application.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0033] In the process of implementing this application, it was found that the "serial daisy chain + instruction decoding configuration + whole chain boundary scan" solution has some problems in the testability design problem of multi-chip testing in 2.5D integrated chips.

[0034] (1) High risk of single point of failure and limited test reliability. In the serial daisy chain structure, the secondary test access port of the lower chip needs to be connected to the main test access port of the upper chip in sequence. Once the microbump interconnect of a chip in the link fails or a chip fails completely, it will directly block the test path of all subsequent chips. The 2.5D package can provide abundant planar wiring resources with the help of the silicon interposer. The use of serial daisy chain not only fails to take advantage of this physical advantage, but also introduces the same chain failure risk as the 3D package.

[0035] (2) The configuration process is cumbersome and the testing time is long. In the standard TAP state machine, each time the target register is configured, the instruction must be shifted into the instruction branch and the instruction register must be updated. Then, the data must be shifted into the data branch and the target register must be updated. When configuring multiple configuration registers, the above jump process must be repeated, which significantly increases the number of clock cycles in the configuration phase.

[0036] (3) High scan chain redundancy and serious invalid shifts. Traditional boundary scan architectures usually connect all boundary registers inside the chip to the internal core scan chain in series, or simply separate the input and output scan chains without distinguishing between register segments for board-level interconnects and those for inter-chip interconnects. In scenarios where only a certain type of interconnect needs to be tested, irrelevant registers still participate in the shift process, resulting in a large number of invalid shift clock cycles and register flips, which significantly increases test time and test power consumption.

[0037] In view of this, embodiments of this application provide a design for testability system, which improves the state machine of the main test access port, distributes configuration registers based on address addressing, segments the scan chain for different interconnection scenarios, and designs the secondary test access port interface circuit with physical isolation and dynamic reconfiguration capabilities to obtain a highly reliable, low-overhead, and flexibly reconfigurable 2.5D integrated design for testability.

[0038] Figure 1 The diagram schematically illustrates the overall architecture of a testability design system according to an embodiment of this application.

[0039] like Figure 1 As shown, the design for testability system of this embodiment includes a main test access port, a configuration register, a segmented scan chain, and a secondary test access port interface circuit.

[0040] The connections between the components are as follows: The main test access port has an external test signal input terminal and multiple control signal output terminals. Its external test signal input terminal is used to receive externally input test signals (including TDI, TMS, TCK, TRST, etc.), and its multiple control signal output terminals are connected to the control input terminal of the configuration register. The data input terminal of the configuration register is used to receive externally input serial configuration data with address identifiers. Its control input terminal is connected to the multiple control signal output terminals of the main test access port. Its first output terminal is connected to the mode control terminal of the segmented scan chain to output the scan chain mode control signal. Its second output terminal is connected to the routing control terminal of the secondary test access port interface circuit to output the interface routing control signal. Its third output terminal is connected to the enable control terminal of the flexible parallel port to output the flexible parallel port control signal. The data input terminal of the segmented scan chain is connected to the external test data path and then connected to the register segments within the chip via a multiplexer and a tri-state gate. Test responses for different test modes are output from different locations. The data input terminal of the secondary test access port interface circuit is used to receive externally input test signals and test response signals returned from each slave chip. Its downlink output terminal is connected to the main test access port of each slave chip, and its uplink output terminal is used to output the summarized test response signal to the outside.

[0041] Based on the above architecture, the working principle of the testability design system in this application embodiment is as follows:

[0042] The main test access port is used to generate multiple control signals for multiple state branches based on externally input test signals. Specifically, the externally input test signals serve as the control reference for the entire design for testability system. The state machine inside the main test access port jumps to the corresponding state branch according to the level changes of the test signals, and outputs control signals for each branch. These signals are used to control the shifting and updating of the configuration register, the loading of instructions into the instruction register, and the shifting of data in the data register.

[0043] The configuration register is used to address and distribute serial configuration data with address identifiers based on multiple control signals input from the main test access port, generating scan chain mode control signals and interface routing control signals. Specifically, after receiving the control signals output from the main test access port, the configuration register serially receives the externally input serial configuration data and distributes the corresponding data segments to the addressed target registers according to the address identifiers. Then, each target register outputs scan chain mode control signals to the segmented scan chain and interface routing control signals to the secondary test access port interface circuit, thereby forming a unified addressing and distribution mechanism for scan chain paths and inter-chip routing.

[0044] The segmented scan chain is used to select pathways for register segments within the chip based on the scan chain mode control signal input from the configuration register. Specifically, the segmented scan chain divides the register resources within the chip into multiple independent register segments according to the test target. Based on the current test mode indicated by the scan chain mode control signal, it selects the corresponding register segment and bypasses or disconnects the remaining register segments. This ensures that the test vector is shifted only in the register segments directly related to the current test target, thereby avoiding invalid shift clock cycles and shortening the shift time of the test vector.

[0045] The secondary test access port interface circuit is used to route externally input test signals and test response signals returned from each slave core based on the interface routing control signal input from the configuration register. It outputs downlink test signals to each slave core and a summarized uplink test response signal. Specifically, under the control of the interface routing control signal, the secondary test access port interface circuit flexibly selects which slave cores to select, whether to switch between serial and parallel links, and whether non-selected slave cores are forced to remain idle. This enables independent and parallel driving of the test paths for each slave core at the hardware level, and allows for routing selection of the test response signals returned from each slave core before outputting them externally.

[0046] Through the above architecture, the design for testability system of this application embodiment can decouple the scan chain mode and inter-chip routing based on a single external input test access interface and the "state-addressing-distribution" mechanism composed of the main test access port and configuration register. The segmented scan chain and the secondary test access port interface circuit respectively realize the on-demand multiplexing of the register segment within the chip and the independent and parallel driving of the multi-chip test path, thereby realizing efficient, accurate and highly reliable testability testing of each chip and its interconnection relationship inside the 2.5D integrated chip.

[0047] Figure 2 The diagram illustrates the structure of a state machine in a main test access port according to an embodiment of this application. In some embodiments, the main test access port includes a state machine and an instruction register.

[0048] The connections between the components are as follows: The state machine has an external test signal input terminal, a reset terminal, and multiple control signal output terminals. Its external test signal input terminal is used to receive an externally input TMS signal, and its reset terminal is used to receive an externally input TRST signal. Its multiple control signal output terminals are connected to the configuration register, instruction register, and data register, respectively, to output corresponding shift enable signals, capture enable signals, and update enable signals under different state branches. The instruction register's data input terminal is used to receive an externally input TDI signal, and its clock control terminal and enable control terminal are respectively connected to the control signals output by the state machine. Its output terminal is connected to the core logic inside the chip to output the decoded instruction signal.

[0049] Specifically, the state machine is used to jump to the corresponding state branch based on the external input test signal, and output the control signal for that state branch to the configuration register. Based on the standard IEEE 1149.1 state machine, this application introduces an independent configuration register branch (Select-CR-Scan branch) into the TAP state machine, so that the configuration register branch, data register branch and instruction register branch exist in parallel and are independent of each other. Furthermore, the intermediate states such as Exit1-DR, Pause-DR, and Exit2-DR have been removed from both the configuration register branch and the instruction register branch.

[0050] like Figure 2As shown, the left side represents the standard state machine. The state machine first jumps sequentially from Test-Logic-Reset to Shift-IR. Instructions are shifted into the Shift-IR state, and after the shift ends, it enters the Update-IR state, updating the instruction register and issuing a control signal to select the configuration register. It then returns to Run-Test / Idle, and from Run-Test / Idle, it jumps sequentially to Shift-DR. Data is shifted into the Shift-DR state, and after the shift ends, it enters the Update-DR state, updating the selected configuration register. When multiple configuration registers exist in the system, the above state transitions must be repeated multiple times, resulting in a long configuration cycle. The right side represents the improved state machine of this invention, which adds an independent configuration register branch. When configuring registers, it first jumps sequentially from Test-Logic-Reset to Shift-CR. Data is shifted into the Shift-CR state, and after the shift ends, it enters the Update-CR state, updating the configuration register. When multiple configuration registers need to be configured sequentially, the state machine only needs to loop within the configuration register branch, without repeatedly switching between instruction and data branches.

[0051] The instruction register is used to serially shift and update externally input instruction data when the state machine jumps to the instruction register branch, and outputs the updated instruction signal to the core logic inside the chip. Since the configuration register branch independently handles the addressing and updating functions of each configuration register, the instruction register no longer needs to handle the function of strobing the configuration register. Therefore, its instruction set is greatly simplified, retaining only four basic instruction categories: function mode instructions, scan mode instructions, device identification instructions, and bypass instructions, thereby reducing the hardware overhead of the instruction decoding logic.

[0052] Furthermore, to support the improved state machine's rapid configuration of the configuration register, the configuration register branch includes sequentially connected configuration register selection, configuration register capture, configuration register shift, and configuration register update states. Correspondingly, the configuration control signal generation unit in the main test access port includes a shift enable subunit, an update enable subunit, and a loop bootstrapping subunit. Specifically, when the state machine transitions to the configuration register shift state, the shift enable subunit outputs a shift enable signal to the configuration register, enabling the configuration register to continuously receive externally input serial configuration data with address identifiers. When the state machine transitions to the configuration register update state, the update enable subunit outputs an update enable signal to the configuration register, enabling the shifted serial configuration data to be updated in parallel to the addressed target register. After the update enable signal is valid, the loop bootstrapping subunit redirects the state machine back to the initial state of the configuration register branch, thereby performing cyclic configuration of multiple target registers based on different address identifiers.

[0053] Figure 3 The illustration schematically shows a timing comparison diagram of the standard IEEE 1838 architecture and the improved architecture according to embodiments of this application when configuring multiple configuration registers. Figure 3 As shown in the upper part, when configuring the flexible parallel port configuration register, die package configuration register, and three-dimensional configuration register in sequence in the standard architecture, the state machine needs to repeatedly switch between instruction branches and data branches, and each switch needs to pass through several intermediate states, resulting in complex TMS signal waveforms and lengthy state sequences. Figure 3 As shown in the lower half, the improved architecture only needs to loop within the configuration register branch, resulting in a simple TMS signal waveform, short state sequence, and a significant reduction in the number of clock cycles during the configuration phase.

[0054] Figure 1 The internal structure of the configuration register according to an embodiment of this application is also schematically illustrated. In some embodiments, the configuration register includes a shared shift register, an address decoding unit, and a plurality of update registers, wherein the plurality of update registers include a flexible parallel port configuration register, a die packaged register configuration register, and a three-dimensional configuration register.

[0055] The connections between the components are as follows: The data input of the shared shift register is used to receive serial configuration data with address identifiers from external input. Its control terminal is connected to the configuration control signal output of the main test access port to receive the shift enable signal. The high-order output of its parallel output is connected to the input of the address decoding unit, and the low-order output is connected to the parallel data input of each update register. The output of the address decoding unit is connected to the update enable terminal of each update register. The output of each update register is connected to the downstream module: the output of the die package register configuration register is connected to the mode control terminal of the segmented scan chain; the output of the three-dimensional configuration register is connected to the routing control terminal of the secondary test access port interface circuit; and the output of the flexible parallel port configuration register is connected to the enable control terminal of the flexible parallel port, outputting the flexible parallel port control signal.

[0056] Specifically, the shared shift register is used to serially shift externally input serial configuration data with address identifiers based on the configuration control signal input from the main test access port, and output parallel configuration data containing address and data segments. In one embodiment of this application, the shared shift register has a bit width of 8 bits, where the high 2 bits are used to carry the address identifier and the low 6 bits are used to carry the configuration data to be written to the corresponding update register; correspondingly, the flexible parallel port configuration register, the die package configuration register, and the three-dimensional configuration register are all 6-bit registers, thereby ensuring that the data segment of the low bits of the shared shift register can be updated in parallel to the selected target update register.

[0057] It should be noted that in this scheme, the shared shift register is used among the three update registers, avoiding the hardware redundancy caused by configuring a shift path separately for each configuration register. At the same time, since the address identifier and data segment are shifted in together in the same shift process, the state machine only needs to perform the "shift-update" operation in a loop within the configuration register branch to complete the configuration of multiple update registers in sequence.

[0058] The address decoding unit decodes the address segments in the parallel configuration data input to the shared shift register and outputs update strobe signals. Specifically, the address decoding unit generates update strobe signals corresponding to the different values ​​of the high 2 bits of the address identifier, so that the lower 6 bits of the data segment of the shared shift register are updated in parallel to the corresponding update register when the update enable terminal of the update register is active.

[0059] Multiple update registers are used to update data segments in the parallel configuration data input from the address decoding unit based on the update strobe signal. These strobe signals are then updated to the selected update registers, and corresponding control signals are output through their respective output terminals. Specifically, the die package configuration register outputs scan chain mode control signals to the segmented scan chain. These signals include the internal test mode signal `intest`, the inter-die interconnect test mode signal `d2d_extest`, and the board-level interconnect test mode signal `pcb_extest`, indicating the current test mode to be entered. The three-dimensional configuration register outputs interface routing control signals to the secondary test access port interface circuit. These signals include slave die strobe signals `Select_S1` and `Select_S2`, the serial-to-parallel mode switching signal `SEL`, and the non-test die idle state control signals `RTI_or_TLR_S1` and `RTI_or_TLR_S2`, controlling the access status of each slave die and the connection configuration of the test paths.

[0060] Figure 4 A schematic diagram of a segmented scan chain according to an embodiment of this application is shown. In a multi-chip system, the chips are connected to the silicon interposer via microbumps, and then connected to the external PCB board via C4 bumps on the silicon interposer. Chips are interconnected with each other via microbumps and the silicon interposer, resulting in a typically extremely large test chain. To save test vector shifting time, this application divides the die package register and boundary scan register within a single chip into four segments using multiplexers and tri-state gates, and these segments, along with the internal scan chain of the chip, form a segmented scan chain.

[0061] The connections between the components are as follows: The segmented scan chain includes an input boundary scan register segment and an output boundary scan register segment for board-level interconnection, an input die package register segment and an output die package register segment for inter-die interconnection, as well as multiple multiplexers and multiple tri-state gates. The input boundary scan register segment and the output boundary scan register segment (represented by green squares in Figure 5) are located at the outermost periphery of the die-level functional pins, and are used to drive and capture signals for PCB-level interconnection, respectively. The input die package register segment and the output die package register segment (represented by blue squares in Figure 5) surround the functional pins for inter-die micro-bumps, and are used to drive and capture signals for inter-die interconnection, respectively. Multiple multiplexers and multiple tri-state gates are respectively located at the key nodes of the above four register segments and the scan chain within the die, and their control terminals are connected to the output of the die package register configuration register to receive the scan chain mode control signals pcb_extest, d2d_extest, and intest.

[0062] It should be noted that the boundary scan register segment in the segmented scan chain has the same structure as each register unit in the die package register segment. Each register unit includes a shift unit, a capture unit, and an update unit, making the two types of register segments fully compatible in physical implementation and facilitating the reuse of the same set of register unit resources in different test modes.

[0063] Figure 5(A) schematically illustrates the working principle of the segmented scan chain in the internal test mode according to an embodiment of the present application; Figure 5(B) schematically illustrates the working principle of the segmented scan chain in the inter-chip interconnect test mode according to an embodiment of the present application; Figure 5(C) schematically illustrates the working principle of the segmented scan chain in the board-level interconnect test mode according to an embodiment of the present application. Specifically, the multiple multiplexers and multiple tri-state gates further include an internal test mode subunit, an inter-chip interconnect test mode subunit, and a board-level interconnect test mode subunit, which dynamically control the access and disconnection of the scan path according to different values ​​of the scan chain mode control signal.

[0064] The internal test mode subunit is used to shield all external functional pins when the scan chain mode control signal indicates internal test mode. It connects the input boundary scan register segment, output boundary scan register segment, input die package register segment, output die package register segment, and the internal scan chain of the chip into a single scan path. As shown in Figure 5(A), the test vector is input from TDI, passes through all boundary scan chain segments, the die package register chain segment, and the internal scan chain in sequence, and is finally output from TDO. This is used to check the functional correctness of the core logic within the chip.

[0065] The inter-chip interconnection test mode subunit is used to bypass the input boundary scan register segment, the output boundary scan register segment, and the internal scan chain of the chip when the scan chain mode control signal indicates the inter-chip interconnection test mode, and to select the scan path composed of the input die package register segment and the output die package register segment. As shown in Figure 5(B), the multiplexer bypasses all boundary scan register segments and internal scan chains, and only selects the scan path composed of the die package register segment; the actual interconnection between multi-chip systems is usually bidirectional (i.e., it includes physical connections from chip 0 output to chip 1 and from chip 1 output to chip 0). To make the diagram clearer, only one direction of the data path (i.e., from the output die package register segment of chip 0 to the input die package register segment of chip 1) is extracted in the figure for illustration. During the test execution phase, the test vector is first serially shifted to the selected die package register scan chain; then, the output die package register of die 0 is given a test stimulus, and the input die package register of die 1 captures the arriving test response; finally, the captured response data is shifted and output through the TDO port to check for interconnection defects between dies through microbumps and silicon interposers.

[0066] The board-level interconnect test mode subunit is used to bypass the input die package register segment, the output die package register segment, and the internal scan chain of the die when the scan chain mode control signal indicates the board-level interconnect test mode, and select the scan path composed of the input boundary scan register segment and the output boundary scan register segment. As shown in Figure 5(C), the multiplexer bypasses all die package register segments and internal scan chains, and only selects the outermost boundary scan register chain segment; actual board-level interconnects usually involve complex bidirectional interconnects between multiple 2.5D integrated systems. The figure also only extracts the data path in one direction (i.e., from the boundary scan register at the output end of 2.5D integrated system 0 to the boundary scan register at the input end of 2.5D integrated system 1) for illustration. During the test execution phase, the test vector is first serially shifted to the selected outermost boundary scan register chain segment; then, the output boundary scan register of the 2.5D integrated system 0 applies the test stimulus, and the input boundary scan register of the 2.5D integrated system 1 captures the arriving test response; finally, the captured response data is shifted and output via the TDO port to check for board-level interconnect defects.

[0067] By using the above segmentation method, under different test objectives, only the register segments directly related to the current test mode participate in the shifting process, while the remaining register segments are bypassed or cut off, thereby eliminating the invalid clock cycle consumption caused by irrelevant register shifts and reducing register toggling to reduce test power consumption.

[0068] Figure 6A schematic diagram illustrating the structure of a secondary test access port interface circuit according to an embodiment of this application is shown. Figure 6 As shown, this application uses core 0 as the main core, and the secondary test access port interface circuit in core 0 leads out the connection to the main test access ports of core 1 and core 2 independently and in parallel.

[0069] The connection relationships between the components are as follows: The secondary test access port interface circuit has multiple external signal input terminals and multiple external output terminals. Its external input terminals are used to connect to test signals such as TDI, TMS, TCK, and TRST, where TDI is used to input test data, TMS is used to control state machine switching, TCK is used to provide the clock, and TRST is used for reset. Its control input terminal is connected to the output terminal of the three-dimensional configuration register to receive Select_S1, Select_S2, RTI_or_TLR_S1, RTI_or_TLR_S2, and SEL signals, which are used to select chip 1 and chip 2, ensure that non-test chips are in an idle state, and control the serial-parallel mode of the interface circuit, respectively. Its downlink output terminals include T... The secondary test access port interface circuit comprises DO_S1 and TDO_S2 (TDI inputs to chip 1 and chip 2), TMS_S1 and TMS_S2 (test mode selection signals distributed to chip 1 and chip 2), TCK_S1 and TCK_S2 (clock signals distributed to chip 1 and chip 2), and TRST_S1 and TRST_S2 (reset signals distributed to chip 1 and chip 2). Its uplink feedback terminals include TDI_S1 and TDI_S2, used to receive test response signals from chip 1 and chip 2, respectively. Its aggregated output terminal is TDO, used as the final output of the entire secondary test access port interface circuit. The secondary test access port interface circuit internally contains several multiplexers, several registers, and several AND gates, which respectively constitute the downlink data routing unit, control signal routing unit, logic isolation unit, and uplink data aggregation unit.

[0070] Specifically, the downlink data routing unit is used to select and route the externally input test data signal TDI and the test response signals returned from each slave core based on the serial-to-parallel mode switching signal SEL in the interface routing control signal input by the configuration register, and output downlink test data signals TDO_S1 and TDO_S2 to each slave core.

[0071] The control signal routing unit is used to select and output the state machine control signals of each slave chip based on the non-test chip idle state control signals RTI_or_TLR_S1 and RTI_or_TLR_S2 from the interface routing control signals input by the configuration register, as well as the externally input test mode selection signal TMS. The output is sent to the downlink control signals TMS_S1 and TMS_S2 of each slave chip. When a slave chip is not selected, its corresponding state machine control signal is forced to remain at the level indicating the idle state, causing the TAP state machine of that slave chip to remain in the Run-Test / Idle or Test-Logic-Reset state, thus avoiding interference with the current test path.

[0072] The logic isolation unit consists of AND gates located at the input terminals of the master chip receiving data returned from each slave chip. These gates are used to logically gate the slave chip selection signals Select_S1 and Select_S2 from the interface routing control signals input from the configuration register, along with the test response signals returned from each slave chip. The output is an isolated uplink test response signal. When a slave chip experiences a power failure or is not selected, the corresponding slave chip selection signal goes low, and the output of the AND gate is forcibly pulled low to a safe level. This prevents leakage current and logic malfunctions caused by high impedance or unknown states at the slave chip's output, ensuring the safety of other normal slave chip test paths.

[0073] The uplink data aggregation unit is used to select from the isolated uplink test response signals input by the logic isolation unit and output them to the uplink test response output terminal TDO of the secondary test access port interface circuit. The downlink test data signal and the downlink control signal together constitute the downlink test signal output by the secondary test access port interface circuit.

[0074] Furthermore, the downlink data routing unit includes a first multiplexer, a first register, and a second register. The first multiplexer is used to select the externally input test data signal TDI and the test response signal TDI_S1 returned from the first slave chip based on the serial-to-parallel mode switching signal SEL, and outputs an intermediate routing signal; the first register is used to register the externally input test data signal TDI, and outputs the downlink test data signal TDO_S1 sent to the first slave chip; the second register is used to register the intermediate routing signal input from the first multiplexer, and outputs the downlink test data signal TDO_S2 sent to the second slave chip.

[0075] Figure 7(A) schematically illustrates the connection method of the secondary test access port interface circuit according to an embodiment of the present application when test core 0 and core 1 are interconnected; Figure 7(B) schematically illustrates the connection method of the secondary test access port interface circuit according to an embodiment of the present application when test core 0 and core 2 are interconnected; Figure 7(C) schematically illustrates the connection method of the secondary test access port interface circuit according to an embodiment of the present application when test core 1 and core 2 are interconnected.

[0076] As shown in Figure 7(A), when testing the interconnection between chip 0 and chip 1, Select_S1=1, Select_S2=0, and SEL=0 are configured so that the external TDI signal passes directly through the first register to TDO_S1 (connected to the TDI of chip 1). The test output data of chip 1 is transmitted back to chip 0 via TDI_S1 and output through TDO. It should be noted that, for clarity of the connection, chip 1 and chip 2 are arranged in a stacked manner, but in reality, they are horizontally distributed on the silicon interposer. When SEL=0, it is in parallel mode. The TDI signal will actually arrive at TDO_S1 and TDO_S2 simultaneously, but because Select_S2=0 prevents chip 2 from being selected, its TAP state machine is forced to remain in an idle state by RTI_or_TLR_S2, so it will not interfere with the current test.

[0077] As shown in Figure 7(B), when testing the interconnection between chip 0 and chip 2, Select_S2=1, Select_S1=0, and SEL=0 are configured so that the external TDI signal passes directly through the first multiplexer and the second register to TDO_S2 (connected to the TDI of chip 2). The test output data of chip 2 is transmitted back to chip 0 via TDI_S2 and output through TDO. This independent and parallel lead-out structure ensures that even if chip 1 is completely damaged, it will not block the normal testing of chip 2, thus overcoming the problem of single-point failure causing the entire chain to be paralyzed in the serial daisy chain structure.

[0078] As shown in Figure 7(C), when testing the interconnection of core 1 and core 2, Select_S1=1, Select_S2=1, and SEL=0 are configured first. Core 0 first issues configuration instructions to core 1 and core 2 simultaneously in parallel state, and synchronizes the TAP state machine of both to enter the external test mode. After the state machine is configured, the system updates the configuration of the three-dimensional configuration register again to make SEL=1, and switches the secondary test access port interface circuit to serial state. At this time, when the serial-to-parallel mode switching signal indicates parallel mode (SEL=0), the externally input test data signal is output in parallel to the first slave chip and the second slave chip via the first register and the second register; when the serial-to-parallel mode switching signal indicates serial mode (SEL=1), the test response signal returned by the first slave chip is output to the downlink test data input terminal of the second slave chip via the first multiplexer and the second register, thereby forming a serial data path between chip 1 and chip 2 at the hardware physical level. The serial interconnect test can be completed by shifting the interconnect test vector; if parallel interconnect test is performed, the test data can be directly input in parallel through the flexible parallel port without going through the interface circuit.

[0079] The design-testability system of this application is further integrated with a silicon interposer and multiple chips to form a complete 2.5D integrated system. Specifically, the multiple chips include a master chip and multiple slave chips, and both the master chip and the multiple slave chips are disposed on the silicon interposer.

[0080] The connection relationship between the master chip and each slave chip is as follows: Independent, parallel physical connections are led out from the silicon interposer via microbumps between the secondary test access port interface circuit of the master chip and the master test access port of each slave chip, outputting test signal paths between chips. Specifically, the downlink leads of the master chip's secondary test access port interface circuit, such as TDO_S1, TMS_S1, TCK_S1, and TRST_S1, are connected to the master test access port of slave chip 1 (i.e., chip 1) via horizontal wiring and microbumps in the silicon interposer. The downlink leads of the master chip, such as TDO_S2, TMS_S2, TCK_S2, and TRST_S2, are connected to the master test access port of slave chip 2 (i.e., chip 2) via horizontal wiring and microbumps in the silicon interposer. The uplink return leads of the master chip, such as TDI_S1 and TDI_S2, receive test response signals from each slave chip via independent physical connections.

[0081] The secondary test access port interface circuit in the master chip is also used for the inter-chip test signal path based on the silicon interposer input, distributing downlink test signals in parallel to each slave chip, and receiving test response signals returned by each slave chip in parallel, outputting a summarized uplink test response signal. Specifically, since the silicon interposer provides abundant horizontal routing resources in the 2.5D package, this application makes full use of this physical advantage, deploying independent and parallel test paths between the master chip and each slave chip, so that each slave chip can simultaneously receive downlink test signals from the master chip and simultaneously return test response signals; when any slave chip fails, the master chip only needs to configure the slave chip strobe signal corresponding to that slave chip to be invalid through the three-dimensional configuration register, so as to bypass the failed chip without affecting the testing of other slave chips, thereby significantly reducing the impact of single-point failure on the entire test network and improving the testability and test reliability of the 2.5D integrated system.

[0082] Through the collaboration between the design for testability system of this application and the aforementioned 2.5D integrated structure, only one set of external test access interfaces is needed to complete the test drive of each chip and its interconnection relationship in the entire 2.5D integrated chip, without the need to bring out external test pins for each chip separately. At the same time, the combination of independent and parallel secondary test access port interface structure, address-based fast configuration mechanism, and test mode-based segmented scan chain structure enables the entire test network to significantly shorten the test configuration time and test vector shift time while maintaining high test coverage, and ensures the safety of the test path of intact chips in the event of failure of any chip through the logic isolation mechanism.

[0083] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of multiple such elements.

[0085] Those skilled in the art will understand that the features described in the various embodiments of this application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this application. In particular, the features described in the various embodiments of this application can be combined and / or combined in various ways without departing from the spirit and teachings of this application. All such combinations and / or combinations fall within the scope of this application.

[0086] The embodiments of this application have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of this application. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of this application, those skilled in the art can make various substitutions and modifications, all of which should fall within the scope of this application.

Claims

1. A design-testability system, characterized in that, include: The main test access port is used to generate multiple control signals for multiple state branches based on externally input test signals. The multiple state branches are the branches of the state machine within the main test access port. The configuration register is used to address and distribute serial configuration data with address identifiers based on the multiple control signals input from the main test access port, and generate scan chain mode control signals, interface routing control signals and flexible parallel port control signals. The segmented scan chain is used to select the path of the register segment within the core based on the scan chain mode control signal input from the configuration register. The secondary test access port interface circuit is used to perform routing switching on externally input test signals and test response signals returned from each slave core based on the interface routing control signal input from the configuration register, and output downlink test signals and selected uplink test response signals sent to each slave core.

2. The system according to claim 1, characterized in that, The main test access port includes: A state machine is used to jump to the corresponding state branch based on the externally input test signal and output the control signal for the state branch to the configuration register; The instruction register is used to serially shift and update the externally input instruction data when the state machine jumps to the instruction register branch, and output it to the core logic inside the chip. The instruction set corresponding to the instruction data only includes function mode instructions, scan mode instructions, device identification instructions and bypass instructions. The multiple state branches include mutually independent configuration register branches, data register branches, and instruction register branches.

3. The system according to claim 2, characterized in that, The configuration register branch includes sequentially connected configuration register select state, configuration register capture state, configuration register shift state, and configuration register update state. The configuration control signal generation unit includes: The shift enable subunit is used to output the shift enable signal to the configuration register when the state machine jumps to the configuration register shift state, so that the configuration register continuously receives the serial configuration data with address identifier from external input; The update enable subunit is used to output the update enable signal to the configuration register when the state machine jumps to the configuration register update state, so that the configuration register updates the serial configuration data that has been shifted to the addressed target register in parallel. The loop bootstrapping subunit is used to reboot the state machine back to the initial state of the configuration register branch after the update enable signal is valid, so as to perform loop configuration of multiple target registers based on different address identifiers.

4. The system according to claim 1, characterized in that, The configuration register includes: A shared shift register is used to serially shift the externally input serial configuration data with address identifier based on the configuration control signal input from the main test access port, and output parallel configuration data containing address and data segments. The address decoding unit is used to decode the address segment in the parallel configuration data input by the shared shift register and output an update strobe signal; Multiple update registers are used to update the data segments in the parallel configuration data input by the shared shift register to the selected update register based on the update strobe signal input by the address decoding unit, and output the scan chain mode control signal, the interface routing control signal and the flexible parallel port control signal through their respective output terminals. The plurality of update registers include a flexible parallel port configuration register, a die package configuration register, and a three-dimensional configuration register. The bit width of the shared shift register is greater than the bit width of any one of the plurality of update registers. The high-order bits of the shared shift register are used to carry the address identifier, and the low-order bits are used to carry the configuration data to be written to the corresponding update register.

5. The system according to claim 4, characterized in that, The output of the die package register configuration register is connected to the segmented scan chain and is used to output the scan chain mode control signal. The scan chain mode control signal includes an internal test mode signal, a die-to-die interconnect test mode signal, and a board-level interconnect test mode signal. The output of the three-dimensional configuration register is connected to the secondary test access port interface circuit and is used to output the interface routing control signal. The interface routing control signal includes a chip selection signal, a serial-parallel mode switching signal, and a non-test chip idle state control signal.

6. The system according to claim 1, characterized in that, The segmented scan chain includes: Input boundary scan register segment and output boundary scan register segment for board-level interconnect; Input die package register segment and output die package register segment for inter-die interconnect; Multiple multiplexers and multiple tri-state gates are used to cut off or select at least one of the input boundary scan register segment, the output boundary scan register segment, the input die package register segment, the output die package segment, and the internal scan chain of the die based on the scan chain mode control signal input to the configuration register. The boundary scan register segment has the same structure as each register unit in the die package register segment, and each register unit includes a shift unit, a capture unit, and an update unit.

7. The system according to claim 6, characterized in that, The plurality of multiplexers and the plurality of tri-state gates include: The internal test mode subunit is used to shield all external function pins when the scan chain mode control signal indicates the internal test mode, and to connect the input boundary scan register segment, the output boundary scan register segment, the input die package register segment, the output die package segment, and the chip internal scan chain in series into a scan path. The inter-die interconnect test mode subunit is used to bypass the input boundary scan register segment, the output boundary scan register segment, and the internal scan chain of the die when the scan chain mode control signal indicates the inter-die interconnect test mode, and to select the scan path formed by the input die package register segment and the output die package register segment. The board-level interconnect test mode subunit is used to bypass the input die package register segment, the output die package register segment, and the internal scan chain of the die when the scan chain mode control signal indicates the board-level interconnect test mode, and to select the scan path formed by the input boundary scan register segment and the output boundary scan register segment.

8. The system according to claim 1, characterized in that, The secondary test access port interface circuit includes: The downlink data routing unit is used to select and route the externally input test data signal and the test response signal returned from each slave core based on the serial-to-parallel mode switching signal in the interface routing control signal input to the configuration register, and output the downlink test data signal sent to each slave core. The control signal routing unit is used to select and output the state machine control signal of each slave core based on the non-test core idle state control signal in the interface routing control signal input to the configuration register and the externally input test mode selection signal, and output the downlink control signal to each slave core. The logic isolation unit is used to perform logic gating based on the slave core selection signal and the test response signal returned by each slave core in the interface routing control signal input by the configuration register, and output the isolated uplink test response signal. The uplink data aggregation unit is used to select based on the isolated uplink test response signal input by the logic isolation unit and output it to the uplink test response output terminal of the secondary test access port interface circuit. The downlink test data signal and the downlink control signal together constitute the downlink test signal output by the secondary test access port interface circuit.

9. The system according to claim 8, characterized in that, The downlink data routing unit includes: A first multiplexer is used to select the externally input test data signal and the test response signal returned from the first core based on the serial-to-parallel mode switching signal, and output an intermediate routing signal. The first register is used to store the test data signal based on the external input and output the downlink test data signal to the first slave chip. The second register is used to store the intermediate routing signal input from the first multiplexer and output the downlink test data signal sent to the second slave chip. Specifically, when the serial-to-parallel mode switching signal indicates parallel mode, the externally input test data signal is output in parallel to the first slave chip and the second slave chip via the first register and the second register; when the serial-to-parallel mode switching signal indicates serial mode, the test response signal returned by the first slave chip is output to the downlink test data input terminal of the second slave chip via the first multiplexer and the second register.

10. The system according to any one of claims 1 to 9, characterized in that, The system also includes a silicon interposer and a plurality of chips; the plurality of chips include a master chip and a plurality of slave chips, and the master chip and the plurality of slave chips are all disposed on the silicon interposer; The silicon interposer is used to draw independent and parallel physical connections between the secondary test access port interface circuit of the main die and the main test access port of each slave die via microbumps, thereby outputting test signal paths between dies. The secondary test access port interface circuit in the master chip is also used to distribute the downlink test signal in parallel to each slave chip based on the inter-chip test signal path input by the silicon interposer, and to receive the test response signal returned by each slave chip in parallel, and output the selected uplink test response signal.

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