Multi-state estimation method for energy storage batteries and embedded platform

Abstract

The embodiment of the application provides a kind of multi-state estimation method and embedded platform of energy storage battery.The method is applied to embedded platform, the method includes: obtaining the electrical parameter of energy storage battery;And obtain the computing power load of the chip of embedded platform;According to computing power load and preset executable instruction set, determine executable instruction;According to computing power load, determine inference cycle configuration;Based on executable instruction and inference cycle configuration, control intelligent model to process electrical parameter, obtain battery state parameter;Wherein, intelligent model is based on neural network model to historical electrical parameter and obtains training;Battery state parameter includes state of charge SOC estimation value, energy state SOE estimation value and health state SOH estimation value.The method is used to realize the effect of giving consideration to energy storage battery multi-state estimation precision and embedded platform computing power resource dynamic adaptation, improve battery state estimation real-time and system running stability.

Description

Technical Field

[0001] This application relates to the field of energy storage battery technology, and in particular to a multi-state estimation method for energy storage batteries and an embedded platform. Background Technology

[0002] Energy storage batteries are widely used in new energy power generation, smart grids, electric vehicles and distributed energy management. Their state parameters, such as State of Charge (SOC), State of Energy (SOE) and State of Health (SOH), are directly related to the safety of battery charging and discharging and energy management, and need to be estimated in real time.

[0003] In related technologies, electrical parameters such as voltage, current, and temperature are typically collected, and neural network models are used to estimate these state parameters. However, when deployed on low-power embedded platforms, existing methods struggle to simultaneously achieve both estimation accuracy and real-time performance due to limitations in chip computing resources.

[0004] Therefore, there is an urgent need for a solution for multi-state estimation of energy storage batteries that can balance accuracy and real-time performance. Summary of the Invention

[0005] This application provides a multi-state estimation method for energy storage batteries and an embedded platform, which can achieve the effect of balancing the multi-state estimation accuracy of energy storage batteries with the dynamic adaptation of computing resources of the embedded platform, improving the real-time performance of battery state estimation and the stability of system operation.

[0006] In a first aspect, embodiments of this application provide a multi-state estimation method for an energy storage battery, the method being applied to an embedded platform; the method includes:

[0007] Obtain the electrical parameters of the energy storage battery; and obtain the computing load of the embedded platform's chips;

[0008] Based on the computing load and the preset set of executable instructions, determine the executable instructions; based on the computing load, determine the inference cycle configuration;

[0009] Based on the executable instructions and the inference cycle configuration, the intelligent model is controlled to process the electrical parameters to obtain battery state parameters; wherein, the intelligent model is obtained by training historical electrical parameters based on a neural network model; the battery state parameters include estimated state of charge (SOC), estimated state of energy (SOE), and estimated state of health (SOH).

[0010] In one possible implementation, executable instructions are obtained based on the computing load and a preset set of executable instructions, including:

[0011] The computing load is compared with a preset threshold.

[0012] If it is determined that the computing load is less than a preset threshold, then based on the preset set of executable instructions, the executable instruction is determined to be the first executable instruction, wherein the first executable instruction is an inference instruction using 16-bit fixed-point quantization;

[0013] If the computing load is determined to be greater than or equal to a preset threshold, then based on the preset set of executable instructions, the executable instruction is determined to be a second executable instruction, wherein the second executable instruction is an inference instruction using 8-bit fixed-point quantization.

[0014] In one possible implementation, determining the inference cycle configuration based on the computing power load includes:

[0015] If it is determined that the computing power load is less than the first threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 100ms, the inference cycle of the SOE estimation task is 500ms, and the inference cycle of the SOH estimation task is 10s.

[0016] If it is determined that the computing load is greater than or equal to the first threshold and less than the second threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 100ms, the inference cycle of the SOE estimation task is 1000ms, and the inference cycle of the SOH estimation task is 30s.

[0017] If the computing load is determined to be greater than or equal to the second threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 500ms, the inference cycle of the SOE estimation task is 5ms, and the inference cycle of the SOH estimation task is 60s.

[0018] In one possible implementation, the electrical parameters include voltage data, current data, and temperature data; based on the executable instructions and the inference cycle configuration, the intelligent model is controlled to process the electrical parameters to obtain battery state parameters, including:

[0019] The voltage data, current data, and temperature data are subjected to fixed-point normalization to obtain normalized fixed-point voltage values, normalized fixed-point current values, and normalized fixed-point temperature values.

[0020] The normalized voltage fixed-point value, the normalized current fixed-point value, and the normalized temperature fixed-point value are concatenated into a feature vector of fixed dimensions.

[0021] Based on the executable instructions and the inference cycle configuration, the feature vector is input into the intelligent model for processing to obtain the battery state parameters.

[0022] In one possible implementation, the feature vector is input into the intelligent model for processing according to the executable instructions and the inference cycle configuration to obtain the battery state parameters, including:

[0023] Based on the inference cycle configuration, the timer for triggering the inference task corresponding to the intelligent model is set;

[0024] Based on the set inference task trigger timer, the feature vector is input into the intelligent model at the trigger time, and convolution and fully connected operations are performed layer by layer according to the inference instructions corresponding to the executable instructions to obtain fixed-point estimates.

[0025] The fixed-point estimate is dequantized to obtain the battery state parameters.

[0026] In one possible implementation, obtaining the computing load of the embedded platform's chip includes:

[0027] Obtain the CPU utilization rate, memory utilization rate, and single-step inference time percentage of the chip;

[0028] The CPU utilization rate, memory utilization rate, and single-step inference time ratio are normalized to obtain normalized values ​​for CPU utilization rate, memory utilization rate, and single-step inference time ratio.

[0029] The normalized values ​​of CPU utilization, memory usage, and single-step inference time are extracted by minimizing the values ​​to obtain the computing power surplus value.

[0030] The computing power load is obtained by converting the computing power surplus value into a load percentage.

[0031] In one possible implementation, the method further includes, prior to obtaining the electrical parameters of the energy storage battery:

[0032] Obtain the number of available computing units, available storage space, and available cache bandwidth of the embedded platform;

[0033] The intermediate format file is parsed to obtain the operator execution queue and operator dependencies; wherein, the intermediate format file is obtained by processing the intelligent model;

[0034] Based on the number of available computing units, the available storage space, and the available cache bandwidth, the operator execution queue and the operator dependency are processed for computational simplification, timing reordering, and resource conflict avoidance to obtain at least two executable instruction sets.

[0035] Write the at least two executable instruction sets into the preset executable instruction set.

[0036] In one possible implementation, the method further includes:

[0037] Obtain the file of the intelligent model; and perform structural parsing processing on the file of the intelligent model to obtain the model structure information and the initial weight parameter set;

[0038] Redundant operators are removed from the model structure information to obtain a simplified core operation layer structure;

[0039] The initial weight parameter set in the simplified core operation layer structure is subjected to fixed-point quantization to obtain the quantized fixed-point parameter set.

[0040] Based on the rated electrical parameters of the energy storage battery, the quantized fixed-point parameter set is subjected to accuracy compensation processing to obtain the compensated quantized parameter set.

[0041] The compensated quantization parameter set is encapsulated in an intermediate format to obtain an intermediate format file; the intermediate format file is then deployed on the embedded platform.

[0042] In one possible implementation, the method further includes:

[0043] Obtain the reference battery state value of the energy storage battery;

[0044] The deviation between the battery state parameters and the reference battery state value is calculated to obtain the state deviation value;

[0045] If the state deviation value is greater than the preset deviation threshold, the quantization parameter set in the intermediate format file is corrected online according to the state deviation value to obtain the corrected quantization parameter set.

[0046] The corrected quantization parameter set is repackaged to obtain an updated intermediate format file; wherein, the intermediate format file is a file generated when deploying the model, and the intelligent model runs based on the intermediate format file.

[0047] Secondly, embodiments of this application provide a multi-state estimation device for an energy storage battery, the device being applied to an embedded platform; the device includes:

[0048] The acquisition module is used to acquire the electrical parameters of the energy storage battery and the computing load of the embedded platform's chips.

[0049] The confirmation module is used to determine executable instructions based on the computing power load and a preset set of executable instructions; and to determine the inference cycle configuration based on the computing power load.

[0050] The processing module is used to control the intelligent model to process the electrical parameters based on the executable instructions and the inference cycle configuration to obtain battery state parameters; wherein, the intelligent model is obtained by training historical electrical parameters based on a neural network model; the battery state parameters include estimated values ​​of state of charge (SOC), state of energy (SOE), and state of health (SOH).

[0051] In one possible implementation, the confirmation module is specifically used for:

[0052] The computing load is compared with a preset threshold.

[0053] If it is determined that the computing load is less than a preset threshold, then based on the preset set of executable instructions, the executable instruction is determined to be the first executable instruction, wherein the first executable instruction is an inference instruction using 16-bit fixed-point quantization;

[0054] If the computing load is determined to be greater than or equal to a preset threshold, then based on the preset set of executable instructions, the executable instruction is determined to be a second executable instruction, wherein the second executable instruction is an inference instruction using 8-bit fixed-point quantization.

[0055] In one possible implementation, the confirmation module is specifically used for:

[0056] If it is determined that the computing power load is less than the first threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 100ms, the inference cycle of the SOE estimation task is 500ms, and the inference cycle of the SOH estimation task is 10s.

[0057] If it is determined that the computing load is greater than or equal to the first threshold and less than the second threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 100ms, the inference cycle of the SOE estimation task is 1000ms, and the inference cycle of the SOH estimation task is 30s.

[0058] If the computing load is determined to be greater than or equal to the second threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 500ms, the inference cycle of the SOE estimation task is 5ms, and the inference cycle of the SOH estimation task is 60s.

[0059] In one possible implementation, the electrical parameters include voltage data, current data, and temperature data; the processing module is specifically used for:

[0060] The voltage data, current data, and temperature data are subjected to fixed-point normalization to obtain normalized fixed-point voltage values, normalized fixed-point current values, and normalized fixed-point temperature values.

[0061] The normalized voltage fixed-point value, the normalized current fixed-point value, and the normalized temperature fixed-point value are concatenated into a feature vector of fixed dimensions.

[0062] Based on the executable instructions and the inference cycle configuration, the feature vector is input into the intelligent model for processing to obtain the battery state parameters.

[0063] In one possible implementation, the processing module is further configured to:

[0064] Based on the inference cycle configuration, the timer for triggering the inference task corresponding to the intelligent model is set;

[0065] Based on the set inference task trigger timer, the feature vector is input into the intelligent model at the trigger time, and convolution and fully connected operations are performed layer by layer according to the inference instructions corresponding to the executable instructions to obtain fixed-point estimates.

[0066] The fixed-point estimate is dequantized to obtain the battery state parameters.

[0067] In one possible implementation, the acquisition module is specifically used for:

[0068] Obtain the CPU utilization rate, memory utilization rate, and single-step inference time percentage of the chip;

[0069] The CPU utilization rate, memory utilization rate, and single-step inference time ratio are normalized to obtain normalized values ​​for CPU utilization rate, memory utilization rate, and single-step inference time ratio.

[0070] The normalized values ​​of CPU utilization, memory usage, and single-step inference time are extracted by minimizing the values ​​to obtain the computing power surplus value.

[0071] The computing power load is obtained by converting the computing power surplus value into a load percentage.

[0072] In one possible implementation, prior to acquiring the module, the device further includes a processing submodule, specifically configured to:

[0073] Obtain the number of available computing units, available storage space, and available cache bandwidth of the embedded platform;

[0074] The intermediate format file is parsed to obtain the operator execution queue and operator dependencies; wherein, the intermediate format file is obtained by processing the intelligent model;

[0075] Based on the number of available computing units, the available storage space, and the available cache bandwidth, the operator execution queue and the operator dependency are processed for computational simplification, timing reordering, and resource conflict avoidance to obtain at least two executable instruction sets.

[0076] Write the at least two executable instruction sets into the preset executable instruction set.

[0077] In one possible implementation, the apparatus further includes a deployment module, specifically configured to:

[0078] Obtain the file of the intelligent model; and perform structural parsing processing on the file of the intelligent model to obtain the model structure information and the initial weight parameter set;

[0079] Redundant operators are removed from the model structure information to obtain a simplified core operation layer structure;

[0080] The initial weight parameter set in the simplified core operation layer structure is subjected to fixed-point quantization to obtain the quantized fixed-point parameter set.

[0081] Based on the rated electrical parameters of the energy storage battery, the quantized fixed-point parameter set is subjected to accuracy compensation processing to obtain the compensated quantized parameter set.

[0082] The compensated quantization parameter set is encapsulated in an intermediate format to obtain an intermediate format file; the intermediate format file is then deployed on the embedded platform.

[0083] In one possible implementation, the device further includes an update module, which is specifically used for:

[0084] Obtain the reference battery state value of the energy storage battery;

[0085] The deviation between the battery state parameters and the reference battery state value is calculated to obtain the state deviation value;

[0086] If the state deviation value is greater than the preset deviation threshold, the quantization parameter set in the intermediate format file is corrected online according to the state deviation value to obtain the corrected quantization parameter set.

[0087] The corrected quantization parameter set is repackaged to obtain an updated intermediate format file; wherein, the intermediate format file is a file generated when deploying the model, and the intelligent model runs based on the intermediate format file.

[0088] Thirdly, embodiments of this application provide an embedded platform, including: a memory and a chip;

[0089] The memory stores computer-executed instructions;

[0090] The chip executes computer execution instructions stored in the memory, causing the chip to perform the first aspect and / or various possible implementations of the first aspect as described above.

[0091] Fourthly, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the first aspect and / or various possible implementations of the first aspect.

[0092] Fifthly, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the first aspect and / or various possible implementations of the first aspect.

[0093] This application provides a multi-state estimation method for energy storage batteries and an embedded platform. By acquiring the electrical parameters of the energy storage battery and the computing load of the embedded platform chip, and matching and determining executable instructions from a preset set of executable instructions based on the computing load, while dynamically determining the inference cycle configuration based on the computing load, the method controls an intelligent model trained on historical electrical parameters by a neural network model to process the electrical parameters, obtaining battery state parameters including SOC estimates, SOE estimates, and SOH estimates. This allows the complexity of the intelligent model's inference instructions and the inference cycle to adaptively adjust according to the real-time computing load of the embedded platform chip. When computing power is sufficient, more refined inference instructions are executed and the inference cycle is shortened to improve estimation accuracy; when computing power is limited, inference instructions are simplified and the inference cycle is extended to avoid computing overload. This achieves a balance between the accuracy of multi-state estimation of energy storage batteries and the dynamic adaptation of embedded platform computing resources, improving the real-time performance of battery state estimation and the stability of system operation. Attached Figure Description

[0094] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0095] Figure 1 A flowchart illustrating a multi-state estimation method for an energy storage battery provided in this application embodiment. Figure 1 ;

[0096] Figure 2 A flowchart illustrating a multi-state estimation method for an energy storage battery provided in this application embodiment. Figure 2 ;

[0097] Figure 3This is a schematic diagram of the structure of a multi-state estimation device for an energy storage battery provided in an embodiment of this application;

[0098] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0099] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0100] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0101] Energy storage battery state monitoring falls under the fields of battery management and embedded data processing technology, and is primarily applied in new energy storage systems, electric vehicle power supply systems, and distributed battery node monitoring systems. Related systems typically consist of sensors, a battery management unit, an embedded processing chip, and a state estimation algorithm module. They collect electrical parameters such as voltage, current, and temperature to perform online analysis of the battery's operating status.

[0102] In existing technologies, a common practice is to pre-deploy an estimation algorithm model based on historical electrical parameters on an embedded platform, and process the collected voltage, current and temperature data according to a fixed inference cycle to output state parameters such as SOC, SOH and SOE for charge and discharge control, life assessment and operation early warning.

[0103] These solutions typically use general-purpose embedded hardware as their operating platform, and their algorithm execution methods are relatively fixed, making them less sensitive to changes in the chip's current computing power usage. When the platform simultaneously undertakes data acquisition, communication, and state estimation tasks, the inference task is easily affected by instantaneous load fluctuations, resulting in problems such as untimely updates to critical states, excessive resource consumption by non-critical tasks, and low overall resource utilization.

[0104] In distributed energy storage node scenarios, the operating load and processing capacity of different nodes are not consistent. Fixed execution strategies are difficult to adapt to the real-time status of each node, which can easily cause some nodes to have delayed estimation response and some nodes to idle resources, thereby affecting the consistency of multi-node monitoring results and adversely affecting battery operation safety and scheduling accuracy.

[0105] Therefore, this application provides a multi-state estimation method for energy storage batteries, which links the multi-state estimation process of energy storage batteries with the real-time operating status of the embedded platform, and introduces the chip computing load into the model execution decision. The sensor acquisition module, processing chip, and model inference module in the embedded platform work together to first acquire the battery electrical parameters and chip computing load, then select executable instructions that are suitable for the current load from a preset set of executable instructions, and simultaneously adjust the inference cycle configuration.

[0106] To address the aforementioned issues, adopting a path that switches the model processing mode according to changes in computing load enables the intelligent model to maintain continuous estimation of SOC, SOE, and SOH under resource-constrained conditions. This alleviates the response lag and resource allocation imbalance caused by fixed inference modes and improves the real-time performance, resource utilization efficiency, and operational stability of multi-state estimation in embedded environments.

[0107] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0108] Figure 1 A flowchart illustrating a multi-state estimation method for an energy storage battery provided in this application embodiment. Figure 1 ,like Figure 1 As shown, the method includes:

[0109] S101. Obtain the electrical parameters of the energy storage battery; and obtain the computing load of the embedded platform chip.

[0110] For example, the electrical parameters of an energy storage battery refer to electrical and thermal quantities that reflect the battery's operating state, including voltage data, current data, and temperature data. Specifically, the voltage data is the potential difference between the positive and negative terminals of the battery, the current data is the current flowing through the battery during charging and discharging, and the temperature data is the measured temperature of the battery itself or its surrounding environment.

[0111] The computing load of an embedded platform chip refers to the degree of computing resource utilization of the chip at a given moment, and is used to characterize how much available computing power the chip can still provide. The computing load is usually determined by a combination of indicators such as the chip's CPU utilization, memory utilization, and single-step inference time percentage. A higher load indicates that the chip is busier, and a lower load indicates that the chip is more idle.

[0112] The purpose of this step is to simultaneously acquire the input data required for model inference and the hardware state information required to determine the inference mode.

[0113] For example, during the operation of the energy storage battery, the analog signals output by the voltage sensor, current sensor, and temperature sensor are sampled in real time through the analog front-end (AFE), and the corresponding digital quantities are obtained through analog-to-digital conversion, serving as the electrical parameters of the energy storage battery. Simultaneously, the operating status data of the embedded platform chip is collected in real time, including CPU utilization, memory utilization, and single-step inference time percentage. These three indicators are normalized to obtain normalized values ​​for CPU utilization, memory utilization, and single-step inference time percentage. Then, the minimum value of the three normalized values ​​is extracted to obtain the computing power surplus value; further, a load percentage conversion is performed based on the computing power surplus value to obtain the chip's computing power load. This computing power load value is stored in the global status register for subsequent instruction matching and periodic configuration.

[0114] S102. Determine the executable instructions based on the computing load and the preset set of executable instructions; determine the inference cycle configuration based on the computing load.

[0115] For example, a pre-defined set of executable instructions refers to multiple sets of executable instructions that are pre-compiled and stored in the chip memory during the embedded platform deployment phase. Each set of instructions corresponds to different inference precision and computational overhead, such as a high-precision inference instruction set using 16-bit fixed-point quantization, a fast inference instruction set using 8-bit fixed-point quantization, etc.

[0116] Executable instructions refer to the operator execution sequence and fixed-point bit-width mode corresponding to the intelligent model when performing inference on the embedded platform. They are used to control the precision with which the model performs operations such as convolution and fully connected operations.

[0117] Inference cycle configuration refers to the triggering cycle set for each state estimation task, such as SOC, SOE, and SOH, based on the importance of different state variables and the chip's computing power load. This is used to control when each task is scheduled for execution.

[0118] For example, after obtaining the chip's computing load, the load value is compared with a preset threshold. When the load value is less than the preset threshold, a high-precision inference instruction set using 16-bit fixed-point quantization from the preset executable instruction set is matched as the current executable instruction; when the load value is greater than or equal to the preset threshold, a fast inference instruction set using 8-bit fixed-point quantization is matched as the current executable instruction. Simultaneously, the inference cycle of SOC, SOE, and SOH is configured according to the load value range: when the load is low, the task cycles are shorter, and inference execution is more frequent; when the load is high, the cycles of low-priority tasks are extended accordingly to release computing resources. The determined executable instructions point to the corresponding operator library entry in the form of function pointers, and the inference cycle configuration is written to the comparison matching register of the timer peripheral to control the trigger time of the next inference.

[0119] Understandably, the purpose of this step is to match suitable executable instructions from the preset instruction set based on the current computing load of the chip, and to determine the inference cycle configuration of each state variable, so as to dynamically adjust the inference accuracy and execution frequency under limited computing power.

[0120] S103. Based on the executable instructions and inference cycle configuration, the intelligent control model processes the electrical parameters to obtain the battery state parameters.

[0121] Among them, the intelligent model is obtained by training historical electrical parameters based on a neural network model; the battery state parameters include the estimated state of charge (SOC), the estimated state of energy (SOE), and the estimated state of health (SOH).

[0122] For example, executable instructions refer to the operator execution sequence and fixed-point bit-width mode corresponding to the intelligent model when performing inference calculations on the embedded platform, which are used to control the precision with which the model performs operations such as convolution and fully connected operations.

[0123] Inference cycle configuration refers to the inference trigger cycle set separately for each state quantity estimation task of SOC, SOE, and SOH based on the chip's computing power load, which is used to control when each task is scheduled to be executed.

[0124] The intelligent model is obtained by training historical electrical parameters based on a neural network model. It can output corresponding battery state estimates based on input electrical parameters such as voltage, current, and temperature.

[0125] Battery state parameters include estimated state of charge (SOC), estimated state of energy (SOE), and estimated state of health (SOH). Among them, SOC reflects the current percentage of remaining charge, SOE reflects the current remaining usable energy, and SOH reflects the battery's health relative to a new battery.

[0126] For example, after acquiring electrical parameters and completing executable instruction matching and inference cycle configuration, the voltage, current, and temperature data in the electrical parameters are first subjected to fixed-point normalization, mapping each parameter to a fixed-point representation in the [0,1] interval, and concatenating them into a fixed-dimensional feature vector. Then, according to the trigger time determined by the inference cycle configuration, the feature vector is input into the intelligent model at that trigger time according to the fixed-point bit-width mode corresponding to the executable instruction. The intelligent model performs convolution and fully connected operations layer by layer according to the operator execution sequence in the executable instruction to obtain the fixed-point estimates of the model output layer. The fixed-point estimates are dequantized to convert them into floating-point values ​​with actual physical meaning, obtaining the SOC estimate, SOE estimate, and SOH estimate. Finally, the above three state estimates are written into the output register and sent to the host computer or master node through the communication interface module to complete the complete output of this inference cycle.

[0127] This application provides a multi-state estimation method for energy storage batteries. It acquires the electrical parameters of the energy storage battery and the computing load of the embedded platform chip. Based on the computing load, it matches and determines executable instructions from a preset set of executable instructions and dynamically determines the inference cycle configuration. Then, based on the determined executable instructions and inference cycle configuration, it controls an intelligent model trained on historical electrical parameters by a neural network model to process the electrical parameters, obtaining battery state parameters including estimated State of Charge (SOC), State of Energy (SOE), and State of Health (SOH). This allows the complexity of the intelligent model's inference instructions and the inference cycle to adaptively adjust according to the real-time computing load of the embedded platform chip. When computing power is sufficient, it executes more refined inference instructions and shortens the inference cycle to improve estimation accuracy. When computing power is limited, it simplifies inference instructions and extends the inference cycle to avoid computing overload. This achieves a balance between the accuracy of multi-state estimation of energy storage batteries and the dynamic adaptation of embedded platform computing resources, improving the real-time performance of battery state estimation and the stability of system operation.

[0128] Figure 2 A flowchart illustrating a multi-state estimation method for an energy storage battery provided in this application embodiment. Figure 2 ,like Figure 2 As shown, in this embodiment... Figure 1 Based on the embodiments, a multi-state estimation method for energy storage batteries is described in detail. The method includes:

[0129] S201. Obtain the electrical parameters of the energy storage battery; and obtain the computing load of the embedded platform chip.

[0130] For example, this step can be referred to step S101, and will not be described again.

[0131] In one example, the CPU utilization, memory utilization, and single-step inference time percentage of the chip are obtained; the CPU utilization, memory utilization, and single-step inference time percentage are normalized to obtain normalized values ​​for CPU utilization, memory utilization, and single-step inference time percentage; the minimum value of the normalized values ​​for CPU utilization, memory utilization, and single-step inference time percentage is extracted to obtain the computing power surplus value; the computing power surplus value is then converted into a load percentage to obtain the computing power load.

[0132] For example, CPU utilization refers to the proportion of processor time occupied by an embedded platform chip in executing tasks per unit time, reflecting the busyness of the chip's computing core; memory utilization refers to the proportion of available storage space on the chip occupied by the currently running program; single-step inference time consumption refers to the proportion of time required to complete one model inference within a preset inference cycle, reflecting the degree to which inference tasks occupy time resources.

[0133] Normalization refers to mapping the three indicators to dimensionless values ​​between 0 and 1 to facilitate unified comparison.

[0134] The computing power surplus value refers to the proportion of available computing power that the chip can currently provide after considering the above three indicators. The minimum value among the three remaining values ​​is taken, and the most scarce resource is used as the representation of the overall computing power surplus.

[0135] Load percentage conversion refers to converting the computing power surplus value into a chip computing power load value. A higher load value indicates that the chip is busier. The load value is equal to 1 minus the computing power surplus value. For example, during the operation of an embedded platform, the chip's CPU utilization, memory utilization, and single-step inference time percentage are collected in real time. These three indicators are normalized: if the indicator itself is a percentage value between 0 and 1, it is directly used as the corresponding normalized value. Then, 1 is subtracted from the normalized value of CPU utilization, memory utilization, and single-step inference time percentage to obtain the three remaining resource ratios. The minimum value of these three remaining resource ratios is extracted and taken as the computing power surplus value, representing the available computing power ratio determined by the most limited resources of the current chip. Finally, the computing power surplus value is converted into a load percentage, and the computing power load value is obtained by subtracting the computing power surplus value from 1. This load value is stored in the global status register for subsequent steps.

[0136] This step simultaneously collects three metrics: CPU utilization, memory usage, and the percentage of time spent in single-step inference. The minimum of these three metrics representing remaining resources is used to determine the degree of computing power surplus. This effectively identifies the most critical bottleneck in chip resources, avoiding misjudgments caused by relying on a single metric. For example, when CPU utilization is low but memory usage is high, looking only at CPU usage might mistakenly indicate sufficient computing power, while taking the minimum value reflects the true situation of memory constraints. Furthermore, converting the degree of computing power surplus into computing load provides an accurate and reliable quantitative basis for subsequent dynamic matching of inference accuracy and adjustment of the inference cycle, thereby improving the adaptability and stability of the multi-state estimation system under complex load conditions.

[0137] S202. Determine the executable instructions based on the computing load and the preset set of executable instructions; determine the inference cycle configuration based on the computing load.

[0138] For example, this step can be referred to step S102, and will not be described again.

[0139] In one example, the computing load is compared with a preset threshold. If the computing load is determined to be less than the preset threshold, an executable instruction is determined as the first executable instruction based on a preset set of executable instructions. The first executable instruction is an inference instruction using 16-bit fixed-point quantization. If the computing load is determined to be greater than or equal to the preset threshold, an executable instruction is determined as the second executable instruction based on the preset set of executable instructions. The second executable instruction is an inference instruction using 8-bit fixed-point quantization.

[0140] For example, the preset threshold refers to the computing load judgment benchmark value that is preset and stored in the embedded platform, used to divide the chip into different load ranges; the preset threshold is one of the specific preset thresholds.

[0141] The pre-defined executable instruction set refers to multiple sets of executable instructions that are pre-compiled and stored in the chip memory during the model deployment phase. Each instruction set corresponds to different inference precision and computational overhead.

[0142] The first executable instruction is an inference instruction using 16-bit fixed-point quantization, which means that during the model inference process, the weight parameters, input data and intermediate calculation results inside the model are all represented and operated using 16-bit fixed-point integers, which has high computational accuracy and moderate computational overhead.

[0143] The second executable instruction is an inference instruction using 8-bit fixed-point quantization. This means that data during model inference is represented and processed using 8-bit fixed-point integers, resulting in faster computation speed and lower storage usage, but with lower precision than 16-bit fixed-point inference. For example, after obtaining the chip's computing load, this load value is compared with a preset threshold. If the computing load is less than the preset threshold, it indicates that the chip's current computing resources are relatively abundant and can handle high-precision inference calculations. In this case, the first executable instruction (i.e., an inference instruction using 16-bit fixed-point quantization) is matched from the preset executable instruction set, and the inference function pointer is pointed to the 16-bit fixed-point operator library entry. If the computing load is greater than or equal to the preset threshold, it indicates that the chip's current computing resources are relatively strained. In this case, the second executable instruction (i.e., an inference instruction using 8-bit fixed-point quantization) is matched from the preset executable instruction set, and the inference function pointer is pointed to the 8-bit fixed-point operator library entry. Through this method, the inference engine will perform layer-by-layer calculations according to the fixed-point bit-width mode corresponding to the matched executable instruction during subsequent model inference.

[0144] In one example, if the computing load is determined to be less than a first threshold, the inference cycle is configured as follows: 100ms for the SOC estimation task, 500ms for the SOE estimation task, and 10s for the SOH estimation task. If the computing load is determined to be greater than or equal to the first threshold and less than a second threshold, the inference cycle is configured as follows: 100ms for the SOC estimation task, 1000ms for the SOE estimation task, and 30s for the SOH estimation task. If the computing load is determined to be greater than or equal to the second threshold, the inference cycle is configured as follows: 500ms for the SOC estimation task, 5ms for the SOE estimation task, and 60s for the SOH estimation task.

[0145] For example, the first threshold and the second threshold are preset benchmark values ​​for judging computing load, used to divide the computing load of the chip into three intervals; the first threshold is less than the second threshold, for example, the first threshold is 50% and the second threshold is 80%.

[0146] Inference cycle configuration refers to the inference trigger cycle set for SOC estimation task, SOE estimation task and SOH estimation task respectively according to the current computing power load range of the chip; the shorter the inference cycle, the higher the frequency of the corresponding state variable being estimated, and the greater the computing power consumption.

[0147] The State of Charge (SOC) estimation task is a task that infers and estimates the battery's state of charge. SOC directly relates to the battery's charge / discharge safety boundary, therefore a high execution frequency is required. The State of Energy (SOE) estimation task is a task that infers and estimates the battery's state of energy, used for system energy allocation, and has lower real-time requirements than SOC. The State of Health (SOH) estimation task is a task that infers and estimates the battery's state of health, characterizing the battery's long-term aging degree; changes are slow, and the execution frequency can be reduced. For example, after obtaining the chip's computing load, the load value is compared with a first threshold and a second threshold. When the computing load is less than the first threshold, it indicates that the chip's computing power is abundant. At this time, a 100ms inference cycle is configured for the SOC estimation task, a 500ms inference cycle for the SOE estimation task, and a 10s inference cycle for the SOH estimation task, ensuring that each task is executed at a high frequency. When the computing load is greater than or equal to the first threshold and less than the second threshold, it indicates that the chip's computing power is at a medium level. In this case, the inference cycle for the SOC estimation task remains unchanged at 100ms, while the inference cycle for the SOE estimation task is extended to 1000ms, and the inference cycle for the SOH estimation task is extended to 30s, to free up some computing power. When the computing load is greater than or equal to the second threshold, it indicates that the chip's computing power is strained. In this case, the inference cycle for the SOC estimation task is extended to 500ms, the inference cycle for the SOE estimation task is extended to 5s, and the inference cycle for the SOH estimation task is extended to 60s, ensuring stable system operation by reducing the overall execution frequency. These configuration parameters are written to the compare-match register of the timer peripheral, thereby updating the hardware timer overflow cycle corresponding to each state quantity estimation task.

[0148] S203. Perform fixed-point normalization on the voltage, current, and temperature data to obtain normalized fixed-point voltage, current, and temperature values; concatenate the normalized fixed-point voltage, current, and temperature values ​​into a fixed-dimensional feature vector; input the feature vector into the intelligent model for processing according to the executable instructions and inference cycle configuration to obtain battery state parameters.

[0149] For example, voltage data refers to the collected value of the terminal voltage of the energy storage battery; current data refers to the value of the current flowing through the battery during charging and discharging; and temperature data refers to the measured value of the battery body or ambient temperature.

[0150] Fixed-point normalization refers to the process of mapping the electrical parameters with different dimensions and numerical ranges to the interval [0,1] and representing them in the form of fixed-point integers; the fixed-point value is the value stored in a fixed-point format after normalization.

[0151] The feature vector is a fixed-dimensional vector formed by concatenating normalized voltage, current, and temperature fixed-point values ​​in a preset order, and is used as the input of the intelligent model.

[0152] Executable instructions refer to the operator execution sequence and fixed-point bit width mode corresponding to the intelligent model when performing inference on the embedded platform, which are used to control the model to perform operations with 16-bit or 8-bit fixed-point precision.

[0153] Inference cycle configuration refers to the inference trigger cycle set for each state quantity estimation task of SOC, SOE, and SOH based on the chip's computing power load, and is used to control when each task is executed.

[0154] The intelligent model is trained on historical electrical parameters using a neural network model and can output battery state parameters based on the input feature vector. These parameters include estimated State of Charge (SOC), State of Energy (SOE), and State of Health (SOH). For example, after acquiring voltage, current, and temperature data, fixed-point normalization is performed on each: the original values ​​are mapped to values ​​within the [0,1] interval based on the actual range of each parameter; then, the mapped floating-point values ​​are converted to fixed-point representations of the corresponding bit width, resulting in normalized fixed-point values ​​for voltage, current, and temperature. These three fixed-point values ​​are then concatenated into a fixed-dimensional feature vector according to a preset order. During inference execution, the current moment is determined based on the inference cycle configuration to determine if it is the trigger moment for the corresponding state quantity estimation task. If the trigger moment is reached, the feature vector is input into the intelligent model according to the fixed-point bit width mode corresponding to the executable instruction. The intelligent model performs convolution and fully connected operations layer by layer according to the operator execution sequence in the executable instruction to obtain the fixed-point estimates of the model's output layer. The fixed-point estimates are dequantized to convert them into floating-point values ​​with actual physical meaning, ultimately yielding the battery state parameters, namely the SOC estimate, SOE estimate, and SOH estimate.

[0155] In one example, the inference task trigger timer corresponding to the intelligent model is set according to the inference cycle configuration; based on the set inference task trigger timer, the feature vector is input into the intelligent model at the trigger time, and convolution and fully connected operations are performed layer by layer according to the inference instructions corresponding to the executable instructions to obtain the fixed-point estimate; the fixed-point estimate is dequantized to obtain the battery state parameters.

[0156] For example, the inference cycle configuration refers to the inference trigger cycle set for the SOC estimation task, SOE estimation task and SOH estimation task respectively according to the real-time computing power load of the embedded platform chip, which is used to control when each state quantity estimation task is executed.

[0157] The inference task trigger timer refers to a hardware timer peripheral in an embedded platform used to generate timer interrupts or trigger signals. When the timer overflows according to the preset period, it triggers the corresponding inference task to start execution.

[0158] Fixed-point estimates refer to the original output values ​​obtained in the output layer after the intelligent model completes convolution and fully connected operations according to fixed-point operation rules. These values ​​are represented in fixed-point format and have not yet been converted into floating-point results with actual physical meaning.

[0159] Dequantization refers to the process of converting fixed-point estimates into floating-point values ​​using preset scaling factors and zeros. For example, after obtaining the inference cycle configuration, the cycle values ​​corresponding to each state estimation task are written into the comparison matching register of their respective inference task trigger timer, completing the timer setting. The timer starts counting, and when the count value reaches the set value in the comparison matching register, an overflow event is generated. This overflow event is the trigger moment for the corresponding state estimation task. At the trigger moment, the pre-prepared feature vector is input into the intelligent model. The intelligent model determines the fixed-point bit-width mode used for this inference based on the currently matched executable instruction, and performs convolution and fully connected operations layer by layer according to the operator execution sequence in the executable instruction to obtain the fixed-point estimates of the model output layer. Dequantization is then performed on the fixed-point estimates, using the scaling factor and zeros of the output layer to convert the fixed-point values ​​into floating-point values ​​with actual physical meaning, obtaining the corresponding SOC estimate, SOE estimate, or SOH estimate. The above process is executed independently for different state estimation tasks, and each task is triggered independently according to its own inference cycle configuration and trigger timer.

[0160] In one possible implementation, the current computing load of the embedded platform chip is 42%, and the inference cycle is configured as 100ms for the SOC estimation task, 500ms for the SOE estimation task, and 10s for the SOH estimation task. The 100ms interval is written to the comparison matching register of the SOC inference task trigger timer, the 500ms interval is written to the comparison matching register of the SOE inference task trigger timer, and the 10s interval is written to the comparison matching register of the SOH inference task trigger timer. Taking the SOC estimation task as an example, the timer generates an overflow event every 100ms, and at the overflow moment, the feature vector [0.769, 0.625, 0.533] is input into the intelligent model. The currently matched executable instruction is a 16-bit fixed-point high-precision inference instruction. The intelligent model performs convolution and fully connected operations layer by layer according to the 16-bit fixed-point operator to obtain the fixed-point estimate of the output layer, for example, a fixed-point representation of [0.785, 0.752, 0.951]. The fixed-point estimates are dequantized to obtain SOC estimates of 78.5%, SOE estimates of 75.2%, and SOH estimates of 95.1%. These estimates are written to the output register and sent to the host computer or master node via the communication interface, completing this inference cycle.

[0161] In one example, the number of available computing units, available storage space, and available cache bandwidth of the embedded platform are obtained; the intermediate format file is parsed to obtain the operator execution queue and operator dependencies; the intermediate format file is obtained by processing the intelligent model; based on the number of available computing units, available storage space, and available cache bandwidth, the operator execution queue and operator dependencies are processed for computational simplification, timing reordering, and resource conflict avoidance to obtain at least two executable instruction sets; the at least two executable instruction sets are written into a preset executable instruction set.

[0162] For example, the number of available computing units refers to the number of computing units in the embedded platform chip that can be used to perform model inference operations, such as the number of available multiply-accumulate units, ALU units, or hardware accelerators. Available storage space refers to the remaining storage capacity in the chip's internal SRAM or external storage that can be used for model inference. Available cache bandwidth refers to the upper limit of the amount of data that the chip can complete data transfer or cache access per unit time, reflecting its data supply capacity.

[0163] The intermediate format file is a model description file obtained by encapsulating the intelligent model according to a preset storage structure after redundancy removal, fixed-point quantization and accuracy compensation. It records the operator type, operator parameters, weight data and dependencies between operators.

[0164] Operator parsing refers to parsing the model structure information in the intermediate format file field by field to extract the execution order of each operator during model inference and the data dependencies between operators. The operator execution queue refers to the execution sequence formed by arranging operators in logical order during model inference.

[0165] Operator dependency refers to the sequential constraint relationship formed when the output of one operator is used as the input of another operator.

[0166] Operation simplification refers to removing redundant operators and invalid computation branches. Timing reordering refers to readjusting the execution order of operators while satisfying dependencies to improve parallelism or reduce waiting. Resource conflict avoidance refers to preventing multiple operators from competing for the same hardware resource simultaneously, which could lead to conflicts or waiting.

[0167] An executable instruction set refers to the set of machine instruction sequences generated after the above processing, which can be directly executed by the chip. A preset executable instruction set is used to store multiple executable instruction sets for matching and calling based on runtime load.

[0168] For example, during the embedded platform deployment phase, the number of available computing units, available storage space, and available cache bandwidth of the chip are first obtained. Simultaneously, the intermediate format file undergoes operator parsing processing to extract all operators required for model inference and their dependencies, forming an operator execution queue and operator dependencies. Subsequently, based on the number of available computing units, the operator execution queue is simplified, removing redundant operators and invalid computation branches to reduce unnecessary computation. Next, based on operator dependencies and available cache bandwidth, the simplified operator execution queue is time-ordered, prioritizing operators that can be executed in parallel while ensuring correct data dependencies, optimizing the timing between data transfer and computation. Then, resource conflict avoidance processing is performed on the rearranged operator execution queue, analyzing the computing unit, storage space, and cache bandwidth requirements of each operator, and avoiding multiple operators competing for the same resource simultaneously by adjusting the execution order or inserting synchronization control. After the above processing, at least two executable instruction sets are generated; different instruction sets can correspond to different operator execution orders or different data segmentation strategies to adapt to different chip resource states. Finally, at least two executable instruction sets generated are written into a preset executable instruction set for runtime matching and invocation based on real-time computing load.

[0169] Understandably, the purpose of this step is to generate multiple optimized executable instruction sets based on the actual hardware resources of the embedded platform during the model deployment phase, for dynamic selection during the runtime phase.

[0170] In one example, the process involves acquiring the file of the intelligent model; performing structural parsing on the file to obtain the model structure information and initial weight parameter set; removing redundant operators from the model structure information to obtain a simplified core computation layer structure; performing fixed-point quantization on the initial weight parameter set in the simplified core computation layer structure to obtain a quantized fixed-point parameter set; performing precision compensation on the quantized fixed-point parameter set based on the rated electrical parameters of the energy storage battery to obtain a compensated quantized parameter set; encapsulating the compensated quantized parameter set in an intermediate format to obtain an intermediate format file; and deploying the intermediate format file on an embedded platform.

[0171] For example, the file for an intelligent model refers to the trained neural network model file, which contains the network structure definition and the weight parameters after training, and is usually stored in floating-point format. Model structure information refers to the structural description of each network layer in the model, such as the type, connection order, input and output dimensions, etc.

[0172] The initial weight parameter set refers to the set of all learnable parameters in the model, including convolutional kernel weights, fully connected layer weights, and bias terms. Redundant operator removal refers to analyzing the model structure and removing redundant operators and ineffective computational branches that do not contribute to the final output, thereby reducing the model's computational load. Simplifying the core computational layer structure refers to the set of network layers that remain after redundancy removal and that actually play a role in the model's inference.

[0173] Fixed-point quantization refers to the process of converting the weight parameters in the model, which were originally represented by 32-bit floating-point numbers, into 8-bit or 16-bit fixed-point integer representations to reduce storage usage and computational overhead.

[0174] The quantized fixed-point parameter set refers to the set of fixed-point format parameters obtained after quantization conversion.

[0175] The rated electrical parameters of an energy storage battery refer to the factory-specified parameters such as the battery's rated voltage, rated capacity, and internal resistance characteristics.

[0176] The compensated quantization parameter set refers to the set of fixed-point parameters after accuracy compensation. Intermediate format encapsulation processing refers to the process of packaging the compensated parameter set and model structure information into a specific format file according to a preset storage structure and parsing rules.

[0177] Intermediate format files are encapsulated model description files, making them easier for embedded platforms to parse and load. Deployment refers to writing the intermediate format file into the embedded platform's memory, enabling it to be read and executed on the platform.

[0178] For example, in the model deployment phase, the trained intelligent model file is first obtained. The intelligent model file undergoes structural analysis to extract the number of network layers, operator types, connection relationships, and weights and bias parameters of each layer, obtaining model structure information and an initial weight parameter set. Next, redundant operator removal is performed on the model structure information, identifying and deleting redundant operators and invalid computation branches that do not contribute to the model output, resulting in a simplified core computation layer structure. Then, the initial weight parameter set in the simplified core computation layer structure undergoes fixed-point quantization, converting 32-bit floating-point parameters into 8-bit or 16-bit fixed-point integers according to a preset quantization bit width, obtaining a quantized fixed-point parameter set. Based on this, precision compensation processing is performed on the quantized fixed-point parameter set based on the rated electrical parameters of the energy storage battery: according to the battery's rated voltage, rated capacity, and internal resistance characteristics, the scaling factor and bias term in the quantization parameters are adjusted to offset quantization errors, resulting in a compensated quantized parameter set. Next, the compensated quantization parameter set is encapsulated in an intermediate format according to a preset storage structure and parsing rules, writing the model structure information, quantization parameters, compensation parameters, and parsing information into an intermediate format file. Finally, the intermediate format file is deployed on an embedded platform and written into the chip's non-volatile memory or external storage, completing the model deployment.

[0179] In one possible implementation, the trained intelligent model is a neural network containing three convolutional layers and two fully connected layers. The original weight parameters are stored in 32-bit floating-point format, and the model file size is 180KB. The model file undergoes structural parsing, yielding the model structure information as "Conv1(3×3×16)→ReLU→Pool→Conv2(3×3×32)→ReLU→Pool→Conv3(3×3×64)→ReLU→FC1(128)→FC2(3)", with an initial weight parameter set containing approximately 42,000 parameters. Redundancy operator removal is performed on the model structure information, revealing a residual connection branch after the second convolutional layer that has no impact on the output. Removing this branch results in a simplified core operation layer structure, reducing the number of parameters to approximately 40,000. Subsequently, fixed-point quantization is performed on the simplified initial weight parameter set. 16-bit fixed-point quantization is selected, converting the floating-point weights to 16-bit integers to obtain the quantized fixed-point parameter set. The energy storage battery has a rated voltage of 3.7V, a rated capacity of 50Ah, and an internal resistance of 5mΩ. Based on these rated parameters, accuracy compensation processing is performed on the quantized fixed-point parameter set. A 0.8% correction is added to the scaling factor of the output layer, and the bias term is adjusted accordingly to obtain the compensated quantized parameter set. The compensated quantized parameter set and the simplified model structure information are packaged according to a preset format to generate an intermediate format file with a file size of 96KB. Finally, this intermediate format file is written to the Flash memory of the embedded platform to complete the deployment.

[0180] In one example, the reference battery state value of the energy storage battery is obtained; the deviation between the battery state parameters and the reference battery state value is calculated to obtain the state deviation value; if the state deviation value is greater than a preset deviation threshold, the quantization parameter set in the intermediate format file is corrected online according to the state deviation value to obtain the corrected quantization parameter set; the corrected quantization parameter set is repackaged to obtain the updated intermediate format file; the intermediate format file is the file generated when deploying the model, and the intelligent model runs based on the intermediate format file.

[0181] For example, the reference battery state value refers to the battery state benchmark value obtained by independent estimation methods other than intelligent model inference, which is used to verify the accuracy of the model output results; the reference battery state value can be obtained by at least one of the ampere-hour integration method, open-circuit voltage method or Kalman filtering method.

[0182] Battery state parameters refer to the SOC, SOE, and SOH estimates output by the intelligent model after reasoning about the electrical parameters.

[0183] Deviation calculation refers to the process of calculating the difference between the battery state parameters output by the model and the reference battery state value to obtain the degree of deviation between the two. The state deviation value is a quantitative deviation result obtained after deviation calculation, reflecting the magnitude of the error between the model output and the reference value.

[0184] The preset deviation threshold refers to the upper limit of the allowable deviation set in advance. When the state deviation value exceeds this threshold, it is considered that the model parameters have drifted unacceptably and need to be corrected.

[0185] The quantization parameter set refers to the set of model parameters stored in the intermediate format file after fixed-point quantization and precision compensation, including the weight parameters, bias terms, and scaling factors of each layer.

[0186] Online correction processing refers to updating drifted parameters directly in the intermediate format file during embedded platform operation, without recompiling or reloading the entire model. The corrected quantization parameter set refers to the set of parameters obtained after correcting the drifted parameters.

[0187] Repackaging refers to repackaging the corrected parameters into a new intermediate format file according to the storage structure and parsing rules of the original intermediate format file. The updated intermediate format file is the model description file used to replace the original file after repackaging, and the intelligent model continues to run based on this updated file. For example, after the intelligent model outputs battery state parameters, a reference battery state value at the same or similar time is obtained. The SOC estimate, SOE estimate, and SOH estimate in the battery state parameters are respectively compared with the corresponding reference battery state value to calculate the state deviation value of each state quantity. The state deviation value is compared with a preset deviation threshold: if the state deviation value is less than or equal to the preset deviation threshold, it indicates that the deviation between the model output and the reference value is within an acceptable range, and the current intermediate format file remains unchanged; if the state deviation value is greater than the preset deviation threshold, it indicates that the model parameters have drifted, and online correction processing is required for the quantization parameter set in the intermediate format file. During online correction processing, the storage address and data segment of the drifted parameters in the intermediate format file are first located, and then the correction amount is calculated based on the state deviation value. The bias term and scaling factor are updated to obtain the corrected quantization parameter set. The corrected quantization parameter set is repackaged according to the original preset storage structure and parsing rules to obtain an updated intermediate format file. The updated intermediate format file replaces the original file, and the intelligent model runs based on the updated parameters in subsequent inference, thereby restoring the estimation accuracy.

[0188] This application provides a multi-state estimation method for energy storage batteries. It acquires the electrical parameters of the energy storage battery and the computing load of the embedded platform chip. Based on the computing load, it matches and determines executable instructions from a preset set of executable instructions, while adaptively determining the inference cycle configuration. Then, it performs fixed-point normalization on voltage, current, and temperature data and concatenates them into a fixed-dimensional feature vector. Finally, it inputs the feature vector into an intelligent model according to the executable instructions and inference cycle configuration to obtain the battery state parameters. This method achieves the effect of dynamically adjusting the model's inference instructions and inference cycle based on real-time computing load under the condition of limited computing resources on the embedded platform, balancing the accuracy of multi-state estimation and operational efficiency. The fixed-point normalization effectively reduces floating-point operation overhead, the fixed-dimensional feature vector ensures the consistency of model input, and the computing power-driven adaptive scheduling mechanism enables the intelligent model to operate stably under different load conditions. This improves the real-time performance, robustness, and resource utilization of the multi-state estimation method for energy storage batteries deployed on embedded systems.

[0189] In one possible implementation, the multi-state estimation method for energy storage batteries provided in this application further includes chip selection and matching processing when building an embedded platform. Specifically, the computing power parameters and main frequency parameters of the target low-power chip are matched and analyzed to obtain a computing power-main frequency matching result; the operating power consumption parameters and standby power consumption parameters of the target low-power chip are compared with thresholds to obtain a power consumption matching result; the number of ADC interfaces, communication interface protocol types, and the number of general-purpose I / O ports of the target low-power chip are matched and analyzed with the number of sensor acquisition channels, analog front-end protocol requirements, and peripheral control requirements to obtain an interface resource matching result; a comprehensive judgment is made based on the computing power-main frequency matching result, the power consumption matching result, and the interface resource matching result. When all three conditions are met, a chip selection confirmation signal suitable for energy storage battery monitoring is obtained.

[0190] Optionally, the embedded platform chip is also equipped with a three-level power scheduling mechanism. Specifically, the operating power consumption parameters, task idle time parameters, and sensor trigger status parameters of the target low-power chip are monitored and comprehensively analyzed in real time to obtain the system operating status classification results. According to the system operating status classification results, when no data acquisition action is detected for 500ms and the algorithm inference task is not started, the chip performs a deep standby mode switching process and shuts down the power supply to peripherals, resulting in a low-power state with standby power consumption ≤50mW. According to the system operating status classification results, when a change in voltage, current, or temperature sensor signal is detected or the inference task is triggered, the chip performs a normal operating mode wake-up process and shuts down unused interface modules, resulting in a normal operating state with operating power consumption ≤500mW.

[0191] Optionally, the multi-state estimation method for energy storage batteries provided in this application embodiment further includes master-slave node partitioning. Specifically, multiple embedded nodes in the energy storage system are configured with roles, with one node configured as the master node and the remaining nodes configured as slave nodes, resulting in a master-slave node network topology.

[0192] The master-slave node partitioning process includes local processing at the slave nodes, communication between master and slave nodes, and global calibration. Specifically, local voltage, current, and temperature data are collected and processed for the batteries connected to each slave node. Local state inference is then performed using a multi-state estimation method to obtain local SOC, SOE, and SOH estimates, as well as inference error parameters for each slave node. These local SOC, SOE, SOH estimates, and inference error parameters are then packaged and cached to obtain the data packets to be uploaded by the slave nodes. A communication connection is established between the master node and each slave node via the MQTT-LW lightweight protocol. The slave nodes send the data packets to be uploaded to the master node, resulting in a multi-node dataset aggregated by the master node. A global weighted average calibration is performed on the hardware difference parameters, ambient temperature deviation parameters, voltage deviation parameters, and inference error quantification parameters of each slave node in the multi-node dataset to obtain global calibration correction coefficients. These global calibration correction coefficients are then distributed to each slave node via the MQTT-LW protocol. Each slave node compensates for its local inference results based on these correction coefficients, resulting in globally consistent distributed monitoring data.

[0193] Figure 3 This is a schematic diagram of the structure of a multi-state estimation device for an energy storage battery provided in an embodiment of this application, as shown below. Figure 3 As shown, the multi-state estimation device 30 for an energy storage battery provided in this embodiment is applied to an embedded platform. The device 30 includes:

[0194] The acquisition module 301 is used to acquire the electrical parameters of the energy storage battery and the computing load of the embedded platform chip.

[0195] The confirmation module 302 is used to determine the executable instructions based on the computing load and the preset set of executable instructions; and to determine the inference cycle configuration based on the computing load.

[0196] The processing module 303 is used to control the intelligent model to process electrical parameters based on executable instructions and inference cycle configuration to obtain battery state parameters; wherein, the intelligent model is obtained by training historical electrical parameters based on a neural network model; the battery state parameters include estimated state of charge (SOC), estimated state of energy (SOE), and estimated state of health (SOH).

[0197] In one possible implementation, the confirmation module 302 is specifically used for:

[0198] The computing load is compared with a preset threshold.

[0199] If it is determined that the computing load is less than a preset threshold, then based on the preset set of executable instructions, the executable instruction is determined as the first executable instruction, wherein the first executable instruction is an inference instruction using 16-bit fixed-point quantization;

[0200] If the computing load is determined to be greater than or equal to a preset threshold, then based on the preset set of executable instructions, the executable instruction is determined to be the second executable instruction, wherein the second executable instruction is an inference instruction using 8-bit fixed-point quantization.

[0201] In one possible implementation, the confirmation module 302 is specifically used for:

[0202] If the computing load is determined to be less than the first threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 100ms, the inference cycle of the SOE estimation task is 500ms, and the inference cycle of the SOH estimation task is 10s.

[0203] If it is determined that the computing load is greater than or equal to the first threshold and less than the second threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 100ms, the inference cycle of the SOE estimation task is 1000ms, and the inference cycle of the SOH estimation task is 30s.

[0204] If the computing load is determined to be greater than or equal to the second threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 500ms, the inference cycle of the SOE estimation task is 5ms, and the inference cycle of the SOH estimation task is 60s.

[0205] In one possible implementation, the electrical parameters include voltage data, current data, and temperature data; the processing module 303 is specifically used for:

[0206] The voltage, current, and temperature data are normalized to obtain normalized voltage, current, and temperature fixed-point values.

[0207] The normalized voltage fixed-point value, the normalized current fixed-point value, and the normalized temperature fixed-point value are concatenated into a feature vector of fixed dimensions.

[0208] Based on the executable instructions and inference cycle configuration, the feature vector is input into the intelligent model for processing to obtain battery state parameters.

[0209] In one possible implementation, the processing module 303 is further configured to:

[0210] Based on the inference cycle configuration, set the timer for triggering the inference task corresponding to the intelligent model;

[0211] Based on the inference task trigger timer set, the feature vector is input into the intelligent model at the trigger time, and convolution and fully connected operations are performed layer by layer according to the inference instructions corresponding to the executable instructions to obtain fixed-point estimates.

[0212] The fixed-point estimates are dequantized to obtain the battery state parameters.

[0213] In one possible implementation, the acquisition module 301 is specifically used for:

[0214] Obtain the chip's CPU utilization, memory usage, and percentage of time spent in single-step inference;

[0215] The CPU utilization, memory utilization, and single-step inference time percentage were normalized to obtain normalized values ​​for CPU utilization, memory utilization, and single-step inference time percentage.

[0216] The minimum values ​​of the normalized values ​​of CPU utilization, memory usage, and single-step inference time are extracted to obtain the computing power surplus value.

[0217] The computing load is obtained by converting the load percentage based on the computing power surplus value.

[0218] In one possible implementation, prior to the acquisition module 301, the device further includes a processing submodule 304, which is specifically used for:

[0219] Obtain the number of available computing units, available storage space, and available cache bandwidth for the embedded platform;

[0220] The intermediate format file is parsed to obtain the operator execution queue and operator dependencies; the intermediate format file is obtained by processing the intelligent model.

[0221] Based on the number of available computing units, available storage space, and available cache bandwidth, the operator execution queue and operator dependencies are processed for computational simplification, timing reordering, and resource conflict avoidance to obtain at least two executable instruction sets.

[0222] Write at least two executable instruction sets into the preset executable instruction set.

[0223] In one possible implementation, the device 30 further includes a deployment module 305, which is specifically used for:

[0224] Obtain the file of the intelligent model; and perform structural parsing on the file of the intelligent model to obtain the model structure information and the initial weight parameter set;

[0225] Redundant operators are removed from the model structure information to obtain a simplified core computation layer structure;

[0226] The initial weight parameter set in the simplified core computing layer structure is subjected to fixed-point quantization to obtain the quantized fixed-point parameter set.

[0227] Based on the rated electrical parameters of the energy storage battery, the quantized fixed-point parameter set is subjected to accuracy compensation processing to obtain the compensated quantized parameter set.

[0228] The compensated quantization parameter set is encapsulated in an intermediate format to obtain an intermediate format file; the intermediate format file is then deployed on an embedded platform.

[0229] In one possible implementation, the device 30 further includes an update module 306, which is specifically used for:

[0230] Obtain the reference battery state value of the energy storage battery;

[0231] The deviation between the battery state parameters and the reference battery state value is calculated to obtain the state deviation value.

[0232] If the state deviation value is greater than the preset deviation threshold, the quantization parameter set in the intermediate format file is corrected online according to the state deviation value to obtain the corrected quantization parameter set.

[0233] The corrected quantization parameter set is repackaged to obtain an updated intermediate format file; the intermediate format file is the file generated when deploying the model, and the intelligent model runs based on the intermediate format file.

[0234] This embodiment provides a multi-state estimation device for an energy storage battery, which can execute the method provided in the above-described method embodiment. Its implementation principle and technical effect are similar, and will not be described in detail here.

[0235] Figure 4 This is a schematic diagram of an embedded platform provided in an embodiment of this application. Figure 4 As shown, the electronic device 40 provided in this embodiment includes at least one chip 401 and a memory 402. Optionally, the device 40 further includes a communication component 403. The chip 401, memory 402, and communication component 403 are connected via a bus 404.

[0236] In the specific implementation process, at least one chip 401 executes computer execution instructions stored in memory 402, causing at least one chip 401 to perform the above-described method.

[0237] The specific implementation process of chip 401 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so it will not be repeated here.

[0238] In the above embodiments, it should be understood that the chip can be a processor, which can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0239] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device.

[0240] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0241] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0242] This application also provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, implement the above-described method.

[0243] The aforementioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium can be any available medium accessible to a general-purpose or special-purpose computer.

[0244] An exemplary readable storage medium is coupled to a processor, enabling the processor to read information from and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and the readable storage medium can exist as discrete components in the device.

[0245] The division of units is merely a logical functional division; in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0246] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0247] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0248] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0249] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0250] Finally, it should be noted that other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This invention is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein, and is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

Claims

1. A multi-state estimation method for an energy storage battery, characterized in that, The method is applied to an embedded platform; the method includes: Obtain the electrical parameters of the energy storage battery; and obtain the computing load of the embedded platform's chips; Based on the computing load and the preset set of executable instructions, determine the executable instructions; based on the computing load, determine the inference cycle configuration; Based on the executable instructions and the inference cycle configuration, the intelligent model is controlled to process the electrical parameters to obtain battery state parameters; wherein, the intelligent model is obtained by training historical electrical parameters based on a neural network model; the battery state parameters include estimated state of charge (SOC), estimated state of energy (SOE), and estimated state of health (SOH).

2. The method according to claim 1, characterized in that, Based on the computing power load and the preset set of executable instructions, executable instructions are obtained, including: The computing load is compared with a preset threshold. If it is determined that the computing load is less than a preset threshold, then based on the preset set of executable instructions, the executable instruction is determined to be the first executable instruction, wherein the first executable instruction is an inference instruction using 16-bit fixed-point quantization; If the computing load is determined to be greater than or equal to a preset threshold, then based on the preset set of executable instructions, the executable instruction is determined to be a second executable instruction, wherein the second executable instruction is an inference instruction using 8-bit fixed-point quantization.

3. The method according to claim 1, characterized in that, Based on the computing power load, determine the inference cycle configuration, including: If it is determined that the computing power load is less than the first threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 100ms, the inference cycle of the SOE estimation task is 500ms, and the inference cycle of the SOH estimation task is 10s. If it is determined that the computing load is greater than or equal to the first threshold and less than the second threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 100ms, the inference cycle of the SOE estimation task is 1000ms, and the inference cycle of the SOH estimation task is 30s. If the computing load is determined to be greater than or equal to the second threshold, then the inference cycle is configured as follows: the inference cycle of the SOC estimation task is 500ms, the inference cycle of the SOE estimation task is 5ms, and the inference cycle of the SOH estimation task is 60s.

4. The method according to claim 1, characterized in that, The electrical parameters include voltage data, current data, and temperature data; Based on the executable instructions and the inference cycle configuration, the intelligent model is controlled to process the electrical parameters to obtain battery state parameters, including: The voltage data, current data, and temperature data are subjected to fixed-point normalization to obtain normalized fixed-point voltage values, normalized fixed-point current values, and normalized fixed-point temperature values. The normalized voltage fixed-point value, the normalized current fixed-point value, and the normalized temperature fixed-point value are concatenated into a feature vector of fixed dimensions. Based on the executable instructions and the inference cycle configuration, the feature vector is input into the intelligent model for processing to obtain the battery state parameters.

5. The method according to claim 4, characterized in that, Based on the executable instructions and the inference cycle configuration, the feature vector is input into the intelligent model for processing to obtain the battery state parameters, including: Based on the inference cycle configuration, the timer for triggering the inference task corresponding to the intelligent model is set; Based on the set inference task trigger timer, the feature vector is input into the intelligent model at the trigger time, and convolution and fully connected operations are performed layer by layer according to the inference instructions corresponding to the executable instructions to obtain fixed-point estimates. The fixed-point estimate is dequantized to obtain the battery state parameters.

6. The method according to claim 1, characterized in that, Obtain the computing load of the embedded platform's chips, including: Obtain the CPU utilization rate, memory utilization rate, and single-step inference time percentage of the chip; The CPU utilization rate, memory utilization rate, and single-step inference time ratio are normalized to obtain normalized values ​​for CPU utilization rate, memory utilization rate, and single-step inference time ratio. The normalized values ​​of CPU utilization, memory usage, and single-step inference time are extracted by minimizing the values ​​to obtain the computing power surplus value. The computing power load is obtained by converting the computing power surplus value into a load percentage.

7. The method according to claim 1, characterized in that, Before obtaining the electrical parameters of the energy storage battery, the method further includes: Obtain the number of available computing units, available storage space, and available cache bandwidth of the embedded platform; The intermediate format file is parsed to obtain the operator execution queue and operator dependencies; wherein, the intermediate format file is obtained by processing the intelligent model; Based on the number of available computing units, the available storage space, and the available cache bandwidth, the operator execution queue and the operator dependency are processed for computational simplification, timing reordering, and resource conflict avoidance to obtain at least two executable instruction sets. Write the at least two executable instruction sets into the preset executable instruction set.

8. The method according to any one of claims 1-7, characterized in that, The method further includes: Obtain the file of the intelligent model; and perform structural parsing processing on the file of the intelligent model to obtain the model structure information and the initial weight parameter set; Redundant operators are removed from the model structure information to obtain a simplified core operation layer structure; The initial weight parameter set in the simplified core operation layer structure is subjected to fixed-point quantization to obtain the quantized fixed-point parameter set. Based on the rated electrical parameters of the energy storage battery, the quantized fixed-point parameter set is subjected to accuracy compensation processing to obtain the compensated quantized parameter set. The compensated quantization parameter set is encapsulated in an intermediate format to obtain an intermediate format file; the intermediate format file is then deployed on the embedded platform.

9. The method according to any one of claims 1-7, characterized in that, The method further includes: Obtain the reference battery state value of the energy storage battery; The deviation between the battery state parameters and the reference battery state value is calculated to obtain the state deviation value; If the state deviation value is greater than the preset deviation threshold, the quantization parameter set in the intermediate format file is corrected online according to the state deviation value to obtain the corrected quantization parameter set. The corrected quantization parameter set is repackaged to obtain an updated intermediate format file; wherein, the intermediate format file is a file generated when deploying the model, and the intelligent model runs based on the intermediate format file.

10. An embedded platform, characterized in that, include: Memory, chip; The memory stores computer-executed instructions; The chip executes computer execution instructions stored in the memory, causing the chip to perform the method as described in any one of claims 1-9.

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