A digital anticoincidence algorithm-based 37 Ar detector electronics system

Abstract

The application discloses a kind of based on digital anticoincidence algorithm 37 The Ar detector electronics system includes a data acquisition module, a data processing and system control module, and a voltage generation module. The data acquisition module realizes the conditioning and digitization of the input signal. The data processing and system control module realizes the processing of the input signal. The system realizes high-voltage and low-voltage output voltage control and communication with the host computer. It uses a fully digital signal processing method, greatly simplifies the complexity of the hardware, improves the integration, increases the reliability, is beneficial to use in mobile and outdoor scenarios, has strong anti-accumulation ability, and avoids the influence of residual pulses left by incomplete signal elimination by analog anticoincidence on spectrum formation.

Description

Technical Field

[0001] This application relates to the field of nuclear electronics technology, and in particular to a digital anti-coincidence algorithm. 37 Ar detector electronics system. Background Technology

[0002] Nuclear tests produce a large number of neutrons, which react with the rocks surrounding the nuclear explosive device. 40 Ca occurs 40 Ca(n, ) 37 Ar reaction, producing a large amount of 37 Ar. 37 Ar has limited sources, a short half-life (35.04 days), and very weak radioactivity; the natural background is only 4.7 × 10⁻⁶. -7 Bq / L; and Ar, as an inert gas, does not participate in chemical reactions and easily diffuses to the surface through geological fissures, therefore it can be collected on-site for several months after a nuclear explosion. Based on its advantages in verification, including extremely low radioactivity, clearly identifiable source, and escape characteristics, 37 Ar has been designated by the Comprehensive Nuclear-Test-Ban Treaty Organization (CTBTO) as a nuclide for on-site inspections. Therefore, achieving high sensitivity... 37 Ar measurement is a core guarantee for verifying the feasibility of underground nuclear tests.

[0003] based on 37 The weak radioactivity of Ar is generally addressed by lowering the measurement limit through methods such as improving detection efficiency, increasing detection time, and reducing the background of the measuring device. However, currently... 37 The proportional counter tubes used in Ar arms control inspections have already achieved a detection efficiency of 90%, leaving limited room for improvement. This was discussed during on-site inspections of arms control verification. 37 The special constraints of Ar measurement (prohibition of long-term residence) render the traditional "increasing measurement time" approach ineffective, making the innovation of electronic systems the core path to break through the bottleneck.

[0004] Background radiation primarily originates from the decay of naturally occurring radioactive nuclides. To effectively reduce background radiation, heavy element materials are typically used to shield the detector. Using 10cm of lead as shielding material can attenuate the influence of external gamma rays to an acceptable level. However, a 10cm thick lead shield would make the entire detector weigh over 600kg (e.g., MARDS-II), making it unsuitable for mobile applications such as field inspections. Furthermore, newly produced lead itself possesses a certain level of background radioactivity; using older lead or low-background lead from the electronics industry would be prohibitively expensive. Additionally, the hard components of cosmic rays... The background radiation from secondary gamma rays and neutrons produced by nuclear neutron generation is also difficult to completely eliminate in mobile applications. While waveform discrimination can be used to remove background radiation in nuclear detection, this is not always feasible due to... 37 Ar decays with an energy of only 2.38 keV, which is easily absorbed by Compton scattering of external gamma rays, making it impossible to distinguish using waveform amplitude analysis. 37 Ar decay electrons and Compton electrons. Therefore, to further reduce the impact of background radiation, in addition to the proper use of shielding materials, anti-coincidence discrimination technology should be used to further reduce the impact of background radiation. 37 The impact of Ar's on-site inspection.

[0005] In existing technologies, the internal components of anti-coincidence detection systems are filled with... 37 For Ar sampling, the main detector is a proportional counter tube, and the anti-coincidence detector is a well-shaped plastic scintillator. A photomultiplier tube converts the optical signal from the plastic scintillator into an electrical signal. The interaction between background gamma rays and the anti-coincidence detection system involves three main processes: first, all the energy of the gamma rays is deposited on the anti-coincidence detector; second, some energy is deposited in the anti-coincidence detector after Compton scattering, and then enters the main detector where it is deposited; and third, external gamma rays pass through the anti-coincidence detector without depositing energy, but enter the main detector where energy is deposited. The first two scenarios both cause the anti-coincidence detector to output energy. Furthermore, due to the different detectors, the first two scenarios are far more likely to occur than the third. 37 The energy from Ar decay is entirely deposited in the main detector, causing only its output. Therefore, by using anti-coincidence discrimination—that is, when the anti-coincidence detector outputs a pulse, the output signals of the main detector within a certain period before and after it are discarded—the background can be suppressed.

[0006] Achieving anti-coincidence identification requires the collaboration of an anti-coincidence detection system and a compatible anti-coincidence electronics system. In the laboratory, anti-coincidence electronics requires two preamplifiers, two high-voltage DC channels, and two low-voltage DC channels to process the detector output signal; a gate generator and signal delay unit for anti-coincidence; and a multichannel analyzer for spectrum generation. These components are necessary to meet the electronic requirements of an anti-coincidence detection system. In addition, a NIM chassis and several cable assemblies are required, and a digitizer or oscilloscope is typically needed for system setup and debugging. The aforementioned anti-coincidence electronics system is numerous, large, and complex, limiting its use to laboratory settings or limited field demonstrations. In actual field inspections, the NIM's plug-in electronics system struggles to withstand harsh transportation conditions and on-site environments. System parameters are easily affected by the environment, and the debugging process is lengthy, hindering the efficiency of military control verification operations. As the number of measurement samples increases, the system complexity increases proportionally. Therefore, current anti-coincidence electronics systems limit their application in... 37Scope of use in Ar on-site inspections.

[0007] In summary, there is a need to invent a rapidly deployable electronic system with anti-coincidence energy spectrum measurement capabilities, as well as auxiliary functions required for measurement and system deployment, and at least two sets of digital anti-coincidence measurement capabilities to meet the requirements. 37 Ar requires on-site inspection. Summary of the Invention

[0008] In view of this, in order to solve 37 Ar's on-site inspection revealed problems such as insufficient system integration, low deployment efficiency, poor reliability, and weak on-site adaptability. This invention provides a solution based on a digital anti-conformance algorithm. 37 An Ar detector electronics system is characterized by comprising: a data acquisition module, a data processing and system control module, and a voltage generation module. The data acquisition module conditions and digitizes the input signal for subsequent fully digital signal processing. The data processing and system control module processes the input signal, including signal correction, shaping, parameter extraction of the shaped pulse, digital inverse coincidence, spectrum generation, waveform acquisition, and parameter analysis. It also controls the high-voltage and low-voltage outputs and communicates with a host computer. The data processing and system control module controls the voltage generation module to supply the high-voltage and low-voltage power required by the preamplifier. The voltage generation module includes a high-voltage generation module, an LDO regulator, and a DAC auxiliary control unit. The data processing and control module controls the voltage generation module to achieve voltage output and power-on / power-off timing control.

[0009] Furthermore, the data acquisition module consists of a signal conditioning unit, an ADC conversion unit, and a clock unit. The signal conditioning unit first adjusts the gain of the detector's input signal to match the ADC's input amplitude requirements; then, it performs baseline calibration on the input signal to maximize the utilization of the ADC's input dynamic range; next, it converts the single-ended input signal into a differential signal to adapt to the ADC interface specification; finally, it performs analog anti-aliasing filtering on the differential signal to generate a conditioning signal to suppress high-frequency interference. The ADC conversion unit digitizes the conditioning signal and transmits it to the data processing and control module. The clock unit provides a low-jitter sampling clock for the ADC.

[0010] Furthermore, the data acquisition module is equipped with a waveform monitoring module. Based on the waveform correction and the digitally shaped signal as input, the module uses channel triggering to capture the waveform and analyze whether there are any abnormalities in the waveform signal count and ladder formation.

[0011] Furthermore, the data processing and control module uses a SoC-type Field-Programmable Gate Array (FPGA) chip as its processing core, specifically an FPGA with an ARM core. This is achieved through a programmable logic (PL) module. 37 Real-time signal processing for Ar anti-coincidence measurement; the data processing and control module implements system control for signals from the ADC conversion unit, performing gain adjustment, baseline calibration, and voltage regulation on the signals; after receiving the signals, the data processing and control module performs waveform analysis, correcting all signals to positive polarity and adjusting the signal gain; making the vertical resolution of waveform sampling more accurate.

[0012] Furthermore, the data processing and control module digitally shapes the signal using a trapezoidal shaping method. The ladder forming algorithm uses formulas (1) and (2): Formula (1) Formula (2) In the formula, The input sequence is... The output sequence represents the shaped trapezoidal pulses. Indicates the sampling period (corresponding to the sampling rate of the ADC). This represents the decay time constant of the nuclear pulse signal. The shaping algorithm contains three shaping parameters: Indicates the peak time of the digital trapezoidal pulse. This represents the sum of the peak time and the digital trapezoidal pulse peak. This represents the width of the digital trapezoidal pulse. Wherein, , , In the formula, , These represent the rising edge width and pulse width of the trapezoidal pulse, respectively. The formed signal is continuously fed into the parameter extraction module. The peak value and arrival time of the input pulse are determined by calculating the height of the trapezoid and its arrival time. Then, the peak value and arrival time of the input pulse are encapsulated together and transmitted to the spectrum generation module. The spectrum generation module is built on a dual-port RAM. The amplitude data input to the spectrum generation module serves as the RAM address. Whenever data is input, the data corresponding to the RAM address is read, incremented by 1, and then written back. Because a dual-port RAM is used, the uploading of spectrum data is not affected during spectrum generation; data can be read sequentially from address 0 during uploading.

[0013] Furthermore, the high-voltage output voltage in the voltage generation module is controlled by the DAC auxiliary control unit. The data processing and control module controls the output voltage of the high-voltage module by controlling the voltage of the DAC auxiliary control unit. The high-voltage output uses a resistor divider, is sampled by an ADC, and then fed back to the data processing and control module. The data processing and control module then adjusts the output of the DAC auxiliary control unit to stabilize the high voltage at the set value. The low-voltage DC in the voltage generation module is used to power the preamplifier.

[0014] Furthermore, the voltage generation module uses an LDO regulator to generate two sets of fixed low-voltage DC voltages: ±12V and ±24V. ±12V and ±24V serve as the power supply voltage for the preamplifier, meeting the general requirements of nuclear measurements.

[0015] Furthermore, the data acquisition module receives signals from four detectors. All four signal input ports are equivalent, and the four signals are paired and assigned to two anti-coincidence modules according to the settings. This invention employs a digital anti-coincidence technique, only determining whether the pulse time parameters extracted from the two input channels meet the anti-coincidence conditions. Specifically, it compares whether there are anti-coincidence detector input pulses within a certain range before and after the extraction time point of the main detector input pulse after laddering. If present, this data is discarded; otherwise, it is sent to the spectrum generation module for spectrum generation. The time range before and after the comparison can be adjusted as needed, correcting inconsistencies in signal transmission link delays, eliminating the need for signal delayers and gate generators, and avoiding interference from simulated anti-coincidence residual pulse waveforms on the final spectrum generation.

[0016] Furthermore, the detector's electronics system adopts a desktop single-board integrated design, integrating all hardware functions such as data acquisition, data processing, system control, and voltage generation onto a single board. To adapt to the power supply standards of different countries during field inspections, the power input range is 90~250VAC, 50 / 60Hz.

[0017] Beneficial effects: This invention employs a fully digital signal processing method, significantly simplifying hardware complexity, improving integration, and increasing reliability, making it suitable for use in mobile and outdoor scenarios. The digital anti-coincidence method used in this invention has strong anti-stacking capabilities, avoiding the influence of residual pulses left by incomplete signal elimination in analog anti-coincidence on spectral analysis. This invention integrates high-voltage and low-voltage power supplies, facilitating test system setup, enabling rapid deployment, and centralized control. This invention integrates four-channel data acquisition, enabling simultaneous measurement of two sets of anti-coincidence samples, saving time during on-site inspections. Attached Figure Description

[0018] Figure 1 A schematic diagram of an existing anti-coincidence detection system; Figure 2This invention is based on a digital anti-coincidence algorithm. 37 Ar detector electronics system hardware block diagram; Figure 3 This invention is based on a digital anti-coincidence algorithm. 37 Schematic diagram of the data processing and control module in the Ar detector electronics system; Figure 4 This is a schematic diagram of the logical algorithm structure for ladder formation in this invention. Detailed Implementation

[0019] The technical solution of the present invention will be described below with reference to the accompanying drawings.

[0020] A schematic diagram of an anti-coincidence detection system is shown below. Figure 1 As shown, the interior is filled with 37 For Ar sampling, the main detector is a proportional counter tube, and the anti-coincidence detector is a well-shaped plastic scintillator. A photomultiplier tube converts the optical signal from the plastic scintillator into an electrical signal. The interaction between background gamma rays and the anti-coincidence detection system involves three main processes: first, all the energy of the gamma rays is deposited on the anti-coincidence detector; second, some energy is deposited in the anti-coincidence detector after Compton scattering, and then enters the main detector where it is deposited; and third, external gamma rays pass through the anti-coincidence detector without depositing energy, but enter the main detector where energy is deposited. The first two scenarios both cause the anti-coincidence detector to output energy. Furthermore, due to the different detectors, the first two scenarios are far more likely to occur than the third. 37 The energy from Ar decay is entirely deposited in the main detector, causing only its output. Therefore, by using anti-coincidence discrimination—that is, when the anti-coincidence detector outputs a pulse, the output signals of the main detector within a certain period before and after it are discarded—the background can be suppressed.

[0021] This invention provides a method based on a digital anti-coincidence algorithm. 37 Ar detector electronics system, such as Figure 2 As shown, the system includes: a data acquisition module, a data processing and system control module, and a voltage generation module. The data acquisition module conditions and digitizes the input signal, facilitating subsequent all-digital signal processing. The data processing and system control module processes the input signal, including input signal correction, shaping, parameter extraction of the shaped pulse, digital inverse coincidence, spectrum generation, waveform acquisition, and parameter analysis. It also controls the high-voltage and low-voltage outputs and communicates with the host computer. The data processing and system control module controls the voltage generation module to provide the high-voltage and low-voltage power supply required by the preamplifier. The voltage generation module includes a high-voltage generation module, an LDO regulator, and a DAC auxiliary control unit. The data processing and control module controls the voltage generation module to achieve voltage output and power-on / power-off timing control.

[0022] Furthermore, the data acquisition module consists of a signal conditioning unit, an ADC conversion unit, and a clock unit. The signal conditioning unit first adjusts the gain of the detector's input signal to match the ADC's input amplitude requirements; then, it performs baseline calibration on the input signal to maximize the utilization of the ADC's input dynamic range; next, it converts the single-ended input signal into a differential signal to adapt to the ADC interface specification; finally, it performs analog anti-aliasing filtering on the differential signal to generate a conditioning signal to suppress high-frequency interference. The ADC conversion unit digitizes the conditioning signal and transmits it to the data processing and control module. The clock unit provides a low-jitter sampling clock for the ADC.

[0023] Furthermore, the data acquisition module is equipped with a waveform monitoring module. Based on the waveform correction and the digitally shaped signal as input, the module uses channel triggering to capture the waveform and analyze whether there are any abnormalities in the waveform signal count and ladder formation.

[0024] Because trapezoidal shaping requires prior knowledge of the peak time and decay time constant of the preamplifier output pulse, the trapezoidal shape must be... It must be greater than the peak time. In this module, by capturing the original waveform, the time from the threshold to the pulse peak can be obtained. This time can then be proportionally widened to obtain the value. Used. Simultaneously, a negative exponential fit is applied to the falling edge of the original waveform to obtain the amplifier attenuation time constant. This can be used for trapezoidal forming calculations.

[0025] Furthermore, the data processing and control module uses a SoC-type Field-Programmable Gate Array (FPGA) chip as its processing core, specifically an FPGA with an ARM core. This is achieved through a programmable logic (PL) module. 37 Real-time signal processing for Ar anti-coincidence measurement; the data processing and control module implements system control over the signal from the ADC conversion unit, performing gain adjustment, baseline calibration, and voltage regulation; after receiving the signal, the data processing and control module performs waveform analysis, correcting all signals to positive polarity and adjusting the signal gain; this makes the vertical resolution of waveform sampling more accurate. Because the nuclear signal is a unipolar signal, to maximize the utilization of the ADC input range, the analog front end adjusts the baseline to its highest or lowest value, and during waveform correction, the baseline of the digitized signal is readjusted to 0. Since the polarity of the preamplifier output signal varies depending on the preamplifier signal, all signals are corrected to positive polarity, and its operating mode is as follows: Figure 3 As shown.

[0026] The purpose of digital shaping is to transform the input pulse into a certain type of pulse while retaining some characteristics of the original pulse. While preserving amplitude and time characteristics, it can correct ballistic defects, reduce accumulation, and reduce the impact of noise. Ladder shaping performs delay, addition, subtraction, and multiplication operations on discrete signal sequences. These operations are very convenient for real-time signal processing in FPGAs through sequential logic in a pipeline manner.

[0027] Furthermore, the data processing and control module digitally shapes the signal using a trapezoidal shaping method. The ladder forming algorithm uses formulas (1) and (2): Formula (1) Formula (2) in, The input sequence is... The output sequence represents the shaped trapezoidal pulses. Indicates the sampling period (corresponding to the sampling rate of the ADC). This represents the decay time constant of the nuclear pulse signal. The shaping algorithm contains three shaping parameters: Indicates the peak time of the digital trapezoidal pulse. This represents the sum of the peak time and the digital trapezoidal pulse peak. This represents the width of the digital trapezoidal pulse. Wherein, , , In the formula, , These represent the rising edge width and pulse width of the trapezoidal pulse, respectively. ; After trapezoidal formation, both exponential kernel pulse signals are shaped into isosceles trapezoids with equal lower bases but different amplitudes, and high-frequency noise in the signal is filtered out. The shaped signals are continuously fed into the parameter extraction module. By calculating the height of the trapezoid and its arrival time, the peak value and arrival time of the input pulse are determined. Then, the peak value and arrival time of the input pulse are encapsulated and transmitted to the spectrum generation module. The spectrum generation module is built on a dual-port RAM. The amplitude data input to the spectrum generation module is used as the RAM address. Whenever a data is input, the data corresponding to the amplitude value at the RAM address is read, incremented by 1, and then written back. Because a dual-port RAM is used, the uploading of spectrum data is not affected during spectrum generation; data can be read sequentially from address 0 during uploading. The logical algorithm structure of the trapezoidal formation is as follows: Figure 4 As shown.

[0028] Furthermore, the high-voltage output voltage in the voltage generation module is controlled by the DAC auxiliary control unit. The data processing and control module controls the output voltage of the high-voltage module by controlling the voltage of the DAC auxiliary control unit. The high-voltage output uses a resistor divider, is sampled by an ADC, and then fed back to the data processing and control module. The data processing and control module then adjusts the output of the DAC auxiliary control unit to stabilize the high voltage at the set value. The low-voltage DC in the voltage generation module is used to power the preamplifier.

[0029] Furthermore, the voltage generation module uses an LDO regulator to generate two sets of fixed low-voltage DC voltages: ±12V and ±24V. ±12V and ±24V serve as the power supply voltage for the preamplifier, meeting the general requirements of nuclear measurements.

[0030] Furthermore, the data acquisition module receives signals from four detectors. All four signal input ports are equivalent, and the four signals are paired and assigned to two anti-coincidence modules according to the settings. This invention employs a digital anti-coincidence technique, only determining whether the pulse time parameters extracted from the two input channels meet the anti-coincidence conditions. Specifically, it compares whether there are anti-coincidence detector input pulses within a certain range before and after the extraction time point of the main detector input pulse after laddering. If present, this data is discarded; otherwise, it is sent to the spectrum generation module for spectrum generation. The time range before and after the comparison can be adjusted as needed, correcting inconsistencies in signal transmission link delays, eliminating the need for signal delayers and gate generators, and avoiding interference from simulated anti-coincidence residual pulse waveforms on the final spectrum generation.

[0031] Furthermore, the detector's electronics system adopts a desktop single-board integrated design, integrating all hardware functions such as data acquisition, data processing, system control, and voltage generation onto a single board. To adapt to the power supply standards of different countries during field inspections, the power input range is 90~250VAC, 50 / 60Hz.

[0032] Example 1 In this embodiment, the analog front-end in data acquisition uses DC coupling, 50 For input impedance, a digitally controlled attenuator (DCA) is used in conjunction with the AD8264 amplifier to achieve gain control, baseline adjustment, and single-ended to differential conversion. When the signal amplitude is greater than the ADC input range, the amplifier gain is set to 0 dB, and only the DCA provides amplitude attenuation. When the input signal amplitude range is less than the ADC input range, the DCA attenuation is set to 0 dB, and the amplifier provides the gain. This method reduces the noise figure by minimizing the amplifier gain. Because the preamplifier output signal is a unipolar signal, to maximize the utilization of the ADC input dynamic range, the input baseline needs to be adjusted to its maximum or minimum value through baseline adjustment. Both the AD8264 gain control and baseline control require external voltage; in this embodiment, a DAC is used to provide this voltage. The preamplifier output pulse rise time is approximately 40ms~50ms, and the AD8264 differential output bandwidth is 75MHz, meeting the signal's bandwidth requirements. The AD8264 output is connected to a Butterworth filter to further limit the bandwidth and suppress high-frequency noise. This embodiment uses the ADS54J69 ADC with 500Msps, 16-bit sampling, and then outputs 250Msps, 16-bit data through HB filtering to limit high-frequency noise, reduce aliasing, and provide a sufficiently high sampling rate for waveform monitoring.

[0033] Each signal is digitized and then processed by the SoC. In this embodiment, the ZYNQ-7000 series SoC is used. A dual-port ring memory with a depth of 16384 and a bit width of 16bit is built on the SoC's PL terminal. An 8-to-1 selector is used to select one of the four raw data streams and four shaped data streams for writing. Data is sequentially and cyclically stored into the ring memory according to its address. Upon triggering, the current write address is recorded, and a certain length is written according to the settings. Upon reading, the data is read from the pre-written count set before triggering, according to the settings.

[0034] After reading the data, find the time difference between the half-maximum of the rising edge and the peak value, and assume that this time difference is half of the rise time. Through data fitting, perform an exponential fit on the trailing edge of the input pulse to find the amplifier time constant.

[0035] Establish the following in the FPGA according to equations (1) and (2): Figure 4 The ladder diagram shown is a structural diagram of the algorithm. It includes six delays for the input signal, two delays for the output signal, and mixed operations of floating-point multiplication and addition / subtraction. In equation (2) , It must be greater than the amplifier's leading edge time. To facilitate anti-coincidence, in this embodiment, the signals of each channel are shaped into isosceles trapezoids with equal upper and lower bases. The set values ​​are all the same and greater than the maximum value of the rising edge of the input signal for each channel. Each channel's... The value represents the time constant of the amplifier connected to each channel. The laddering algorithm in this embodiment can achieve pipelined operation without dead-time limitations. The high 12 bits of data are extracted and sent to subsequent modules.

[0036] The waveform after laddering is sent to the parameter extraction module. When the input signal is greater than the effective threshold and five consecutive points of positive growth occur, peak finding is initiated. During peak finding, the current data is continuously compared with the historical maximum value, and the larger one replaces the historical maximum value in the register. During peak finding, when five consecutive points of negative growth occur, and the difference between the current data and the historical maximum value exceeds 1 / 64 of the historical maximum value, the maximum value in the register is considered to be the peak value, and this moment is the timing point.

[0037] The extracted data has a width of 64 bits. The high 52 bits represent the clock count value, and the low 12 bits represent the peak value; both are sent to the anti-coincidence module. In this embodiment, the anti-coincidence is implemented as follows: two FIFOs, 16 bits deep and 64 bits wide, are established, named FIFO_A and FIFO_B, with their corresponding outputs connected to register R. A and R B Assume the parameters of the input pulse to the anti-coincidence detector are stored in FIFO_A, the parameters of the input pulse to the main detector are stored in FIFO_B, and the parameters of the input pulse to the anti-coincidence detector are stored in FIFO_B. t f Time period and after t e The time interval within the time period is the inverse coincidence interval. When R A and R B When data is available for both, compare R. B Is it in R? A If the interval is inversely related to the given condition, then read the new data from FIFO_B into R. B If R B exist t f Previously, R B Send to the spectrum generation module for spectrum generation, if R B exist t f Then, new data is read from FIFO_A into R. A When R A There is data R B If there is no value in the counter, check if the counter is in the middle. t e Then, if R is present, update it. A If it is not present, no action is taken. When R... A No data available in R. B When there is data, compare R B With counter, if R B The time data is ahead of the counter by more than [time value].t e Then R B Send it for a score; otherwise, leave it unprocessed. Adjustments will be made. t e and t f It can adjust the coincidence interval and correct inconsistencies in the link delay of the detector output signal.

[0038] In this embodiment, a dual-port RAM with a depth of 4096 is built into the FPGA for data storage. After the pulse amplitude parameter is sent to the spectrum generation module, its amplitude is used as the address. The RAM data at the corresponding address is read, incremented by 1, and then stored back at the original address. When reading the spectrum data, it can be read sequentially starting from address 0.

[0039] In this embodiment, an onboard high-voltage module is selected to generate the control voltage via a DAC. 1G is used. and 1M The voltage is sampled using a resistor divider, and the sampled voltage is digitized by an ADC and fed back to the FPGA. The FPGA then uses a PID controller to stabilize the output voltage to the set value using a DAC. In this embodiment, an LDO is used to generate low-noise DC voltages of ±12V and ±24V, which are output via a DB9 interface for user selection.

[0040] The present invention has been described in detail above with reference to specific embodiments and exemplary examples. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments; the above descriptions should not be construed as limiting the present invention. Those skilled in the art will understand that various equivalent substitutions, modifications, or improvements can be made to the technical solutions and implementation methods of the present invention without departing from the spirit and scope of the invention, and all such modifications and improvements fall within the scope of the present invention; the scope of protection of the present invention is determined by the appended claims.

Claims

1. A digital anti-synthesis algorithm 37 Ar detector electronics system, characterized in that The detector's electronics system includes: a data acquisition module, a data processing and system control module, and a voltage generation module; The data acquisition module conditions and digitizes the input signal; the data processing and system control module processes the input signal, controls the voltage output of high and low voltages, and communicates with the host computer; the data processing and system control module controls the voltage generation module to provide the high and low voltage power supply required by the preamplifier; the voltage generation module includes a high voltage generation module, an LDO voltage regulator, and a DAC auxiliary control unit, and the data processing and control module controls the voltage generation module to achieve voltage output and power-on / power-off timing control.

2. A method based on the digital anti-coincidence algorithm according to claim 1 37 Ar detector electronics system, characterized in that The data acquisition module consists of a signal conditioning unit, an ADC conversion unit, and a clock unit. The signal conditioning unit first adjusts the gain of the detector's input signal, then performs baseline calibration on the input signal, then converts the single-ended input signal into a differential signal, and finally performs analog anti-aliasing filtering on the differential signal to generate a conditioning signal to suppress high-frequency interference. The ADC conversion unit digitizes the conditioning signal and transmits it to the data processing and control module. The clock unit provides a low-jitter sampling clock for the ADC.

3. A method based on the digital anti-coincidence algorithm according to claim 2 37 Ar detector electronics system, characterized in that The data acquisition module is equipped with a waveform monitoring module. It uses the waveform correction model and the digitally shaped signal as input, and uses channel triggering to capture the waveform for analysis of whether there are any abnormalities in the waveform signal count and ladder formation.

4. A method based on the digital anti-coincidence algorithm according to claim 1 37 Ar detector electronics system, characterized in that The data processing and control module implements system control on the signal from the ADC conversion unit, and performs gain adjustment, baseline calibration and voltage regulation on the signal. After receiving the signal, the data processing and control module performs waveform analysis, and all signals are corrected to positive polarity, and the gain of the signal is corrected.

5. A method based on the digital anti-coincidence algorithm according to claim 4 37 Ar detector electronics system, characterized in that The data processing and control module performs digital shaping on the signal using a trapezoidal shaping method. The trapezoidal shaping algorithm uses formulas (1) and (2): Official (1) Official (2) The input sequence is... For the output sequence, The sampling period is The decay time constant of the nuclear pulse signal; This refers to the peak time of the digital trapezoidal pulse. The sum of peak time and digital trapezoidal pulse peak. This represents the width of the digital trapezoidal pulse; where, , , , , These are the rising edge width and pulse width of the trapezoidal pulse, respectively. ; The trapezoidal signal is continuously fed into the parameter extraction module. The peak value and arrival time of the input pulse are determined by calculating the height of the trapezoid and the arrival time of the trapezoid. Then, the peak value and arrival time of the input pulse are encapsulated together and transmitted to the spectrum generation module. The spectrum generation module is built on a dual-port RAM. The amplitude data of the spectrum generation module is used as the address of the RAM. Whenever a data is input, the data corresponding to the RAM address of the amplitude value is read out, incremented by 1, and then written.

6. A method based on a digital anti-coincidence algorithm according to claim 1 37 Ar detector electronics system, characterized in that In the voltage generation module, the high voltage output voltage is controlled by the DAC auxiliary control unit. The high voltage output uses a resistor divider, and after sampling by an ADC, it is fed back to the data processing and control module. The data processing and control module then adjusts the output of the DAC auxiliary control unit to stabilize the high voltage at the set value. In the voltage generation module, the low voltage DC is used to power the preamplifier.

7. A method based on a digital anti-coincidence algorithm according to claim 6 37 Ar detector electronics system, characterized in that The voltage generation module uses an LDO voltage regulator to generate two sets of fixed low-voltage DC voltages: ±12V and ±24V.

8. A method based on a digital anti-coincidence algorithm according to claim 1 37 Ar detector electronics system, characterized in that The data acquisition module receives signals from four detectors. The four signal input ports are all equivalent. According to the settings, the four signals are distributed in pairs to two anti-coincidence modules.

9. A method based on a digital anti-coincidence algorithm according to claim 1 37 Ar detector electronics system, characterized in that The detector electronics system adopts a desktop single-board integrated design.

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