Method for preparing observation section of coupling region of integrated device of photonic chip and structure

Abstract

The application discloses a preparation method and structure of an observation section of a coupling region of a photonic chip integrated device, and the preparation method comprises the following steps: drawing a cutting layout of a coupling region of a photonic chip integrated device to be observed according to a preset etching window position; preparing a mask for a photonic chip to be observed based on the cutting layout; transferring a mask pattern to the upper surface of a silicon substrate of the photonic chip to be observed through etching; and vertically etching the silicon substrate in the etching window and forming a groove. The application can realize efficient preparation of the observation section of the coupling region of the photonic chip integrated device, the sample is not polluted and deformed during the preparation process, mass production can be realized, and the sample is not damaged.

Description

Technical Field

[0001] This invention relates to the field of photonic chip microstructure technology, and in particular to a method and structure for preparing the observation cross section of the coupling region of a photonic chip integrated device. Background Technology

[0002] In the development of photonic integrated circuits, it is necessary to design various integrated optical devices with coupling structures, such as microring resonators, directional couplers, grating couplers, and mode field converters.

[0003] The coupling gap between the microring resonator and the straight waveguide is a core parameter that determines the device performance, such as coupling efficiency and quality factor Q. This coupling gap may change slightly with high-temperature processes such as cladding deposition and annealing, which may affect the final device fabrication result. Therefore, it needs to be carefully characterized during and after the fabrication process.

[0004] Besides microring resonators, in high-performance silicon photonic chips, the gap of the directional coupler or the tooth profile accuracy of the grating coupler directly determines the bandwidth and loss. These areas are often distributed throughout the chip, which traditional focused ion beams cannot cover.

[0005] Currently, existing technologies for preparing and observing the cross-sectional morphology of this coupling region mainly include: Focused ion beam (FIB) cutting: Extremely low efficiency: It is a point-to-point processing method, which can only prepare one cross section at a time, making it impossible to achieve statistical analysis of multiple sites across the entire chip.

[0006] Ion contamination: Gallium ion (Ga) implantation alters the optical properties of materials, resulting in sample loss after observation.

[0007] High cost: FIB equipment and machine time are expensive, and deep, multi-point cutting takes a very long time.

[0008] Mechanical dicing: Insufficient precision: Mechanical cleavage is difficult to precisely control at the coupling center position at the micrometer or even submicrometer level.

[0009] Highly destructive: It easily causes small-sized samples (small pieces) to break, and the cross-sectional roughness is high, making it difficult to observe the nanoscale waveguide sidewalls.

[0010] Existing methods are not only inefficient in preparation and pose a risk of ion contamination, but the resulting thermal effects may also cause morphological distortions in sensitive coupling structures (such as thin-film lithium niobate and polymer cladding), which is highly destructive to the samples and cannot reflect the true state of the samples.

[0011] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0012] In view of the shortcomings of the prior art, the purpose of this invention is to provide a method and structure for preparing the observation cross section of the coupling region of a photonic chip integrated device, so as to solve the problems of low efficiency, high risk of sample contamination and morphological distortion, and high destructiveness to the sample in the preparation of the observation cross section of the coupling region of the photonic chip.

[0013] The technical solution of the present invention is as follows: In a first aspect, the present invention provides a method for preparing an observation cross section of the coupling region of a photonic chip integrated device, comprising: Draw the cut-out layout of the coupling region of the photonic chip integrated device to be observed according to the preset etching window position; Based on the layout to be cut, a mask is prepared for the photonic chip to be observed; The mask pattern is transferred to the upper surface of the silicon substrate of the photonic chip to be observed by etching. The silicon substrate within the etching window is vertically etched to form a groove.

[0014] In a further embodiment of the present invention, the mask preparation process employs deep ultraviolet exposure, electron beam exposure, or laser direct writing methods for photolithography. The photolithography process includes: using the physical device closest to the coupling region of the photonic chip integrated device to be observed as a local alignment reference source; and having the scanning module in the exposure device perform multi-point line scanning on the local alignment reference source to calculate and correct the translation, angular deflection, and non-orthogonal higher-order geometric distortions generated in the coupling region of the photonic chip integrated device to be observed during loading.

[0015] In a further embodiment of the present invention, when the photonic chip is a non-complete wafer sample, a carrier coplanarization assembly process is performed before mask preparation. Specifically, this includes: fixing the photonic chip on a removable flexible substrate or in a carrier wafer with grooves; and using the carrier wafer, mechanical fine-tuning to keep the upper surface of the integrated photonic chip to be observed and the upper surface of the carrier wafer at the same horizontal height plane.

[0016] A further feature of the present invention is that the mask pattern is transferred to the upper surface of the silicon substrate of the photonic chip to be observed by reactive ion etching or inductively coupled plasma etching.

[0017] A further provision of the present invention, which involves vertically etching the silicon substrate within the etching window to form a groove, specifically includes: The Bosch process is used for cyclic etching, with each cycle including a passivation deposition step, a first etching step, and a second etching step. The passivation deposition step uses octafluorocyclobutane process gas to deposit a polymer protective layer on the inner wall of the etching tank. The duration of the passivation deposition step increases with the increase of etching depth. The first etching process uses sulfur hexafluoride process gas with lower electrode bias to open the polymer protective layer at the bottom of the etching tank. The sulfur hexafluoride process gas pressure in the second etching is greater than that in the first etching, and the etching time in the second etching is greater than that in the first etching.

[0018] Secondly, the present invention provides a cross-sectional structure obtained by the above-mentioned method for preparing the observation cross-section of the coupling region of a photonic chip integrated device, wherein the cross-sectional structure comprises, from bottom to top: a substrate layer, a device layer consisting of a lower cladding layer, a core optical waveguide layer, and an upper cladding layer; The substrate is a monocrystalline silicon substrate; The lower cladding layer is a silicon dioxide thermally oxidized layer stacked on the upper surface of the substrate layer; The core optical waveguide layer contains an integrated device coupling region made of a high-refractive-index material. The upper cladding is a dielectric protective layer covering the core optical waveguide layer; The grooves etched along the vertical direction extend vertically downwards from the uppermost surface of the upper cladding layer, continuously penetrating the entire upper cladding layer, core optical waveguide layer, and lower cladding layer, and extending into the interior of the substrate layer. The interface edge of the core optical waveguide layer is provided with a step, which protrudes outward or is recessed inward relative to the cross-sectional edge of the adjacent layer of the core optical waveguide layer.

[0019] In a further embodiment of the present invention, the groove is generally presented as a rectangular groove or a non-symmetrical stepped structure.

[0020] In a further embodiment of the present invention, the core optical waveguide layer and the upper cladding layer are provided with multiple layers spaced apart.

[0021] In a further embodiment of the present invention, the high refractive index material is silicon nitride, thin-film lithium niobate, or single-crystal silicon, and the upper cladding material is silicon dioxide.

[0022] A further provision of the present invention includes a charge-discharge hard mask layer, which is a thin metal film layer attached to the uppermost surface of the upper cladding layer.

[0023] The present invention provides a method and structure for fabricating observation cross-sections of coupling regions of photonic chip integrated devices, which has the following advantages: The fabrication method of the present invention can pre-set a large number of monitoring window positions on the mask pattern, providing observation conditions for simultaneous observation of the coupling gaps of each device across the entire wafer. This provides crucial process uniformity data support for large-area mass production. Using a single photolithography and etching process, cross-sections of coupling regions of hundreds or thousands of integrated devices can be fabricated simultaneously on the same wafer, achieving high-efficiency mass production. This greatly improves R&D efficiency and supports full-wafer evaluation of process uniformity. Furthermore, the fabrication process is free from sample contamination and deformation risks, is non-destructive to the sample, and the fabrication precision is controlled through precise etching. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0025] Figure 1 This is a flowchart of a method for preparing the observation cross section of the coupling region of a photonic chip integrated device according to one embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of the structure of the observation cross section of the coupling region of a photonic chip integrated device in one embodiment of the present invention.

[0027] Figure 3 This is an example image of the SEM image of the coupling region of a photonic chip integrated device in one embodiment of the present invention.

[0028] Figure 4 This is a top view schematic diagram of the cut layout of the sample to be observed and the relationship of the coupling region in one embodiment of the present invention.

[0029] Figure 5 This is a process flow diagram of the method for fabricating the cross-section of the coupling region of a photonic chip integrated device according to one embodiment of the present invention.

[0030] Figure reference numerals: 1-upper cladding, 2-core optical waveguide layer, 3-lower cladding, 4-substrate layer. Detailed Implementation

[0031] This invention provides a method and structure for preparing the observation cross-section of the coupling region of a photonic chip integrated device. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0032] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0033] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements present. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0034] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0035] Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0036] The preparation method described in this invention is not only applicable to silicon-on-insulator (SOI) or silicon-on-insulator (SiNOI) systems, but also applicable to photonic integrated chip platforms containing active or passive micro-nano coupling structures, such as thin-film lithium niobate (LNOI), gallium arsenide (GaAs), and indium phosphide (InP). Material substitutions for the above platforms are all within the protection scope of this invention.

[0037] Please refer to the instruction manual appendix. Figure 1 This invention provides an embodiment of a method for preparing an observation cross section of the coupling region of a photonic chip integrated device, comprising the following steps: S100. Draw the cut-out pattern of the coupling region of the photonic chip integrated device to be observed according to the preset etching window position.

[0038] Specifically, the pattern to be cut is pre-drawn according to the preset etching window position to prepare for opening the etching window in the coupling area of ​​the photonic chip integrated device to be observed.

[0039] S200. Based on the pattern to be cut, a mask is prepared for the photonic chip to be observed.

[0040] Specifically, a mask is prepared on top of the photonic chip to be observed, based on the pattern to be cut pre-drawn in the previous step.

[0041] S300: The mask pattern is transferred to the upper surface of the silicon substrate of the photonic chip to be observed by etching.

[0042] S400, Vertical etching is performed on the silicon substrate within the etching window to form a groove.

[0043] This invention provides observation conditions for simultaneous observation of coupling gaps between devices across the entire wafer by pre-setting a massive number of monitoring windows on the mask pattern. This provides crucial process uniformity data support for large-area mass production. Using a single photolithography and etching process, cross-sections of coupling regions of hundreds or thousands of integrated devices can be fabricated simultaneously on a single wafer, achieving high-efficiency, high-volume fabrication. This significantly improves R&D efficiency and supports full-wafer evaluation of process uniformity. Furthermore, the fabrication process is free from sample contamination and deformation risks, is non-destructive, and allows for precise etching control of fabrication accuracy.

[0044] In this embodiment of the invention, during mask fabrication, deep ultraviolet (DUV) exposure, electron beam lithography (EBL), or laser direct writing methods are used for photolithography. The photolithography process includes: using the physical device closest to the coupling region of the photonic chip integrated device to be observed as a local alignment reference source; the scanning module (alignment camera or electron beam scanner) in the exposure device performs multi-point line scanning on the local alignment reference source, calculating and correcting the translation, angular deflection, and non-orthogonal higher-order geometric distortions generated during loading of the coupling region of the photonic chip integrated device to be observed. This achieves nanometer-level in-situ alignment: direct alignment of the local waveguide pattern and higher-order algorithm correction completely eliminate physical deviations caused by mechanical placement and irregular chip cutting, ensuring that the alignment accuracy between the target boundary of the etching window and the geometric center line of the micro-ring / straight waveguide coupling area consistently reaches ≤100nm. This ensures that subsequent "process slicing" can be precisely cut on the core coupling region (Gap), solving the pain points of traditional processes such as "not finding the alignment mark" and "inaccurate cutting" on small wafers. Eliminating edge rounding and jagged effects to ensure atomic-level flatness of the cross-section: By refining the overlap of light spots and edge energy trimming, the microscopic jaggedness or corner rounding produced by conventional exposure at the window edges is eliminated. This results in the patterned mask exhibiting a vertical, straight, and steep longitudinal boundary section with a ridge angle ≥88° at the overlap line. This directly determines the cross-sectional quality after subsequent ICP etching and transfer, and is a prerequisite for achieving high-resolution SEM observation.

[0045] When the photonic chip is a non-complete wafer sample, a carrier coplanarization assembly process is performed before mask fabrication. Specifically, the photonic chip is fixed on a removable flexible substrate (such as a blue film) or in a carrier wafer with grooves. When using the carrier wafer, mechanical fine-tuning is used to ensure that the upper surface of the integrated photonic chip to be observed is kept at the same horizontal level as the upper surface of the carrier wafer (coplanarity error ≤ 5 μm). Here, a non-complete wafer sample refers to a photonic chip sample to be observed that is not a complete wafer. The method of this invention avoids ion implantation contamination, and this process scheme does not depend on the cleavage surface of a specific material. It can be widely applied to various material systems such as Si, silicon nitride, and thin-film lithium niobate, and is compatible with samples of different sizes (full wafers or fragments). Traditional direct spin coating of photonic chips will block the photoresist due to hydrodynamic edge effects, resulting in severe "resin buildup" at the chip edge (the edge resist thickness is usually 2 to 5 times that of the central area). This invention utilizes coplanar assembly to simulate the boundary of small wafers as a continuous wafer surface, eliminating the photoresist buildup effect at the edges of the wafers. Since the etching window edge of this invention must be adjacent to and precisely coincide with the device coupling region, eliminating photoresist buildup ensures extremely high uniformity of the photoresist film thickness within the window boundary area (deviation ≤ ±1%). This avoids insufficient exposure or large-angle tilting of the contour caused by uneven photoresist thickness, laying the foundation for subsequent high-precision patterning.

[0046] In this embodiment of the invention, a mask pattern is transferred to the upper surface of the silicon substrate of the photonic chip to be observed by reactive ion etching (RIE) or inductively coupled plasma (ICP) etching.

[0047] Reactive ion etching (RIE) or inductively coupled plasma (ICP) etching processes are employed. By adjusting the type and flow rate ratio of fluorine-containing process gases (such as CHF3, SF6, C4F8, etc.) and dilution / auxiliary gases (such as H2, Ar, O2), free fluorine radicals are consumed, thereby improving the selectivity of the photoresist and achieving high-selectivity anisotropic etching. The etching process must penetrate vertically through the cladding layer (such as SiO2) and the core optical waveguide layer (such as Si3N4) to precisely transfer the mask pattern to the silicon substrate surface.

[0048] Mask adaptation: If a photoresist mask is used, a thick polymer protective layer is generated by using a low-fluorine-to-carbon ratio fluorocarbon process gas (such as CHF3) and a high gas ratio of H2. This ensures that the selectivity of the cladding SiO2 and the core optical waveguide layer Si3N4 to the photoresist is greater than 4, meeting the requirements for deep trench processing. If a metal hard mask is used, a high concentration of fluorine radicals is generated by using a high-fluorine-to-carbon ratio fluorocarbon process gas (such as C4F8) and approximately 20% oxygen. This etchant reacts significantly with SiO2 and Si3N4, but forms inert fluorides with the metal mask, hindering further reactions. This allows the selectivity to be increased by an order of magnitude, resulting in a sharper cross-sectional profile.

[0049] like Figure 5 As shown, vertical etching of the silicon substrate within the etching window to form a groove specifically includes: The Bosch process is used for cyclic etching, with each cycle including a passivation deposition step, a first etching step, and a second etching step. The passivation deposition step uses octafluorocyclobutane process gas to deposit a polymer protective layer on the inner wall of the etching tank. The duration of the passivation deposition step increases with the increase of etching depth. The first etching process uses sulfur hexafluoride process gas with lower electrode bias to open the polymer protective layer at the bottom of the etching tank. The sulfur hexafluoride process gas pressure in the second etching is greater than that in the first etching, and the etching time in the second etching is greater than that in the first etching.

[0050] In this embodiment of the invention, deep silicon etching is performed in 50-100 cycles. The core of this step is to create a sufficient physical clearance space on the side of the waveguide coupling region through multiple etching cycles, thereby eliminating the substrate's obstruction of the electron beam and facilitating direct, high-resolution observation of the waveguide cross-section and its coupling gap by scanning electron microscopy (SEM) at a large tilt angle. The resist on the sample surface can be removed using a plasma resist removal process (if a hard mask is present, it can be removed using various etching solutions; alternatively, the hard mask can be retained to increase conductivity during SEM characterization). Residues (polymers and deposits) from the etched cross-section can be removed using standard cleaning processes such as SCI and DHF. DHF can also be used for highly selective wet etching to strengthen the contour of the Si3N4 core optical waveguide layer, making it easier to identify under SEM. After resist removal and cleaning, the chip can be directly observed using SEM at a tilt stage without physically splitting it. Alternatively, an SEM cross-section observation stage can be used to observe the vertical sidewalls generated by the etching; this method provides more accurate measured data of the coupling region. The method of this invention creatively introduces the deep silicon etching technology originally used in MEMS manufacturing into the preparation and analysis of photonic chip cross-sections. By manufacturing groove sidewalls, physical damage such as edge chipping caused by traditional cutting is avoided.

[0051] Compared to the impact stress and edge chipping caused by mechanical dicing, this embodiment uses plasma dry etching, which is a non-contact process that greatly reduces physical damage to the waveguide edges and ensures that the cross-sectional morphology observed under a scanning electron microscope is closer to the actual physical state of the device during operation.

[0052] In this embodiment, as Figure 2 As shown, the present invention provides a cross-sectional structure obtained by the above-mentioned method for preparing the observation cross-section of the coupling region of the photonic chip integrated device. The cross-sectional structure includes, from bottom to top, a substrate layer 4, a device layer composed of a lower cladding layer 3, a core optical waveguide layer 2, and an upper cladding layer 1. The substrate 4 is a monocrystalline silicon substrate; The lower cladding layer 3 is a silicon dioxide thermally oxidized layer stacked on the upper surface of the substrate layer; The core optical waveguide layer 2 contains an integrated device coupling region made of a high refractive index material; The upper cladding layer 1 is a dielectric protective layer covering the core optical waveguide layer; The grooves etched vertically extend vertically downwards from the uppermost surface of the upper cladding 1, continuously penetrating the entire upper cladding 1, core optical waveguide layer 2, and lower cladding 3, and extending into the interior of the base layer 4. The interface edge of the core optical waveguide layer 2 is provided with a step, which protrudes outward or is recessed inward relative to the cross-sectional edge of the adjacent layer of the core optical waveguide layer.

[0053] The cross-sectional structure of this invention provides observational conditions for the coupling gaps (Gaps) of various devices, offering crucial process uniformity data support for the large-area mass production of photonic chips. During fabrication, the cross-sectional structure of the sample is free from contamination and deformation risks, causing no damage to the sample. The vertically etched grooves extend vertically from the uppermost surface of the upper cladding layer, continuously penetrating the entire upper cladding layer, core optical waveguide layer, and lower cladding layer, and extending into the substrate layer. The vertical sidewalls of the etched grooves can be directly observed using a scanning electron microscope on an inclined stage. The presence of a horizontally oriented, statically protruding or inwardly recessed step structure at the cross-sectional edge of the core optical waveguide layer creates a boundary with abrupt contour changes in three-dimensional space, enhancing the contrast of secondary electron scattering during electron beam bombardment.

[0054] In some embodiments, the vertically etched grooves extend vertically downwards from the uppermost surface of the upper cladding layer, continuously penetrating the entire upper cladding layer, core optical waveguide layer, and lower cladding layer, and extending into the substrate layer to a depth of 50-100 μm. The cross-sectional edge of the core optical waveguide layer has a step that statically protrudes outwards or recesses inwards in the horizontal direction by 5-50 nm relative to the cross-sectional edge of the adjacent layer. The core optical waveguide layer contains an integrated device coupling region made of a high-refractive-index material, wherein the high-refractive-index material is silicon nitride, thin-film lithium niobate, or single-crystal silicon. The upper cladding material of the dielectric protective layer covering the core optical waveguide layer is silicon dioxide.

[0055] In some embodiments, multiple core optical waveguide layers and upper cladding layers are spaced apart. The core optical waveguide layers and upper cladding layers can alternate and cycle to form a multilayer structure. In this cyclic structure, the cladding layer sandwiched between two core optical waveguide layers is called an intermediate cladding layer. For example, from bottom to top, it can be: base layer - lower cladding layer - core optical waveguide layer 1 - intermediate cladding layer 1 - core optical waveguide layer 2 - intermediate cladding layer 2 - core optical waveguide layer 3 - upper cladding layer.

[0056] The coupling region of a photonic chip integrated device can include a first optical waveguide unit (such as a straight waveguide) and a second optical waveguide unit (such as the arc-shaped waveguide boundary of a microring resonator). The first and second optical waveguide units are close to each other in the horizontal plane, forming a nanometer-scale optical coupling gap at their nearest neighbor. The vertical longitudinal section containing the geometric center axis of the optical coupling gap is defined as the geometric center tangent. For example... Figure 4 As shown, the edge of the photoresist mask coincides with the centerline of the coupling region. The vertically etched groove has at least one flat internal observation sidewall that is coplanar with the geometric center sectional plane of the integrated device coupling region.

[0057] The cross-sectional morphology of the first optical waveguide unit, the second optical waveguide unit, and the optical coupling gap between them are exposed without damage on the inner observation sidewall of the vertically etched groove, forming a static microscopic physical test profile. The horizontal opening width of the groove inside the substrate layer is ≥10μm, and the groove as a whole presents a rectangular groove or an asymmetrical stepped structure, which is used to provide a 50°~70° tilted unobstructed channel for the electron beam incident of the external scanning electron microscope (SEM) in space.

[0058] The fabrication process of the cross-sectional structure in this embodiment of the invention includes: drawing a layout of the coupling region of the photonic chip integrated device to be observed according to a preset etching window position; preparing a mask for the photonic chip to be observed based on the layout; transferring the mask pattern to the upper surface of the silicon substrate of the photonic chip to be observed through etching; and vertically etching the silicon substrate within the etching window to form a groove. When drawing the layout, based on the original layout of the photonic chip to be observed, an etching window (rectangular or other shape that can expose the etching surface over a large area) is opened above the integrated device in each coupling region of the photonic chip to be observed. The positional relationship between the etching window and the integrated device is defined as follows: the etching window has at least one straight boundary (called the target alignment edge) for defining the observation section. In the two-dimensional layout design, the longitudinal geometric trajectory of the target alignment edge completely coincides with the geometric center tangent line of the coupling region of the photonic chip integrated device to be observed (e.g., the narrowest tangential gap between a micro-ring and a straight waveguide, the central symmetry plane of the double parallel waveguide of a directional coupler, or the characteristic tooth profile of a grating coupler) in the vertical projection direction. The remaining boundaries of the etched window extend away from the geometric center tangent line to define a rectangular or large-area exposed region. Patterning and Mask Preparation: Mask preparation is performed on the photonic chip to be observed. A hard mask (e.g., metals such as Al or Cr) is deposited in advance using a PVD device, or photoresist is used directly as the mask (the mask selection depends on the specific etching process used). Both the hard mask and the photoresist mask are formed using a spin coater. After spin coating, patterning is performed using DUV (deep ultraviolet exposure), EBL (electron beam exposure), or laser direct writing (determined by the actual photoresist selection and alignment requirements). Small samples can be spin-coated using a blue film (removable flexible substrate) attached to a spin coater compatible with small samples, or spin-coated using a fully automated coating and developing machine via carrier wafer bonding. A multi-step dynamic spin-coating method is used on the spin coater to spin-coat photoresist or hard mask precursor. This includes a dynamic dispensing step and at least two spin-coating stages with different rotation speeds. The mask preparation method for the photonic chip to be observed based on the multi-step dynamic spin coating method includes: first, dropping spin coating liquid into the center of the surface to be spin coated, and then setting at least two spin coating stages with different rotation speeds, the rotation speeds of the different spin coating stages increasing sequentially from first to last.

[0059] It also includes a charge-dissipation hard mask layer, which is a thin metal film layer attached to the uppermost surface of the upper cladding layer, made of aluminum or chromium. The thickness is 5nm~5μm. The hard mask layer features collinear edges: it is statically retained only on the surface of the upper cladding layer outside the groove, and its terminal boundary closest to the groove is flush with and collinear with the uppermost edge of the internal observation sidewall. The charge-dissipation hard mask layer not only acts as an etching baffle but also functions as a conductive layer in scanning electron microscopy, effectively mitigating charge accumulation on strongly insulating substrates such as quartz and SOI (Silicon-On-Insulator) under electron beams. During in-situ electron microscopy characterization, it directly conducts accumulated charge away from the top edge of the cross-section, directly improving imaging quality. SOI is a special silicon-based substrate material whose core structure consists of a thin silicon layer directly stacked with an insulating layer (usually silicon dioxide). It has a three-layer structure: top layer: monocrystalline silicon layer (used to manufacture transistors, extremely thin, from nanometer to micrometer scale); middle layer: buried silicon dioxide layer (as an insulating layer, which is key to SOI); bottom layer: silicon substrate.

[0060] like Figure 3 As shown, the microscopic morphology of the internal observation sidewalls is characterized by sidewall etching marks left by high-selectivity etching that do not affect morphological observation. The lower part has a periodic micro-wave topological structure, namely the scallop sidewall morphology left by Bosch etching, with a period on the nanometer scale. The static angle between this sidewall and the bottom surface of the substrate is 88°~90°.

[0061] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for preparing an observation cross section of the coupling region of a photonic chip integrated device, characterized in that, include: Draw the cut-out layout of the coupling region of the photonic chip integrated device to be observed according to the preset etching window position; Based on the layout to be cut, a mask is prepared for the photonic chip to be observed; The mask pattern is transferred to the upper surface of the silicon substrate of the photonic chip to be observed by etching. The silicon substrate within the etching window is vertically etched to form a groove.

2. The method for preparing the observation cross section of the coupling region of the photonic chip integrated device according to claim 1, characterized in that, During the mask fabrication process, photolithography is performed using deep ultraviolet exposure, electron beam exposure, or laser direct writing methods. The photolithography process includes: The physical device closest to the coupling region of the photonic chip integrated device to be observed is used as a local alignment reference source; The scanning module in the exposure device performs multi-point line scanning on the local alignment reference source, and calculates and corrects the translation, angular deflection and non-orthogonal higher-order geometric distortions generated in the coupling region of the photonic chip integrated device under observation during loading.

3. The method for preparing the observation cross section of the coupling region of the photonic chip integrated device according to claim 1, characterized in that, When the photonic chip is a non-complete wafer sample, a carrier coplanarization assembly process is performed before mask fabrication, specifically including: The photonic chip is fixed on a removable flexible substrate or in a carrier wafer with grooves; When using the carrier wafer, mechanical fine-tuning is used to keep the upper surface of the integrated photonic chip to be observed and the upper surface of the carrier wafer at the same horizontal level.

4. The method for preparing the observation cross section of the coupling region of the photonic chip integrated device according to claim 1, characterized in that, Mask patterns are transferred to the silicon substrate of the photonic chip to be observed using reactive ion etching or inductively coupled plasma etching.

5. The method for preparing the observation cross section of the coupling region of the photonic chip integrated device according to claim 1, characterized in that, The process of vertically etching the silicon substrate within the etching window to form a groove specifically includes: The Bosch process is used for cyclic etching, with each cycle including a passivation deposition step, a first etching step, and a second etching step. The passivation deposition step uses octafluorocyclobutane process gas to deposit a polymer protective layer on the inner wall of the etching tank. The duration of the passivation deposition step increases with the increase of etching depth. The first etching process uses sulfur hexafluoride process gas with lower electrode bias to open the polymer protective layer at the bottom of the etching tank. The sulfur hexafluoride process gas pressure in the second etching is greater than that in the first etching, and the etching time in the second etching is greater than that in the first etching.

6. A cross-sectional structure obtained by the method for preparing the observation cross-section of the coupling region of the photonic chip integrated device according to any one of claims 1-5, characterized in that, The cross-sectional structure, from bottom to top, includes: a substrate layer, a device layer consisting of a lower cladding layer, a core optical waveguide layer, and an upper cladding layer; The substrate is a monocrystalline silicon substrate; The lower cladding layer is a silicon dioxide thermally oxidized layer stacked on the upper surface of the substrate layer; The core optical waveguide layer contains an integrated device coupling region made of a high-refractive-index material. The upper cladding is a dielectric protective layer covering the core optical waveguide layer; The grooves etched along the vertical direction extend vertically downwards from the uppermost surface of the upper cladding layer, continuously penetrating the entire upper cladding layer, core optical waveguide layer, and lower cladding layer, and extending into the interior of the substrate layer. The interface edge of the core optical waveguide layer is provided with a step, which protrudes outward or is recessed inward relative to the cross-sectional edge of the adjacent layer of the core optical waveguide layer.

7. The cross-sectional structure according to claim 6, characterized in that, The groove has a rectangular groove or an asymmetrical stepped structure.

8. The cross-sectional structure according to claim 6, characterized in that, The core optical waveguide layer and the upper cladding layer are spaced apart by multiple layers.

9. The cross-sectional structure according to claim 6, characterized in that, The high refractive index material is silicon nitride, thin-film lithium niobate, or single-crystal silicon, and the upper cladding material is silicon dioxide.

10. The cross-sectional structure according to claim 6, characterized in that, It also includes a charge-discharge hard mask layer, which is a thin metal film layer attached to the uppermost surface of the upper cladding.

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