Packaging structure with embedded multi-functional partitioned shielding and stress relief and its fabrication method

Abstract

This invention discloses a packaging structure with embedded multifunctional partitioned shielding and stress relief, belonging to the field of advanced semiconductor packaging technology. The packaging structure includes a ceramic substrate pin assembly, a heterogeneous wafer assembly, an embedded partitioned shielding wall, an optoelectronic interface assembly, and a plastic protective shell. The partitioned shielding wall is made by integrally filling vertical silicon vias within an interposer with electroplated metal, exhibiting a continuous wavy or sawtooth geometric topology in its horizontal projection, and is electrically connected to the ground plane at its bottom. This structure achieves an electromagnetic shielding effectiveness of no less than 80dB in the 10MHz to 3000MHz frequency band, while utilizing the mechanical flexibility of the continuous topology to disperse thermal stress caused by the mismatch in the thermal expansion coefficients of copper and silicon, and can withstand temperatures ranging from -40℃ to 150℃. A method for manufacturing this packaging structure is also provided. This packaging structure is suitable for the electromagnetic environment and thermal cycling conditions of electric vehicles, exhibiting high integration and good process compatibility.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology applications, specifically to a packaging structure with embedded multi-functional partitioned shielding and stress relief, and its preparation method. Background Technology

[0002] With the rapid development of the electric vehicle industry, in-vehicle electronic systems are gradually evolving towards a centralized electronic and electrical architecture. To meet the demands for high computing power, miniaturization, and integration, the industry commonly adopts 2.5D / 3D advanced packaging technology to integrate high-performance AI logic chips, high-bandwidth memory, and high-voltage driver chips into a single package. Heterogeneous integration and automotive-grade 3D packaging, as key technologies for continuing Moore's Law in the "post-Moore's Law era," are deeply converging. Through 2.5D / 3D advanced packaging, chips with different process nodes and functions are assembled into a super system, achieving optimization of system-level performance, power consumption, and area (PPA).

[0003] However, highly compact heterogeneous chip integration solutions present two major technical challenges for advanced automotive packaging.

[0004] First, there is the issue of electromagnetic interference (EMI) crosstalk. During high-frequency switching, the high-voltage driver chip and inverter within the package radiate a large amount of high-frequency electromagnetic signals. This EMI can penetrate the dielectric layer inside the package, causing signal crosstalk to adjacent AI logic chips, thereby leading to logic operation errors, abnormal data transmission, and other malfunctions, seriously affecting the operational stability of the vehicle's electronic control system.

[0005] Second, there is the issue of thermal stress failure. To address EMI crosstalk, existing technologies typically employ continuous metal shielding walls between heterogeneous wafers. However, the coefficient of thermal expansion of copper, a commonly used material for metal shielding, is approximately 17 × 10⁻⁶. -6 / K, while the coefficient of thermal expansion of silicon substrate is approximately 2.6 × 10⁻⁶. -6 / K, there is a significant difference between the two. The operating temperature range of electric vehicles is typically -40℃ to 150℃. Under these severe thermal cycling conditions, continuous shear stress is generated between the continuous metal shielding wall and the silicon interposer and redistribution layer. As stress accumulates, it can easily lead to interposer interface delamination, microcracks around the through-silicon via (TSV), and even directly cause wafer brittleness, significantly reducing the lifespan and reliability of packaged products.

[0006] Currently, while solutions exist in the industry for suppressing electromagnetic crosstalk by placing metal shielding layers between heterogeneous wafers, achieving efficient partitioned electromagnetic shielding and thermal stress relief simultaneously within a small packaging space remains a critical technological bottleneck in the field of advanced automotive-grade heterogeneous wafer packaging. Existing continuous metal shielding wall designs, while addressing the single electromagnetic shielding issue, actually exacerbate the problem of thermal stress concentration, creating a technical contradiction that is difficult to resolve simultaneously. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention provides a packaging structure with embedded multifunctional partitioned shielding and stress relief, and its fabrication method. This structure abandons the traditional rigid continuous metal shielding wall design and adopts a wavy or sawtooth continuous topology structure. It retains the excellent electromagnetic shielding performance of the metal material and utilizes the mechanical flexibility of the geometric structure to laterally disperse and buffer the concentrated thermal shear stress caused by copper-silicon CTE mismatch, thereby significantly reducing interface stress and fundamentally avoiding failure problems such as interlayer and redistribution layer delamination, TSV cracks, and wafer brittleness.

[0008] The technical solution of the present invention is: a packaging structure with embedded multi-functional partitioned shielding and stress relief, comprising: a ceramic substrate pin assembly, a heterogeneous wafer assembly, an electromagnetic shielding layer, an optical / electrical interface assembly, and a plastic protective shell, wherein the plastic protective shell covers all internal structures except the optical / electrical interface assembly, forming an integrated sealed package; The heterogeneous wafer assembly includes a high-voltage driver wafer, an AI logic wafer, and an interposer layer. The electromagnetic shielding layer is an embedded partitioned shielding wall, vertically embedded inside the interposer and located between the two wafers. It is made by integrally filling multiple vertical silicon vias with an electroplated metal layer. The projection of the partitioned shielding wall on the horizontal plane of the interposer is a continuous wavy or sawtooth geometric topology, and its bottom is electrically connected to the grounding structure in the ceramic substrate pin assembly.

[0009] Furthermore, the electroplated metal layer of the partitioned shielding wall is pure copper or a copper-nickel alloy; When the metal layer is a copper-nickel alloy, the copper mass fraction in the copper-nickel alloy is 80% and the nickel mass fraction is 20%. The electromagnetic shielding effectiveness of the partitioned shielding wall in the frequency band of 10MHz to 3000MHz is ≥80dB, and the total connection resistance between the partitioned shielding wall and the grounding terminal is ≤0.05Ω.

[0010] Furthermore, the partitioned shielding wall has a continuous sawtooth geometric topology, the turning angle of the sawtooth structure is 90°-130°, and there is a gap of 1μm-3μm between adjacent sawtooth segments, the gap is filled with polyimide stress buffer filler.

[0011] Furthermore, the partitioned shielding wall has a continuous wave-shaped geometric topology, with a wave peak to trough amplitude of 50 μm and a bending radius of 120 μm. The bending radius is set in a gradient according to the thermomechanical stress tensor distribution inside the intermediate layer. The closer to the stress concentration area on the outer edge of the intermediate layer, the smaller the bending radius.

[0012] A method for fabricating a packaging structure with embedded multi-functional partitioned shielding and stress relief includes the following steps: Step 1: Preparation of ceramic substrate pin assembly: Alumina ceramic blank is provided, and after being cut, ground, polished and cleaned in sequence, a copper grounding layer is deposited in a designated area of ​​the substrate. The grounding conductor pin and the copper grounding layer are integrally formed by high-temperature sintering, and electrical interconnection lines and pins are prepared. Step 2, Interposer Pretreatment: The wafer-level interposer is cleaned, its dimensions are inspected, and its initial internal stress is pre-inspected to screen qualified interposers; Step 3, TSV deep hole etching: Using deep hole reactive ion etching process, vertical silicon through-hole array is processed along a preset wavy or sawtooth trajectory inside the interposer layer and corresponding to the separation area between the high voltage drive wafer and the AI ​​logic wafer. Step 4: Electroplating and filling of embedded partitioned shielding wall: Electroplating a metal layer is performed to integrally fill the vertical silicon through-holes to form the partitioned shielding wall; When step 3 uses a sawtooth trajectory, polyimide stress buffer filler is filled into the corresponding segment gaps and cured. Step 5, heterogeneous wafer assembly: The high-voltage driver wafer and the AI ​​logic wafer are assembled to a designated area on the upper surface of the interposer layer using a eutectic bonding process to form a heterogeneous wafer assembly; Step 6, Component docking and assembly: The heterogeneous wafer assembly is attached and fixed to the ceramic substrate pin assembly, so that the bottom of the partition shield wall is electrically connected to the copper grounding layer; Step 7, Optoelectronic Interface Integration: Assemble the miniature fiber optic coupling interface and the BGA electrical interconnect interface into the reserved window position of the package, and perform welding and sealant coating and curing; Step 8: Overall molding: Use epoxy molding compound to injection mold all internal structures except the optoelectronic interface assembly to form a molded protective shell; Step 9, Post-processing: After molding, the packaged body is purged with high-pressure nitrogen to remove dust, left to stand at room temperature for 4-6 hours to release stress, laser-marked, and subjected to full appearance inspection. Step 10, Comprehensive Performance Testing: This includes testing core indicators such as electromagnetic shielding, optical signal transmission, thermal stress resistance, insulation, and conductivity.

[0013] Furthermore, in step 1, the thickness of the alumina ceramic substrate is 1.0±0.05mm, and the thickness of the copper grounding layer is 12μm±1μm; In step 3, the depth of the vertical silicon via is 250 μm, the diameter is 25 μm, and the aspect ratio is 10:1.

[0014] Furthermore, in step 3, the amplitude of the wave-like trajectory is 50 μm and the radius of curvature is 120 μm; In step 4, the electroplating temperature is 40℃±2℃, and the current density is 1.2A / dm² to 1.5A / dm².

[0015] Furthermore, in step 3, the turning angle of the sawtooth trajectory is 90° to 130°, and the segment gap is 1μm to 3μm; In step 4, the curing temperature of the polyimide is 80°C to 100°C and the curing time is 30 min to 45 min.

[0016] Furthermore, in step 5, the eutectic welding temperature is 200℃-220℃, the welding pressure is 0.5MPa to 1.0MPa, the center distance between the high-voltage drive chip and the AI ​​logic chip is 1.0mm±0.05mm, and the assembly offset is ≤0.03mm.

[0017] The beneficial technical effects of this invention are: 1. This application abandons the traditional rigid continuous metal shielding wall design and adopts a wave-shaped or sawtooth continuous topology structure, which not only retains the excellent electromagnetic shielding performance of metal materials, but also utilizes the mechanical flexibility of the geometric structure to laterally disperse and buffer the concentrated thermal shear stress caused by copper-silicon CTE mismatch, thereby significantly reducing interface stress and fundamentally avoiding failure problems such as interlayer and redistribution layer delamination, TSV cracks, and wafer brittleness.

[0018] 2. The embedded partitioned shielding wall and grounding structure are seamlessly connected with low resistance, forming a three-dimensional partitioned shielding barrier inside the package. The shielding effectiveness is ≥80dB in the 10MHz-3000MHz high frequency band commonly used in automotive applications. It can block electromagnetic interference generated when the high voltage drive chip is switching on and off, and protect the stable operation of the AI ​​logic chip.

[0019] 3. This structure is based on existing mature wafer-level TSV etching, metal plating, and packaging processes. It does not require additional complex processes or equipment, does not occupy additional external packaging space, has high integration, and controllable production costs, making it suitable for laboratory research and development as well as large-scale industrial production.

[0020] 4. The curvature radius, turning angle, and segment gap of the partitioned shielding wall can be adjusted according to the stress distribution of the interlayer. At the same time, two topologies, wave-shaped and sawtooth-shaped, can be selected as needed to adapt to heterogeneous integrated chip packaging scenarios of different sizes and power.

[0021] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the ceramic substrate pin assembly structure of the present invention; Figure 2 This is a schematic diagram of the structure of the deep hole in the interposer layer TSV of the present invention; Figure 3 This is a schematic diagram of the heterogeneous wafer assembly structure of the present invention; Figure 4 This is a schematic diagram of the assembly of the heterogeneous wafer assembly and the ceramic substrate pin assembly of the present invention; Figure 5 This is a schematic diagram of the overall package structure of the present invention; Figure 6 This is a process flow diagram of the present invention.

[0023] The attached figures are labeled as follows: 10. Ceramic substrate pin assembly; 11. Alumina ceramic substrate; 12. Copper ground plane; 13. Electrical interconnect pins; 131. BGA electrical interconnect interface; 20. Heterogeneous chip assembly; 21. Intermediate layer; 22. Partition shielding wall; 23. High voltage driver chip; 24. AI logic chip; 241. Miniature fiber optic coupling interface; 30. Plastic encapsulation protective housing. Detailed Implementation

[0024] In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0025] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate for the embodiments of this application described herein.

[0026] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship described in the embodiments and shown in the accompanying drawings, or the orientation or positional relationship that the product of this invention is usually placed in during use. They are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention. Example 1

[0027] like Figure 1 As shown, the present invention specifically relates to a packaging structure with embedded multi-functional partitioned shielding and stress relief, including: a ceramic substrate pin assembly 10, a heterogeneous wafer assembly 20, an electromagnetic shielding layer, an optical / electrical interface assembly, and a plastic protective shell 30. The plastic protective shell 30 covers all internal structures except the optical / electrical interface assembly, forming an integrated sealed package.

[0028] The heterogeneous wafer assembly 20 includes a high-voltage driver wafer 23, an AI logic wafer 24, and an interposer layer 21. The electromagnetic shielding layer is an embedded partitioned shielding wall 22, which is vertically embedded inside the intermediary layer 21 and located between the two wafers. It is made by integrally filling multiple vertical silicon vias with an electroplated metal layer. The projection of the partitioned shielding wall 22 on the horizontal plane of the intermediary layer 21 is a continuous wavy or sawtooth geometric topology, and its bottom is electrically connected to the grounding structure in the ceramic substrate pin assembly 10.

[0029] The overall base is an alumina ceramic substrate 11 with a thickness of 1.0 mm and a tolerance of 0.05 mm, and a thermal conductivity ≥200 W / (m·K). A copper grounding layer 12 with a thickness of 12 μm and a tolerance of 1 μm is bonded to the surface of the alumina ceramic substrate 11. The grounding conductor pin and the copper grounding layer 12 are integrally formed by high-temperature sintering, and the total grounding resistance is less than or equal to 0.1 Ω.

[0030] Intermediate layer 21 is fixedly disposed at the center of alumina ceramic substrate 11. High voltage driver chip 23 and AI logic chip 24 are arranged side by side on the upper surface of intermediate layer 21. The center-to-center distance between high voltage driver chip 23 and AI logic chip 24 is 1.0 mm, the tolerance is 0.05 mm, and the assembly offset is ≤0.03 mm.

[0031] Inside the interposer layer 21, and in the separation area between the high-voltage driver chip 23 and the AI ​​logic chip 24, an embedded partition shielding wall 22 is vertically disposed. The forming process of the partition shielding wall 22 is as follows: First, a vertical silicon through-hole array with an aspect ratio of 10:1 is processed in the interposer layer 21 using a deep-hole reactive ion etching process. The depth of the TSV holes is 250μm and the diameter is 25μm.

[0032] The TSV array is arranged along a continuous wavy trajectory; then, the TSV holes are integrally filled with pure copper or a copper-nickel alloy through an electroplating process. When a copper-nickel alloy is used for electroplating, the mass fraction of copper is 80% and the mass fraction of nickel is 20%. The projection of the partitioned shielding wall 22 on the horizontal plane is a continuous wavy topology, with an amplitude of 50 μm from crest to trough and a bending radius of 120 μm. The bottom of the partitioned shielding wall 22 is attached to the copper grounding layer 12 and forms an electrical connection with the grounding conductor pin through an electroplating process, with a total connection resistance ≤0.05Ω.

[0033] Electroplating temperature is controlled at 40±2℃, current density: 1.2-1.5A / dm³ 2 .

[0034] The bending radius of the partitioned shielding wall 22 is set in a gradient based on the simulation results of the thermomechanical stress tensor inside the interposer layer 21. Specifically, in the stress concentration area near the outer edge of the interposer layer 21, the bending radius is reduced accordingly to provide stronger stress release capability; in the central region of the interposer layer 21, the bending radius is appropriately increased to ensure the continuity of electromagnetic shielding.

[0035] The optoelectronic interface components are integrated on one side of the package, including a miniature fiber optic coupling interface 241 and a BGA electrical interconnect interface 131. The outer side of the interface is coated with a high-temperature resistant sealant, which, after curing, forms a protective sealing layer with a dustproof and waterproof rating of IP67.

[0036] The plastic protective housing 30 is made of low-light-loss epoxy molding compound, which completely covers all internal components except for the optoelectronic interface components, with a molding layer thickness of 0.8mm to 1.2mm.

[0037] The performance of the packaging structure in this embodiment was tested, and the results are as follows: Electromagnetic shielding performance test: Under the conditions of 800V bias and 250GHz high-frequency switching, the electromagnetic shielding effectiveness of the partitioned shielding wall 22 in the frequency band from 10MHz to 3000MHz is 85dB; the optical isolation of the AI ​​logic chip 24 is 65dB, the signal transmission efficiency is 99.5%, and no electromagnetic crosstalk was detected.

[0038] Thermal stress reliability testing: The package structure was subjected to thermal cycling tests from -40℃ to 150℃ for a total of 3000 cycles. The corrugated shield wall dispersed stress by utilizing its elastic buckling effect, and the maximum principal stress at the copper-silicon interface was reduced by 68% compared to the continuous metal shield wall. No delamination, microcracks, or brittleness were observed in the interposer layer 21, the TSV structure, or the redistribution layer. Example 2

[0039] This embodiment provides an automotive-grade advanced packaging structure using a continuous sawtooth topology partitioned shielding wall 22. The overall base, chip layout, and package shape are basically the same as in Embodiment 1. The difference lies in the structural form and matching design of the partitioned shielding wall 22.

[0040] The projection of the partitioned shielding wall 22 onto the horizontal plane is a continuous sawtooth topology, with the turning angle of the sawtooth structure ranging from 90° to 130°. A gap of 1μm to 3μm is reserved between adjacent sawtooth segments. The gaps are filled with low-modulus polyimide as a stress-reducing filler. The polyimide curing temperature is 80-100℃, and the curing time is 30-45 minutes.

[0041] The length of a single metal segment of the partitioned shielding wall 22 is no greater than 500 μm. The continuous metal wall is divided into multiple micro-segments to interrupt the linear shear stress accumulated along the wall's length. The connection resistance between the shielding wall and the grounding pin is ≤0.05Ω. Because the width of the segment gaps is 1 μm to 3 μm, much smaller than the wavelength of electromagnetic waves in the 10MHz to 3000MHz frequency band, electromagnetic signals cannot leak from the gaps. Therefore, the electromagnetic shielding effectiveness of this shielding wall in the target frequency band is 82 dB.

[0042] Performance tests were conducted on the packaging structure of this embodiment, and the results are as follows: The continuous serrated structure combined with polyimide buffer filler can reduce the local stress concentration at the copper-silicon interface caused by thermal expansion coefficient mismatch by 80%. After undergoing extreme salt spray, high humidity, and extensive thermal cycling tests, all bonding interfaces remained tightly bonded without delamination, demonstrating good structural stability. The structure of this embodiment is suitable for miniaturized, ultra-wideband automotive integrated device packaging.

[0043] According to the trajectory form definition in Examples 1 and 2: Waves and sawtooth patterns are single, complete, closed, continuous lines: starting from the outer edge of the chip, they continuously and uninterruptedly circle around the perimeter and return to the starting point, without any breaks or gaps.

[0044] Wave continuity: a smooth, continuous undulating curve with a closed loop connecting the beginning and end; Continuous sawtooth: A straight line with continuous sawtooth at angles, where each tooth is connected without breaks, forming a closed loop.

[0045] Why can't it be a discontinuous segmented trajectory? The shielding wall of this structure, i.e., the subsequent vertical protective through-hole layout path, needs to form a complete Faraday cage with the intermediate composite shielding layer; If the trajectory is segmented and there is a break, an electromagnetic shielding blind zone will be formed at that location. EMP and high-frequency EMI will diffract and invade the chip from the gap, making it impossible to achieve full-area shielding effectiveness. Example 3

[0046] A method for fabricating a packaging structure with embedded multi-functional partitioned shielding and stress relief includes the following steps: Step 1: Preparation of ceramic substrate pin assembly: Alumina ceramic blank is provided, and after being cut, ground, polished and cleaned in sequence, a copper grounding layer 12 is deposited in a designated area of ​​the substrate. The grounding conductor pin and the copper grounding layer 12 are integrally formed by high-temperature sintering, and electrical interconnection lines and pins are prepared. An alumina ceramic blank is provided, which is then sequentially cut, ground, polished, and cleaned. The cut dimensions are 6.0mm × 4.0mm, with rounded corners of R0.3mm. The thickness of the alumina ceramic substrate 11 is 1.0±0.05mm. A high-purity copper layer, with a purity greater than or equal to 99.99%, is deposited in a designated area of ​​the substrate using magnetron sputtering. The thickness of the copper grounding layer 12 is 12μm±1μm. The grounding conductor pins are integrally formed with the copper grounding layer 12 through a high-temperature sintering process. The thickness of the grounding conductor pins is 20-30μm, the width is 0.5-1mm, the length is 2-3mm, and the perpendicularity is ≤0.05mm.

[0047] The Ti layer is 50-100 nm thick, and the Cu layer is 1-2 μm thick. Electrical interconnects and pins are formed using photolithography and etching processes. The electrical interconnect pins are 0.2-0.5 mm wide, 1-2 mm long, and have an adhesion of ≥5 N / mm². 2 Each piece was tested for surface resistance ≤0.05Ω, and the total grounding resistance ≤0.1Ω.

[0048] Step 2, Intermediate layer pretreatment: The wafer-level intermediate layer 21 is cleaned, its dimensions are inspected, and its initial internal stress is pre-inspected to screen qualified intermediate layers 21; The wafer-level interposer 21 undergoes incoming material verification, full visual inspection, and dimensional and thickness checks. The flatness tolerance of interposer 21 is less than or equal to 0.03 mm. The cleaning water temperature is 35℃±2℃, and the cleaning time is 5-8 minutes, followed by constant-temperature nitrogen drying. The initial internal stress of interposer 21 is tested, and unqualified products with excessive stress are screened out.

[0049] Step 3, TSV deep hole etching: Using deep hole reactive ion etching process, vertical silicon through-hole array is processed along a preset wave-shaped or sawtooth trajectory inside the interposer layer 21 and corresponding to the separation area between the high voltage drive wafer 23 and the AI ​​logic wafer 24. A vertical silicon through-hole array is fabricated along a preset wavy or sawtooth trajectory inside the interposer layer 21 and in the separation area between the high-voltage drive wafer 23 and the AI ​​logic wafer 24 using a deep-hole reactive ion etching (DRIE) process.

[0050] The machining parameters for the TSV holes are: hole depth 250μm, hole diameter 25μm, depth-to-width ratio 10:1, etching temperature 20℃±2℃, and vacuum degree ≤5×10 -3 Pa.

[0051] When a wavy trajectory is used, the amplitude is 50 μm and the radius of curvature is 120 μm.

[0052] When using a zigzag trajectory, the turning angle is 90°-130° and the segment gap is 1μm to 3μm.

[0053] Step 4: Electroplating and filling of embedded partitioned shielding wall: Electroplating a metal layer is performed to integrally fill the vertical silicon through-holes to form the partitioned shielding wall 22; After activating the TSV channels, an electroplating process was used to integrally fill them with pure copper or a copper-nickel alloy (80% copper and 20% nickel by mass). The electroplating temperature was 40℃±2℃, and the current density was 1.2-1.5A / dm². After filling, the thickness, uniformity, and conductivity of the metal layer were tested.

[0054] When step 3 uses a sawtooth trajectory, low-modulus polyimide stress buffer filler should be filled in the gaps between the sawtooth segments. The curing temperature is 80℃-100℃ and the curing time is 30-45min.

[0055] Step 5, heterogeneous wafer assembly: The high voltage drive wafer 23 and the AI ​​logic wafer 24 are assembled to a designated area on the upper surface of the interposer layer 21 by eutectic bonding process to form a heterogeneous wafer assembly 20. The assembly positions of the high-voltage driver chip 23 and the AI ​​logic chip 24 are marked on the upper surface of the interposer layer 21, with a center-to-center distance of 1.0 mm ± 0.05 mm between the two chips. An automated die bonder sequentially picks up the two chips and assembles them into the designated area using a eutectic bonding process. The bonding temperature is 200-220℃, the bonding pressure is 0.5-1.0 MPa, the holding time is 60-90 s, and the assembly offset is ≤0.03 mm.

[0056] Step 6, Component docking and assembly: The heterogeneous wafer assembly 20 is attached and fixed to the ceramic substrate pin assembly 10, so that the bottom of the partition shielding wall 22 is electrically connected to the copper grounding layer 12; Clean the upper surface of the ceramic substrate and the bottom surface of the intermediate layer 21 respectively. Align the intermediate layer 21 assembly with the ceramic substrate reference line using a visual positioning system. Perform pressure bonding under a bonding pressure of 0.3-0.5MPa to form an electrical connection between the bottom of the partition shielding wall 22 and the copper grounding layer 12. After bonding, test the grounding continuity, line continuity, and insulation performance; the connection resistance should be ≤0.05Ω.

[0057] Step 7, Optoelectronic Interface Integration: Assemble the miniature fiber optic coupling interface 241 and the BGA electrical interconnect interface 131 into the reserved window position of the package, and perform welding and sealant coating and curing. A miniature fiber optic coupling interface 241 and a BGA electrical interconnect interface 131 are assembled in the reserved window position of the package. The BGA electrical interconnect interface 131 is soldered to the electrical interconnect pin 13. The BGA electrical interface is reflow soldered at a temperature of 230℃±5℃ for 8-12 seconds. The miniature fiber optic coupling interface 241 is precisely aligned with the photonic optical path. High-temperature resistant sealant is uniformly coated on the outside of the interface and then sent to a curing oven to complete the sealant curing.

[0058] Step 8: Overall molding: Use epoxy molding compound to injection mold all internal structures except the optoelectronic interface component to form a molded protective shell 30; A low-light-loss epoxy molding compound is used for overall injection molding encapsulation. The injection pressure is 6-8 MPa, the holding time is 90-120 seconds, the mold temperature is 170℃±5℃, and the molding compound temperature is 90℃±3℃. The molding layer thickness is 0.8-1.2 mm, the light loss of the molding compound is ≤0.1 dB / cm, and the insulation resistance is ≥10 Ω·cm. 14 Ω·cm. After curing, remove any flash, leaving the optoelectronic interface components exposed.

[0059] After curing, the plastic layer is tightly bonded to the ceramic substrate, intermediate layer 21, etc., without delamination or peeling.

[0060] Step 9, Post-processing: After molding, the packaged body is purged with high-pressure nitrogen to remove dust, left to stand at room temperature for 4-6 hours to release stress, laser-marked, and subjected to full appearance inspection. Step 10, Comprehensive Performance Testing: This includes testing core indicators such as electromagnetic shielding, optical signal transmission, thermal stress resistance, insulation, and conductivity.

[0061] The above embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and are not intended to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the scope of the technology disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention.

Claims

1. A packaging structure with embedded multi-functional partitioned shielding and stress relief, characterized in that, include: The package includes a ceramic substrate pin assembly, a heterogeneous wafer assembly, an electromagnetic shielding layer, an optical / electrical interface assembly, and a plastic protective shell, wherein the plastic protective shell covers all internal structures except the optical / electrical interface assembly, forming an integrated sealed package. The heterogeneous wafer assembly includes a high-voltage driver wafer, an AI logic wafer, and an interposer layer. The electromagnetic shielding layer is an embedded partitioned shielding wall, vertically embedded inside the interposer and located between the two wafers. It is made by integrally filling multiple vertical silicon vias with an electroplated metal layer. The projection of the partitioned shielding wall on the horizontal plane of the interposer is a continuous wavy or sawtooth geometric topology, and its bottom is electrically connected to the grounding structure in the ceramic substrate pin assembly.

2. The packaging structure with embedded multi-functional partitioned shielding and stress relief as described in claim 1, characterized in that, The electroplated metal layer of the partitioned shielding wall is pure copper or a copper-nickel alloy. When the metal layer is a copper-nickel alloy, the copper mass fraction in the copper-nickel alloy is 80% and the nickel mass fraction is 20%. The electromagnetic shielding effectiveness of the partitioned shielding wall in the frequency band of 10MHz to 3000MHz is ≥80dB, and the total connection resistance between the partitioned shielding wall and the grounding terminal is ≤0.05Ω.

3. The packaging structure with embedded multi-functional partitioned shielding and stress relief as described in claim 1, characterized in that, The partitioned shielding wall has a continuous sawtooth geometric topology, with a turning angle of 90°-130° and a gap of 1μm-3μm between adjacent sawtooth segments. The gap is filled with polyimide stress buffer filler.

4. The packaging structure with embedded multi-functional partitioned shielding and stress relief as described in claim 1, characterized in that, The partitioned shielding wall has a continuous wave-shaped geometric topology, with a wave peak to trough amplitude of 50 μm and a bending radius of 120 μm. The bending radius is set in a gradient according to the thermomechanical stress tensor distribution inside the intermediate layer. The closer to the stress concentration area on the outer edge of the intermediate layer, the smaller the bending radius.

5. A method for preparing a packaging structure as described in any one of claims 1 to 4, characterized in that, Includes the following steps: Step 1: Preparation of ceramic substrate pin assembly: Alumina ceramic blank is provided, and after being cut, ground, polished and cleaned in sequence, a copper grounding layer is deposited in a designated area of ​​the substrate. The grounding conductor pin and the copper grounding layer are integrally formed by high-temperature sintering, and electrical interconnection lines and pins are prepared. Step 2, Interposer Pretreatment: The wafer-level interposer is cleaned, its dimensions are inspected, and its initial internal stress is pre-inspected to screen qualified interposers; Step 3, TSV deep hole etching: Using deep hole reactive ion etching process, vertical silicon through-hole array is processed along a preset wavy or sawtooth trajectory inside the interposer layer and corresponding to the separation area between the high voltage drive wafer and the AI ​​logic wafer. Step 4: Electroplating and filling of embedded partitioned shielding wall: Electroplating a metal layer is performed to integrally fill the vertical silicon through-holes to form the partitioned shielding wall; When step 3 uses a sawtooth trajectory, polyimide stress buffer filler is filled into the corresponding segment gaps and cured. Step 5, heterogeneous wafer assembly: The high-voltage driver wafer and the AI ​​logic wafer are assembled to a designated area on the upper surface of the interposer layer using a eutectic bonding process to form a heterogeneous wafer assembly; Step 6, Component docking and assembly: The heterogeneous wafer assembly is attached and fixed to the ceramic substrate pin assembly, so that the bottom of the partition shield wall is electrically connected to the copper grounding layer; Step 7, Optoelectronic Interface Integration: Assemble the miniature fiber optic coupling interface and the BGA electrical interconnect interface into the reserved window position of the package, and perform welding and sealant coating and curing; Step 8: Overall molding: Use epoxy molding compound to injection mold all internal structures except the optoelectronic interface assembly to form a molded protective shell; Step 9, Post-processing: After molding, the packaged body is purged with high-pressure nitrogen to remove dust, left to stand at room temperature for 4-6 hours to release stress, laser-marked, and subjected to full appearance inspection. Step 10, Comprehensive Performance Testing: This includes testing core indicators such as electromagnetic shielding, optical signal transmission, thermal stress resistance, insulation, and conductivity.

6. The method according to claim 5, characterized in that, In step 1, the thickness of the alumina ceramic substrate is 1.0 ± 0.05 mm, and the thickness of the copper grounding layer is 12 μm ± 1 μm. In step 3, the depth of the vertical silicon via is 250 μm, the diameter is 25 μm, and the aspect ratio is 10:

1.

7. The method according to claim 5, characterized in that, In step 3, the amplitude of the wave-like trajectory is 50 μm and the radius of curvature is 120 μm; In step 4, the electroplating temperature is 40℃±2℃, and the current density is 1.2A / dm² to 1.5A / dm².

8. The method according to claim 5, characterized in that, In step 3, the turning angle of the sawtooth trajectory is 90° to 130°, and the segment gap is 1μm to 3μm; In step 4, the curing temperature of the polyimide is 80°C to 100°C and the curing time is 30 min to 45 min.

9. The method according to claim 5, characterized in that, The eutectic welding temperature in step 5 is 200℃-220℃, the welding pressure is 0.5MPa to 1.0MPa, the center distance between the high-voltage drive chip and the AI ​​logic chip is 1.0mm±0.05mm, and the assembly offset is ≤0.03mm.

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