Display panel and display device

Abstract

This application relates to a display panel and a display device. The display panel includes: a plurality of pixel circuits, each pixel circuit including: a first thin-film transistor (TFT) and a second thin-film transistor (TFT), both the first terminals of the first TFT and the second TFT being connected to a data line, and both the second terminals of the first TFT and the second TFT being connected to a pixel electrode; the gate of the first TFT being connected to a scan line corresponding to the pixel circuit; and a control circuit configured to: during the display phase, when the temperature of the display panel is lower than a first preset temperature, increase the voltage of the gate of the second TFT to turn on the second TFT; and when the temperature is not lower than the first preset temperature, reset the voltage of the gate of the second TFT to turn off the second TFT and reduce the leakage current of the second TFT to a preset leakage current. This solves the problems of insufficient charging and leakage current in pixels in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] In an LCD display panel, pixels are controlled by thin film transistors (TFT) to charge pixel electrodes. In practical applications, the display panel needs to adapt to a wide working temperature range. The mobility of carriers in the semiconductor active layer of the thin film transistor is highly sensitive to temperature changes, resulting in significant drift of the switching characteristics with temperature. When the display panel is in a low-temperature environment, the mobility of carriers in the semiconductor active layer of the thin film transistor decreases, causing the opening ability of the thin film transistor to decrease, the pixel charging rate to be insufficient, and further causing display defects such as color cast and rough picture. When the display panel is in a high-temperature environment, the mobility of carriers in the semiconductor active layer of the thin film transistor increases, resulting in a large leakage current after the thin film transistor is turned off, and the charge on the pixel electrode leaks through the thin film transistor to the data line, further causing display abnormalities such as vertical crosstalk.

[0003] In summary, the display panel in the prior art is prone to pixel charging deficiency and pixel leakage problems in a wide working temperature range. SUMMARY

[0004] The present application provides a display panel and a display device to solve the problems of pixel charging deficiency and leakage in the prior art.

[0005] In a first aspect, the present application provides a display panel, comprising: a plurality of pixel circuits, each pixel circuit comprising: a first thin film transistor and a second thin film transistor, a first end of the first thin film transistor and a first end of the second thin film transistor are connected to a data line, a second end of the first thin film transistor and a second end of the second thin film transistor are connected to a pixel electrode, and a gate of the first thin film transistor is connected to a scan line corresponding to the pixel circuit; and a control circuit configured to: in a display stage, when a temperature of the display panel is less than a first preset temperature, raise a voltage of a gate of the second thin film transistor to turn on the second thin film transistor, and when the temperature is not less than the first preset temperature, reset the voltage of the gate of the second thin film transistor to turn off the second thin film transistor and make a leakage current of the second thin film transistor less than a preset leakage current.

[0006] Optionally, the display panel comprises: a plurality of control lines, one of the plurality of control lines corresponding to one row of pixel circuits in the plurality of pixel circuits, the control line being connected with the gate of the second thin film transistor of the corresponding pixel circuit; and the control circuit comprises: a temperature control voltage dividing module, the temperature control voltage dividing module comprising: a first resistive unit and a third thin film transistor, a first end of the first resistive unit being connected with a first high voltage end configured to be connected with a first preset high voltage, a second end of the first resistive unit being connected with a first end of the third thin film transistor, and a connection node being a first control node, a second end of the third thin film transistor being connected with a first low voltage end configured to be connected with a first preset low voltage, and a gate of the third thin film transistor being connected with a voltage input end configured to be connected with a second preset high voltage, a resistance value of a conduction resistance of the third thin film transistor being negatively correlated with the temperature of the display panel, so that the third thin film transistor lifts the voltage of the first control node when the temperature of the display panel is less than the first preset temperature, and the third thin film transistor resets the voltage of the first control node when the temperature of the display panel is not less than the first preset temperature; a plurality of potential selection modules, one of the plurality of potential selection modules corresponding to one of the plurality of control lines, the potential selection module comprising: a first switch unit and a second switch unit, a first end of the first switch unit being connected with a controlled end of the first switch unit and the first control node, a second end of the first switch unit being connected with a first end of the second switch unit, a controlled end of the second switch unit being connected with the scan line, and a second end of the second switch unit being connected with the corresponding control line; the first switch unit being configured to lift the voltage of the first end of the second switch unit when the voltage of the first control node is lifted; and the second switch unit being configured to lift the voltage of the corresponding control line when the scan line outputs the scan signal and the voltage of the first end of the second switch unit is lifted.

[0007] Optionally, the resistance value of the first resistive unit is equal to the resistance value of the conduction resistance of the third thin film transistor at a second preset temperature, the second preset temperature being greater than the first preset temperature.

[0008] Optionally, the potential selection module comprises: a third switch unit, a first end of the third switch unit being connected with a second low voltage end connected with a second preset low voltage, a second end of the third switch unit being connected with the corresponding control line, and a controlled end of the third switch unit being connected with a next row of scan lines of the scan line; the third switch unit being configured to reset the voltage of the corresponding control line when the next row of scan lines of the scan line outputs the scan signal.

[0009] Optionally, the control circuit comprises an inverter, an input terminal of the inverter is connected with the first control node, the potential selection module comprises a fourth switch unit, a first terminal of the fourth switch unit is connected with the first control node, a second terminal of the fourth switch unit is connected with the corresponding control line, a controlled terminal of the fourth switch unit is connected with an output terminal of the inverter, and the connection node is a second control node; the inverter is configured to lift the voltage of the second control node when the voltage of the first control node is reset; the fourth switch unit is configured to reset the voltage of the corresponding control line when the voltage of the second control node is lifted.

[0010] Optionally, the inverter comprises a second resistive unit and a fourth thin film transistor, an input terminal of the inverter is a controlled terminal of the fourth thin film transistor, an output terminal of the inverter is a first terminal of the fourth thin film transistor, a first terminal of the second resistive unit is connected with a second high voltage terminal, the second high voltage terminal is configured to be connected with a third preset high voltage, a second terminal of the second resistive unit is connected with the first terminal of the fourth thin film transistor, a second terminal of the fourth thin film transistor is connected with a third low voltage terminal, the third low voltage terminal is configured to be connected with a third preset low voltage.

[0011] Optionally, a material of the semiconductor active layer of the third thin film transistor is amorphous silicon.

[0012] Optionally, the display panel has a display area and a non-display area, the plurality of pixel circuits are arranged in the display area, and the control circuit is arranged in the non-display area.

[0013] Optionally, the voltage input terminal, the first low voltage terminal, the third low voltage terminal, the first high voltage terminal and the second high voltage terminal are connected with a source driving circuit of the display panel, and the second low voltage terminal is connected with a scanning driving unit corresponding to the corresponding pixel circuit in a gate driving circuit of the display panel.

[0014] In a second aspect, the present application provides a display device, comprising any one of the display panels.

[0015] In the display stage, when the temperature of the display panel is less than the first preset temperature, i.e. when the display panel is in a low-temperature environment, the voltage of the gate of the second thin film transistor is raised to turn on the second thin film transistor. At this time, the first thin film transistor and the second thin film transistor work in parallel, the effective channel width-length ratio of the pixel circuit charging is the sum of the channel width-length ratio of the first thin film transistor and the channel width-length ratio of the second thin film transistor, the effective channel width-length ratio is significantly increased, the charging current of the pixel circuit is significantly increased, and thus the charging rate of the pixel circuit when the display panel is in a low temperature is improved. When the temperature is not less than the first preset temperature, i.e. when the display panel is in a high-temperature environment, the voltage of the gate of the second thin film transistor is reset to turn off the second thin film transistor and make the drain current of the second thin film transistor less than a preset drain current, thereby effectively inhibiting the drain of the pixel electrode to the data line when the display panel is in a high temperature, and thus solving the problems of insufficient charging and drain of the pixel in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present application and, together with the description, further serve to explain the principles of the application.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0018] One or more embodiments are exemplarily illustrated by the pictures in the drawings corresponding thereto, and these exemplary illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, unless otherwise specified. The drawings in the drawings do not constitute a proportional limitation.

[0019] Figure 1 A structural schematic diagram of a pixel circuit in the prior art; Figure 2 A structural schematic diagram of a first display panel provided in the embodiments of the present application; Figure 3 A structural schematic diagram of a control circuit provided in the embodiments of the present application; Figure 4 A structural schematic diagram of a second display panel provided in the embodiments of the present application; The following is an explanation of the reference numerals in the drawings of the specification: 1, display area; 10, pixel circuit; 2, non-display area; 20, control circuit; 200, temperature control voltage dividing module; 2000, first resistive unit; 201, potential selection module; 2010, first switch unit; 2011, second switch unit; 2012, third switch unit; 2013, fourth switch unit; 202, inverter; 2020, second resistive unit; 30, fan-out area; 31, frame area; 21, source driving circuit. DETAILED DESCRIPTION

[0020] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0021] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplicity, the elements and settings of particular examples in the following description are shown in great detail. Of course, they are merely examples and are presented to illustrate the application. There is no intent to limit the application to these examples. In addition, the application can be implemented in different examples with variations as to the elements and settings. Such variations are meant to be within the scope of the application.

[0022] Figure 1 A structural schematic diagram of a pixel circuit in the prior art is shown in FIG. 1. Figure 1 As shown in FIG. 1, the pixel circuit 10 includes a first thin film transistor T1, a pixel electrode P and a common electrode COM, the source of the first thin film transistor T1 is connected with a data line (the Mth column data line is represented by SourceM, M is a positive integer), the gate of the first thin film transistor T1 is connected with a scan line (the Nth row scan line is represented by GateN, N is a positive integer), the drain of the first thin film transistor T1 is connected with the pixel electrode P, the pixel electrode P and the common electrode COM are oppositely arranged in the thickness direction of the display panel to form a liquid crystal capacitor C1, for driving liquid crystal molecules to deflect according to a data voltage to display a picture, the pixel electrode P and the common electrode COM are oppositely arranged in the thickness direction to form a storage capacitor C2, for maintaining the data voltage, during normal operation of the display panel, the scan line outputs a scan signal to make the first thin film transistor T1 open, and the data line writes the data voltage into the pixel electrode P through the first thin film transistor T1.

[0023] In practical applications, the display panel needs to adapt to a wide working temperature range, and the mobility of the carriers in the semiconductor active layer of the first thin film transistor T1 is highly sensitive to temperature changes, resulting in a significant drift of the switching characteristics with temperature. When the display panel is in a low-temperature environment, the mobility of the carriers in the semiconductor active layer of the first thin film transistor T1 decreases, causing the turn-on capability of the first thin film transistor T1 to decrease, the pixel charging rate to be insufficient, and further causing display defects such as color cast and rough picture. When the display panel is in a high-temperature environment, the mobility of the carriers in the semiconductor active layer of the first thin film transistor T1 increases, resulting in a large leakage current of the first thin film transistor T1 after being turned off, the charge on the pixel electrode P being leaked to the data line through the first thin film transistor T1, and further causing display abnormalities such as vertical crosstalk.

[0024] In the case where the data voltage provided by the data line is fixed, if the pixel charging capability in a low-temperature environment is to be improved, a conventional method is to increase the channel width-length ratio (W / L, W is the channel width and L is the channel length) of the first thin film transistor T1. However, directly increasing the channel width-length ratio of the first thin film transistor T1 will increase the load of the scan line, causing the output capability of the scan unit providing the scan signal for the scan line in a low-temperature environment to be insufficient, easily leading to the failure of the step-by-step transmission of the scan signal, and further causing display defects such as color cast and rough picture. At the same time, if the channel width-length ratio of the first thin film transistor T1 is too large, the leakage current of the first thin film transistor T1 after being turned off is large in a high-temperature environment, the pixel leakage is serious, and further causing display abnormalities such as vertical crosstalk.

[0025] To solve the problems of insufficient charging and leakage of the pixel in the prior art, the present application provides a display panel and a display device, which can solve the problems of insufficient charging and leakage of the pixel in the prior art.

[0026] Figure 2 A display panel provided by an embodiment of the present application, as shown in Figure 2 The display panel comprises: a plurality of pixel circuits 10, each of the pixel circuits 10 comprising: a first thin film transistor T1 and a second thin film transistor T2, the first end of the first thin film transistor T1 and the first end of the second thin film transistor T2 being connected to a data line, the second end of the first thin film transistor T1 and the second end of the second thin film transistor T2 being connected to a pixel electrode P, and the gate of the first thin film transistor T1 being connected to a scan line corresponding to the pixel circuit; Specifically, as shown in Figure 2As shown in the figure, the first end of the first thin film transistor T1 is the source of the first thin film transistor T1, the first end of the second thin film transistor T2 is the source of the second thin film transistor T2, the second end of the first thin film transistor T1 is the drain of the first thin film transistor T1, the second end of the second thin film transistor T2 is the drain of the second thin film transistor T2, and the first thin film transistor T1 and the second thin film transistor T2 are both N-type thin film transistors (N-TFT, N-channel Thin Film Transistor).

[0027] The control circuit 20 is configured to: In the display stage, when the temperature of the display panel is less than a first preset temperature, the voltage of the gate of the second thin film transistor T2 is raised to turn on the second thin film transistor T2, and when the temperature is not less than the first preset temperature, the voltage of the gate of the second thin film transistor T2 is reset to turn off the second thin film transistor T2 and make the drain current of the second thin film transistor T2 less than a preset drain current.

[0028] Specifically, as shown in the figure, Figure 2 The plurality of pixel circuits 10 are arranged in rows and columns.

[0029] Specifically, as shown in the figure, Figure 2 Gate1, Gate2...GateN, GateN+1 represent the first row of scan lines, the second row of scan lines...the Nth row of scan lines and the N+1th row of scan lines in turn, N is a positive integer, Source1, Source2...SourceM represent the first column of data lines, the second column of data lines...the Mth column of data lines in turn, M is a positive integer, wherein a row of scan lines is connected with a corresponding row of pixel circuits, and a column of data lines is connected with a corresponding column of pixel circuits.

[0030] Specifically, as shown in the figure, Figure 2 The semiconductor active layers of the first thin film transistor T1 and the second thin film transistor T2 are both made of a-Si (amorphous silicon).

[0031] In the above embodiment, in the display stage, when the temperature of the display panel is less than the first preset temperature, i.e. when the display panel is in a low-temperature environment, the voltage of the gate of the second thin film transistor is raised to turn on the second thin film transistor, at this time, the first thin film transistor and the second thin film transistor work in parallel, the effective channel width-length ratio of the pixel circuit charging is the sum of the channel width-length ratio of the first thin film transistor and the channel width-length ratio of the second thin film transistor, the effective channel width-length ratio is significantly increased, the charging current of the pixel circuit is significantly increased, and thus the charging rate of the pixel circuit when the display panel is in a low temperature is improved, when the temperature is not less than the first preset temperature, i.e. when the display panel is in a high-temperature environment, the voltage of the gate of the second thin film transistor is reset to turn off the second thin film transistor and make the drain current of the second thin film transistor less than the preset drain current, thereby effectively inhibiting the drain of the pixel electrode to the data line when the display panel is in a high temperature, thereby solving the problems of insufficient charging and drain of the pixel in the prior art.

[0032] In an alternative embodiment, the display panel described above comprises: a plurality of control lines, one of the plurality of control lines corresponds to one row of pixel circuits in the plurality of pixel circuits, the control line is connected to the gate of the second thin film transistor T2 of the corresponding pixel circuit, as shown in Figure 2 and Figure 3 The control circuit 20 comprises: a temperature control voltage dividing module 200, the temperature control voltage dividing module 200 comprises: a first resistive unit 2000 and a third thin film transistor T3, the first end of the first resistive unit 2000 is connected to a first high voltage end VDD1, the first high voltage end VDD1 is configured to access a first preset high voltage, the second end of the first resistive unit 2000 is connected to the first end of the third thin film transistor T3, and the connection node is a first control node Q1, the second end of the third thin film transistor T3 is connected to a first low voltage end VSS1, the first low voltage end VSS1 is configured to access a first preset low voltage, the gate of the third thin film transistor T3 is connected to a voltage input end Vin, the voltage input end Vin is configured to access a second preset high voltage, the resistance value of the on-resistance of the third thin film transistor T3 is negatively correlated with the temperature of the display panel, so that the third thin film transistor T3 raises the voltage of the first control node Q1 when the temperature of the display panel is less than the first preset temperature, and the third thin film transistor T3 resets the voltage of the first control node Q1 when the temperature of the display panel is not less than the first preset temperature; A plurality of potential selection modules 201, one of the plurality of potential selection modules 201 corresponds to one of the plurality of rows of control lines, the potential selection module 201 includes: a first switch unit 2010 and a second switch unit 2011, a first end of the first switch unit 2010 is connected to a controlled end of the first switch unit 2010 and the first control node Q1, a second end of the first switch unit 2010 is connected to a first end of the second switch unit 2011, a controlled end of the second switch unit 2011 is connected to the scan line, and a second end of the second switch unit 2011 is connected to the corresponding control line; The first switch unit 2010 is configured to raise the voltage of the first end of the second switch unit 2011 when the voltage of the first control node Q1 is raised. The second switch unit 2011 is configured to raise the voltage of the corresponding control line when the scan line outputs the scan signal and the voltage of the first end of the second switch unit 2011 is raised.

[0033] Specifically, as shown in Figure 2 and Figure 3 K1, K2...KN, and KN+1 represent the first row of control lines, the second row of control lines...the Nth row of control lines, and the N+1th row of control lines, respectively.

[0034] Specifically, as shown in Figure 3 , the first resistive unit is a first resistor R1.

[0035] Specifically, as shown in Figure 3 , the semiconductor active layer of the third thin film transistor T3 is made of a-Si (amorphous silicon), the first end of the third thin film transistor T3 is the source of the third thin film transistor T3, the second end of the third thin film transistor T3 is the drain of the third thin film transistor T3, the third thin film transistor T3 is an N-type thin film transistor, the gate of the third thin film transistor T3 is configured to be connected to the second preset high voltage, so that the third thin film transistor T3 is turned on, and the on-resistance of the third thin film transistor T3 is the equivalent resistance of the third thin film transistor T3 when the third thin film transistor T3 is turned on.

[0036] Specifically, as shown in Figure 3 and Figure 4As shown in the figure, the first switch unit 2010 is a fifth thin film transistor T5, the first end of the first switch unit 2010 is the source of the fifth thin film transistor T5, the second end of the first switch unit 2010 is the drain of the fifth thin film transistor T5, and the controlled end of the first switch unit 2010 is the gate of the fifth thin film transistor T5. The fifth thin film transistor T5 is an N-type thin film transistor, and the semiconductor active layer of the fifth thin film transistor T5 is made of a-Si (amorphous silicon) in an example.

[0037] Specifically, as shown in the figure, Figure 3 and Figure 4 As shown in the figure, the second switch unit 2011 is a sixth thin film transistor T6, the first end of the second switch unit 2011 is the source of the sixth thin film transistor T6, the second end of the second switch unit 2011 is the drain of the sixth thin film transistor T6, and the controlled end of the second switch unit 2011 is the gate of the sixth thin film transistor T6. The sixth thin film transistor T6 is an N-type thin film transistor, and the semiconductor active layer of the sixth thin film transistor T6 is made of a-Si (amorphous silicon) in an example.

[0038] Specifically, the first preset high voltage is greater than the first preset low voltage.

[0039] Specifically, as shown in the figure, Figure 3 As shown in the figure, the temperature control voltage division module 200 includes a first resistive unit 2000 and a third thin film transistor T3, and the first resistive unit is a first resistor R1. The potential selection module 201 includes a first switch unit 2010 and a second switch unit 2011. The carrier mobility of the semiconductor active layer of the third thin film transistor T3 changes with the change of the temperature of the display panel (positively correlated with the change of the temperature), and the semiconductor active layer is made of a-Si (amorphous silicon) in an example. The change rule of the electron mobility of a-Si with the change of the temperature of the display panel conforms to the Arrhenius equation, and the Arrhenius equation is shown in formula (1). Formula (1) is as follows: Formula (1); Wherein, u0 is the electron mobility of a-Si at a known temperature of the display panel (for example, the known temperature is the normal temperature 25℃), Ea is the activation energy (unit: eV), T is the current temperature of the display panel (unit: Kelvin), kb is the Boltzmann constant, and u(T) is the electron mobility of a-Si at the current temperature T. As can be seen from formula (1), the electron mobility of a-Si gradually increases with the increase of the temperature of the display panel, and the actual measurement results show that the electron mobility of a-Si can increase several times or even tens of times due to different manufacturing processes when the temperature of the display panel increases from -40°C to 85°C. Since the first end of the first resistor R1 is connected to the first high voltage end VDD1, the first high voltage end VDD1 is connected to the first preset high voltage, the second end of the first resistor R1 is connected to the first end of the third thin film transistor T3, the connection node is the first control node Q1, the second end of the third thin film transistor T3 is connected to the first low voltage end VSS1, the first low voltage end VSS1 is connected to the first preset low voltage, and the gate of the third thin film transistor T3 is connected to the second preset high voltage, therefore, the voltage of the first control node Q1 is determined by the voltage division relationship between the first resistor R1 and the third thin film transistor T3, and the voltage of the first control node Q1 is shown in formula (2) as follows: , formula (2); wherein, V Q is the voltage of the first control node Q1, V VDD1 is the first preset high voltage, V vss1 is the first preset low voltage, R1 is the resistance value of the first resistor R1, and Rtft is the on-resistance of the third thin film transistor T3. When the temperature of the display panel is less than the first preset temperature, the electron mobility of the semiconductor active layer of the third thin film transistor T3 is relatively low, and the on-resistance Rtft of the third thin film transistor T3 is relatively large. At this time, the voltage of the first control node Q1 tends to the first preset high voltage, that is, the third thin film transistor T3 lifts the voltage of the first control node Q1 when the temperature of the display panel is less than the first preset temperature. When the temperature is not less than the first preset temperature, the electron mobility of the semiconductor active layer of the third thin-film transistor T3 is relatively high, and the on-resistance Rtft of the third thin-film transistor T3 is relatively small. At this time, the voltage of the first control node Q1 tends to the first preset low voltage, that is, the third thin-film transistor T3 resets the voltage of the first control node Q1 when the temperature of the display panel is not less than the first preset temperature. Thus, the voltage of the first control node Q1 is lifted when the display panel is at low temperature, and the voltage of the first control node Q1 is reset when the display panel is at high temperature. When the voltage of the first control node Q1 is lifted, the first switch unit 2010 is turned on, and the voltage of the first end of the second switch unit 2011 is lifted when the first switch unit 2010 is turned on. When the voltage of the first control node Q1 is reset, the first switch unit 2010 is turned off. In the display stage of the frame period, the second switch unit 2011 is turned on when the scanning line outputs the scanning signal Figure 3The potential selection module 201 in the Nth row is connected with the controlled end of the second switch unit 2011 in the potential selection module, and the second switch unit 2011 is opened when the Nth row scan line GateN outputs a scanning signal. If the voltage of the first end of the second switch unit 2011 is lifted (when the display panel is at low temperature), the voltage of the corresponding control line is lifted when the second switch unit 2011 is opened, so that the voltage of the gate of the second thin film transistor connected with the control line in the pixel circuit is lifted, and the second thin film transistor is opened, thereby realizing that the second thin film transistor is opened in the display stage and when the display panel is at low temperature. As shown in the examples, Figure 3 In the Nth row, the second end of the second switch unit 2011 in the potential selection module is connected with the Nth row control line KN, as shown in Figure 2 and Figure 3 When the voltage of the Nth row control line KN is lifted, the Nth row control line KN is connected with the gate of the second thin film transistor T2 of the Nth row pixel circuit, the voltage of the gate of the second thin film transistor T2 of the Nth row pixel circuit is lifted, the second thin film transistor T2 of the Nth row pixel circuit is opened, and the Nth row pixel circuit is charged. The driving mode of the display panel is as follows: in each frame period, the 1st row scan line Gate1, the 2nd row scan line Gate2,..., the Nth row scan line GateN and the N+1th row scan line GateN+1 output scanning signals row by row. Since the voltage of the Nth row control line KN is lifted only when the Nth row scan line GateN outputs a scanning signal in the Nth potential selection module, the pixel circuit can be charged row by row.

[0040] Specifically, as shown in Figure 2 and Figure 3 , it is assumed that the first preset high voltage and the second preset high voltage are both 20V, the first preset low voltage is-20V, the resistance value of the first resistor R1 is 7kΩ, the channel width-length ratio of the third thin film transistor T3 is 5000μm / 5μm, the semiconductor active layer of the third thin film transistor T3 is made of a-Si, and in the simulation model, the electron mobility of the semiconductor active layer is 0.168cm² / (V·s) when the temperature of the display panel is-40℃, and the electron mobility of the semiconductor active layer is The voltage is 1.02 cm² / (V·s). When the display panel temperature is -40℃, the simulation shows that the voltage of the first control node Q1 is approximately 12.3V. At this time, the voltage on the control line is 12.3V, which makes the voltage difference between the gate and source of the second thin-film transistor T2 greater than the turn-on threshold voltage of the second thin-film transistor T2, 2V. Therefore, the second thin-film transistor T2 is turned on. When the display panel temperature is 85℃, the simulation shows that the voltage of the first control node Q1 is approximately -9.5V. At this time, the voltage on the control line is -9.5V, which makes the voltage difference between the gate and source of the second thin-film transistor T2 less than the turn-on threshold voltage of the second thin-film transistor T2, 2V. Therefore, the second thin-film transistor T2 is turned off.

[0041] In one optional embodiment, the resistance value of the first resistive unit is equal to the resistance value of the conduction resistance of the third thin-film transistor at a second preset temperature, and the second preset temperature is greater than the first preset temperature.

[0042] Specifically, such as Figure 3 As shown in the above formula (1), assuming the resistance value of the first resistor R1 is fixed, if the resistance value of the first resistor R1 is much smaller than the resistance value of the on-resistance of the third thin-film transistor T3, the on-resistance of the third thin-film transistor T3 can obtain a very large voltage. No matter how the temperature of the display panel changes, the voltage of the first control node Q1 is infinitely close to the voltage of the first high voltage terminal VDD1. The voltage of the first control node Q1 is not sensitive to temperature changes (not sensitive to changes in the electron mobility of the semiconductor active layer of the third thin-film transistor T3). If the resistance value of the first resistor R1 is much larger than the resistance value of the on-resistance of the third thin-film transistor T3, the on-resistance of the third thin-film transistor T3 can obtain a very small voltage. No matter how the temperature of the display panel changes, the voltage of the first control node Q1 is infinitely close to the voltage of the first high voltage terminal VDD1. The voltage of the first control node Q1 is not sensitive to temperature changes (not sensitive to changes in the electron mobility of the semiconductor active layer of the third thin-film transistor T3). Regardless of temperature changes, the voltage of the first control node Q1 remains infinitely close to the voltage of the first low-voltage terminal VSS1. The voltage of the first control node Q1 is not sensitive to temperature changes. Therefore, the closer the resistance value of the first resistor R1 is to the on-resistance value of the third thin-film transistor T3, the more obvious the voltage of the first control node Q1 changes with the temperature of the display panel. For example, the second preset temperature can be a normal temperature of 25°C. The resistance value of the first resistive unit is equal to the on-resistance value of the third thin-film transistor at the second preset temperature. The on-resistance value of the third thin-film transistor T3 is about several thousand ohms. Therefore, the resistance value of the first resistive unit is also set to several thousand ohms. In this way, the resistor winding will not be too long and will not affect the wiring space of the display panel.

[0043] In one optional embodiment, the difference between the first preset high voltage and the first preset low voltage is greater than a preset voltage difference.

[0044] Specifically, such as Figure 3As shown, and referring to the above formula (1), the voltage of the first control node Q1 is positively correlated with the difference between the voltage of the first high voltage end VDD1 (the first preset high voltage V VDD1 ) and the voltage of the first low voltage end VSS1 (the first preset low voltage V Vss1 ). When the temperature of the display panel changes by a certain value, i.e., the electron mobility of the semiconductor active layer of the third thin film transistor T3 changes by a certain value, i.e., the on-resistance Rtft of the third thin film transistor T3 changes by a certain value, the voltage of the first control node Q1 changes more obviously when the difference between the voltage of the first high voltage end VDD1 and the voltage of the first low voltage end VSS1 is larger. Therefore, the difference between the first preset high voltage and the first preset low voltage is greater than the preset voltage difference.

[0045] In an alternative embodiment, as shown in Figure 3 and Figure 4 , the above-mentioned potential selection module 201 comprises: A third switch unit 2012, a first end of the third switch unit 2012 is connected with a second low voltage end VGL, the second low voltage end VGL is connected with a second preset low voltage, a second end of the third switch unit 2012 is connected with a corresponding control line, and a controlled end of the third switch unit 2012 is connected with a next row of scan lines of the above-mentioned scan lines. The third switch unit 2012 is configured to reset the voltage of the corresponding control line when the next row of scan lines of the above-mentioned scan lines outputs the above-mentioned scan signal.

[0046] Specifically, as shown in Figure 3 and Figure 4 , the third switch unit 2012 is a seventh thin film transistor T7, the first end of the third switch unit 2012 is the source electrode of the seventh thin film transistor T7, the second end of the third switch unit 2012 is the drain electrode of the seventh thin film transistor T7, the controlled end of the third switch unit 2012 is the gate electrode of the seventh thin film transistor T7, and the seventh thin film transistor T7 is an N-type thin film transistor.

[0047] Specifically, as shown in Figure 2 , Figure 3 and Figure 4As shown, the driving mode of the display panel is as follows: in each frame period, the 1st row scan line Gate1, the 2nd row scan line Gate2, …, the Nth row scan line GateN and the (N+1)th row scan line GateN+1 output the scan signals row by row, and charge the pixel circuit row by row. For the Nth potential selection module, the control end of the third switch unit 2012 in the potential selection module is connected with the (N+1)th row scan line GateN+1. When the Nth row scan line GateN does not output the scan signal and the (N+1)th row scan line GateN+1 outputs the scan signal, the voltage of the Nth control line KN is reset, the Nth control line KN is connected with the gate of the second thin film transistor T2 of the Nth row pixel circuit, the voltage of the gate of the second thin film transistor T2 of the Nth row pixel circuit is reset, the second thin film transistor T2 of the Nth row pixel circuit is turned off, and the charging of the Nth row pixel circuit is stopped. Thus, the voltage of the control line corresponding to the row of pixel circuits can be reset in time after the charging of the row of pixel circuits is completed, so that the second thin film transistor of the row of pixel circuits can keep a reliable off state in the non-charging period.

[0048] In an optional embodiment, the control circuit 20 includes an inverter 202, the input end of the inverter 202 is connected with the first control node Q1, and the potential selection module 201 includes: a fourth switch unit 2013, the first end of the fourth switch unit 2013 is connected with the first control node Q1, the second end of the fourth switch unit 2013 is connected with the corresponding control line, the control end of the fourth switch unit 2013 is connected with the output end of the inverter 202, and the connection node is the second control node Q2; The inverter 202 is configured to lift the voltage of the second control node Q2 when the voltage of the first control node Q1 is reset; The fourth switch unit 2013 is configured to reset the voltage of the corresponding control line when the voltage of the second control node Q2 is lifted.

[0049] Specifically, as shown in Figure 3 and Figure 4 Specifically, as shown in

[0050] Specifically, as shown in Figure 2 , Figure 3 and Figure 4As shown, referring to the above, the third thin film transistor T3 resets the voltage of the first control node Q1 when the temperature of the display panel is not less than the first preset temperature, so as to realize that the voltage of the first control node Q1 is reset when the display panel is at high temperature, the inverter 202 lifts the voltage of the second control node Q2 when the voltage of the first control node Q1 is reset, the fourth switch unit 2013 is turned on when the voltage of the second control node Q2 is lifted, and resets the voltage of the corresponding control line when turned on, so that the voltage of the gate of the second thin film transistor connected with the control line in the pixel circuit is reset, and the second thin film transistor is turned off, so as to realize that the second thin film transistor is turned off when the display panel is at high temperature in the display stage, and the example, Figure 3 The potential selection module 201 in the Nth row is the Nth potential selection module, the second end of the fourth switch unit 2013 in the potential selection module is connected with the Nth row control line KN, the fourth switch unit 2013 is turned on when the display panel is at high temperature, and resets the voltage of the Nth row control line KN when turned on, the Nth row control line KN is connected with the gate of the second thin film transistor T2 of the Nth row pixel circuit, the voltage of the gate of the second thin film transistor T2 of the Nth row pixel circuit is reset, and the second thin film transistor T2 of the Nth row pixel circuit is turned off.

[0051] Specifically, as shown in Figure 2 and Figure 3 The first switch unit 2010, the second switch unit 2011, the third switch unit 2012 and the fourth switch unit 2013 in the potential selection module 201 control whether the voltage of the first control node Q1 reaches the control line.

[0052] Specifically, as shown in Figure 2 and Figure 3 As shown in the above formula (1), the voltage of the first control node Q1 can be adjusted by adjusting the voltage of the first high voltage end VDD1 and the voltage of the first low voltage end VSS1, and the voltage of the first control node Q1 determines the size of the voltage on the control line when the display panel is at high temperature, so that the drain current of the second thin film transistor of the pixel circuit is less than the preset drain current when the display panel is at high temperature (i.e. the temperature of the display panel is not less than the first preset temperature) by controlling the voltage of the first high voltage end VDD1 (the first preset high voltage) and the voltage of the first low voltage end VSS1 (the first preset low voltage), thereby effectively inhibiting the leakage of the pixel electrode to the data line in the high temperature environment of the display panel.

[0053] In an optional embodiment, as shown in Figure 3 The above inverter 202 includes: The second resistive unit 2020 and the fourth thin film transistor T4, an input end of the inverter 202 is a controlled end of the fourth thin film transistor T4, an output end of the inverter 202 is a first end of the fourth thin film transistor T4, a first end of the second resistive unit 2020 is connected with a second high voltage end VDD2, the second high voltage end VDD2 is configured to access a third preset high voltage, a second end of the second resistive unit 2020 is connected with the first end of the fourth thin film transistor T4, a second end of the fourth thin film transistor T4 is connected with a third low voltage end VSS2, the third low voltage end VSS2 is configured to access a third preset low voltage.

[0054] Specifically, as shown in Figure 3 The second resistive unit 2020 is a second resistor R2.

[0055] Specifically, the third preset high voltage is greater than the third preset low voltage.

[0056] In the embodiment, as shown in Figure 3 The temperature control voltage dividing module 200 and the inverter 202 have the same structure, and the difference lies in that the gate of the third thin film transistor in the temperature control voltage dividing module 200 accesses a constant second preset high voltage, while the gate of the fourth thin film transistor T4 in the inverter 202 is connected with the first control node Q1, so the voltage of the gate of the fourth thin film transistor T4 is variable. When the voltage of the first control node Q1 is lifted, the fourth thin film transistor T4 is turned on, at this time, the voltage of the second control node Q2 tends to the voltage of the third low voltage end VSS2. Considering that the on-resistance of the fourth thin film transistor T4 is relatively large, in order to make the voltage of the second control node Q2 tend to the voltage of the third low voltage end VSS2 as much as possible, the resistance value of the second resistor R2 needs to be as large as possible, that is, the fourth thin film transistor T4 resets the voltage of the second control node Q2. When the voltage of the first control node Q1 is reset, the fourth thin film transistor T4 is turned off, the resistance of the fourth thin film transistor T4 approaches infinity, and the voltage of the second control node Q2 tends to the voltage of the second high voltage end VDD2, that is, the fourth thin film transistor T4 lifts the voltage of the second control node Q2, thereby realizing that when the voltage of the first control node Q1 is lifted, the voltage of the second control node Q2 is reset, and when the voltage of the first control node Q1 is reset, the voltage of the second control node Q2 is lifted.

[0057] In an optional embodiment, the display panel has a display area 1 and a non-display area 2, the plurality of pixel circuits 10 are arranged in the display area 1, and the control circuit 20 is arranged in the non-display area 2.

[0058] Specifically, as shown in Figure 2 and Figure 4As shown, the non-display area 2 includes a fan-out area 30 and a frame area 31. The fan-out area 30 is located at one side of the outgoing line end of the source driving circuit 21. The temperature control voltage dividing module 200 and the inverter 202 in the control circuit 20 are arranged at the side of the fan-out area 30. In this way, the first resistor R1 in the temperature control voltage dividing module 200 and the second resistor R2 in the inverter 202 can be arranged in as large a space as possible without occupying too much space of the non-display area 2. The potential selection module 201 is arranged in the frame area 31.

[0059] In an alternative embodiment, as shown in Figure 2 and Figure 4 The voltage input end Vin, the first low voltage end VSS1, the third low voltage end VSS2, the first high voltage end VDD1 and the second high voltage end VDD2 are connected to the source driving circuit 21 of the display panel. The second low voltage end VGL is connected to the corresponding scan driving unit of the gate driving circuit of the display panel.

[0060] Specifically, the voltage input end Vin, the first low voltage end VSS1, the third low voltage end VSS2, the first high voltage end VDD1 and the second high voltage end VDD2 are connected to the source driving circuit 21 of the display panel, i.e. the source driving circuit 21 provides signals for the temperature control voltage dividing module 200 and the inverter 202. The gate driving circuit includes a plurality of cascaded scan driving units, one scan driving unit providing a scan signal for one row of scan lines. The second low voltage end VGL in the potential selection module 201 is connected to the corresponding scan driving unit, i.e. the corresponding scan driving unit provides signals for the potential selection module 201.

[0061] The display device provided by the embodiments of the present application includes any one of the display panels described above.

[0062] It should be understood that the terms used herein are for the purpose of describing particular example embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", "including" and "has" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order in which they are described, unless specifically identified as an order dependent step. It is also to be understood that additional or alternative steps can be employed.

[0063] The foregoing is considered as illustrative only of the principles of the application. Numerous modifications and changes will readily occur to those skilled in the art, and it is intended to embrace all such modifications and changes that fall within the scope of the application. Accordingly, the application is not to be restricted in scope to the specific embodiments disclosed herein but is to be accorded the full scope that the principles and novel features request appropriately granted.

Claims

1. A display panel, characterized in that, The display panel includes: Multiple pixel circuits, each pixel circuit including: a first thin-film transistor and a second thin-film transistor, wherein a first terminal of the first thin-film transistor and a first terminal of the second thin-film transistor are both connected to a data line, a second terminal of the first thin-film transistor and a second terminal of the second thin-film transistor are both connected to a pixel electrode, and the gate of the first thin-film transistor is connected to a scan line corresponding to the pixel circuit. Control circuit, the control circuit being configured to: During the display phase, when the temperature of the display panel is lower than the first preset temperature, the voltage of the gate of the second thin-film transistor is increased to turn on the second thin-film transistor. When the temperature is not lower than the first preset temperature, the voltage of the gate of the second thin-film transistor is reset to turn off the second thin-film transistor and make the leakage current of the second thin-film transistor less than the preset leakage current.

2. The display panel according to claim 1, characterized in that, The display panel includes: multiple rows of control lines, one row of control lines corresponding to one row of pixel circuits in the plurality of pixel circuits, the control lines being connected to the gate of the second thin-film transistor of the corresponding pixel circuit, and the control circuit including: A temperature-controlled voltage divider module includes: a first resistive unit and a third thin-film transistor. A first terminal of the first resistive unit is connected to a first high-voltage terminal, which is configured to receive a first preset high voltage. A second terminal of the first resistive unit is connected to a first terminal of the third thin-film transistor, and the connection node is a first control node. A second terminal of the third thin-film transistor is connected to a first low-voltage terminal, which is configured to receive a first preset low voltage. The gate of the third thin-film transistor is connected to a voltage input terminal, which is configured to receive a second preset high voltage. The resistance value of the on-resistance of the third thin-film transistor is negatively correlated with the temperature of the display panel, so that the third thin-film transistor raises the voltage of the first control node when the temperature of the display panel is lower than the first preset temperature, and resets the voltage of the first control node when the temperature of the display panel is not lower than the first preset temperature. Multiple potential selection modules are provided, one of which corresponds to one row of control lines in the multiple rows of control lines. Each potential selection module includes a first switch unit and a second switch unit. A first end of the first switch unit is connected to the controlled end of the first switch unit and to the first control node. A second end of the first switch unit is connected to the first end of the second switch unit. The controlled end of the second switch unit is connected to the scan line. The second end of the second switch unit is connected to the corresponding control line. The first switching unit is configured to raise the voltage at the first terminal of the second switching unit when the voltage of the first control node is raised; The second switching unit is configured to raise the voltage of the corresponding control line when the scan line outputs a scan signal and the voltage at the first terminal of the second switching unit is raised.

3. The display panel according to claim 2, characterized in that, The resistance value of the first resistive unit is equal to the resistance value of the conduction resistance of the third thin-film transistor at a second preset temperature, and the second preset temperature is greater than the first preset temperature.

4. The display panel according to claim 2, characterized in that, The potential selection module includes: The third switching unit has a first terminal connected to a second low voltage terminal, the second low voltage terminal being connected to a second preset low voltage, a second terminal connected to a corresponding control line, and a controlled terminal connected to the next row of scan lines of the scan line. The third switching unit is configured to reset the voltage of the corresponding control line when the scan signal is output on the next scan line of the scan line.

5. The display panel according to claim 4, characterized in that, The control circuit includes an inverter, the input terminal of which is connected to the first control node; the potential selection module includes: The fourth switching unit has a first end connected to the first control node, a second end connected to the corresponding control line, and a controlled end connected to the output end of the inverter, with the connection node being the second control node. The inverter is configured to raise the voltage of the second control node when the voltage of the first control node is reset; The fourth switching unit is configured to reset the voltage of the corresponding control line when the voltage of the second control node is raised.

6. The display panel according to claim 5, characterized in that, The inverter includes: The second resistive unit and the fourth thin-film transistor, wherein the input terminal of the inverter is the controlled terminal of the fourth thin-film transistor, the output terminal of the inverter is the first terminal of the fourth thin-film transistor, the first terminal of the second resistive unit is connected to a second high-voltage terminal, the second high-voltage terminal is configured to be connected to a third preset high voltage, the second terminal of the second resistive unit is connected to the first terminal of the fourth thin-film transistor, the second terminal of the fourth thin-film transistor is connected to a third low-voltage terminal, and the third low-voltage terminal is configured to be connected to a third preset low voltage.

7. The display panel according to claim 3, characterized in that, The semiconductor active layer of the third thin-film transistor is made of amorphous silicon.

8. The display panel according to claim 6, characterized in that, The display panel has a display area and a non-display area, the plurality of pixel circuits are disposed in the display area, and the control circuit is disposed in the non-display area.

9. The display panel according to claim 8, characterized in that, The voltage input terminal, the first low voltage terminal, the third low voltage terminal, the first high voltage terminal, and the second high voltage terminal are all connected to the source driving circuit of the display panel, and the second low voltage terminal is connected to the scan driving unit corresponding to the corresponding pixel circuit in the gate driving circuit of the display panel.

10. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1 to 9.

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