Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device, which are used for reducing film layer step difference at a via hole and improving display uniformity. The array substrate provided by the embodiment of the application comprises a substrate, a plurality of first signal lines, a first insulating layer, a first electrode, a second insulating layer and a plurality of connecting parts. The first insulating layer comprises a plurality of first vias penetrating through the thickness of the first insulating layer. The second insulating layer comprises a plurality of second vias penetrating through the thickness of the second insulating layer. The second via in the orthographic projection of the substrate covers the first via in the orthographic projection of the substrate, and the first electrode in the orthographic projection of the substrate overlaps with the second via in the orthographic projection of the substrate. The connecting part in the orthographic projection of the substrate overlaps with the second via in the orthographic projection of the substrate. The connecting part is electrically connected with the first electrode through the second via, and the connecting part is electrically connected with the first signal line through the second via and the first via.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] For LCD touch display panels, one touch solution involves reusing the common electrode of the array substrate as the touch electrode, with the touch signal line and the common electrode arranged on the same layer. However, this solution has a relatively small pixel aperture ratio, making it unsuitable for high pixel density and high resolution products. To improve the pixel aperture ratio, the touch signal line and the common electrode are placed on different layers. However, compared to the case where the touch signal line and the common electrode are arranged on the same layer, the film layer difference at the vias where the touch signal line and the common electrode are electrically connected is larger, affecting the diffusion uniformity of the alignment film and thus the display uniformity. Summary of the Invention

[0003] This application provides an array substrate, a display panel, and a display device to reduce film layer differences at vias and improve display uniformity.

[0004] An array substrate is provided in this application embodiment. The array substrate includes: a substrate, a plurality of first signal lines located on one side of the substrate, a first insulating layer located on the side of the plurality of first signal lines away from the substrate, a first electrode located on the side of the first insulating layer away from the plurality of first signal lines, a second insulating layer located on the side of the first electrode away from the first insulating layer, and a plurality of connecting portions located on the side of the second insulating layer away from the first electrode.

[0005] The first insulating layer includes a plurality of first vias that penetrate its thickness;

[0006] The second insulating layer includes a plurality of second vias extending through its thickness; the orthographic projection of the second vias onto the substrate covers the orthographic projection of the first vias onto the substrate, and the orthographic projection of the first electrode onto the substrate overlaps with the orthographic projection of the second vias onto the substrate.

[0007] The orthographic projection of the connecting portion onto the substrate overlaps with the orthographic projection of the second via onto the substrate; the connecting portion is electrically connected to the first electrode through the second via, and the connecting portion is electrically connected to the first signal line through the second via and the first via.

[0008] In some embodiments, the first electrode includes:

[0009] Multiple sub-electrodes are arranged in an array along a first direction and a second direction; the first direction intersects the second direction, and the first direction intersects the extension direction of the first signal line; the orthographic projection of the first signal line on the substrate and the orthographic projection of the sub-electrodes on the substrate do not overlap, and the orthographic projection of the first signal line on the substrate overlaps with the orthographic projection of the region between two adjacent sub-electrodes in the first direction on the substrate.

[0010] Multiple connecting electrodes; adjacent sub-electrodes are electrically connected through connecting sub-electrodes; the orthographic projection of the first via on the substrate does not overlap with the orthographic projection of the connecting electrode on the substrate, a portion of the orthographic projection of the second via on the substrate falls within the orthographic projection of the connecting electrode on the substrate, and the connecting portion is electrically connected to the connecting electrode through the second via.

[0011] In some embodiments, the first signal line includes a plurality of first sub-sections and a plurality of second sub-sections; the first sub-sections and the second sub-sections are alternately arranged in the extending direction of the first signal line;

[0012] The first via, the second via, the connecting electrode, and the orthographic projection of the connecting portion onto the substrate overlap with the orthographic projection of the second sub-part onto the substrate. The connecting electrode is electrically connected to the second sub-part through the second via and the first via.

[0013] In some embodiments, the plurality of sub-electrodes are divided into: a plurality of sub-electrode columns arranged along a first direction and a plurality of sub-electrode rows arranged along a second direction;

[0014] The first signal line's orthographic projection onto the substrate falls within the region between two adjacent sub-electrode columns. The first sub-part and the second sub-part are arranged alternately in the second direction. The intersection region of the second sub-part's orthographic projection onto the substrate with the region between two adjacent sub-electrode columns and the region between two adjacent sub-electrode rows overlaps with the orthographic projection onto the substrate.

[0015] In some embodiments, the orthographic projections of the first via and the second via on the substrate fall within the orthographic projection of the second sub-part on the substrate, and the orthographic projections of the connecting part and the connecting electrode on the substrate overlap with the orthographic projection of the second sub-part on the substrate.

[0016] In some embodiments, the plurality of connection electrodes includes: a plurality of first connection electrodes and a plurality of second connection electrodes;

[0017] The first connecting electrode and the second connecting electrode are both electrically connected to two sub-electrodes adjacent in the first direction. The orthographic projection of each second sub-part on the substrate overlaps with the orthographic projection of a first connecting electrode and a second connecting electrode on the substrate.

[0018] The orthographic projection of the first via on the substrate does not overlap with the orthographic projections of the first connecting electrode and the second connecting electrode on the substrate, and the orthographic projection of the first via on the substrate falls within the orthographic projection of the substrate in the region between the first connecting electrode and the second connecting electrode corresponding to a second sub-part.

[0019] The orthographic projection of the second via on the substrate does not overlap with the orthographic projection of the second connecting electrode on the substrate. The orthographic projections of the second via and the connecting electrode on the substrate overlap with the orthographic projection of the first connecting electrode on the substrate. The connecting electrode is electrically connected to the first connecting electrode through the second via.

[0020] In some embodiments, in a first direction, the width of the first sub-part is smaller than the width of the second sub-part.

[0021] In some embodiments, the plurality of sub-electrodes are divided into: a plurality of sub-electrode columns arranged along a first direction and a plurality of sub-electrode rows arranged along a second direction;

[0022] The orthographic projection of the first sub-part onto the substrate falls within the orthographic projection of the region between two adjacent sub-electrode rows onto the substrate. The orthographic projection of the second sub-part onto the substrate overlaps with the orthographic projection of the region between two adjacent sub-electrode rows onto the substrate, and the orthographic projection of the second sub-part onto the substrate overlaps with the orthographic projection of the sub-electrode rows onto the substrate.

[0023] In some embodiments, in the region where the connecting portion is electrically connected to the second sub-part and the connecting electrode, the orthographic projection of the first via on the substrate is located on the side of the first sub-part that is electrically connected to the second sub-part away from the orthographic projection of the connecting electrode on the substrate.

[0024] In some embodiments, in the same first signal line, the orthographic projection of the second sub-part onto the substrate overlaps with the orthographic projection of the same sub-electrode column onto the substrate.

[0025] In some embodiments, the array substrate further includes: a plurality of thin-film transistors and a plurality of pixel electrodes;

[0026] The thin-film transistor is located between the first signal line and the substrate.

[0027] The pixel electrode is located on the side of the first electrode away from the substrate, and the connecting part is disposed on the same layer as the pixel electrode.

[0028] In some embodiments, the array substrate further includes a plurality of scan lines and a plurality of data lines arranged in a cross configuration;

[0029] The orthographic projection of the first signal line onto the substrate and the orthographic projection of the data line onto the substrate both overlap.

[0030] The number of signal lines is less than the number of data lines.

[0031] In some embodiments, the orthographic projection of the second via onto the substrate overlaps with the orthographic projections of the scan line and the data line onto the substrate.

[0032] This application provides a display panel comprising: an array substrate provided in this application, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

[0033] This application provides a display device, including a display panel provided in this application embodiment.

[0034] The array substrate, display panel, and display device provided in this application embodiment have the first signal line and the first electrode located on different layers, thereby increasing the aperture ratio of the array substrate and improving the pixel density and resolution of the array substrate. Furthermore, since the first electrode is located on the side of the first signal line away from the substrate, its thickness is smaller. Compared to cases where the film layers are reversed, the depth of the vias in the connection area can be reduced, i.e., the film layer step difference in the via area of ​​the array substrate can be reduced. Subsequent coating of the alignment layer can improve the diffusion uniformity of the alignment layer. When the array substrate is applied to a display panel, it can improve display uniformity, product yield, and quality. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application;

[0037] Figure 2 An embodiment of this application provides a method for... Figure 1 A schematic diagram of the cross-sectional structure of AA';

[0038] Figure 3 This is a schematic diagram of another array substrate provided in an embodiment of this application;

[0039] Figure 4 This is a schematic diagram of another array substrate provided in the embodiments of this application;

[0040] Figure 5 This is a schematic diagram of another array substrate provided in the embodiments of this application;

[0041] Figure 6 This is a schematic diagram of another array substrate provided in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram of another array substrate provided in the embodiments of this application;

[0043] Figure 8 This is a schematic diagram of another array substrate provided in the embodiments of this application;

[0044] Figure 9 This is a schematic diagram of another array substrate provided in the embodiments of this application;

[0045] Figure 10 An embodiment of this application provides a method for... Figure 9 A schematic diagram of the cross-sectional structure of BB';

[0046] Figure 11 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0047] Figure 12 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0049] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0050] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this application. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0051] In related technologies, in order not to affect the aperture ratio of the display panel, the touch trace is located on the side of the touch electrode away from the substrate. The touch trace and the touch electrode are electrically connected through a connecting electrode, which is also located on the side of the touch trace away from the substrate. Due to the thickness of the touch trace, the vias for the electrical connection between the connecting electrode and the touch electrode are relatively deep, resulting in a large film layer difference in the via area. This will cause uneven diffusion of the alignment film during subsequent coating, affecting display uniformity, product yield and quality.

[0052] This application provides an array substrate, such as... Figure 1 , Figure 2 As shown, the array substrate includes: a substrate 1, a plurality of first signal lines 4 located on one side of the substrate 1, a first insulating layer 3 located on the side of the plurality of first signal lines 4 away from the substrate 1, a first electrode 2 located on the side of the first insulating layer 3 away from the plurality of first signal lines 4, a second insulating layer 5 located on the side of the first electrode 2 away from the first insulating layer 3, and a plurality of connecting portions 6 located on the side of the second insulating layer 5 away from the first electrode 2.

[0053] The first insulating layer 3 includes a plurality of first vias 301 that penetrate its thickness;

[0054] The second insulating layer 5 includes a plurality of second vias 501 that penetrate its thickness; the orthographic projection of the second vias 501 onto the substrate 1 covers the orthographic projection of the first via 301 onto the substrate 1, and the orthographic projection of the first electrode 2 onto the substrate 1 overlaps with the orthographic projection of the second vias 501 onto the substrate 1.

[0055] The orthographic projection of the connecting part 6 on the substrate 1 overlaps with the orthographic projection of the second via 501 on the substrate 1; the connecting part 6 is electrically connected to the first electrode 2 through the second via 501, and the connecting part 6 is electrically connected to the first signal line 4 through the second via 501 and the first via 301.

[0056] The array substrate provided in this application embodiment has the first signal line and the first electrode located on different layers, thereby increasing the aperture ratio of the array substrate and improving the pixel density and resolution. Furthermore, since the first electrode is located on the side of the first signal line away from the substrate, its thickness is smaller. Compared to cases where the film layers are reversed, this reduces the depth of the vias in the connection area, thus reducing the film layer step difference in the via area. Subsequent coating of the alignment layer can improve the diffusion uniformity of the alignment layer. When the array substrate is applied to a display panel, it can improve display uniformity, product yield, and overall quality.

[0057] It should be noted that, Figure 2 For along Figure 1 Cross-sectional view of AA'.

[0058] In some embodiments, the thickness of the first signal line is greater than the thickness of the first electrode.

[0059] In some embodiments, the thickness of the first signal line is about 0.3 micrometers, and the thickness of the first electrode is about 0.04 micrometers.

[0060] In some embodiments, the array substrate further includes an alignment film located on the side of the connection portion facing away from the substrate. The material of the alignment film is, for example, polyimide.

[0061] In specific implementation, the first electrode is a common electrode and is reused as a touch electrode, and the first signal line is used to transmit touch signals or common voltage signals.

[0062] In some embodiments, such as Figure 1 As shown, the first electrode 2 includes:

[0063] Multiple sub-electrodes 201 are arranged in an array along a first direction X and a second direction Y; the first direction X intersects the second direction Y, and the first direction X intersects the extension direction of the first signal line 4; the orthographic projection of the first signal line 4 on the substrate 1 and the orthographic projection of the sub-electrodes 201 on the substrate 1 do not overlap, and the orthographic projection of the first signal line 4 on the substrate 1 overlaps with the orthographic projection of the region between two adjacent sub-electrodes 201 in the first direction X on the substrate 1.

[0064] Multiple connecting electrodes 202; adjacent sub-electrodes 201 are electrically connected through connecting sub-electrodes 201; the orthographic projection of the first via 301 on the substrate 1 does not overlap with the orthographic projection of the connecting electrode 202 on the substrate 1, a portion of the orthographic projection of the second via 501 on the substrate 1 falls within the orthographic projection of the connecting electrode 202 on the substrate 1, and the connecting portion 6 is electrically connected to the connecting electrode 202 through the second via 501.

[0065] In the array substrate provided in this application embodiment, when the first electrode is multiplexed as a touch electrode, the sub-electrodes of the first electrode are touch electrode blocks. The sub-electrodes are electrically connected to each other through connecting electrodes, making the first electrode an electrode that is electrically connected as a whole across the entire surface. The orthographic projection of the first via on the substrate does not overlap with the orthographic projection of the connecting electrode on the substrate, thereby preventing the connecting electrode from affecting the electrical connection between the connecting part and the first signal line. A portion of the orthographic projection of the second via on the substrate falls within the orthographic projection of the connecting electrode on the substrate, thereby enabling the connecting part to be electrically connected to the connecting electrode through the second via.

[0066] In specific implementation, such as Figure 1As shown, the array substrate includes multiple sub-pixel regions 16. When the array substrate is applied to a display panel, the sub-pixel regions correspond to the sub-pixel opening regions of the display panel. The sub-pixel regions 16 fall within the orthographic projection of the sub-electrode 201 onto the substrate 1, and the areas of the connecting electrode 202 and the sub-pixel regions 16 overlap.

[0067] In some embodiments, such as Figure 1 , Figure 3 As shown, the array substrate also includes: multiple thin-film transistors 8 and multiple pixel electrodes 9;

[0068] The thin-film transistor 8 is located between the first signal line (not shown) and the substrate 1;

[0069] The pixel electrode 9 is located on the side of the first electrode 2 away from the substrate 1, and the connecting part (not shown) is disposed on the same layer as the pixel electrode 9.

[0070] In some embodiments, the distance between the connector and the pixel electrode is greater than 3.5 micrometers. This avoids short circuits when the two are disposed on the same layer.

[0071] In some embodiments, such as Figure 3 As shown, the thin film transistor 8 includes: an active layer 801, a gate G, a source S and a drain D located on the side of the gate G away from the substrate 1; the thin film transistor 8 is a top gate structure, that is, the gate G is located on the side of the active layer 801 away from the substrate 1.

[0072] The array substrate further includes: a buffer layer 12 located between the substrate 1 and the active layer 801, a gate insulating layer 13 located between the active layer 801 and the gate G, an interlayer insulating layer 14 located between the gate G and the source S and the drain D, and a first passivation layer 15 located between the source S and the drain D and the first electrode 2.

[0073] The pixel electrode 9 is electrically connected to the drain electrode D through a third via 18 that penetrates the second insulating layer 5, the first insulating layer 3, and the first passivation layer 15.

[0074] In some embodiments, the pixel electrode or the first electrode further includes multiple slits. Figure 1 The example of a pixel electrode 9 comprising multiple slits is used for illustration.

[0075] In some embodiments, such as Figure 1 As shown, the array substrate also includes multiple scan lines 10 and multiple data lines 11 arranged in a cross pattern;

[0076] Scan line 10 extends approximately along the first direction X, and data line 11 extends approximately along the second direction Y.

[0077] In some embodiments, the scan line and the gate are disposed on the same layer and integrally connected; that is, a portion of the scan line can be regarded as the gate.

[0078] The data cable is set on the same layer as the source and drain and is connected as a whole, which means that a part of the data cable can be regarded as the source.

[0079] It should be noted that, in this application, "same layer" refers to a layer structure formed using the same film deposition process to create a film layer for a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may be at the same height or have the same thickness, or they may be at different heights or have different thicknesses.

[0080] In some embodiments, such as Figure 1 As shown, the extension direction of the first signal line 4 is the same as the extension direction of the data line 11; that is, the first signal line 4 extends approximately along the second direction Y.

[0081] It should be noted that the first signal line and data line extend roughly along the second direction Y, and can be as follows: Figure 1 As shown, the first signal line and data line bend and extend in the second direction Y, meaning that the extension direction of a portion of the first signal line and data line may not be parallel to the second direction Y. Alternatively, the first signal line and data line may extend in a straight line in the second direction Y.

[0082] In some embodiments, the orthographic projection of the first signal line 4 onto the substrate 1 and the orthographic projection of the data line 11 onto the substrate 1 both overlap.

[0083] In practice, at least some sub-pixel areas are located within the area enclosed by the scan lines and data lines.

[0084] In some embodiments, such as Figure 1 As shown, the region between adjacent sub-electrodes 201 in the first direction X overlaps with the orthographic projection of the data line 11 on the substrate 1 in the first direction X, and the width between adjacent sub-electrodes 201 in the first direction X is greater than the line width of the data line 11. This reduces the coupling capacitance between the first electrode and the data line and the first signal line, thus avoiding signal interference.

[0085] In some embodiments, such as Figure 1As shown, the orthographic projections of the sub-electrode 201 and pixel electrode 9 onto the substrate 1 overlap with the orthographic projection of the scan line 10 onto the substrate 1. That is, the sub-electrode and pixel electrode extend into the region between adjacent sub-pixel areas, which is beneficial for increasing the size of the sub-pixel area and improving the sub-pixel aperture ratio.

[0086] In some embodiments, such as Figure 4 As shown, the number of first signal lines 4 is less than the number of data lines 11. Therefore, even if there is a misalignment between the two, the impact on the size of the sub-pixel area can be reduced, thereby reducing the impact on the aperture ratio of the display product.

[0087] It should be noted that, Figure 4 In order to facilitate the distinction between the first signal line 4 and the data line 11, the first signal line 4 is represented by a dashed line.

[0088] In some embodiments, n columns of sub-pixel regions 16 are spaced apart between two adjacent first signal lines; n is an integer greater than 1.

[0089] In some embodiments, three columns of sub-pixel regions are spaced between two adjacent first signal lines.

[0090] In some embodiments, such as Figure 1 As shown, the orthographic projection of the second via 501 onto the substrate 1 does not overlap with the sub-pixel region 16.

[0091] In some embodiments, such as Figure 1 As shown, the orthographic projection of the second via 501 onto the substrate 1 overlaps with the orthographic projections of the scan line 10 and the data line 11 onto the substrate 1.

[0092] That is, the second via is located in the area where the scan line and the data line intersect. It should be noted that, for example... Figure 1 , Figure 4 As shown, between the two columns of sub-pixel areas 16 corresponding to a first signal line 4.

[0093] In some embodiments, not every region where a scan line intersects with a data line is provided with a second via. The number of second vias corresponding to a first signal line is less than the number of regions where scan lines intersect with data lines between two columns of sub-pixel areas. In specific implementations, the second vias are distributed in an array when projected onto the substrate. Second vias corresponding to two adjacent first signal lines can be located in the same row. Alternatively, second vias corresponding to two adjacent first signal lines can be located in different rows.

[0094] In some embodiments, such as Figure 1 , Figure 5As shown, the first signal line 4 includes a plurality of first sub-sections 401 and a plurality of second sub-sections 402; the first sub-sections 401 and the second sub-sections 402 are arranged alternately in the extension direction of the first signal line 4;

[0095] The first via 301, the second via 501, the connecting electrode 202, and the connecting portion 6 overlap on the substrate 1 with the second sub-part 402 on the substrate 1. The connecting electrode 202 is electrically connected to the second sub-part 402 through the second via 501 and the first via 301.

[0096] It should be noted that, in order to clearly illustrate the patterns of the first signal line 4, the first electrode 2, and the connecting part 6, as well as the overlapping relationship between the three, Figure 5 The pixel electrode, scan line, data line, and drain have been removed.

[0097] In some embodiments, such as Figure 1 , Figure 5 As shown, the multiple sub-electrodes 201 are divided into: multiple sub-electrode columns 24 arranged along the first direction X, and multiple sub-electrode rows 25 arranged along the second direction Y.

[0098] In some embodiments, such as Figure 1 , Figure 5 As shown, the first signal line 4 is projected onto the substrate 1 in the region between two adjacent sub-electrode rows 24. The first sub-part 401 and the second sub-part 402 are arranged alternately in the second direction Y. The intersection of the second sub-part 402's projection onto the substrate 1 with the region between two adjacent sub-electrode rows 24 and the region between two adjacent sub-electrode rows 25 overlaps with the projection onto the substrate 1.

[0099] In the array substrate provided in this application embodiment, the first signal line 4 extends in the region between two adjacent sub-electrode columns.

[0100] In some embodiments, such as Figure 1 , Figure 5 As shown, the orthographic projections of the first via 301 and the second via 501 onto the substrate 1 fall within the orthographic projection of the second sub-part 402 onto the substrate 1, and the orthographic projections of the connecting part 6 and the connecting electrode 202 onto the substrate 1 overlap with the orthographic projection of the second sub-part 402 onto the substrate 1.

[0101] That is, the connecting part is electrically connected to the second sub-part of the first signal line.

[0102] In some embodiments, such as Figure 1 , Figure 5 As shown, the plurality of connecting electrodes 202 include: a plurality of first connecting electrodes 2021 and a plurality of second connecting electrodes 2022;

[0103] The first connecting electrode 2021 and the second connecting electrode 2022 are both electrically connected to two adjacent sub-electrodes 201 in the first direction X. The orthographic projection of each second sub-part 402 on the substrate 1 overlaps with the orthographic projection of a first connecting electrode 2021 and a second connecting electrode 2022 on the substrate 1.

[0104] The orthographic projection of the first via 301 onto the substrate 1 does not overlap with the orthographic projections of the first connecting electrode 2021 and the second connecting electrode 2022 onto the substrate 1, and the orthographic projection of the first via 301 onto the substrate 1 falls within the region between the first connecting electrode 2021 and the second connecting electrode 2022 corresponding to a second sub-part 402, which is within the orthographic projection of the substrate 1.

[0105] The orthographic projection of the second via 501 on the substrate 1 and the orthographic projection of the second connecting electrode 2022 on the substrate 1 do not overlap. The orthographic projections of the second via 501 and the connecting electrode 202 on the substrate 1 overlap with the orthographic projection of the first connecting electrode 2021 on the substrate 1. The connecting electrode 202 is electrically connected to the first connecting electrode 2021 through the second via 501.

[0106] The array substrate provided in this application embodiment divides the connection electrode of the first electrode into two parts, a first connection electrode and a second connection electrode, in the area where the first via and the second via are provided. The first via avoids the area where the connection electrode is provided, so that the connection electrode will not affect the electrical connection between the connection part and the first signal line.

[0107] In some embodiments, the plurality of connecting electrodes further includes a plurality of third connecting electrodes, which are electrically connected to four adjacent sub-electrodes arranged in an array. The orthographic projection of the third connecting electrode onto the substrate does not overlap with the orthographic projections of the first via and the second via onto the substrate. That is, for areas where the first via, the second via, and the connecting portion are not required, the four adjacent sub-electrodes arranged in an array can be electrically connected through the same connecting electrode.

[0108] In some embodiments, in the first direction X, the width of the first sub-part 401 is smaller than the width of the second sub-part 402. Therefore, the electrical connection between the connecting part and the second sub-part of the first signal line can reduce the difficulty of electrical connection between the two, that is, reduce the design and manufacturing difficulty of the first via and the second via.

[0109] In some embodiments, such as Figure 1 , Figure 5 As shown, the first sub-part 401 has a strip shape in the orthographic projection of the substrate 1, and the second sub-part 402 has a block shape in the orthographic projection of the substrate 1.

[0110] Alternatively, in some embodiments, such as Figure 6 , Figure 7 As shown, the orthographic projection of the first sub-part 401 onto the substrate 1 falls within the orthographic projection of the substrate 1 between two adjacent sub-electrode rows 24. The orthographic projection of the second sub-part 402 onto the substrate 1 overlaps with the orthographic projection of the region between two adjacent sub-electrode rows 25 onto the substrate 1. Furthermore, the orthographic projection of the second sub-part 402 onto the substrate 1 overlaps with the orthographic projection of the sub-electrode rows 24 onto the substrate 1.

[0111] In the array substrate provided in this application embodiment, the first signal line no longer extends only between two sub-electrode columns, the first sub-section is located in the region between two adjacent sub-electrode columns, and the second sub-section bends and extends relative to the first sub-section to the region between the sub-electrode rows.

[0112] In some embodiments, such as Figure 6 As shown, the two first sub-parts 401 connected to the second sub-part 402 are located between different sub-electrode columns 25.

[0113] In some embodiments, such as Figure 6 As shown, the two first sub-parts 401 connected by the second sub-part 402 are spaced apart by a sub-electrode column 25.

[0114] In some embodiments, such as Figure 6 As shown, in the same first signal line 4, the orthographic projection of the second sub-part 402 onto the substrate 1 overlaps with the orthographic projection of the same sub-electrode array 24 onto the substrate 1. This avoids the distance between different first sub-parts being too large, thus preventing any impact on the uniformity of the touch signal.

[0115] Alternatively, in some embodiments, the two first sub-sub ...

[0116] In some embodiments, such as Figure 7 As shown, in the region where the connecting portion 6 is electrically connected to the second sub-portion 402 and the connecting electrode 202, the orthographic projection of the first via 301 on the substrate 1 is located on the side of the orthographic projection of the connecting electrode 202 on the substrate 1 that is far away from the first sub-portion 401 that is electrically connected to the second sub-portion 402.

[0117] In the array substrate provided in this application embodiment, when the first sub-part and the second sub-part are bent, and the first via is located on the side of the first sub-part that is electrically connected to the second sub-part, the projection of the connecting electrode on the substrate is away from the first sub-part. Thus, within the second via, the connecting electrode is only covered on one side. Figure 7The positions of arrows C1, C2, and C3 in the diagram do not have connecting electrodes, allowing the alignment film to diffuse uniformly. This arrangement increases the area of ​​uniform diffusion of the alignment film outside the connecting electrodes, which is beneficial for improving the diffusion uniformity of the alignment film.

[0118] In some embodiments, the connecting portion can be electrically connected to either end of the second sub-part in the direction of its extension. It should be noted that... Figure 7 An example is given by describing the electrical connection between the connecting part 6 and one end of the right side of the second sub-part 402. Alternatively, as... Figure 8 As shown, the connecting part 6 can also be electrically connected to one end of the left side of the second sub-part 402.

[0119] In some embodiments, such as Figure 9 As shown, when the second sub-part 402 bends relative to the first sub-part 401 to the region between the sub-electrode rows 24, as Figure 9 , Figure 10 As shown, the first electrode 2 can also be located below the first signal line 4. Even if the first signal line 4 is thick, the first signal line 4 will only have one-sided coverage within the second via 501. Figure 9 The positions of arrows C1, C2, and C3, where no first signal line is present, allow the alignment film to diffuse uniformly. This arrangement increases the area of ​​uniform diffusion of the alignment film outside the first signal line, thus improving the diffusion uniformity of the alignment film. Figure 10 For along Figure 9 Cross-sectional view of BB'.

[0120] Based on the same inventive concept, embodiments of this application also provide a display panel, such as... Figure 11 As shown, the display panel includes: an array substrate 19 provided in this application embodiment, a counter substrate 20 disposed opposite to the array substrate 19, and a liquid crystal layer 21 located between the array substrate 19 and the counter substrate 20.

[0121] Based on the same inventive concept, embodiments of this application also provide a display device, such as... Figure 12 As shown, it includes the display panel 22 provided in the embodiments of this application.

[0122] In some embodiments, such as Figure 12 As shown, the display device also includes: a backlight module 23; the display panel 22 is located on the light-emitting side of the backlight module 23.

[0123] The display device provided in this application embodiment includes any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, and navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this application. Implementation of this display device can refer to the embodiments of the display panel and array substrate described above; repeated details will not be elaborated upon.

[0124] In summary, the array substrate, display panel, and display device provided in this application have the first signal line and the first electrode located on different layers, which can improve the aperture ratio of the array substrate and is beneficial for improving the pixel density and resolution of the array substrate. Furthermore, since the first electrode is located on the side of the first signal line away from the substrate, its thickness is smaller. Compared to the case where the film layers are in opposite positions, the depth of the vias in the connection area can be reduced, i.e., the film layer step difference in the via area of ​​the array substrate can be reduced. Subsequent coating of the alignment layer can improve the diffusion uniformity of the alignment layer. When the array substrate is applied to a display panel, it can improve display uniformity, product yield, and quality.

[0125] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0126] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An array substrate, characterized in that, The array substrate includes: a substrate, a plurality of first signal lines located on one side of the substrate, a first insulating layer located on the side of the plurality of first signal lines away from the substrate, a first electrode located on the side of the first insulating layer away from the plurality of first signal lines, a second insulating layer located on the side of the first electrode away from the first insulating layer, and a plurality of connecting portions located on the side of the second insulating layer away from the first electrode. The first insulating layer includes a plurality of first vias that penetrate its thickness; The second insulating layer includes a plurality of second vias penetrating its thickness; the orthographic projection of the second vias onto the substrate covers the orthographic projection of the first vias onto the substrate, and the orthographic projection of the first electrode onto the substrate overlaps with the orthographic projection of the second vias onto the substrate. The orthographic projection of the connecting portion on the substrate overlaps with the orthographic projection of the second via on the substrate; the connecting portion is electrically connected to the first electrode through the second via, and the connecting portion is electrically connected to the first signal line through the second via and the first via.

2. The array substrate according to claim 1, characterized in that, The first electrode includes: Multiple sub-electrodes are arranged in an array along a first direction and a second direction; the first direction intersects the second direction, and the first direction intersects the extension direction of the first signal line; the orthographic projection of the first signal line on the substrate and the orthographic projection of the sub-electrodes on the substrate do not overlap, and the orthographic projection of the first signal line on the substrate overlaps with the orthographic projection of the region between two adjacent sub-electrodes in the first direction on the substrate. Multiple connecting electrodes; adjacent sub-electrodes are electrically connected through the connecting sub-electrodes; the orthographic projection of the first via on the substrate does not overlap with the orthographic projection of the connecting electrode on the substrate, a portion of the orthographic projection of the second via on the substrate falls within the orthographic projection of the connecting electrode on the substrate, and the connecting portion is electrically connected to the connecting electrode through the second via.

3. The array substrate according to claim 2, characterized in that, The first signal line includes a plurality of first sub-sections and a plurality of second sub-sections; the first sub-sections and the second sub-sections are arranged alternately in the extending direction of the first signal line; The first via, the second via, the connecting electrode, and the connecting portion overlap in their orthographic projections on the substrate with the orthographic projection of the second sub-part on the substrate. The connecting electrode is electrically connected to the second sub-part through the second via, the first via, and the second sub-part.

4. The array substrate according to claim 3, characterized in that, The plurality of sub-electrodes are divided into: a plurality of sub-electrode columns arranged along the first direction and a plurality of sub-electrode rows arranged along the second direction; The region between two adjacent sub-electrode columns in the orthographic projection of the first signal line onto the substrate is within the orthographic projection of the substrate. The first sub-part and the second sub-part are arranged alternately in the second direction. The intersection region of the second sub-part in the orthographic projection of the substrate with the region between two adjacent sub-electrode columns and the region between two adjacent sub-electrode rows overlaps in the orthographic projection of the substrate.

5. The array substrate according to claim 4, characterized in that, The orthographic projections of the first via and the second via on the substrate fall within the orthographic projection of the second sub-part on the substrate, and the orthographic projections of the connecting part and the connecting electrode on the substrate overlap with the orthographic projection of the second sub-part on the substrate.

6. The array substrate according to claim 5, characterized in that, The plurality of connecting electrodes includes: a plurality of first connecting electrodes and a plurality of second connecting electrodes; The first connecting electrode and the second connecting electrode are both electrically connected to two sub-electrodes that are adjacent in the first direction. The orthographic projection of each second sub-part on the substrate overlaps with the orthographic projections of one first connecting electrode and one second connecting electrode on the substrate. The orthographic projection of the first via on the substrate does not overlap with the orthographic projections of the first connecting electrode and the second connecting electrode on the substrate, and the orthographic projection of the first via on the substrate falls within the orthographic projection of the substrate of a region between the first connecting electrode and the second connecting electrode corresponding to a second sub-part. The orthographic projection of the second via on the substrate and the orthographic projection of the second connecting electrode on the substrate do not overlap. The orthographic projections of the second via and the connecting electrode on the substrate overlap with the orthographic projection of the first connecting electrode on the substrate. The connecting electrode is electrically connected to the first connecting electrode through the second via.

7. The array substrate according to any one of claims 4 to 6, characterized in that, In the first direction, the width of the first sub-part is smaller than the width of the second sub-part.

8. The array substrate according to claim 3, characterized in that, The plurality of sub-electrodes are divided into: a plurality of sub-electrode columns arranged along the first direction and a plurality of sub-electrode rows arranged along the second direction; The first sub-part's orthographic projection on the substrate falls within the region between two adjacent sub-electrode rows in the orthographic projection of the substrate. The second sub-part's orthographic projection on the substrate overlaps with the region between two adjacent sub-electrode rows in the orthographic projection of the substrate. Furthermore, the second sub-part's orthographic projection on the substrate overlaps with the sub-electrode rows in the orthographic projection of the substrate.

9. The array substrate according to claim 8, characterized in that, In the region where the connecting portion is electrically connected to the second sub-part and the connecting electrode, the orthographic projection of the first via on the substrate is located on the side of the orthographic projection of the connecting electrode on the substrate away from the first sub-part electrically connected to the second sub-part.

10. The array substrate according to claim 9, characterized in that, In the same first signal line, the orthographic projection of the second sub-part on the substrate overlaps with the orthographic projection of the same sub-electrode column on the substrate.

11. The array substrate according to any one of claims 1 to 6, 8 to 10, characterized in that, The array substrate further includes: multiple thin-film transistors and multiple pixel electrodes; The thin-film transistor is located between the first signal line and the substrate. The pixel electrode is located on the side of the first electrode away from the substrate, and the connecting portion is disposed in the same layer as the pixel electrode.

12. The array substrate according to any one of claims 1 to 6, 8 to 10, characterized in that, The array substrate also includes multiple scan lines and multiple data lines arranged in a cross pattern; The orthographic projection of the first signal line onto the substrate and the orthographic projection of the data line onto the substrate both overlap; The number of the first signal lines is less than the number of the data lines.

13. The array substrate according to claim 12, characterized in that, The orthographic projection of the second via on the substrate overlaps with the orthographic projection of the scan line on the substrate and the orthographic projection of the data line on the substrate.

14. A display panel, characterized in that, The display panel includes: an array substrate according to any one of claims 1 to 13, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate.

15. A display device, characterized in that, Includes the display panel according to claim 14.

Images