Array substrate, display panel and display device

Abstract

The application discloses an array substrate, a display panel and a display device. The array substrate comprises a substrate layer, a signal line, a first insulating layer, a transfer line, a second insulating layer, a sleeve hole structure, a bridging layer and a GOA circuit. The signal line extends along a first direction, the transfer line extends along a second direction, the sleeve hole structure comprises an outer hole, a first sub-hole and a second sub-hole, the outer hole extends from the top of the second insulating layer to the substrate layer, the first sub-hole and the second sub-hole are arranged at intervals and communicate with the bottom of the outer hole, the bottom of the first sub-hole exposes part of the surface of the signal line, and the bottom of the second sub-hole exposes part of the surface of the transfer line. In the second direction, the spacing between at least one of the edge of the outer hole, the edge of the first sub-hole and the edge of the second sub-hole and the starting end of the transfer line is greater than or equal to 2 μm, and the starting end is the end of the transfer line away from the display area. The transfer line is electrically connected to the signal line through the bridging layer. The GOA circuit is electrically connected to the transfer line.

Description

Technical Field

[0001] This application belongs to the field of display technology, and in particular relates to an array substrate, a display panel, and a display device. Background Technology

[0002] The Pressure Cooker Test (PCT) evaluates the airtightness of the display panel in a high-temperature, high-pressure, and high-humidity environment, thereby preventing moisture from entering the display panel into the casing under extreme conditions.

[0003] GOA stands for Gate Driven on Array, a technology that integrates gate drivers on an array substrate to achieve progressive scan driving functionality in display panels. The GOA circuitry is located in the non-display area of ​​the display panel and is electrically connected to the signal lines via adapter cables. In related technologies, during PCT testing, moisture may enter the cell along the adapter cables, causing the display panel's PCT performance to fail to meet standards.

[0004] It should be noted that the information in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This application provides an array substrate, a display panel, and a display device that can at least partially block moisture and delay the time it takes for moisture to enter the box, thereby helping to improve the PCT performance of the display panel.

[0006] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0007] A first aspect of this application provides an array substrate, comprising: a display area and a non-display area disposed on at least one side of the display area, the array substrate comprising:

[0008] Substrate layer;

[0009] A signal line is disposed on one side of the substrate, located in the non-display area, and extends along a first direction;

[0010] A first insulating layer covers the signal line;

[0011] The adapter cable is disposed on the side of the first insulating layer away from the substrate layer, located in the non-display area, and extends along a second direction, which intersects with the first direction;

[0012] A second insulating layer covers the adapter cable;

[0013] A via structure is provided, comprising an outer hole, a first sub-hole, and a second sub-hole. The outer hole extends from the top of the second insulating layer toward the substrate layer. The first sub-hole and the second sub-hole are spaced apart and communicate with the bottom of the outer hole. The bottom of the first sub-hole exposes a portion of the surface of the signal line, and the bottom of the second sub-hole exposes a portion of the surface of the adapter cable.

[0014] In the second direction, the distance between at least one of the edge of the outer hole, the edge of the first sub-hole, and the edge of the second sub-hole and the starting end of the adapter cable is greater than or equal to 2 μm, and the starting end is the end of the adapter cable away from the display area.

[0015] A bridging layer covers the outer hole, the first sub-hole, and the second sub-hole, and the adapter cable is electrically connected to the signal line through the bridging layer;

[0016] The GOA circuit is disposed on one side of the substrate layer, between the signal line and the display area, and is electrically connected to the adapter cable.

[0017] Optionally, the second insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer stacked sequentially. The first sub-insulating layer includes a first blocking portion, the second sub-insulating layer includes a second blocking portion, and the third sub-insulating layer includes a third blocking portion. The first blocking portion, the second blocking portion and the third blocking portion are stacked sequentially, and the third blocking portion covers the side of the first blocking portion.

[0018] There are multiple external holes, and the multiple external holes include:

[0019] A first external aperture extends from the top of the third sub-insulating layer toward the substrate layer, and the first sub-aperture communicates with the bottom of the first external aperture;

[0020] The second outer aperture extends from the top of the third sub-insulating layer toward the substrate layer, and the second sub-aperture communicates with the bottom of the second outer aperture;

[0021] In the second direction, a first blocking portion and a third blocking portion covering the side of the first blocking portion are provided between the starting end of the adapter cable and the first sub-hole.

[0022] Optionally, the second insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer stacked sequentially, wherein the third sub-insulating layer includes a fourth blocking portion;

[0023] There is one outer hole, and the first sub-hole and the second sub-hole are connected to the bottom of the outer hole;

[0024] In the second direction, the fourth blocking part is provided between the starting end of the adapter cable and the first sub-hole.

[0025] Optionally, the first sub-insulating layer and the third sub-insulating layer are inorganic insulating layers, and the second sub-insulating layer is an organic insulating layer.

[0026] Optionally, in the second direction, the starting end is located between the first sub-hole and the second sub-hole, the edge of the first sub-hole near the display area has a first distance from the starting end, the edge of the second sub-hole away from the display area has a second distance from the starting end, the edge of the outer hole away from the display area has a third distance from the edge of the first sub-hole away from the display area, and the edge of the outer hole near the display area has a fourth distance from the edge of the second sub-hole near the display area.

[0027] Wherein, at least one of the first spacing, the second spacing, the third spacing, and the fourth spacing is greater than or equal to 2 μm.

[0028] Optionally, at least one of the first spacing, the second spacing, the third spacing, and the fourth spacing is greater than or equal to 2.5 μm.

[0029] Optionally, at least one of the following must be satisfied:

[0030] The ratio between the third spacing and the first spacing is in the range of 0.6-0.9;

[0031] The ratio between the fourth spacing and the second spacing is in the range of 0.6-0.9;

[0032] The ratio between the sum of the first spacing and the third spacing and the sum of the second spacing and the fourth spacing is in the range of 0.6-0.9.

[0033] Optionally, the ratio between the fourth spacing and the second spacing is in the range of 0.5-1.0.

[0034] Optionally, at least one of the following must be satisfied:

[0035] In the second direction, the width of the first sub-hole ranges from 3μm to 6μm;

[0036] In the second direction, the width of the second sub-hole ranges from 3μm to 6μm;

[0037] In the second direction, the width of the outer hole ranges from 5μm to 20μm.

[0038] Optionally, the sidewall inclination angle of the outer hole is smaller than that of the sidewall of the first sub-hole, and / or the sidewall inclination angle of the outer hole is smaller than that of the sidewall of the second sub-hole.

[0039] Optionally, it also includes:

[0040] A first metal layer is disposed between the substrate layer and the first insulating layer, and the signal line is located in the first metal layer;

[0041] A second metal layer is disposed between the first insulating layer and the second insulating layer, and the adapter wire is located in the second metal layer;

[0042] In a direction perpendicular to the substrate layer, the depth of the first sub-hole is greater than the depth of the second sub-hole.

[0043] Optionally, the signal line includes a clock signal line.

[0044] Optionally, it also includes:

[0045] An adapter hole extends from the top of the second insulating layer toward the substrate layer and exposes a portion of the surface of the adapter cable, which is electrically connected to the GOA circuit through the adapter hole.

[0046] A second aspect of this application provides a display panel, comprising: an array substrate as described in any of the first aspects, a color filter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the color filter substrate.

[0047] A third aspect of this application provides a display device, including an array substrate as described in any of the first aspects, or a display panel as described in the second aspect.

[0048] The array substrate of this application embodiment includes: a display area and a non-display area disposed on at least one side of the display area. The array substrate includes: a substrate layer, signal lines, a first insulating layer, a second insulating layer, a via structure, a bridging layer, and a GOA circuit. The signal lines are disposed on one side of the substrate layer, located in the non-display area, and extend along a first direction. The first insulating layer covers the signal lines. A transition line is disposed on the side of the first insulating layer away from the substrate layer, located in the non-display area, and extends along a second direction, which intersects the first direction. The second insulating layer covers the transition line. The via structure includes an outer hole, a first sub-hole, and a second sub-hole. The outer hole extends from the top of the second insulating layer toward the substrate layer. The first and second sub-holes are spaced apart and communicate with the bottom of the outer hole. The bottom of the first sub-hole exposes a portion of the surface of the signal line, and the bottom of the second sub-hole exposes a portion of the surface of the transition line. In the second direction, at least one of the edges of the outer hole, the first sub-hole, and the second sub-hole is spaced apart from the starting end of the transition line, with the starting end being the end of the transition line away from the display area. The bridging layer covers the outer via, the first sub-via, and the second sub-via. The adapter cable is electrically connected to the signal line through the bridging layer. The GOA circuit is located on one side of the substrate layer, between the signal line and the display area, and is electrically connected to the adapter cable.

[0049] Therefore, this application found through research that the starting end of the adapter cable is a weak point for moisture intrusion. The distance between at least one of the edges of the outer hole, the first sub-hole, and the second sub-hole and the starting end of the adapter cable is set to be greater than or equal to 2μm. This distance can delay the time for moisture to intrude into the box along the extension direction of the adapter cable to a certain extent, which will help improve the PCT performance of the display panel.

[0050] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0051] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0052] Figure 1 A schematic diagram showing the connection relationship between the clock signal line and the GOA circuit is shown.

[0053] Figure 2 A schematic diagram of the planar layout of the array substrate according to an embodiment of this application is shown;

[0054] Figure 3A first partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown;

[0055] Figure 4 It shows Figure 3 A top view of the sleeve structure in the middle;

[0056] Figure 5 A second partial cross-sectional schematic diagram of the array substrate according to an embodiment of this application is shown;

[0057] Figure 6 A third partial cross-sectional schematic diagram of the array substrate according to an embodiment of this application is shown;

[0058] Figure 7 It shows Figure 6 A top view of the sleeve structure in the middle;

[0059] Figure 8 It shows Figure 3 Enlarged view of the area within the dashed box;

[0060] Figure 9 A fourth partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown;

[0061] Figure 10 A fifth partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown;

[0062] Figure 11 A sixth partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown;

[0063] Figure 12 A seventh partial cross-sectional view of the array substrate according to an embodiment of this application is shown.

[0064] Figure 13 This illustration shows an eighth partial cross-sectional view of the array substrate according to an embodiment of this application.

[0065] Figure 14 A ninth partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown;

[0066] Figure 15 A schematic diagram of the structure of the display panel according to an embodiment of this application is shown;

[0067] Figure 16 A structural block diagram of a display device according to an embodiment of this application is shown.

[0068] 100 - Array substrate; 101 - Display area; 102 - Non-display area; 1 - Substrate layer; 2 - Signal line; 21 - Clock signal line; 3 - First insulating layer; 4 - Adapter line; 41 - Start end; 5 - Second insulating layer; 51 - First sub-insulating layer; 52 - Second sub-insulating layer; 53 - Third sub-insulating layer; 51A - First blocking part; 52A - Second blocking part; 53A - Third blocking part; 53B - Fourth blocking part; 6 - Sleeve structure; 61 - Outer hole; 61A - First outer hole; 61B - Second outer hole; 62 - First sub-hole; 63 - Second sub-hole; 7 - Transition layer; 8 - GOA circuit; 9 - Gate Epipolar lines; X – First direction; Y – Second direction; Z – Direction perpendicular to the substrate layer; H1 – Depth of the first sub-via; H2 – Depth of the second sub-via; D1 – First pitch; D2 – Second pitch; D3 – Third pitch; D4 – Fourth pitch; α – Sidewall corner of the outer hole; β2 – Sidewall angle of the first sub-via; β2 – Sidewall angle of the second sub-via; 10 – Adapter hole; 200 – Display panel; 21 – Color filter substrate; 22 – Liquid crystal layer; 23 – Sealing adhesive; 201 – First alignment film; 202 – Second alignment film; 203 – Cover layer; 204 – Light shielding layer; 205 – Color filter layer; 300 – Display device. Detailed Implementation

[0069] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0070] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0071] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0072] It should also be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such uses of these terms can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described.

[0073] As used herein, “about,” “approximately,” “close to,” or “basically” includes the value stated and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0074] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0075] The scale of the figures in this application can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this application are only schematic diagrams of the structure, and the embodiments of this application are not limited to the shapes or values ​​shown in the figures.

[0076] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0077] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0078] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0079] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0080] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0081] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0082] The Pressure Cooker Test (PCT) evaluates the airtightness of the display panel in a high-temperature, high-pressure, and high-humidity environment, thereby preventing moisture from entering the display panel into the casing under extreme conditions.

[0083] In the development of display panels, compared to improvements in product display performance, research and improvement of PCT performance have lagged behind. This is mainly due to the complex film structure of display panels and the lack of clear methods to characterize the interface and traces of moisture intrusion. Early PCT testing required display panels to meet a 24-hour testing standard (i.e., under high temperature, high pressure, and high humidity conditions, moisture should not penetrate the display panel's casing within 24 hours). In recent years, as some display panels have failed to meet this standard, testing standards have been gradually lowered, and some display panels have even failed to meet the 12-hour testing standard.

[0084] Taking LCD (Liquid Crystal Display) as an example, it is generally believed that the PCT performance of LCD display panels is mainly related to the material of the sealant, the alignment film, and the PVX (passivation layer) film. However, with the processes for these film layers becoming increasingly stable and universal, the films themselves are essentially solidified, and the differences in the films or materials used in different LCD display panels are almost negligible. Therefore, if an LCD display panel still fails to meet the PCT test standards, the problem may not be caused by the aforementioned film layers or materials.

[0085] Further research by the inventors revealed that, according to Fick's law in diffusion theory—a law describing the relationship between mass transfer flux and concentration gradient during molecular diffusion when mass transfer occurs without macroscopic mixing—the diffusion flux (J) is proportional to the concentration gradient at that cross-section per unit time through a unit cross-sectional area perpendicular to the diffusion direction. The simplified mathematical expression is as follows: J = akx -1 Where 'a' represents the material diffusion coefficient, 'k' represents the proportionality constant, and 'x' represents the water vapor diffusion distance. From the above mathematical expression, it can be seen that as the water vapor diffusion distance increases, its diffusion rate and concentration decrease in an inverse exponential manner. Therefore, it can be inferred that if there are differences in the PCT performance of existing display panels, it indicates that water vapor does not penetrate from the sealant, alignment film, and PVX film itself as commonly believed. It is possible that physical gaps exist between the film layers, leading to increased water vapor diffusion, which in turn causes the display panel's PCT performance to fail to meet the test standards.

[0086] Currently, the PCT performance of Oxide display panels generally meets the 24-hour testing standard, and some Oxide display panels can even reach 36 or 48 hours in the extreme PCT test. However, for a-Si (amorphous silicon) display panels, the PCT performance of some a-Si display panels is still poor, only reaching a maximum of 12 hours.

[0087] Regarding the performance differences of different display panels in PCT testing, the inventors analyzed the reasons as follows: First, the PCT performance difference between Oxide display panels and a-Si display panels is mainly due to the difference in the structure of their PVX1 (first passivation layer) film. The PVX1 film in a-Si display panels is thinner (PVX1 covers the adapter lines; when PVX1 is thinner, physical gaps are more likely to occur between it and the adapter lines). Second, the PCT performance difference between display panels with and without a GIMask (gate insulating layer mask) is mainly due to the structural difference in the via structure (used to connect signal lines and adapter lines). Display panels without a GIMask require a separately fabricated via structure. Third, even display panels using a-Si without a GIMask may exhibit PCT performance differences, mainly due to structural or performance differences in the adapter lines within each display panel (e.g., differences in the structure of the adapter lines themselves or differences in the coverage of the adapter lines by PVX1).

[0088] The above analysis shows that factors such as the via structure of the signal lines and adapters, and the coverage of the PVX1 film on the adapters (adapter morphology, PVX1 material or thickness), all affect the PCT performance of the display panel. Currently, research has found that display panels using a-Si without GIMask generally have poor PCT performance. Therefore, the embodiments of this application primarily aim to improve the PCT performance of the aforementioned types of display panels.

[0089] As mentioned above, the components involved in the failure of the display panel's PCT performance to meet the test standards include signal lines, adapter cables, and GOA circuits. The relevant principles of the GOA circuit will be introduced below.

[0090] In traditional active matrix displays, the row scan signal is implemented by an external integrated circuit (G-COF). However, using a GOA (Gate-of-Area) circuit for driving the row scan, with only a few control signals provided by the external circuit, allows for the fabrication of the row scan drive circuit using the same process technology as thin-film transistors (TFTs), achieving progressive scan driving. Therefore, using a GOA driver saves on integrated circuits related to scan driving, reduces the manufacturing cost of the display panel, and facilitates narrow bezel designs.

[0091] As can be seen from the driving principle of the display panel, the row scanning driving circuit is actually equivalent to a shift register. Under the control signal of the external circuit, it generates a shift pulse signal. This shift pulse signal drives the pixels of the current row to turn on the TFT (thin-film transistor), and also serves as the start signal for the next row (the first row is triggered by the frame start signal STV) and the end signal for the previous row. The control signals of the external circuit mainly include the frame start signal (STV), the clock signals CLK and CLKB with opposite phases, the DC voltage signal VSS (typically -8V) that drives the thin-film transistor to turn off, and possibly the DC voltage signal VDD.

[0092] The GOA circuit can include multiple circuits, which are cascaded together and use a voltage-phase related clock signal to control CLK and CLKB, the input signal, the gate off signal (VSS), the reset signal, and the output signal of the current row. The output signal of the current row (e.g., Output N) not only drives the pixels in this row but also serves as both the reset signal for the previous row and the input signal for the next row. In the entire GOA driving circuit, the input signal of the first row's GOA circuit is the frame start signal STV, and the first row does not output a reset signal. The last row's GOA circuit connects to a redundant row of GOA circuits to reset the current row. Thus, under the action of external control signals, the GOA units in different rows influence each other, generating shift pulse signals, and scanning is performed line by line sequentially.

[0093] Figure 1 A schematic diagram showing the connection relationship between the clock signal line and the GOA circuit is provided.

[0094] like Figure 1As shown, taking clock signal line 21 as an example, GOA circuit 8 can scan the gate lines 9 in the product line by line through the alternating switching of multi-phase clock signals (e.g., clock signal pairs CLK and CLKB). These clock signals need to be transmitted to different GOA circuits 8 in a specific order. Clock signal line 21 and GOA circuit 8 are located in the non-display area 102 of the display panel. Considering factors such as layout space, the fabrication process of clock signal line 21 and GOA circuit 8, clock signal line 21 may not be directly connected to GOA circuit 8. Therefore, to achieve electrical connection between clock signal line 21 and GOA circuit 8, adapter cable 4 can be provided to connect clock signal line 21 and GOA circuit 8 respectively. In some cases, adapter cable 4 and clock signal line 21 are on different layers. To achieve electrical connection between adapter cable 4 and clock signal line 21, a via structure 6 can be provided to connect clock signal line 21 and adapter cable 4. In addition, the GOA circuit 8 is connected to the gate line 9 disposed in the display area 101, and the gate drive signal is output by the GOA circuit 8 to scan each pixel unit in the pixel array of the display area 101 line by line.

[0095] Based on the analysis of the reasons why the PCT performance of the display panel could not meet the test standards, and the introduction of the relevant principles of the GOA circuit 8, the relevant structure and principle of the array substrate 100 included in the display panel of this application embodiment are described below with reference to the specific accompanying drawings.

[0096] This application provides an array substrate 100 that can at least delay the time it takes for moisture to enter the cell, which helps to improve the PCT performance of the display panel.

[0097] Figure 2 A schematic diagram of the planar layout of the array substrate according to an embodiment of this application is shown; Figure 3 A first partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown; Figure 4 It shows Figure 3 A top view of the sleeve structure.

[0098] In some embodiments, the array substrate 100 includes: a display area 101 (AA area) and a non-display area 102 disposed on at least one side of the display area 101. The non-display area 102 is located in the border area and can be divided into an upper border, a lower border, a left border, and a right border. The lower border is provided with a DP (Data Pad side), including a glass electrode edge for bonding external electronic devices (e.g., driver ICs and flexible circuit boards). The upper border is provided with a DPO (Data Pad Opposite side), including a Gate metal trace area. The left border and / or the right border are provided with a GOA (Gate on Array), which is provided with a Gate metal layer, an SD (Source / Drain metal layer), an Active layer, and a passivation layer.

[0099] In some embodiments, the array substrate 100 includes: a substrate layer 1, a signal line 2, a first insulating layer 3, a connecting line 4, a second insulating layer 5, a via structure 6, a bridging layer 7, and a GOA circuit 8. The signal line 2 is disposed on one side of the substrate layer 1, located in the non-display area 102, and extends along a first direction X. The first insulating layer 3 covers the signal line 2. The connecting line 4 is disposed on the side of the first insulating layer 3 away from the substrate layer 1, located in the non-display area 102, and extends along a second direction Y, which intersects the first direction X. The second insulating layer 5 covers the connecting line 4. The via structure 6 includes an outer hole 61, a first sub-hole 62, and a second sub-hole 63. The outer hole 61 extends from the top of the second insulating layer 5 toward the substrate layer 1. The first sub-hole 62 and the second sub-hole 63 are spaced apart and communicate with the bottom of the outer hole 61. The bottom of the first sub-hole 62 exposes a portion of the surface of the signal line 2, and the bottom of the second sub-hole 63 exposes a portion of the surface of the connecting line 4. In the second direction Y, the distance between at least one of the edges of the outer hole 61, the first sub-hole 62, and the second sub-hole 63 and the starting end 41 of the adapter cable 4 is greater than or equal to 2 μm, and the starting end 41 is the end of the adapter cable 4 furthest from the display area 101. A bridging layer 7 covers the outer hole 61, the first sub-hole 62, and the second sub-hole 63, and the adapter cable 4 is electrically connected to the signal line 2 through the bridging layer 7. A GOA circuit 8 is disposed on one side of the substrate layer 1, located between the signal line 2 and the display area 101, and is electrically connected to the adapter cable 4.

[0100] The mechanism by which moisture enters the cell of the display panel is explained below, taking the array substrate 100 of the LCD display panel as an example:

[0101] During PCT testing, moisture first diffuses along the physical gaps between the interfaces in the second insulating layer 5 (which may contain multiple organic and / or inorganic insulating layers) to the via structure 6. This moisture accumulates in the outer via 61, the first sub-via 62, and the second sub-via 63, and then penetrates into the starting end 41 of the adapter cable 4 through the first sub-via 62 and / or the second sub-via 63. Due to etching damage to the buffer (located on the side of the adapter cable 4 closest to the substrate layer 1, not shown), the side of the adapter cable 4 closest to the substrate layer 1 is exposed, forming a moisture intrusion end. Alternatively, the multilayer structure of the adapter cable 4 itself may have defects such as a tip (a sharp edge formed by uneven etching of the adapter cable 4) or an undercut (the lower layer of the adapter cable 4 is over-etched, causing the upper layer to be suspended). The aforementioned defects are prone to occur at the starting end 41 of the adapter cable 4, meaning that the starting end 41 is a weak point for moisture intrusion. In addition, there is a physical gap between the adapter cable 4 and the second insulating layer 5. Moisture can intrude into the starting end 41 of the adapter cable 4 along the first sub-hole 62 and / or the second sub-hole 63, and then into the box along the physical gap between the adapter cable 4 and the second insulating layer 5. That is, the intrusion path of the moisture after reaching the starting end 41 of the adapter cable 4 is basically consistent with the extension direction of the adapter cable 4. When extending towards the display area 101 along the physical gap between the adapter cable 4 and the second insulating layer 5, it may continue to intrude through the adapter hole 10 (used to electrically connect the adapter cable 4 and the GOA circuit 8) near the display area 101. Taking the LCD display panel as an example, moisture may also intrude into the liquid crystal layer of the LCD through the adapter hole 10, thereby causing the PCT performance of the display panel to fail to meet the test standards.

[0102] Analysis of the mechanism of moisture intrusion into the casing reveals that the starting end 41 of the adapter cable 4 is a significant weak point, making it susceptible to moisture intrusion. Based on the moisture intrusion path, moisture primarily enters the starting end 41 of the adapter cable 4 through the first sub-hole 62 and / or the second sub-hole 63 of the sleeve structure 6. Therefore, this embodiment of the application increases the distance between at least one of the edges of the outer hole 61 of the sleeve structure 6, the first sub-hole 62, and the second sub-hole 63, and the starting end 41 of the adapter cable 4 to a value greater than or equal to 2 μm. This distance increases the distance moisture travels from the sleeve structure 6 to the starting end 41 of the adapter cable 4, thereby delaying the time it takes for moisture to intrude into the starting end 41 of the adapter cable 4, and ultimately ensuring that the PCT performance of the display panel meets the test standards.

[0103] In some embodiments, there may be multiple signal lines 2, such as 4, 6, or 8, which are spaced apart and extend along the first direction X. The signal lines 2 and the adapter cable 4 may have a one-to-one, one-to-many, or many-to-one relationship; for example, one signal line 2 may be electrically connected to one adapter cable 4.

[0104] For example, signal line 2 includes clock signal line 21, which is electrically connected to adapter line 4 via via structure 6 and bridging layer 7, and then electrically connected to GOA circuit 8. Clock signal line 21 is used to provide timing control signals to GOA circuit 8. By periodically switching between high and low levels, it drives the transistors inside GOA circuit 8 to turn on or off step by step, thereby generating scanning signals and activating the pixel units in the display panel line by line.

[0105] Of course, it is understood that the signal line 2 in the embodiments of this application may also be a frame start signal line 2STV, a power signal line 2, and a reset signal line 2Reset, etc., and is not limited here.

[0106] In some embodiments, there may be multiple adapter cables 4, such as 4, 6, or 8 cables, which are spaced apart and extend along the second direction Y. For example, one adapter cable 4 is connected to one signal line 2.

[0107] Figure 5 A second partial cross-sectional schematic diagram of the array substrate according to an embodiment of this application is shown.

[0108] In some embodiments, it also includes:

[0109] The adapter hole 10 extends from the top of the second insulating layer 5 toward the substrate layer 1 and exposes a portion of the surface of the adapter cable 4, which is electrically connected to the GOA circuit 8 through the adapter hole 10.

[0110] The GOA circuit 8 is equipped with a clock signal input terminal, and the adapter cable 4 can be electrically connected to the clock signal input terminal of the GOA circuit 8 through the adapter hole 10. It is understood that the adapter hole 10 should be filled with a conductive bridging layer 7.

[0111] In some embodiments, the array substrate 100 further includes: a first metal layer and a second metal layer (not shown). The first metal layer is disposed between the substrate layer 1 and the first insulating layer 3, and the signal line 2 is located in the first metal layer; the second metal layer is disposed between the first insulating layer 3 and the second insulating layer 5, and the adapter line 4 is located in the second metal layer; in a direction perpendicular to the substrate layer 1, the depth H1 of the first sub-hole is greater than the depth H2 of the second sub-hole.

[0112] In other words, in this embodiment of the application, signal line 2 can be fabricated in the same layer as the non-display area 102 when the first metal layer is fabricated. Similarly, adapter line 4 can be fabricated in the same layer as the non-display area 102 when the second metal layer is fabricated, thereby improving process efficiency. The first metal layer can be a gate metal layer, and the second metal layer can be a source / drain metal layer; or, the first metal layer can be a source / drain metal layer, and the second metal layer can be a gate metal layer; no limitation is made here. Taking the first metal layer as a gate metal layer and the second metal layer as a source / drain metal layer as an example, when fabricating the gate metal layer in the display area 101, signal line 2 can be fabricated in the non-display area 102; when fabricating the source / drain metal layer in the display area 101, adapter line 4 can be fabricated in the non-display area 102.

[0113] It is understandable that, since signal line 2 is located in the first metal layer and adapter line 4 is located in the second metal layer, and the first metal layer is closer to the substrate layer 1 than the second metal layer, in order to expose the surface of signal line 2, the depth H1 of the first sub-hole is etched to be greater than the depth H2 of the second sub-hole in the direction Z perpendicular to the substrate layer. The first sub-hole 62 extends from the bottom of the outer hole 61 to the surface of signal line 2, and the second sub-hole 63 extends from the bottom of the outer hole 61 to the surface of adapter line 4.

[0114] In some embodiments, when the first metal layer is a gate metal layer, the first insulating layer 3 may be a gate insulating layer. In the non-display area 102, the gate insulating layer covers the signal line 2 and provides protection for the signal line 2.

[0115] In some embodiments, the second insulating layer 5 includes a first sub-insulating layer 51, a second sub-insulating layer 52, and a third sub-insulating layer 53 that are stacked sequentially.

[0116] It is understood that the first sub-insulating layer 51 and the third sub-insulating layer 53 can be organic insulating layers, and the second sub-insulating layer 52 can be an inorganic insulating layer. For example, the first sub-insulating layer 51 can be PVX1 (first passivation layer), the third sub-insulating layer 53 can be PVX2 (second passivation layer), and the second sub-insulating layer 52 can be ORG (Organic Gate Insulator). The first and second passivation layers are used to protect the internal circuitry from environmental factors (such as moisture, ion contamination, and mechanical damage), while providing electrical insulation and surface smoothing. They can be fabricated using materials such as silicon nitride and silicon oxide. The organic gate insulating layer is an organic dielectric layer used in transistors (such as OTFTs, organic thin-film transistors) or special device structures, serving as an insulating medium between the gate and the channel. It can be fabricated using materials such as polymethyl methacrylate, polystyrene, polyvinylidene fluoride (PVDF), and their copolymers.

[0117] For a-Si display panels, the thickness of PVX1 is usually thinner in the direction Z perpendicular to the substrate layer. This makes it easy for a physical gap to form at the interface between PVX1 and the adapter 4 when PVX1 covers the adapter 4, thus providing a physical channel for moisture intrusion.

[0118] Figure 6 A third partial cross-sectional schematic diagram of the array substrate according to an embodiment of this application is shown; Figure 7 It shows Figure 6 A top view of the sleeve structure.

[0119] In some embodiments, the first sub-insulating layer 51 includes a first blocking portion 51A, the second sub-insulating layer 52 includes a second blocking portion 52A, and the third sub-insulating layer 53 includes a third blocking portion 53A. The first blocking portion 51A, the second blocking portion 52A, and the third blocking portion 53A are stacked sequentially, and the third blocking portion 53A covers the side surface of the first blocking portion 51A. There are multiple external holes 61, including a first external hole 61A and a second external hole 61B. The first external hole 61A extends from the top of the third sub-insulating layer 53 toward the substrate layer 1, and the first sub-hole 62 communicates with the bottom of the first external hole 61A. The second external hole 61B extends from the top of the third sub-insulating layer 53 toward the substrate layer 1, and the second sub-hole 63 communicates with the bottom of the second external hole 61B. In the second direction Y, the first blocking portion 51A and the third blocking portion 53A covering the side surface of the first blocking portion 51A are provided between the starting end 41 of the adapter cable 4 and the first sub-hole 62.

[0120] It is understandable that by setting multiple outer holes 61, i.e., one outer hole 61 is connected to one sub-hole, multiple sub-insulating layers can be used to block the first outer hole 61A and the second outer hole 61B, and the first sub-hole 62 and the second sub-hole 63. That is, the first blocking part 51A, the second blocking part 52A and the third blocking part 53A are used for blocking. This increases the coverage of the second insulating layer 5 on the starting end 41 of the adapter cable 4, eliminates the erosion of the second insulating layer 5 on the second sub-hole 63 in the lateral (second direction Y) direction by the etching of the first sub-hole 62, and eliminates the possibility of moisture entering the starting end 41 of the adapter cable 4 from the first sub-hole 62 by the blocking of the first blocking part 51A to the third blocking part 53A. This increases the lateral (second direction Y) coverage protection of the starting end 41 (weak point) of the adapter cable 4 by the second insulating layer 5, delays the time for moisture to enter the starting end 41 of the adapter cable 4, and subsequently helps to improve the PCT performance of the display panel.

[0121] In some embodiments, the second insulating layer 5 includes a first sub-insulating layer 51, a second sub-insulating layer 52, and a third sub-insulating layer 53 stacked sequentially, wherein the third sub-insulating layer 53 includes a fourth blocking portion 53B. There is one external hole 61, and the first sub-hole 62 and the second sub-hole 63 communicate with the bottom of the external hole 61; in the second direction Y, the fourth blocking portion 53B is provided between the starting end 41 of the adapter cable 4 and the first sub-hole 62.

[0122] It is understandable that when an outer hole 61 is connected to the first sub-hole 62 and the second sub-hole 63 respectively, due to etching, a portion of the top area of ​​the adapter cable 4 is only covered by the third sub-insulating layer 53, while the remaining portion is sequentially covered by the first sub-insulating layer 51, the second sub-insulating layer 52, and the third sub-insulating layer 53. Based on this, the third sub-insulating layer 53 has poor lateral coverage of the starting end 41 of the adapter cable 4, so moisture may penetrate from the first sub-hole 62 to the starting end 41 of the adapter cable 4, causing poor PCT performance of the display panel. Therefore, this application increases the distance between at least one of the edges of the outer hole 61 of the sleeve structure 6, the first sub-hole 62, and the second sub-hole 63 and the starting end 41 of the adapter cable 4 to a value greater than or equal to 2 μm. This distance increases the distance moisture travels from the sleeve structure 6 to the starting end 41 of the adapter cable 4, thereby delaying the time it takes for moisture to penetrate to the starting end 41 of the adapter cable 4, and thus ensuring that the PCT performance of the display panel meets the test standards.

[0123] Figure 8 It shows Figure 3 A magnified view of the area within the dashed box.

[0124] In some embodiments, in the second direction Y, the starting end 41 is located between the first sub-hole 62 and the second sub-hole 63. The edge of the first sub-hole 62 near the display area 101 has a first distance D1 with the starting end 41. The edge of the second sub-hole 63 away from the display area 101 has a second distance D2 with the starting end 41. The edge of the outer hole 61 away from the display area 101 has a third distance D3 with the edge of the first sub-hole 62 away from the display area 101. The edge of the outer hole 61 near the display area 101 has a fourth distance D4 with the edge of the second sub-hole 63 near the display area 101. At least one of the first distance D1, the second distance D2, the third distance D3, and the fourth distance D4 is greater than or equal to 2 μm (micrometers), for example, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, etc.

[0125] It is understandable that, within the allowable wiring space of the non-display area 102 of the array substrate 100, one or more of the first spacing D1, the second spacing D2, the third spacing D3, and the fourth spacing D4 can be set as large as possible, so that at least one of the edges of the outer hole 61, the first sub-hole 62, and the second sub-hole 63 maintains a large distance from the starting end 41 of the adapter cable 4. This can increase the path of moisture intrusion to a certain extent, delay the time for moisture to intrude into the starting end 41 of the adapter cable 4, and thus delay the time for moisture to intrude into the cell, which helps to improve the PCT performance of the display panel.

[0126] It should be noted that if an external hole 61 is connected to the first sub-hole 62 and the second sub-hole 63, in the second direction Y, the external hole 61 has two edges: the edge of the external hole 61 furthest from the display area 101 (referred to as the first edge) and the edge of the external hole 61 closest to the display area 101 (the second edge). The first edge refers to the edge where the projection of the external hole 61 onto the substrate 1 is furthest from the display area 101, and the second edge refers to the edge where the projection of the external hole 61 onto the substrate 1 is closest to the display area 101. If the first external hole 61A is connected to the first sub-hole 62, and the second external hole 61B is connected to the second sub-hole 63, in the second direction Y, the first edge can refer to the edge where the projection of the first external hole 61A onto the substrate 1 is furthest from the display area 101, and the second edge can refer to the edge where the projection of the second outer shell onto the substrate 1 is closest to the display area 101.

[0127] It should be noted that the edge of the first sub-hole 62 closest to the display area 101 (referred to as the third edge) can refer to the edge of the first sub-hole 62 projected onto the substrate layer 1 that is closest to the display area 101, and the edge of the second sub-hole 63 closest to the display area 101 (referred to as the fourth edge) can refer to the edge of the second sub-hole 63 projected onto the substrate layer 1 that is closest to the display area 101.

[0128] Figure 9 A fourth partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown. (Comparison) Figure 9 and Figure 3 It can be seen that, Figure 9 The first spacing D1 in the middle is increased.

[0129] It is understandable that if the first pitch D1 is increased as much as possible, the transmission path of water vapor in the first sub-hole 62 to the starting end 41 of the adapter cable 4 can be increased, the time for water vapor to enter the starting end 41 of the adapter cable 4 can be delayed, and the time for water vapor to enter the box can be delayed, thereby improving the PCT performance of the display panel.

[0130] Figure 10A fifth partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown. (Comparison) Figure 10 and Figure 3 It can be seen that, Figure 10 The second spacing D2 in the middle increases.

[0131] Figure 11 A sixth partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown. (Comparison) Figure 11 and Figure 5 It can be seen that, Figure 11 The second spacing D2 in the middle increases.

[0132] If the second spacing D2 is increased as much as possible, the transmission path of water vapor in the second sub-hole 63 to the starting end 41 of the adapter cable 4 can be increased, the time for water vapor to enter the starting end 41 of the adapter cable 4 can be delayed, and the time for water vapor to enter the box can be delayed, thereby improving the PCT performance of the display panel.

[0133] Figure 12 A seventh partial cross-sectional view of the array substrate according to an embodiment of this application is shown. (Comparison) Figure 12 and Figure 3 It can be seen that, Figure 12 The third spacing D3 in the middle is increased.

[0134] If the third pitch D3 is increased as much as possible, that is, the width of the outer hole 61 in the second direction Y is increased, the time for water vapor entering the outer hole 61 to accumulate to the first sub-hole 62 and / or the second sub-hole 63 can be delayed, thereby delaying the time for water vapor to enter the starting end 41 of the adapter cable 4, and further delaying the time for water vapor to enter the box, thus improving the PCT performance of the display panel PCT.

[0135] Figure 13 This diagram shows an eighth partial cross-sectional view of the array substrate according to an embodiment of this application. (Comparison) Figure 13 and Figure 3 It can be seen that, Figure 13 The fourth spacing D4 in the middle is increased.

[0136] Figure 14 A ninth partial cross-sectional structural schematic diagram of the array substrate according to an embodiment of this application is shown. (Comparison) Figure 14 and Figure 5 It can be seen that, Figure 14 The fourth space, D4, increases.

[0137] If the fourth pitch D4 is increased as much as possible, that is, the width of the outer hole 61 in the second direction Y is increased, the time for water vapor entering the outer hole 61 to accumulate to the first sub-hole 62 and / or the second sub-hole 63 can be delayed, thereby delaying the time for water vapor to invade the starting end 41 of the adapter cable 4, and thus delaying the time for water vapor to invade the box, thereby improving the PCT performance of the display panel PCT.

[0138] It is understandable that, since the second sub-hole 63 is located on the surface of the adapter cable 4, the moisture in the second sub-hole 63 is more likely to penetrate into the starting end 41 of the adapter cable 4. Therefore, when the total width of the first spacing D1 and the second spacing D2 is fixed, it can be ensured that the second spacing D2 is greater than or equal to 2μm.

[0139] It should be noted that the third pitch D3 refers to the distance between the edge of the outer hole 61 away from the display area 101 and the edge of the first sub-hole 62 away from the display area 101. In other words, the distance between the edge of the outer hole 61 away from the display area 101 and the starting end 41 of the adapter cable 4 is actually equal to the sum of the third pitch D3, the width of the first sub-hole 62, and the first pitch D1. Therefore, when the third pitch D3 is greater than or equal to 2 μm, the distance between the edge of the outer hole 61 away from the display area 101 and the starting end 41 of the adapter cable 4 is also greater than or equal to 2 μm. μm; In addition, the fourth pitch D4 refers to the distance between the edge of the outer hole 61 near the display area 101 and the edge of the second sub-hole 63 near the display area 101. That is, the distance between the edge of the outer hole 61 near the display area 101 and the starting end 41 of the adapter cable 4 is actually equal to the sum of the fourth pitch D4, the width of the second sub-hole 63 and the second pitch D2. Therefore, when the fourth pitch D4 is greater than or equal to 2μm, the distance between the edge of the outer hole 61 near the display area 101 and the starting end 41 of the adapter cable 4 is also greater than or equal to 2μm.

[0140] It is understandable that during the fabrication process, when forming the via structure 6 based on photolithography, precise control of the mask design can ensure that at least one of the aforementioned first spacing D1 to fourth spacing D4 is greater than or equal to 2 μm. For example, the first spacing D1 can be set to 3 μm to ensure sufficient moisture-retaining spacing between the starting end 41 of the adapter line 4 and the first sub-via 62; the second spacing D2 can be set to 2.5 μm to ensure sufficient moisture-retaining spacing between the starting end 41 of the adapter line 4 and the second sub-via 63; and the third spacing D3 and the fourth spacing D4 can be set to 3 μm to ensure sufficient moisture-retaining spacing between the edge of the outer aperture 61 and the starting end 41 of the adapter line 4.

[0141] In some embodiments, at least one of the first spacing D1, the second spacing D2, the third spacing D3, and the fourth spacing D4 is greater than or equal to 2.5 μm, for example: 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm, etc.

[0142] It is understandable that increasing the spacing from the first to the fourth distance D4 can be achieved by increasing the width of the outer aperture 61 in the second direction Y, or by decreasing the width of the first sub-aperture 62 or the second sub-aperture 63, or by adjusting the etching positions of the first and second sub-apertures 62 and 63. Due to limitations in wiring space, the width of the outer aperture 61 is restricted; due to limitations in exposure process, the reduction in the width of the first and second sub-apertures 62 and 63 is also restricted; and due to the positional relationship between the outer aperture 61 and the first and second sub-apertures 62 and 63, the etching positions of the first and second sub-apertures 62 and 63 are also restricted. It is understandable that, based on the above limitations, further increasing at least one of the first to the fourth distance D4 can, to a certain extent, delay moisture intrusion.

[0143] In some embodiments, at least one of the following conditions is met: the ratio between the third spacing D3 and the first spacing D1 is in the range of 0.6-0.9, for example, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, etc.; the ratio between the fourth spacing D4 and the second spacing D2 is in the range of 0.6-0.9, for example, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, etc.; the ratio between the sum of the first spacing D1 and the third spacing D3 and the sum of the second spacing D2 and the fourth spacing D4 is in the range of 0.6-0.9, for example, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, etc.

[0144] It is understood that in the embodiments of this application, the limitations of each spacing and the limitations of each ratio range are ensured as synchronously as possible. When the spacing cannot be ensured at the same time, the limitation of the ratio range can be ensured first.

[0145] In some embodiments, the ratio between the fourth spacing D4 and the second spacing D2 is in the range of 0.5-1.0, for example, 0.5, 0.6, 0.7, 0.8, 0.9 or 1.0.

[0146] Understandably, when the first external hole 61A is connected to the first sub-hole 62, and the second external hole 61B is connected to the second sub-hole 63, the use of the first blocking part 51A, the second blocking part 52A, and the third blocking part 53A increases the coverage of the second insulating layer 5 over the starting end 41 of the adapter cable 4. This eliminates the erosion of the second insulating layer 5 by the etching of the first sub-hole 62 on the lateral (second direction Y) coverage of the second insulating layer 5 over the second sub-hole 63, and eliminates the possibility of moisture intruding into the starting end 41 of the adapter cable 4 from the first sub-hole 62. This increases the lateral (second direction Y) coverage protection of the starting end 41 (weak point) of the adapter cable 4 by the second insulating layer 5. In this case, the first spacing D1 and the third spacing D3 are substantially increased. In this case, it is advisable to set the second spacing D2 and / or the fourth spacing D4 to be greater than or equal to 2μm, or greater than or equal to 2.5μm. Furthermore, considering that the independence of the first sub-hole 62 and the second sub-hole 63 can delay the intrusion of water vapor to a certain extent, the requirement for the ratio range of the fourth spacing D4 and the second spacing D2 can be relaxed, that is, set to 0.5-1.0.

[0147] In some embodiments, at least one of the following conditions is met: in the second direction Y, the width of the first sub-hole 62 is in the range of 3μm-6μm, for example, 3μm, 4μm, 5μm or 6μm; in the second direction Y, the width of the second sub-hole 63 is in the range of 3μm-6μm, for example, 3μm, 4μm, 5μm or 6μm; in the second direction Y, the width of the outer hole 61 is in the range of 5μm-20μm, for example, 5μm, 6μm, 8μm, 10μm, 12μm, 15μm, 16μm, 18μm or 20μm.

[0148] Understandably, when there is only one external hole 61, the width of the external hole 61 can be set to be relatively large, for example, 15μm-20μm; when there are multiple external holes 61, the width of each external hole 61 can be set to be relatively small, for example, 5μm-10μm.

[0149] See also Figure 3 In some embodiments, the sidewall inclination angle of the outer hole 61 is smaller than that of the sidewall of the first sub-hole 62, and / or the sidewall inclination angle of the outer hole 61 is smaller than that of the sidewall inclination angle β2 of the second sub-hole.

[0150] It should be noted that the sidewall inclination angle of the outer hole 61 refers to the angle between the outer hole 61 and the plane where the substrate layer 1 is located, the sidewall inclination angle β2 of the first sub-hole refers to the angle between the sidewall of the first sub-hole 62 and the plane where the substrate layer 1 is located, and the sidewall inclination angle β2 of the second sub-hole refers to the angle between the sidewall of the second sub-hole 63 and the plane where the substrate layer 1 is located.

[0151] It is understandable that when the sidewall inclination angle of the outer hole 61 is smaller than that of the first sub-hole 62, and / or the sidewall inclination angle of the outer hole 61 is smaller than the sidewall inclination angle β2 of the second sub-hole, for example, when the sidewall inclination angle of the outer hole 61 is less than 90 degrees, and the sidewall inclination angle β2 of the first sub-hole 62 and the second sub-hole is approximately equal to 90 degrees, water vapor will find it more difficult to accumulate from the outer hole 61 to the first sub-hole 62 and / or the second sub-hole 63, thus delaying water vapor intrusion to a certain extent.

[0152] In some embodiments, the array substrate 100 further includes:

[0153] A pixel electrode layer (not shown) is disposed on the side of the second insulating layer 5 away from the substrate and located in the display area 101.

[0154] A common electrode layer (not shown) is disposed on the side of the second insulating layer 5 away from the substrate, and is located in the display area 101;

[0155] The bridging layer 7 is located in the pixel electrode layer or the common electrode layer.

[0156] It is understood that the pixel electrode layer and the common electrode layer can be fabricated using ITO (Indium Tin Oxide), with one of the pixel electrode layer and the common electrode layer referred to as 1ITO and the other as 2ITO.

[0157] Taking LCD display panels as an example, 1ITO and 2ITO refer to indium tin oxide (ITO) conductive layers with different layers or functions. 1ITO can refer to the first ITO conductive layer in the LCD panel closest to the glass substrate, located on one side of the liquid crystal layer, and is used as an electrode layer to form an electric field to drive the liquid crystal molecules to deflect. 2ITO refers to the ITO conductive layer on the other side of the LCD panel, opposite to 1ITO, with liquid crystal material sandwiched in between, and is used as a common electrode to form the electric field driving the liquid crystal together with 1ITO.

[0158] The bridging layer 7 located in the pixel electrode layer or the common electrode layer can be fabricated in the same layer as the pixel electrode layer or the common electrode layer, for example, in the same layer as 2ITO. That is, when 2ITO is fabricated in the display area 101, the same material can be used to fabricate the bridging layer 7 in the non-display area 102, and the bridging layer 7 is used to realize the electrical connection between the signal line 2 and the adapter cable 4, and / or to realize the adapter cable.

[0159] Figure 15 A schematic diagram of the structure of a display panel according to an embodiment of this application is shown.

[0160] A second aspect of this application provides a display panel 200, comprising: an array substrate as described in any of the first aspects, a color filter substrate 21 disposed opposite to the array substrate, and a liquid crystal layer 22 located between the array substrate and the color filter substrate 21.

[0161] The display area of ​​the display panel 200 is provided with a pixel circuit for controlling the display of pixel units. The pixel circuit includes multiple gate lines and multiple data lines arranged in a cross pattern, and also includes thin-film transistors connected between the gate lines and data lines. The thin-film transistors are arranged corresponding to the pixel units. Thin-film transistors located in the same row of pixel units are connected to the same gate line, and thin-film transistors located in the same column of pixel units are connected to the same data line.

[0162] The non-display area of ​​the display panel 200 includes a gate driving circuit and a data driving circuit. The gate driving circuit is connected to the gate lines of the display area, and the data driving circuit is connected to the data lines of the display area. In use, the gate driving circuit outputs a gate driving signal to scan each pixel unit in the pixel array line by line; the data driving circuit converts the display data to be displayed into a data voltage signal. While scanning each row of gate lines, the data driving circuit writes the data voltage signal corresponding to the pixel in that row to the pixel circuit of that row through each data line to light up the pixel unit in that row, thereby realizing the display of the entire display area.

[0163] In some embodiments, the display panel 200 further includes:

[0164] The first alignment film 201 is disposed on the side of the second insulating layer away from the substrate.

[0165] The sealing adhesive 23 is disposed between the first alignment film 201 and the color filter substrate 21, and is located in the non-display area;

[0166] The color filter substrate 21 further includes: a color filter layer 205, a light-shielding layer 204 (e.g., a black matrix), a cover layer 203, and a second alignment film 202, which are stacked in sequence, and the sealing adhesive 23 is disposed between the first alignment film 201 and the second alignment film 202.

[0167] Figure 16 A structural block diagram of a display device according to an embodiment of this application is shown.

[0168] A third aspect of this application provides a display device 300, including an array substrate 100 as described in any of the first aspects, or a display panel 200 as described in the second aspect.

[0169] For example, the display device 300 can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0170] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0171] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An array substrate, characterized in that, include: The array substrate includes a display area and a non-display area disposed on at least one side of the display area, and the array substrate comprises: Substrate layer; A signal line is disposed on one side of the substrate, located in the non-display area, and extends along a first direction; A first insulating layer covers the signal line; The adapter cable is disposed on the side of the first insulating layer away from the substrate layer, located in the non-display area, and extends along a second direction, which intersects with the first direction; A second insulating layer covers the adapter cable; A via structure is provided, comprising an outer hole, a first sub-hole, and a second sub-hole. The outer hole extends from the top of the second insulating layer toward the substrate layer. The first sub-hole and the second sub-hole are spaced apart and communicate with the bottom of the outer hole. The bottom of the first sub-hole exposes a portion of the surface of the signal line, and the bottom of the second sub-hole exposes a portion of the surface of the adapter cable. In the second direction, the distance between at least one of the edge of the outer hole, the edge of the first sub-hole, and the edge of the second sub-hole and the starting end of the adapter cable is greater than or equal to 2 μm, and the starting end is the end of the adapter cable away from the display area. A bridging layer covers the outer hole, the first sub-hole, and the second sub-hole, and the adapter cable is electrically connected to the signal line through the bridging layer; The GOA circuit is disposed on one side of the substrate layer, between the signal line and the display area, and is electrically connected to the adapter cable.

2. The array substrate according to claim 1, characterized in that, The second insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer stacked in sequence. The first sub-insulating layer includes a first blocking portion, the second sub-insulating layer includes a second blocking portion, and the third sub-insulating layer includes a third blocking portion. The first blocking portion, the second blocking portion and the third blocking portion are stacked in sequence, and the third blocking portion covers the side of the first blocking portion. There are multiple external holes, and the multiple external holes include: A first external aperture extends from the top of the third sub-insulating layer toward the substrate layer, and the first sub-aperture communicates with the bottom of the first external aperture; The second outer aperture extends from the top of the third sub-insulating layer toward the substrate layer, and the second sub-aperture communicates with the bottom of the second outer aperture; In the second direction, a first blocking portion and a third blocking portion covering the side of the first blocking portion are provided between the starting end of the adapter cable and the first sub-hole.

3. The array substrate according to claim 1, characterized in that, The second insulating layer includes a first sub-insulating layer, a second sub-insulating layer and a third sub-insulating layer stacked sequentially, wherein the third sub-insulating layer includes a fourth blocking portion; There is one outer hole, and the first sub-hole and the second sub-hole are connected to the bottom of the outer hole; In the second direction, the fourth blocking part is provided between the starting end of the adapter cable and the first sub-hole.

4. The array substrate according to claim 2 or 3, characterized in that, The first and third sub-insulating layers are inorganic insulating layers, while the second sub-insulating layer is an organic insulating layer.

5. The array substrate according to any one of claims 1-3, characterized in that, In the second direction, the starting end is located between the first sub-hole and the second sub-hole, the edge of the first sub-hole near the display area has a first distance from the starting end, the edge of the second sub-hole away from the display area has a second distance from the starting end, the edge of the outer hole away from the display area has a third distance from the edge of the first sub-hole away from the display area, and the edge of the outer hole near the display area has a fourth distance from the edge of the second sub-hole near the display area. Wherein, at least one of the first spacing, the second spacing, the third spacing, and the fourth spacing is greater than or equal to 2 μm.

6. The array substrate according to claim 5, characterized in that, At least one of the first spacing, the second spacing, the third spacing, and the fourth spacing is greater than or equal to 2.5 μm.

7. The array substrate according to claim 5, characterized in that, At least one of the following must be met: The ratio between the third spacing and the first spacing is in the range of 0.6-0.9; The ratio between the fourth spacing and the second spacing is in the range of 0.6-0.9; The ratio between the sum of the first spacing and the third spacing and the sum of the second spacing and the fourth spacing is in the range of 0.6-0.

9.

8. The array substrate according to claim 5, characterized in that, The ratio between the fourth spacing and the second spacing is in the range of 0.5-1.

0.

9. The array substrate according to any one of claims 1-3, 6-8, characterized in that, At least one of the following must be met: In the second direction, the width of the first sub-hole ranges from 3μm to 6μm; In the second direction, the width of the second sub-hole ranges from 3μm to 6μm; In the second direction, the width of the outer hole ranges from 5μm to 20μm.

10. The array substrate according to claim 1, characterized in that, The inclination angle of the outer hole's sidewall is smaller than that of the first sub-hole's sidewall, and / or the inclination angle of the outer hole's sidewall is smaller than that of the second sub-hole's sidewall.

11. The array substrate according to claim 1, characterized in that, Also includes: A first metal layer is disposed between the substrate layer and the first insulating layer, and the signal line is located in the first metal layer; A second metal layer is disposed between the first insulating layer and the second insulating layer, and the adapter wire is located in the second metal layer; In a direction perpendicular to the substrate layer, the depth of the first sub-hole is greater than the depth of the second sub-hole.

12. The array substrate according to claim 1, characterized in that, The signal lines include clock signal lines.

13. The array substrate according to claim 1, characterized in that, Also includes: An adapter hole extends from the top of the second insulating layer toward the substrate layer and exposes a portion of the surface of the adapter cable, which is electrically connected to the GOA circuit through the adapter hole.

14. A display panel, characterized in that, include: The array substrate as described in any one of claims 1-13, the color filter substrate disposed opposite to the array substrate, and the liquid crystal layer located between the array substrate and the color filter substrate.

15. A display device, characterized in that, It includes the array substrate as described in any one of claims 1-13, or the display panel as described in claim 14.

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