A high-precision IC carrier plate interlayer alignment compensation manufacturing method and system

Abstract

The application provides a high-precision IC carrier board interlayer alignment compensation manufacturing method and system, and belongs to the technical field of semiconductor packaging substrate manufacturing. The method comprises the following steps: manufacturing at least three alignment targets on an inner layer reference substrate and recording reference coordinates; measuring actual coordinates of each target on a current build-up layer; calculating a translation offset and a rotation offset angle according to the reference coordinates and the actual coordinates, combining historical offset compensation data, and calculating final compensation parameters through a weighted moving average algorithm; loading the compensation parameters to an LDI exposure device for exposure, development, electroplating, flash etching to form a finished product line; measuring a finished product line width, calculating a deviation from a target line width, updating a smoothing coefficient of the weighted moving average algorithm according to the deviation, and storing current layer data for next build-up layer calculation. The application can compensate for translation and rotation offsets at the same time, and uses line width deviation to adaptively adjust the compensation parameters, thereby improving the interlayer alignment accuracy and line width consistency of the high-layer IC carrier board.

Description

Technical Field

[0001] This application belongs to the field of semiconductor packaging substrate manufacturing technology, specifically relating to a high-precision IC substrate interlayer alignment compensation manufacturing method and system. Background Technology

[0002] IC packaging substrates, or IC carriers, serve as a crucial connection between chips and printed circuit boards. Their manufacturing precision directly impacts the signal transmission performance and packaging reliability of semiconductor devices. With the increasing demands for I / O density and signal rates from 5G communication, artificial intelligence, and high-performance computing chips, IC carriers are evolving towards ultra-fine circuitry with over 20 layers and linewidths and spacings down to 8μm. FCBGA, CSP, and SiP products all rely on SAP or mSAP processes to achieve large-scale production of high-density, fine-line circuitry.

[0003] In the manufacturing of high-layer IC substrates based on SAP / mSAP processes, interlayer alignment accuracy is a core issue determining product yield. Specifically, during multiple heating, pressing, cooling, and wet processing of multilayer substrates, the inner layer patterns undergo gradual and non-linear expansion and contraction deformation due to the inherent differences in the coefficients of thermal expansion between the core board, the add-on film, and the copper foil, as well as the cumulative process stress layer by layer. Existing technologies typically use fixed reference targets for alignment or measure a few target points before each layer exposure for overall translational compensation. However, this approach cannot effectively compensate for the continuously accumulating rotational offset and non-linear deformation as the number of layers increases, leading to short circuits or open circuit defects in 8μm-level fine lines due to alignment deviations. Furthermore, existing methods lack iterative optimization of interlayer compensation parameters, resulting in irregular fluctuations in alignment errors between consecutive layers within the same batch, which are difficult to correct through simple statistical process control.

[0004] Therefore, there is an urgent need for a method for interlayer alignment manufacturing of IC substrates that can simultaneously compensate for translational and rotational offsets and has interlayer adaptive optimization capabilities. Summary of the Invention

[0005] In a first aspect, embodiments of this application provide a method for manufacturing a high-precision IC substrate with interlayer alignment compensation, comprising the following steps: S1. Fabricate at least three targets for alignment on the inner reference substrate and record the reference coordinate position of each target in the reference coordinate system; S2. On the current add-in layer to be fabricated, the actual coordinate positions corresponding to each target on the inner layer reference substrate are obtained by optical measurement; S3. Based on the recorded reference coordinate position and the measured actual coordinate position, calculate the translation offset and rotation offset angle of the current layer addition, and then combine the stored historical layer addition offset compensation data to calculate the final compensation parameters of the current layer addition through the weighted moving average algorithm. S4. The final compensation parameters are loaded into the LDI exposure equipment to expose the current overlay. The circuit pattern is formed by development, and copper is electroplated to fill the developed circuit pattern area. The dry film is then removed, and the seed copper layer is removed by flash etching to form the finished circuit. S5. Measure the actual linewidth of the finished circuit after flash erosion, calculate the deviation between the actual linewidth and the target linewidth, update the smoothing coefficient of the weighted moving average algorithm according to the deviation value according to the preset feedback rule, and store the offset data and compensation parameters of the current layer addition for the calculation of the next layer addition.

[0006] Furthermore, the specific steps of step S1 are as follows: S11. Select the copper-clad laminate core board with completed surface treatment as the inner layer reference substrate; S12. At least three targets are made at a predetermined position on the inner reference substrate by laser drilling or etching, and the targets are marked in the shape of a cross or a circle. S13. Using a coordinate measuring machine or an LDI camera system, measure the reference coordinates of each target in the reference coordinate system, and record them as follows: ,in N is the number of targets. The reference coordinates are then stored in the database.

[0007] Furthermore, the specific steps of step S2 are as follows: S21. On the current add-on layer to be fabricated after the photoresist coating is completed, the camera system of the LDI equipment is used to locate the position corresponding to the target on the inner layer reference substrate; S22. Sequentially photograph the actual imaging position of each target on the current layer, obtain the measured value of the actual coordinates, and record it as... ; S23. After associating the measured values ​​of the actual coordinates with the identification information of the current layer, store them in the database.

[0008] Furthermore, the specific steps of step S3 are as follows: S31. Read the actual coordinate measurement values ​​of the current layer from the database. and the corresponding reference coordinates Calculate the measured translational offset of the current k-layer addition using the following formula. and : ; Where N is the number of targets, N≥3, and i is the target number, i=1,2,…,N; This represents the x-translation offset of the current k-layer addition. This represents the y-shift offset of the current k-layer addition; S32. Calculate the measured rotation offset angle of the current added layer using the following formula. : ; S33. Read the final compensation amount of the previous layer from the database, i.e., the k-1 layer. ,in, The x-coordinate compensation amount for the added layer k-1, The y-coordinate compensation amount for the added layer k-1, The rotation angle compensation amount is for layer k-1, with layer 1 as the reference layer, and the initial compensation amount for layer 1 is set to... ; S34. Using the weighted moving average algorithm, calculate the final compensation parameters for the current k-layer increment according to the following formula:

[0009]

[0010]

[0011] in, The x-coordinate compensation amount for the current k-layer addition. The compensation amount for the y-coordinate of the current k-layer addition. This is the rotation angle compensation amount for the current k-layer addition; This is the translation smoothing coefficient. This is the rotational smoothing coefficient; S35. The calculated result The final compensation parameter for the current k-incrementing layer is stored in the database.

[0012] Furthermore, in the weighted moving average algorithm of step S34, when the current layer number k≤3, the equally weighted arithmetic mean is used instead of the weighted moving average, that is, taking... This is to accelerate the convergence speed of the initial compensation parameters.

[0013] Furthermore, the specific steps of step S4 are as follows: S41. Final compensation parameters Loaded into the control system of the LDI exposure equipment; S42. The LDI exposure device performs translation and rotation transformations on the original CAM graphic data according to the compensation parameters to generate a compensated exposure graphic; S43. Expose the current uplayer photoresist using the compensated exposure pattern. After exposure, develop the photoresist to remove the unexposed areas and expose the circuit pattern to be electroplated. S44. Electroplating copper fills the exposed circuit pattern area after development according to preset electroplating parameters, so that the thickness of the electroplated copper layer reaches the target value; the electroplating parameters include current density and electroplating time; S45. Remove the remaining photoresist, and then use an alkaline or acidic etchant to flash-etch and remove the seed copper layer at the bottom to form the final finished circuit.

[0014] Furthermore, in step S45, prior to flash etching, the measured copper plating thickness distribution of the current layer is determined. and seed copper layer thickness Predicting the linewidth shrinkage after flash erosion Adjust the flashover time according to the following rules. :

[0015] in, The empirical etching coefficient is... This represents the average copper thickness after electroplating. like If the historical statistical value of the deviation from the target linewidth in step S5 exceeds the threshold, then the etching time is dynamically compensated before flash etching:

[0016] in, The etch time is compensated. For standard etching time, For etching rate, This is the average value of the linewidth deviation of the previous few layers.

[0017] Furthermore, the specific steps of step S5 are as follows: S51. Using an automated optical inspection device, select at least five measurement points on the finished circuit after flash etching, measure the actual line width at each point, and record the average value as follows: ; S52. Read the target line width from the database. Calculate the line width deviation using the following formula: ; S53. Based on the line width deviation Update the smoothing coefficient in the weighted moving average algorithm using the following formula. and :

[0018] in, , These are the translation smoothing coefficient and rotation smoothing coefficient used for the current layer, respectively. For translation feedback coefficients, For rotational feedback coefficients; S54. Adjust the measured offset of the current added layer. Final compensation parameters Line width deviation and the updated displacement smoothing coefficient Rotational smoothing coefficient Stored in the database as historical data for the next layer in step S3.

[0019] Furthermore, the following warpage prediction step is included before step S2: The overall warpage of the current add-on substrate was obtained using a 3D profilometer. ; The number of targets is dynamically determined based on the warp. :

[0020] in, This is for rounding down.

[0021] Secondly, embodiments of this application also provide a high-precision IC substrate interlayer alignment compensation manufacturing system, comprising: The reference establishment module is used to fabricate at least three targets for alignment on the inner reference substrate and record the reference coordinate position of each target in the reference coordinate system. The optical measurement module is used to obtain the actual coordinate positions of each target on the inner layer reference substrate through optical measurement on the current add-in layer to be fabricated. The compensation calculation module is used to calculate the translational offset and rotational offset angle of the current layer addition based on the recorded reference coordinate position and the measured actual coordinate position. Then, combined with the stored historical layer addition offset compensation data, the final compensation parameters of the current layer addition are calculated through a weighted moving average algorithm. The exposure and circuit forming module is used to load the final compensation parameters into the LDI exposure equipment, expose the current overlay, form the circuit pattern through development, electroplat copper fill the developed circuit pattern area, remove the dry film, remove the seed copper layer through flash etching, and form the finished circuit. The linewidth feedback and parameter update module is used to measure the actual linewidth of the finished line after flash erosion, calculate the deviation between the actual linewidth and the target linewidth, update the smoothing coefficient of the weighted moving average algorithm according to the deviation value according to the preset feedback rules, and store the offset data and compensation parameters of the current layer addition for the calculation of the next layer addition.

[0022] As can be seen from the above technical solutions, this application has the following advantages: The high-precision IC substrate interlayer alignment compensation manufacturing method and system provided in this application measures at least three targets and calculates the translational offset and rotational offset angle respectively. During exposure, the pattern is translated and rotated, which overcomes the shortcomings of traditional methods that can only compensate for translation but ignore rotation. This improves the interlayer alignment accuracy of IC substrates with a high layer count. By introducing a weighted moving average algorithm based on historical data and using finished product linewidth deviation feedback to update the smoothing coefficient in the algorithm in real time, the compensation parameters can learn and optimize as the number of layers increases, improving the consistency of the alignment between front and back layers in mass production. Attached Figure Description

[0023] To more clearly illustrate the technical solution of this application, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic flowchart of the high-precision IC substrate interlayer alignment compensation manufacturing method of the present invention.

[0025] Figure 2 This is a schematic diagram of the interlayer alignment compensation manufacturing system for the high-precision IC substrate of the present invention. Detailed Implementation

[0026] The various embodiments of this disclosure will be described more fully in the detailed steps of the manufacturing method for interlayer alignment compensation of high-precision IC substrates described below. This disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of this disclosure to the specific embodiments disclosed herein, but rather this disclosure should be understood to cover all adjustments, equivalents, and / or alternatives falling within the spirit and scope of the various embodiments of this disclosure.

[0027] For example, with the increasing demands for I / O density and signal rate from 5G, AI, and high-performance computing chips, IC substrates are evolving towards higher layer counts (20+ layers) and ultra-fine lines at the 8μm level. However, in SAP and mSAP processes, the nonlinear deformation and rotational offset caused by multilayer lamination and thermal cycling make traditional alignment techniques that only compensate for translational offsets insufficient to meet accuracy requirements, easily leading to short circuits or open circuits in the fine lines. Furthermore, existing methods lack the ability to iteratively optimize parameters based on historical data, resulting in fluctuations in interlayer alignment errors. Therefore, the industry urgently needs a high-precision interlayer alignment manufacturing solution that can simultaneously compensate for translational and rotational offsets and possess adaptive optimization capabilities.

[0028] To address the aforementioned issues, this embodiment provides a high-precision IC substrate interlayer alignment compensation manufacturing method that takes into account both translational and rotational deviation compensation, and combines linewidth feedback to adaptively adjust parameters, thereby improving interlayer alignment accuracy and linewidth consistency.

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Please see Figure 1 The diagram shows a flowchart of a high-precision IC carrier board interlayer alignment compensation manufacturing method in a specific embodiment. The method includes the following steps: S1. Fabricate at least three targets for alignment on the inner reference substrate and record the reference coordinate position of each target in the reference coordinate system; It should be noted that by setting the number of targets to no less than three, this step provides the minimum constraint for subsequent calculations of translation and rotation offsets, thus solving the problem that traditional single-target or double-target methods cannot solve for rotation angles. S2. On the current add-in layer to be fabricated, the actual coordinate positions corresponding to each target on the inner layer reference substrate are obtained by optical measurement; It should be noted that this step obtains the actual coordinates of the target on the current layer using optical means, which can capture the positional deviation of the current layer relative to the reference layer in a non-contact and high-precision manner. S3. Based on the recorded reference coordinate position and the measured actual coordinate position, calculate the translation offset and rotation offset angle of the current layer addition, and then combine the stored historical layer addition offset compensation data to calculate the final compensation parameters of the current layer addition through the weighted moving average algorithm. It should be noted that by combining the current measured translation and rotation offsets with historical compensation data, the algorithm calculates the final compensation parameters, which solves the problem that relying solely on the current measurement value is easily affected by random errors or that relying solely on historical data has a lag, and achieves the optimal estimation. S4. The final compensation parameters are loaded into the LDI exposure equipment to expose the current overlay. The circuit pattern is formed by development, and copper is electroplated to fill the developed circuit pattern area. The dry film is then removed, and the seed copper layer is removed by flash etching to form the finished circuit. It should be noted that this step loads the final compensation parameters, which include translation and rotation components, into the LDI exposure equipment. After performing translation and rotation transformations on the CAM graphic data, the exposure is performed, so that the exposed graphic is precisely matched with the actual deformed substrate, improving the alignment accuracy of the circuit pattern. Furthermore, after completing the copper plating and flash etching, the finished circuit is formed, and the compensation parameters are finally converted into the size and position accuracy of the actual circuit. S5. Measure the actual line width of the finished circuit after flash erosion, calculate the deviation between the actual line width and the target line width, update the smoothing coefficient of the weighted moving average algorithm according to the deviation value according to the preset feedback rule, and store the offset data and compensation parameters of the current layer addition for the calculation of the next layer addition. It should be noted that by measuring the actual linewidth of the finished circuit after flash etch and calculating the deviation from the target linewidth, the data originally used only for quality inspection is transformed into a feedback signal to drive process optimization. The smoothing coefficient of the weighted moving average algorithm is updated according to the linewidth deviation, so that the alignment compensation strategy of subsequent layers can be adaptively adjusted according to the actual situation of the finished linewidth, forming a closed-loop control and improving product consistency.

[0031] This embodiment addresses the complex deformation in multilayer lamination by introducing rotation offset angle compensation and iterative calculation of historical data. Combined with a closed-loop feedback mechanism based on linewidth deviation, it can adaptively adjust the algorithm smoothing coefficient, thereby improving the interlayer alignment accuracy and circuit pattern consistency of high-density IC substrates.

[0032] Furthermore, as a refinement and extension of the specific implementation of the above embodiments, in order to fully illustrate the specific implementation process in this embodiment, another high-precision IC substrate interlayer alignment compensation manufacturing method is provided, which includes the following steps: S1. Fabricate at least three targets for alignment on the inner reference substrate and record the reference coordinate position of each target in the reference coordinate system; The specific steps of step S1 are as follows: S11. Select a copper-clad laminate core board with completed surface treatment as the inner layer reference substrate; the surface treatment includes micro-etching and cleaning to enhance the target fabrication quality; S12. At least three targets are made at preset positions on the inner reference substrate by laser drilling or etching. The targets are cross-shaped or circular. The preset positions are usually selected near the four corners and center of the substrate to fully reflect the substrate deformation. Cross-shaped targets are convenient for sub-pixel level positioning, while circular targets are convenient for rapid identification. S13. Using a coordinate measuring machine or an LDI camera system, measure the reference coordinates of each target in the reference coordinate system, and record them as follows: ,in N is the number of targets. The reference coordinates are then stored in the database. In this step, the target is usually cross-shaped or circular to facilitate automatic identification and positioning by the optical system; the record of the reference coordinates serves as the absolute reference for all subsequent layer additions and does not change with the process, thus avoiding cumulative errors. S2. On the current add-in layer to be fabricated, the actual coordinate positions corresponding to each target on the inner layer reference substrate are obtained by optical measurement; The specific steps of step S2 are as follows: S21. On the current add-on layer to be fabricated after the photoresist coating is completed, the camera system of the LDI equipment is used to locate the position corresponding to the target on the inner layer reference substrate; during positioning, it is necessary to ensure that the optical parameters of the camera system (such as magnification and focal length) are consistent with those measured on the reference layer to avoid systematic errors; S22. Sequentially photograph the actual imaging position of each target on the current layer, obtain the measured value of the actual coordinates, and record it as... ; S23. After associating the measured values ​​of the actual coordinates with the identification information of the current layer, store them in the database; In actual measurement, the CCD camera system built into the LDI equipment is usually used to photograph each target in sequence. The measurement data is then stored in the database after being associated with the current layer addition marker for subsequent calculation. This measurement should be completed after the photoresist is applied and before exposure to accurately reflect the deformation state of the current layer. S3. Based on the recorded reference coordinate position and the measured actual coordinate position, calculate the translation offset and rotation offset angle of the current layer addition, and then combine the stored historical layer addition offset compensation data to calculate the final compensation parameters of the current layer addition through the weighted moving average algorithm. The specific steps of step S3 are as follows: S31. Read the actual coordinate measurement values ​​of the current layer from the database. and the corresponding reference coordinates Calculate the measured translational offset of the current k-layer addition using the following formula. and : ; Where N is the number of targets, N≥3, and i is the target number, i=1,2,…,N; This represents the x-translation offset of the current k-layer addition. This represents the y-translation offset of the current k-layer addition; the formula uses an equal-weighted arithmetic average, which is simple to calculate and fast, making it suitable for online real-time applications; S32. Calculate the measured rotation offset angle of the current added layer using the following formula. : ; It should be noted that the arctan function returns a value in radians, which is typically between -π / 2 and π / 2. This approximation is accurate enough for small angular offsets. If higher accuracy is required, the least squares method can be used instead of the arithmetic mean, but the arithmetic mean is used in this embodiment to reduce computational overhead. S33. Read the final compensation amount of the previous layer from the database, i.e., the k-1 layer. ,in, The x-coordinate compensation amount for the added layer k-1, The y-coordinate compensation amount for the added layer k-1, The rotation angle compensation amount is for layer k-1, with layer 1 as the reference layer, and the initial compensation amount for layer 1 is set to... ; S34. Using the weighted moving average algorithm, calculate the final compensation parameters for the current k-layer increment according to the following formula:

[0033]

[0034]

[0035] in, The x-coordinate compensation amount for the current k-layer addition. The compensation amount for the y-coordinate of the current k-layer addition. This is the rotation angle compensation amount for the current k-layer addition; This is the translation smoothing coefficient. This is the rotational smoothing coefficient, and its value range is... The initial value is preset to 0.5; and Independent settings allow translation and rotation to be smoothed separately according to their respective characteristics. For example, if the rotational offset is relatively stable but the translation fluctuates greatly, the settings can be reduced. ,improve ,vice versa; In the weighted moving average algorithm of step S34, when the current layer number k≤3, the equal-weighted arithmetic mean is used instead of the weighted moving average, that is, taking... This is to accelerate the convergence speed of the initial compensation parameters; In the initial stage (i.e. the first 3 layers), there is less historical data, and the effect of weighted moving average is not obvious. Using arithmetic average can respond to the actual offset more quickly, allowing the compensation parameters to enter a stable range rapidly. S35. The calculated result The final compensation parameters for the current k-incrementing layer are stored in the database. S4. The final compensation parameters are loaded into the LDI exposure equipment to expose the current overlay. The circuit pattern is formed by development, and copper is electroplated to fill the developed circuit pattern area. The dry film is then removed, and the seed copper layer is removed by flash etching to form the finished circuit. The specific steps of step S4 are as follows: S41. Final compensation parameters Loaded into the control system of the LDI exposure equipment; S42. The LDI exposure equipment performs a translation transformation (translation amount) on the original CAM graphic data according to the compensation parameters. , ) and rotation transformation (rotation angle) The process generates a compensated exposure pattern; the transformation sequence is translation followed by rotation to ensure mathematical correctness; the rotation transformation is based on the geometric center of the substrate to avoid edge distortion. S43. Expose the current uplayer photoresist using the compensated exposure pattern. After exposure, develop the photoresist to remove the unexposed areas and expose the circuit pattern to be electroplated. S44. After development, the exposed circuit pattern area is filled with copper by electroplating according to preset electroplating parameters to achieve the target copper layer thickness. The electroplating parameters include current density (e.g., 1.0-2.0 ASD) and electroplating time (e.g., 30-90 minutes). During the electroplating process, the copper thickness distribution is monitored periodically using an X-ray fluorescence thickness gauge or an eddy current thickness gauge to provide a data basis for subsequent flash erosion compensation. S45. Remove the remaining photoresist, and then use an alkaline or acidic etchant to flash-etch and remove the seed copper layer at the bottom to form the final finished circuit. It should be noted that the electroplating process typically uses DC electroplating, with the current density controlled at 1.0-2.0 ASD and the time at 30-90 minutes. The target copper thickness depends on the product design. The flash etching process uses alkaline or acidic etching solutions to precisely remove the base copper by controlling the etching time, thus forming the final linewidth. In step S45, prior to flash etching, the measured copper plating thickness distribution of the current layer is determined. and seed copper layer thickness Predicting the linewidth shrinkage after flash erosion Adjust the flashover time according to the following rules. :

[0036] in, The empirical etching coefficient is... This represents the average copper thickness after electroplating. Pre-calibration is achieved through process experiments, such as measuring the relationship between different copper thickness differences and corresponding linewidth shrinkage on a test board, and then fitting the linear coefficient; typical values ​​are approximately 0.8-1.2. like If the historical statistical value of the deviation from the target linewidth in step S5 exceeds the threshold, then the etching time is dynamically compensated before flash etching:

[0037] in, The etch time is compensated. For standard etching time, For etching rate, This is the average of the linewidth deviations of the previous few layers; the threshold is usually set to 0.5μm. Experiments were conducted to determine, for example, the relationship between etching time and the amount of copper removed from the substrate under standard conditions. S5. Measure the actual line width of the finished circuit after flash erosion, calculate the deviation between the actual line width and the target line width, update the smoothing coefficient of the weighted moving average algorithm according to the deviation value according to the preset feedback rule, and store the offset data and compensation parameters of the current layer addition for the calculation of the next layer addition. The specific steps of step S5 are as follows: S51. Using an automated optical inspection device, select at least five measurement points on the finished circuit after flash etching, measure the actual line width at each point, and record the average value as follows: The measurement points should cover the center, edges, and densely patterned areas of the substrate to ensure the representativeness of the sample. AOI equipment typically uses backlighting and sub-pixel edge detection algorithms, achieving a measurement accuracy of up to 0.1μm. S52. Read the target line width from the database. Calculate the line width deviation using the following formula: ; S53. Based on the line width deviation Update the smoothing coefficient in the weighted moving average algorithm using the following formula. and :

[0038] in, , These are the translation smoothing coefficient and rotation smoothing coefficient used for the current layer, respectively. For translation feedback coefficients, For rotational feedback coefficient, , The range of values ​​is ; If the calculation yields If the value is less than 0.2, set it to 0.2; if the value is greater than 0.8, set it to 0.8. Similarly; S54. Adjust the measured offset of the current added layer. Final compensation parameters Line width deviation and the updated displacement smoothing coefficient Rotational smoothing coefficient Stored in the database as historical data for the next layer in step S3; In this embodiment, the IC substrate adopts FCBGA, CSP, or SiP type, with more than 20 layers added, and the target linewidth of the finished circuit is... The range is: Target linewidth of finished circuit The scope covers the current mainstream high-end IC substrate requirements, including applications of AI chips, GPUs, and CPUs.

[0039] In some embodiments, unlike the embodiments described above, the following warpage prediction step is included before step S2: The overall warpage of the current add-on substrate was obtained using a 3D profilometer. Warpage is defined as the maximum deformation of a substrate in a free state, and is usually obtained by laser triangulation or structured light scanning. The number of targets is dynamically determined based on the warp. :

[0040] in, To round down; The greater the warpage, the more targets are used to ensure compensation accuracy; The meaning of this formula is: when the warpage... When the diameter is less than 0.1 mm, the minimum number of targets is 3. For every 0.1mm increase, the number of targets increases by 1, up to a maximum of 9; this improves measurement efficiency on high-precision production lines with small deformations, and ensures compensation quality on low-end production lines with large deformations or on special products.

[0041] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0042] like Figure 2As shown, the following are embodiments of the high-precision IC substrate interlayer alignment compensation manufacturing system provided in this disclosure. This system and the high-precision IC substrate interlayer alignment compensation manufacturing method of the above embodiments belong to the same inventive concept. For details not described in detail in the embodiments of the high-precision IC substrate interlayer alignment compensation manufacturing system, please refer to the embodiments of the high-precision IC substrate interlayer alignment compensation manufacturing method.

[0043] The system includes: The reference establishment module is used to fabricate at least three targets for alignment on the inner reference substrate and record the reference coordinate position of each target in the reference coordinate system. The optical measurement module is used to obtain the actual coordinate positions of each target on the inner layer reference substrate through optical measurement on the current add-in layer to be fabricated. The compensation calculation module is used to calculate the translational offset and rotational offset angle of the current layer addition based on the recorded reference coordinate position and the measured actual coordinate position. Then, combined with the stored historical layer addition offset compensation data, the final compensation parameters of the current layer addition are calculated through a weighted moving average algorithm. The exposure and circuit forming module is used to load the final compensation parameters into the LDI exposure equipment, expose the current overlay, form the circuit pattern through development, electroplat copper fill the developed circuit pattern area, remove the dry film, remove the seed copper layer through flash etching, and form the finished circuit. The linewidth feedback and parameter update module is used to measure the actual linewidth of the finished line after flash erosion, calculate the deviation between the actual linewidth and the target linewidth, update the smoothing coefficient of the weighted moving average algorithm according to the deviation value according to the preset feedback rules, and store the offset data and compensation parameters of the current layer addition for the calculation of the next layer addition.

[0044] This embodiment achieves simultaneous compensation for interlayer translation and rotation offset through the interactive collaboration of the reference establishment module, optical measurement module, compensation calculation module, exposure and circuit forming module, and linewidth feedback and parameter update module. By dynamically updating the compensation algorithm parameters through linewidth deviation feedback, adaptive optimization is achieved, thereby improving the alignment accuracy and circuit consistency of high-layer IC substrates.

[0045] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for manufacturing a high-precision IC substrate with interlayer alignment compensation, characterized in that, Includes the following steps: S1. Fabricate at least three targets for alignment on the inner reference substrate and record the reference coordinate position of each target in the reference coordinate system; S2. On the current add-in layer to be fabricated, the actual coordinate positions corresponding to each target on the inner layer reference substrate are obtained by optical measurement; S3. Based on the recorded reference coordinate position and the measured actual coordinate position, calculate the translation offset and rotation offset angle of the current layer addition, and then combine the stored historical layer addition offset compensation data to calculate the final compensation parameters of the current layer addition through the weighted moving average algorithm. S4. The final compensation parameters are loaded into the LDI exposure equipment to expose the current overlay. The circuit pattern is formed by development, and copper is electroplated to fill the developed circuit pattern area. The dry film is then removed, and the seed copper layer is removed by flash etching to form the finished circuit. S5. Measure the actual linewidth of the finished circuit after flash erosion, calculate the deviation between the actual linewidth and the target linewidth, update the smoothing coefficient of the weighted moving average algorithm according to the deviation value according to the preset feedback rule, and store the offset data and compensation parameters of the current layer addition for the calculation of the next layer addition.

2. The high-precision IC carrier board interlayer alignment compensation manufacturing method according to claim 1, characterized in that, The specific steps of step S1 are as follows: S11. Select the copper-clad laminate core board with completed surface treatment as the inner layer reference substrate; S12. At least three targets are made at a predetermined position on the inner reference substrate by laser drilling or etching, and the targets are marked in the shape of a cross or a circle. S13. Using a coordinate measuring machine or an LDI camera system, measure the reference coordinates of each target in the reference coordinate system, and record them as follows: ,in N is the number of targets. The reference coordinates are then stored in the database.

3. The high-precision IC carrier board interlayer alignment compensation manufacturing method according to claim 2, characterized in that, The specific steps of step S2 are as follows: S21. On the current add-on layer to be fabricated after the photoresist coating is completed, the camera system of the LDI equipment is used to locate the position corresponding to the target on the inner layer reference substrate; S22. Sequentially photograph the actual imaging position of each target on the current layer, obtain the measured value of the actual coordinates, and record it as... ; S23. After associating the measured values ​​of the actual coordinates with the identification information of the current layer, store them in the database.

4. The high-precision IC carrier board interlayer alignment compensation manufacturing method according to claim 1, characterized in that, The specific steps of step S3 are as follows: S31. Read the actual coordinate measurement values ​​of the current layer from the database. and the corresponding reference coordinates Calculate the measured translational offset of the current k-layer addition using the following formula. and : ； Where N is the number of targets, N≥3, and i is the target number, i=1,2,…,N; This represents the x-translation offset of the current k-layer addition. This represents the y-shift offset of the current k-layer addition; S32. Calculate the measured rotation offset angle of the current added layer using the following formula. : ； S33. Read the final compensation amount of the previous layer from the database, i.e., the k-1 layer. ,in, The x-coordinate compensation amount for the added layer k-1, The y-coordinate compensation amount for the added layer k-1, The rotation angle compensation amount is for layer k-1, with layer 1 as the reference layer, and the initial compensation amount for layer 1 is set to... ; S34. Using the weighted moving average algorithm, calculate the final compensation parameters for the current k-layer increment according to the following formula: in, The x-coordinate compensation amount for the current k-layer addition. The compensation amount for the y-coordinate of the current k-layer addition. This is the rotation angle compensation amount for the current k-layer addition; This is the translation smoothing coefficient. This is the rotational smoothing coefficient; S35. The calculated result The final compensation parameter for the current k-incrementing layer is stored in the database.

5. The high-precision IC carrier board interlayer alignment compensation manufacturing method according to claim 4, characterized in that, In the weighted moving average algorithm of step S34, when the current layer number k≤3, the equal-weighted arithmetic mean is used instead of the weighted moving average, that is, taking... This is to accelerate the convergence speed of the initial compensation parameters.

6. The high-precision IC carrier board interlayer alignment compensation manufacturing method according to claim 4, characterized in that, The specific steps of step S4 are as follows: S41. Final compensation parameters Loaded into the control system of the LDI exposure equipment; S42. The LDI exposure device performs translation and rotation transformations on the original CAM graphic data according to the compensation parameters to generate a compensated exposure graphic; S43. Expose the current uplayer photoresist using the compensated exposure pattern. After exposure, develop the photoresist to remove the unexposed areas and expose the circuit pattern to be electroplated. S44. Electroplating copper fills the exposed circuit pattern area after development according to preset electroplating parameters, so that the thickness of the electroplated copper layer reaches the target value; the electroplating parameters include current density and electroplating time; S45. Remove the remaining photoresist, and then use an alkaline or acidic etchant to flash-etch and remove the seed copper layer at the bottom to form the final finished circuit.

7. The high-precision IC carrier board interlayer alignment compensation manufacturing method according to claim 6, characterized in that, In step S45, prior to flash etching, the measured copper plating thickness distribution of the current layer is determined. and seed copper layer thickness Predicting the linewidth shrinkage after flash erosion Adjust the flashover time according to the following rules. : in, The empirical etching coefficient is... This represents the average copper thickness after electroplating. like If the historical statistical value of the deviation from the target linewidth in step S5 exceeds the threshold, then the etching time is dynamically compensated before flash etching: in, The etch time is compensated. For standard etching time, For etching rate, This is the average value of the linewidth deviation of the previous few layers.

8. The high-precision IC carrier board interlayer alignment compensation manufacturing method according to claim 1, characterized in that, The specific steps of step S5 are as follows: S51. Using an automated optical inspection device, select at least five measurement points on the finished circuit after flash etching, measure the actual line width at each point, and record the average value as follows: ; S52. Read the target line width from the database. Calculate the line width deviation using the following formula: ； S53. Based on the line width deviation Update the smoothing coefficient in the weighted moving average algorithm using the following formula. and : in, , These are the translation smoothing coefficient and rotation smoothing coefficient used for the current layer, respectively. For translation feedback coefficients, For rotational feedback coefficients; S54. Calculate the measured offset of the current added layer. Final compensation parameters Line width deviation and the updated displacement smoothing coefficient Rotational smoothing coefficient Stored in the database as historical data for the next layer in step S3.

9. The high-precision IC carrier board interlayer alignment compensation manufacturing method according to claim 1, characterized in that, The following warpage prediction step is included before step S2: The overall warpage of the current add-on substrate was obtained using a 3D profilometer. ; The number of targets is dynamically determined based on the warp. : in, This is for rounding down.

10. A high-precision IC substrate interlayer alignment compensation manufacturing system, characterized in that, include: The reference establishment module is used to fabricate at least three targets for alignment on the inner reference substrate and record the reference coordinate position of each target in the reference coordinate system. The optical measurement module is used to obtain the actual coordinate positions of each target on the inner layer reference substrate through optical measurement on the current add-in layer to be fabricated. The compensation calculation module is used to calculate the translational offset and rotational offset angle of the current layer addition based on the recorded reference coordinate position and the measured actual coordinate position. Then, combined with the stored historical layer addition offset compensation data, the final compensation parameters of the current layer addition are calculated through a weighted moving average algorithm. The exposure and circuit forming module is used to load the final compensation parameters into the LDI exposure equipment, expose the current overlay, form the circuit pattern through development, electroplate copper to fill the developed circuit pattern area, remove the dry film, remove the seed copper layer through flash etching, and form the finished circuit. The linewidth feedback and parameter update module is used to measure the actual linewidth of the finished line after flash erosion, calculate the deviation between the actual linewidth and the target linewidth, update the smoothing coefficient of the weighted moving average algorithm according to the deviation value according to the preset feedback rules, and store the offset data and compensation parameters of the current layer addition for the calculation of the next layer addition.

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