Parameter testing circuit and method for a time-to-digital converter

Abstract

The embodiment of the present application provides a parameter test circuit and method of time-to-digital converter, the parameter test circuit comprises: a signal shaping matching module, an input end of the signal shaping matching module is used for receiving a start signal output by a time-to-digital converter chip to be tested; a controllable delay waveform generator, an input end of the controllable delay waveform generator is connected with an output end of the signal shaping matching module, and the controllable delay waveform generator is used for generating a stop signal with a controllable delay relative to the start signal when the start signal is received; a reference clock module, output ends of the reference clock module are connected with a reference clock input end of the controllable delay waveform generator and a sampling clock input end of the time-to-digital converter to be tested respectively, and the reference clock module is used for providing the same clock signal to the controllable delay waveform generator and the time-to-digital converter to be tested; an interface, the interface is used for connecting the time-to-digital converter to be tested; wherein the reference clock module, the signal shaping matching module, the controllable delay waveform generator and the interface are arranged on the same printed circuit board.

Description

Technical Field

[0001] This application relates to the field of time-to-digital converter technology, and more specifically, the embodiments of this application relate to a parameter testing circuit and method for a time-to-digital converter. Background Technology

[0002] Time-of-Flight (ToF) technology is currently widely used in mobile phones, robotic vacuum cleaners, drones, and automotive systems. This technology can be further divided into two main categories: indirect time-of-flight (iToF) measurement and direct time-of-flight (dToF) measurement. Compared to iToF technology, dToF technology offers higher ranging accuracy and a longer ranging distance; therefore, the performance of its core sensor chip is highly dependent on the time measurement accuracy of its internal Time-to-Digital Converter (TDC).

[0003] The performance parameters of TDC chips include time resolution, differential nonlinearity (DNL), integral nonlinearity (INL), maximum measurable time interval, noise floor, and temperature drift characteristics. Traditional testing methods typically employ independent testing for each parameter, requiring different test fixtures and instrument configurations for different parameters. This process is cumbersome and makes it difficult to obtain comprehensive performance data for all chip metrics in a single test run. Another common industry approach relies on high-end specialized instruments, such as picosecond delay generators, high-speed timing analyzers, and phase noise testing equipment. These large instruments are not only extremely expensive to purchase but also have stringent requirements for the testing environment, making them difficult to deploy in ordinary laboratories and hindering large-scale testing in mass production.

[0004] In a more common laboratory testing approach, only a programmable waveform generator is connected to the TDC chip under test. During testing, the waveform generator's delay-triggered function generates a series of pulse signals with different preset step delays. These signals are then used as stop signals and directly input to the TDC chip's stop signal port. The TDC chip itself outputs a start signal. The chip measures the time interval between its own output start signal and the stop signal received from the external waveform generator, and outputs the corresponding digital code value. Based on these code values, various parameters of the TDC are calculated. However, this approach has significant accuracy limitations. Due to the waveform generator's own output jitter, and the long traces and large parasitic parameters between the instrument and the chip, considerable additional delay errors and phase noise are introduced into the signal transmission path. These errors are directly coupled to the TDC's time measurement results, resulting in poor test repeatability, especially when accurately evaluating nonlinear parameters such as DNL and INL. The measurement results fail to accurately reflect the chip's performance.

[0005] Furthermore, existing TDC testing technologies suffer from the following key limitations. First, the testing equipment is expensive, heavily reliant on imported high-end specialized instruments, such as picosecond-level high-precision delay generators and timing analyzers. Second, the accuracy of the test signal is difficult to guarantee, with complex and diverse sources of error. The connection between external instruments and the chip under test via long coaxial cables and connectors not only introduces additional signal jitter but also causes reflections and ringing due to impedance mismatch, ultimately degrading the steepness of the signal edges and resulting in significant errors in time measurements triggered by signal edges. Third, traditional solutions generally lack the capability for automated testing across the entire temperature range in conjunction with temperature control equipment. The temperature drift characteristics of a TDC chip are a crucial indicator of its reliability, requiring continuous parameter acquisition under varying ambient temperatures. Current methods typically require manually placing the circuit board in the temperature chamber, completing the test at a single temperature point, removing it, and then manually adjusting the temperature for the next test. This lack of automated temperature scanning and continuous testing across the entire temperature range makes it difficult to comprehensively assess the chip's performance drift patterns and reliability levels over a wide temperature range. Summary of the Invention

[0006] The purpose of this application is to provide a parameter testing circuit and method for a time-to-digital converter. Some embodiments of this application integrate the signal shaping and matching module, the controllable delay waveform generator, and the reference clock module with the TDC under test on the same PCB board, eliminating parasitic parameters and signal reflections introduced by long-distance coaxial cables in traditional discrete instrument solutions; by providing the same clock signal to the controllable delay waveform generator and the TDC under test through the reference clock module, the relative phase drift and asynchronous jitter introduced by the two using independent clock sources are eliminated, providing a low-jitter reference clock reference for TDC time interval measurement.

[0007] In a first aspect, embodiments of this application provide a parameter testing circuit for a time-to-digital converter (TD-DC converter). The parameter testing circuit includes: a signal shaping and matching module, whose input terminal is used to receive a start signal output by the TD-DC converter chip under test; a controllable delay waveform generator, whose input terminal is connected to the output terminal of the signal shaping and matching module, used to generate a stop signal with a controllable delay relative to the start signal upon receiving the start signal, and output the stop signal to the stop signal input terminal of the TD-DC converter under test; and a reference clock module, whose output terminal is connected to both the reference clock input terminal of the controllable delay waveform generator and the sampling clock input terminal of the TD-DC converter under test, used to provide the same clock signal to both the controllable delay waveform generator and the TD-DC converter under test; wherein the reference clock module, the signal shaping and matching module, and the controllable delay waveform generator are disposed on the same printed circuit board.

[0008] The embodiments of this application integrate the signal shaping and matching module, the controllable delay waveform generator, and the reference clock module with the TDC under test on the same PCB board, eliminating parasitic parameters and signal reflections introduced by long-distance coaxial cables in traditional discrete instrument solutions; by providing the same clock signal to the controllable delay waveform generator and the TDC under test through the reference clock module, the relative phase drift and asynchronous jitter introduced by the two using independent clock sources are eliminated, providing a low-jitter reference clock reference for TDC time interval measurement.

[0009] In some embodiments, the signal shaping and matching module includes: a differential amplifier, connected to the start signal output terminal of the time-to-test digital converter and the output terminal of the reference clock module, respectively, for converting the differential signal output by the time-to-test digital converter into a single-ended signal; and a first comparator, connected to the output terminal of the differential amplifier, for shortening the edge rise time of the single-ended signal and performing level conversion.

[0010] The embodiments of this application convert the LVDS differential signal (swing of about 350mV) into a single-ended signal using a differential amplifier, and use a comparator to shorten the signal edge rise time from a relatively large value to below a smaller target value, thereby reducing the trigger timing jitter caused by comparator input noise and improving the response accuracy of the controllable delay waveform generator to the start signal.

[0011] In some embodiments, the signal shaping and matching module further includes: an adjustable threshold voltage circuit connected to the reference voltage input terminal of the first comparator, for providing an adjustable comparison threshold voltage; and an impedance matching resistor connected to the output terminal of the first comparator, for achieving impedance matching with the input terminal of the controllable delay waveform generator.

[0012] The adjustable threshold voltage circuit provided in the embodiments of this application enables the comparator's trigger threshold to adapt to different signal amplitudes, ensuring reliable triggering under different test conditions; the impedance matching resistor eliminates signal reflection in PCB traces and coaxial cable transmission, reduces edge glitch and distortion, and further improves the stability of the trigger moment.

[0013] In some embodiments, the controllable delay waveform generator includes: a main delay chain and a bypass calibration path; the main delay chain includes a tapped delay chain composed of multiple inverters for generating an adjustable delay pulse signal; the bypass calibration path is a PCB trace path that characterizes the minimum physical delay of the test circuit; wherein, the input terminal of the bypass calibration path is connected in parallel with the input terminal of the main delay chain to receive the same start signal; the output terminal of the main delay chain and the output terminal of the bypass calibration path are respectively connected to the first input terminal and the second input terminal of the two-way switch, and the common output terminal of the two-way switch serves as the output terminal of the controllable delay waveform generator.

[0014] The main delay chain of the embodiments of this application provides a controllable delay step for TDC parameter testing; the bypass calibration path serves as the physical delay reference of the test circuit itself, and switches between normal testing and calibration cycles through a two-to-one switch, enabling the test circuit to obtain the inherent delay value at the current temperature before formal measurement, providing a measured basis for subsequent correction without relying on external standard instruments.

[0015] In some embodiments, the parameter testing circuit further includes: a programmable temperature control box, wherein the printed circuit board is disposed inside the programmable temperature control box, for placing the parameter testing circuit and the time-to-measure digital converter in the same temperature environment; a control and data processing module, communicatively connected to the controllable delay waveform generator, for sending a delay step control signal to the controllable delay waveform generator and receiving the digital code value output by the time-to-measure digital converter; the control and data processing module is also communicatively connected to the programmable temperature control box, for receiving the temperature value fed back by the programmable temperature control box, and for correcting the digital code value according to the temperature value.

[0016] In the embodiments of this application, the PCB board is placed inside a programmable temperature control box, so that the test circuit and the TDC under test are in the same temperature field, eliminating the uncorrectable system error caused by the different temperatures of the external test instrument and the chip under test in the traditional solution; the test computer realizes the automated closed loop of delay step control, digital code value acquisition and temperature feedback correction through communication connection, supporting automated testing in the whole temperature range.

[0017] Secondly, some embodiments of this application provide a parameter testing method for a time-to-digital converter, executed by a parameter testing circuit as described in any of the embodiments included in the first aspect. The parameter testing method includes: controlling a programmable temperature control box to adjust the ambient temperature of the printed circuit board to multiple different preset temperature values; during a constant temperature phase at each preset temperature value, obtaining a calibration value of the inherent delay of the parameter testing circuit itself at the current temperature; controlling the controllable delay waveform generator to generate a stop signal with a progressive delay relative to the start signal; driving the time-to-digital converter under test to measure the time interval between the start signal and the stop signal, and acquiring the raw code value of the output data; correcting the raw code value according to the calibration value to eliminate the error introduced by the delay of the parameter testing circuit itself with temperature drift, thereby obtaining the true performance parameters of the time-to-digital converter under test.

[0018] In the embodiments of this application, calibration operations are performed during the isothermal phase at each preset temperature point to obtain the inherent delay calibration value of the test circuit at the current temperature, and the calibration value is removed from the measurement results, so that the final output TDC performance parameters are not affected by the delay of the test circuit itself with temperature drift, which is suitable for full-temperature range automated testing scenarios.

[0019] In some embodiments, the step of correcting the original code value based on the calibration value includes: subtracting the calibration value from the original time interval measured by the time-to-digital converter under test to obtain the true time interval of the time-to-digital converter under test, so as to complete the correction of the measurement result.

[0020] The correction steps in the embodiments of this application use subtraction to eliminate the inherent delay of the test circuit. This method has low computational load, strong real-time performance, and does not require iteration or complex signal processing. It is suitable for rapid correction processing of large amounts of test data in mass production testing.

[0021] In some embodiments, before controlling the controllable delay waveform generator to generate a stop signal with a progressive delay relative to the start signal, the method further includes: generating an original start signal by the time-to-test digital converter, performing level conversion, edge shaping, and impedance matching on the original start signal via a signal shaping and matching module, and then sending the original start signal to the trigger input terminal of the controllable delay waveform generator; controlling the controllable delay waveform generator to generate a stop signal with a progressive delay relative to the start signal includes: the controllable delay waveform generator using a clock provided by a reference clock module as a reference clock, generating a delay-adjustable stop signal (Stop signal) in response to the start signal and outputting it to the time-to-test digital converter.

[0022] The embodiments of this application define the entire signal processing flow from the generation of the start signal of the TDC under test to the output of the stop signal of the controllable delay waveform generator, including level conversion, edge shaping, impedance matching and common clock reference, to ensure that the start signal has a steep edge and complete signal integrity when it reaches the trigger input of the controllable delay waveform generator, and to avoid measurement errors caused by edge jitter near the trigger threshold.

[0023] In some embodiments, during the isothermal phase at each preset temperature value, acquiring a calibration value reflecting the inherent delay of the parameter testing circuit at the current temperature includes: reading the current temperature fed back by the programmable temperature control box. Substitute the current temperature into the temperature drift model to calculate the delay value at the current temperature, which serves as the calibration value for the inherent delay of the parameter test circuit corresponding to the current temperature.

[0024] In some embodiments, before substituting the current temperature into the temperature drift model to calculate the delay value at the current temperature, the parameter testing method further includes: within a preset temperature range, after holding at each temperature point for a predetermined time in predetermined temperature steps, performing a calibration step, the calibration step including: switching the two-way switch inside the controllable delay waveform generator to the bypass calibration path; sending a first pulse to the controllable delay waveform generator; measuring the delay time of the first pulse after passing through the bypass calibration path, and recording it as the delay value at the current temperature point. After completing the measurements at all temperature points, calculate the delay value at each temperature point. By performing a polynomial fit on the following functional expression, the temperature drift model of calibration delay as a function of temperature is obtained: The parameters a, b, c, and d of the temperature drift model are stored in a configuration file.

[0025] The method provided in the embodiments of this application introduces a start signal into the bypass calibration path by switching between two options, and measures the delay value of the path at the current temperature. The delay value is then subtracted from the measurement results in real time as an inherent delay of the test circuit at the current temperature; the physical length of the bypass calibration path is extremely short (<5mm), and its temperature drift is negligible (<0.1ps / ℃), therefore the measured... It accurately reflects the temperature-dependent delay of active devices such as comparators and drivers inside the controllable delay waveform generator, so that the correction has a physical measurement basis rather than relying on theoretical estimation.

[0026] In some embodiments, the step of correcting the original code value based on the calibration value involves obtaining the calibration value at the current temperature. The raw code value obtained by the time-to-digital converter under test. Convert to time units to obtain the original time interval. Where LSB is the time resolution of the time-to-digital converter under test; from the original time interval Subtract the calibration value from the middle To obtain the actual time interval:

[0027] The actual performance parameters of the time-to-digital converter under test are determined based on the actual time interval. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is one of the architecture diagrams of the parameter testing circuit for a time-to-digital converter provided in an embodiment of this application.

[0030] Figure 2 The second diagram shows the architecture of the parameter testing circuit for the time-to-digital converter provided in the embodiments of this application.

[0031] Figure 3 The third diagram of the parameter testing circuit for the time-to-digital converter provided in this application embodiment.

[0032] Figure 4A flowchart of a parameter testing method for a time-to-digital converter provided in an embodiment of this application. Detailed Implementation

[0033] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0034] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0035] Unlike related solutions, the embodiments of this application integrate the dispersed benchtop instruments (waveform generator, clock source) and the TDC under test (TD) into a single PCB board. A shared reference clock ensures that the signal source and sampling end are clocked from the same source, eliminating asynchronous phase drift. Furthermore, the embodiments of this application establish a bypass calibration path within the controllable delay waveform generator, combine this with full-temperature-range offline calibration to build a temperature drift model, and perform online compensation based on the real-time temperature feedback from the temperature chamber during actual testing. This dynamically eliminates the inherent delay of the test circuit itself and its temperature-dependent variations from the measurement results. Based on these concepts, this application can meet the required testing needs without using picosecond-level delay generators, timing analyzers, or other instruments, thus reducing testing costs. For example, embodiments of this application reduce trigger jitter from picosecond to sub-picosecond levels through signal shaping and bypass calibration path design, thereby improving measurement repeatability; embodiments of this application use real-time compensation of the temperature drift model to control the additional delay error introduced by the test circuit in the full temperature range (-40℃ to 125℃) within a preset range, and support full-temperature range automated testing and regression verification.

[0036] Please refer to Figure 1 ,Should Figure 1 This is a schematic diagram of the parameter testing circuit for a time-to-digital converter provided in some embodiments of this application. For example... Figure 1 As shown, the parameter testing circuit includes: an integrated test PCB board 100 and a reference clock module 110, a controllable delay waveform generator 130, a signal shaping and matching module 140, and an interface 120 for connecting the TDC under test (i.e., the time-to-digital converter under test) on the PCB board. The TDC under test is connected to the parameter testing circuit through the interface 120 (or, in some other embodiments of this application, the TDC under test can be directly disposed on the PCB board 100).

[0037] The input terminal of the signal shaping and matching module 140 is used to receive the start signal (i.e., Start signal) output by the TDC under test. The output terminal of the signal shaping and matching module 140 is connected to the input terminal of the controllable delay waveform generator 130. The signal shaping and matching module is used to perform level conversion, edge shaping and impedance matching on the start signal and then output it to the controllable delay waveform generator 130.

[0038] The input terminal of the controllable delay waveform generator 130 is connected to the output terminal of the signal shaping and matching module 140. The controllable delay waveform generator 130 is used to generate a stop signal with a controllable delay relative to the start signal and output the stop signal to the stop signal input terminal of the TDC under test.

[0039] The output of the reference clock module 110 is connected to the reference clock input of the controllable delay waveform generator 130 and the sampling clock input of the TDC under test, respectively, to provide the same clock signal to the controllable delay waveform generator and the TDC under test.

[0040] In some embodiments of this application, the reference clock module 110, the controllable delay waveform generator 130, and the signal shaping and matching module 140 are disposed on the same printed circuit board (i.e., integrated test PCB board 100). It is understood that the TDC under test is also located on the same printed circuit board during testing or calibration. Figure 1 As shown, in some embodiments of this application, the parameter testing circuit further includes: a programmable temperature control box 160 and a test computer 170 (as an example of a control and data processing module).

[0041] The programmable temperature control box 160 has an internal cavity that accommodates the integrated test PCB board 100. The integrated test PCB board 100 is entirely disposed inside the programmable temperature control box 160. The programmable temperature control box 160 is used to ensure that the parameter test circuit and the TDC under test are in the same temperature environment.

[0042] The test computer 170 is communicatively connected to the controllable delay waveform generator 130 and the programmable temperature control box 160, respectively. It controls the delay step of the controllable delay waveform generator 130, receives the digital code value (i.e., the original code value) output by the TDC under test, and corrects the digital code value based on the current temperature feedback from the programmable temperature control box 160. Specifically, the programmable temperature control box 160 sends a temperature feedback signal and / or a temperature stability flag to the test computer 170; the TDC under test sends its output original code value to the test computer 170.

[0043] like Figure 2As shown, in some embodiments of this application, the signal shaping and matching module includes a differential amplifier 141 and a first comparator 142.

[0044] The differential amplifier is connected to the start signal output terminal of the time-to-test digital converter and the output terminal of the reference clock module, respectively, to convert the LVDS differential signal output by the time-to-test digital converter into a single-ended signal.

[0045] For example, in some embodiments of this application, the differential amplifier 141 is selected as a fully differential amplifier with low noise and high bandwidth characteristics (e.g., Analog Devices AD8132). The differential amplifier 141 has a differential non-inverting input, a differential inverting input, a common-mode reference voltage input, a non-inverting differential output, and an inverting differential output. The differential non-inverting input and the differential inverting input are respectively connected to the LVDS non-inverting output (LVDS_P) and the LVDS inverting output (LVDS_N) of the TDC under test, respectively, to receive the LVDS differential signal (swing of approximately 350mV) output by the TDC under test. The non-inverting differential output of the differential amplifier 141 serves as a single-ended signal output, and the inverting differential output is grounded through a resistor whose value matches the output impedance of the differential amplifier, thus converting the differential output to a single-ended output. The common-mode reference voltage input of differential amplifier 141 is connected to a reference voltage source (e.g., +1.25V) to set the common-mode level of the output single-ended signal. The power supply terminal of differential amplifier 141 is connected to a +3.3V or +5V DC power supply, and the ground terminal is connected to the circuit common ground. The LVDS differential signal output from the TDC under test is amplified by differential amplifier 141 and converted into a single-ended voltage signal with a swing of approximately +1.25V to +2.5V, which is output from the non-inverting differential output terminal of differential amplifier 141 to the signal input terminal of the first comparator 142.

[0046] The first comparator, connected to the output of the differential amplifier, is used to shorten the rise time of the single-ended signal and perform level conversion.

[0047] For example, in some embodiments of this application, the first comparator 142 is a voltage comparator with high-speed response characteristics (e.g., the Texas Instruments TLV3501 with a rise time of 2.2 ns), which has a non-inverting input, an inverting input, a power supply terminal, a ground terminal, and a push-pull output terminal. The non-inverting input of the first comparator 142 is connected to the non-inverting differential output of the differential amplifier 141 to receive the single-ended voltage signal output by the differential amplifier 141. The inverting input of the first comparator 142 is connected to the output of the adjustable threshold voltage circuit 143 to receive the adjustable comparison threshold voltage. The power supply terminal of the first comparator 142 is connected to a +3.3V DC power supply, and the ground terminal is connected to the circuit common ground. The first comparator 142 adopts a push-pull output architecture, and its push-pull output terminal is the output terminal of the first comparator 142. The comparator compares the analog single-ended voltage signal output from the differential amplifier 141 with a comparison threshold voltage: when the analog single-ended voltage signal is higher than the comparison threshold voltage, the push-pull output terminal outputs a high level (approximately +3.3V); when the analog single-ended voltage signal is lower than the comparison threshold voltage, the push-pull output terminal outputs a low level (approximately 0V). Through this comparison operation, the first comparator 142 converts the relatively flat-edge analog signal (rise time approximately 1ns) output from the differential amplifier 141 into a steep-edge digital level signal (rise time shortened to below 300ps), and simultaneously converts the signal level from the approximately +1.25V to +2.5V level range output from the differential amplifier 141 to the +3.3V digital level range. The push-pull output terminal of the first comparator 142 is connected in series to one end of the impedance matching resistor 144, and is connected to the trigger input terminal of the controllable delay waveform generator 130 through the impedance matching resistor 144.

[0048] like Figure 2 As shown, in some other embodiments of this application, the signal shaping and matching module further includes: an adjustable threshold voltage circuit 143 and an impedance matching resistor 144.

[0049] An adjustable threshold voltage circuit is connected to the reference voltage input terminal of the first comparator to provide an adjustable comparison threshold voltage.

[0050] For example, in some embodiments of this application, the adjustable threshold voltage circuit 143 is composed of a voltage divider resistor network, including a first resistor and a second resistor connected in series between a reference voltage source and ground. The reference voltage source can be the same +1.25V or +2.5V reference voltage as the reference clock module 110, or it can be a separate precision reference voltage source chip (e.g., ADR441). One end of the first resistor is connected to the reference voltage source, and the other end of the first resistor is connected to one end of the second resistor, with this node serving as the output of the adjustable threshold voltage circuit 143. The other end of the second resistor is grounded. The first or second resistor is an adjustable resistor (e.g., a digital potentiometer or a mechanical trimmer). By adjusting the resistance value of this adjustable resistor, the voltage division ratio between the first and second resistors can be changed, thereby obtaining an adjustable comparison threshold voltage at the node. The output of the adjustable threshold voltage circuit 143 is connected to the inverting input of the first comparator 142. By adjusting the value of the adjustable resistor, the comparison threshold voltage can be set to 50% of the amplitude of the single-ended signal output by the differential amplifier 141 (for example, when the output swing of the differential amplifier 141 is +1.25V to +2.5V, the threshold voltage can be set to approximately +1.875V), ensuring that the first comparator 142 flips at the middle level of the signal edge, reducing the trigger timing jitter caused by comparator input noise.

[0051] An impedance matching resistor is connected to the output of the first comparator to achieve impedance matching with the input of the controllable delay waveform generator.

[0052] For example, in some embodiments of this application, one end of the impedance matching resistor 144 is connected to the push-pull output of the first comparator 142, and the other end of the impedance matching resistor 144 serves as the output of the signal shaping and matching module, connected to the trigger input of the controllable delay waveform generator 130. The resistance value of the impedance matching resistor 144 is set to be equal to the characteristic impedance of the transmission line at the input of the controllable delay waveform generator 130 (e.g., 50Ω, corresponding to the characteristic impedance of subsequent PCB traces or coaxial cables). In the circuit connection, the impedance matching resistor 144 acts as a series terminating resistor, used to absorb signal reflections on the transmission line between the push-pull output of the first comparator 142 and the input of the controllable delay waveform generator 130, eliminating signal edge overshoot, undershoot, and ringing caused by impedance discontinuities, ensuring that the trigger signal received by the trigger input of the controllable delay waveform generator 130 has clean edges, and avoiding false triggering or uncertain triggering timing of the controllable delay waveform generator 130 due to edge glitches.

[0053] like Figure 3As shown, in some embodiments of this application, the trigger input of the controllable delay waveform generator 130 is connected to the output of the signal shaping and matching module 140 to receive the shaped start signal. The controllable delay waveform generator 130 includes a main delay chain 131, a bypass calibration path 132, and a two-to-one switch 133. The output of the controllable delay waveform generator 130 is the common output of the two-to-one switch 133, which is connected to the stop signal input of the TDC under test (TDC) to output a stop signal with adjustable delay to the TDC. The reference clock input of the controllable delay waveform generator 130 is connected to the output of the reference clock module 110 to receive the reference clock signal as the reference clock for its internal delay chain, ensuring the accuracy and stability of the delay step. The input terminal of the bypass calibration path is connected in parallel with the input terminal of the main delay chain to receive the same start signal; the output terminal of the main delay chain and the output terminal of the bypass calibration path are respectively connected to the first input terminal and the second input terminal of the two-to-one switch, and the common output terminal of the two-to-one switch serves as the output terminal of the controllable delay waveform generator.

[0054] The controllable delay waveform generator 130 has two operating modes: normal test mode and calibration mode. In normal test mode, the shaped start signal is sent to the main delay chain 131, and after passing through a tapped delay chain composed of multiple inverters to generate an adjustable delay, it is output from the common output terminal of the two-to-one switch 133 as a stop signal provided to the TDC under test. In calibration mode, the shaped start signal is sent to the bypass calibration path 132, and after passing through an extremely short physical path, it is output from the common output terminal of the two-to-one switch 133 to measure the bypass calibration path delay value of the controllable delay waveform generator 130 at the current temperature. This delay value reflects the temperature-dependent delay of the comparators, drivers, and high-speed analog switches inside the controllable delay waveform generator at the current temperature.

[0055] For example, in some embodiments of this application, the main delay chain 131 is composed of N stages of inverters (e.g., 64 stages) cascaded sequentially, where N is a positive integer greater than or equal to 2. Specifically, the input terminal of the first stage inverter serves as the signal input terminal of the main delay chain 131, connected to the trigger input terminal of the controllable delay waveform generator 130, for receiving the start signal processed by the signal shaping and matching module 140. The output terminal of the first stage inverter is connected to the input terminal of the second stage inverter, the output terminal of the second stage inverter is connected to the input terminal of the third stage inverter, and so on, with the output terminal of the Nth stage inverter connected to the first input terminal (e.g., normally open input terminal) of the two-to-one switch 133. The power supply terminals of each stage inverter are all connected to the internal operating power supply (e.g., +1.8V or +3.3V) of the controllable delay waveform generator 130, and the ground terminals are all connected to the circuit common ground.

[0056] Inverters are cascaded in stages to form a tapped delay chain: each inverter output has a tap, and each tap is connected to the corresponding input of a multiplexer (MUX). The output of this multiplexer serves as the delay tap output of the main delay chain 131 and is connected to the first input of a two-to-one switch 133. The selection control terminal of the multiplexer is connected to the control output of the test computer 170 to receive the delay step control signal. By changing the value of the delay step control signal, the test computer 170 controls the multiplexer to select different numbers of inverter taps, thereby selecting the number of inverter stages the start signal passes through in the main delay chain 131. Since each inverter has a fixed propagation delay time (e.g., approximately 10 ps per stage), the delay time experienced by the start signal from the input of the main delay chain 131 to the selected tap output is equal to the number of inverter stages multiplied by the propagation delay time of each inverter stage, thus achieving digitally adjustable control of the delay. The signal output by the selected tap is a pulse signal with a controllable delay. This pulse signal is sent to the first input terminal of the two-to-one switch 133 via the output terminal of the multiplexer.

[0057] It should be noted that, in the embodiments of this application, the correspondence between the selection logic of the multiplexer and the delay amount output by the controllable delay waveform generator 130 can be realized by a lookup table or linear mapping algorithm in the test computer 170: that is, the test computer 170 calculates the corresponding tap number according to the required delay amount, outputs the corresponding binary selection code to the selection control terminal of the multiplexer, so that the multiplexer selects the tap corresponding to the delay amount.

[0058] For example, in some embodiments of this application, the bypass calibration path 132 consists of PCB traces and a high-speed analog switch, representing the shortest physical delay path achievable within the controllable delay waveform generator 130 besides the main delay chain. Specifically, the input of the bypass calibration path 132 is connected to the trigger input of the controllable delay waveform generator 130, i.e., connected in parallel to the input of the first-stage inverter of the main delay chain 131 at the same node, so that the start signal can be simultaneously fed into both the main delay chain 131 and the bypass calibration path 132. The total length of the PCB traces of the bypass calibration path 132 is less than 5mm, and its trace width and spacing are designed according to the minimum trace width / spacing rules of PCB manufacturing process to ensure that the physical delay of this path is minimized and repeatable. The output of the bypass calibration path 132 is connected to the input of the high-speed analog switch. The high-speed analog switch uses an analog switch chip (such as Maxim's MAX4544) with low on-resistance (e.g., Ron < 5Ω) and fast switching characteristics (e.g., switching time < 10ns). Its power supply terminal is connected to a +3.3V DC power supply, its ground terminal is connected to the circuit common ground, and its control terminal is connected to the control output terminal of the test computer 170 (which can share the same control signal with the control terminal of the two-to-one switch 133 described below or be controlled independently). The output terminal of the high-speed analog switch is connected to the second input terminal (e.g., normally closed input terminal) of the two-to-one switch 133.

[0059] A test point for injecting a test signal is also provided on the bypass calibration path 132. This test point is connected to the analog-to-digital converter input (or time-to-digital converter measurement input) of the test computer 170 and is used to measure the delay time of the start signal after passing through the bypass calibration path 132 during the calibration cycle. The test point is positioned between the output of the high-speed analog switch and the second input of the two-to-one switch 133 to ensure that the measured delay time includes the full contribution of PCB traces and the conduction delay of the high-speed analog switch.

[0060] The bypass calibration path is connected in parallel with the input of the main delay chain, and its output is merged into a two-to-one switch. For example, the trigger input of the controllable delay waveform generator 130 is connected to a signal distribution node, which is simultaneously connected to the input of the first-stage inverter of the main delay chain 131 and the input of the bypass calibration path 132. That is, the main delay chain 131 and the bypass calibration path 132 are connected in parallel on the input side. The output of the multiplexer of the main delay chain 131 (i.e., the delay tap output of the main delay chain 131) is connected to the first input of the two-to-one switch 133 (e.g., normally open input IN1); the output of the high-speed analog switch in the bypass calibration path 132 is connected to the second input of the two-to-one switch 133 (e.g., normally closed input IN2). The common output (COM terminal) of the two-to-one switch 133 serves as the output of the controllable delay waveform generator 130 and is connected to the stop signal input of the TDC under test. The control terminal of the two-way switch 133 is connected to the control output terminal of the test computer 170 to receive the mode switching control signal. That is, the output terminal of the main delay chain 131 and the output terminal of the bypass calibration path 132 are respectively connected to two different input terminals of the two-way switch 133, and the common output terminal of the two-way switch 133 selects one of the two paths as the output of the controllable delay waveform generator 130.

[0061] The switching logic and operating mode of the two-to-one switch in this embodiment are as follows: The two-to-one switch 133 adopts a single-pole double-throw analog switch with fast switching capability, which has a first input terminal IN1, a second input terminal IN2, a common output terminal COM, and a control terminal SEL. The control terminal SEL is connected to the digital control output terminal of the test computer 170. When the test computer 170 outputs a first level (e.g., high level +3.3V) to the control terminal SEL, the two-to-one switch 133 connects the common output terminal COM with the first input terminal IN1. At this time, the controllable delay waveform generator 130 operates in normal test mode. The start signal is sent to the main delay chain 131 through the signal distribution node. After being delayed by the selected number of inverter stages, it is sent from the multiplexer output terminal of the main delay chain 131 to the first input terminal IN1 of the two-to-one switch 133, and then output to the TDC under test through the common output terminal COM as a stop signal. When the test computer 170 outputs a second level (e.g., low level 0V) to the control terminal SEL, the two-to-one switch 133 connects the common output terminal COM with the second input terminal IN2. At this time, the controllable delay waveform generator 130 operates in calibration mode. The start signal is sent to the bypass calibration path 132 through the signal distribution node, and after passing through the PCB trace and the high-speed analog switch, it is sent from the output terminal of the high-speed analog switch to the second input terminal IN2 of the two-to-one switch 133, and then output through the common output terminal COM to the measurement input terminal of the TDC under test or the test computer 170, for measuring the inherent delay of the controllable delay waveform generator 130 at the current temperature.

[0062] It should be noted that the embodiments of this application obtain measured samples of the inherent delay during the offline calibration stage through calibration operations (i.e., switching bypass paths, transmitting pulses, and measuring delay), denoted as... This is used to establish a temperature drift model; in the online application phase, the estimated value of the inherent delay is obtained by substituting the current temperature value into the temperature drift model, denoted as . , used to correct the original code value.

[0063] The following is combined with Figure 4 This application exemplifies a parameter testing method for a time-to-digital converter according to some embodiments. This method can be implemented by... Figure 1 The parameter test circuit is executed.

[0064] The parameter testing method for the time-to-digital converter provided in this application includes:

[0065] The S410 controls the programmable temperature control box to adjust the ambient temperature of the printed circuit board to several different preset temperature values.

[0066] S420, during the isothermal phase at each preset temperature value, obtains the calibration value of the inherent delay of the parameter test circuit itself at the current temperature.

[0067] S430, control the controllable delay waveform generator to generate a stop signal with a progressive delay relative to the start signal, wherein the start signal comes from the time-to-be-tested digital converter, and the progressive delay means that the delay time of the stop signal relative to the start signal gradually increases according to a preset step amount.

[0068] S440, drive the time-to-measure digital converter to measure the time interval between the start signal and the stop signal to obtain the raw code value, wherein the raw code value is used to characterize the digital mapping result of the physical time interval between the start signal and the stop signal.

[0069] S450, the original code value is corrected according to the calibration value to eliminate the error introduced by the delay of the parameter test circuit itself due to temperature drift, so as to obtain the true performance parameters of the time-to-digital converter under test.

[0070] For example, in some embodiments of this application, the step of correcting the original code value according to the calibration value in S450 includes: subtracting the calibration value from the original time interval measured by the time-to-digital converter under test to obtain the true time interval of the time-to-digital converter under test, so as to complete the correction of the measurement result.

[0071] For example, in some embodiments of this application, before controlling the controllable delay waveform generator to generate a stop signal with a progressive delay relative to the start signal, the method further includes: generating an original start signal by the time-to-test digital converter, performing level conversion, edge shaping, and impedance matching on the original start signal through a signal shaping and matching module, and then sending the original start signal to the trigger input terminal of the controllable delay waveform generator; the step of controlling the controllable delay waveform generator to generate a stop signal with a progressive delay relative to the start signal includes: the controllable delay waveform generator using the clock provided by the reference clock module as a reference clock, generating a stop signal with an adjustable delay (i.e., a Stop signal) in response to the start signal and outputting it to the time-to-test digital converter.

[0072] For example, in some embodiments of this application, the step of performing a calibration operation during the isothermal stage at each preset temperature value to obtain a calibration value reflecting the inherent delay of the test circuit itself at the current temperature includes: the test computer obtaining the delay value of the controllable delay waveform generator at the current temperature based on the current temperature fed back by the programmable temperature control box, as the calibration value of the inherent delay of the test circuit itself at the current temperature.

[0073] For example, in some embodiments of this application, during the isothermal phase at each preset temperature value, obtaining a calibration value reflecting the inherent delay of the parameter testing circuit itself at the current temperature includes: reading the current temperature fed back by the programmable temperature control box. Substitute the current temperature into the temperature drift model to calculate the delay value at the current temperature, which serves as the calibration value for the inherent delay of the parameter test circuit corresponding to the current temperature.

[0074] In some embodiments of this application, before substituting the current temperature into the temperature drift model to calculate the delay value at the current temperature, the parameter testing method further includes the following process of determining the parameters of the temperature drift model through offline calibration: within a preset temperature range, with predetermined temperature steps, after holding at each temperature point for a predetermined time, a calibration step is performed, the calibration step including: switching the two-way switch inside the controllable delay waveform generator to the bypass calibration path; sending a first pulse to the controllable delay waveform generator; measuring the delay time of the first pulse after passing through the bypass calibration path, and recording it as the delay value at the current temperature point. After completing the measurements at all temperature points, calculate the delay value at each temperature point. By performing a polynomial fit on the following functional expression, the temperature drift model of calibration delay as a function of temperature is obtained: The parameters a, b, c, and d of the temperature drift model are stored in a configuration file.

[0075] In some embodiments of this application, the step of correcting the original code value based on the calibration value involves obtaining the calibration value at the current temperature. The raw code value obtained by the time-to-digital converter under test. Convert to time units to obtain the original time interval. Where LSB is the time resolution of the time-to-digital converter under test; from the original time interval Subtract the calibration value from the middle To obtain the actual time interval:

[0076] The actual performance parameters of the time-to-digital converter under test are determined based on the actual time interval.

[0077] In other words, in some embodiments of this application, the original code value is modified according to the following formula: ,in, The actual time interval measured by the time-to-digital converter under test is the true value; LSB is the time resolution of the time-to-digital converter under test. The temperature drift is calculated based on a pre-generated temperature drift model at the current temperature. The inherent delay value of the test circuit described below.

[0078] It is easy to understand that the above technical solution can solve the problems of existing testing solutions, such as reliance on high-end instruments, low testing efficiency, and difficulty in temperature drift testing. In other words, the parameter testing circuit and parameter testing method provided in the embodiments of this application can achieve at least the following three improvement objectives:

[0079] First, it enables the construction of low-cost dedicated test circuits, eliminating reliance on high-end timing test instruments and significantly reducing mass production testing costs. For example, in some embodiments of this application, a waveform generator is used for testing. By configuring an external trigger and controlling the phase of the output signal of the waveform generator via a computer, a pulse signal with adjustable delay can be generated, which can also serve as a standard time reference for testing the linearity of the TDC.

[0080] Second, optimize the signal link to reduce parasitic jitter and delay errors in testing, thereby improving the accuracy and repeatability of TDC parameter testing.

[0081] It should be noted that, based on the above technical solutions, the following specific technical means are adopted in this embodiment to achieve the technical objective:

[0082] 1. Low-jitter reference clock sharing mechanism

[0083] The test circuit board features a reference clock module with low temperature drift (e.g., ±0.5ppm / ℃) and low jitter (e.g., RMS jitter <1ps). The output clock signal of this module simultaneously supplies:

[0084] A controllable delay waveform generator is used as the reference clock for its delay step; the TDC chip under test is used as its sampling clock.

[0085] The embodiments of this application eliminate the relative phase drift and asynchronous jitter introduced by the waveform generator and TDC chip using independent clocks in traditional schemes by sharing a single clock source.

[0086] 2. Signal shaping and impedance matching circuit

[0087] The signal shaping and matching module uses a high-speed comparator (such as TI's TLV3501, with a rise time of 2.2ns) in conjunction with an adjustable threshold voltage circuit. The LVDS differential signal (swing of approximately 350mV) output by the TDC chip under test is first converted into a single-ended signal by a broadband differential amplifier (such as AD8132) before being fed into the high-speed comparator. The comparator's reference threshold is set to 50% of the signal amplitude (approximately 1.25V), and a 50Ω resistor is connected in parallel at the output to achieve impedance matching with the input of the subsequent waveform generator.

[0088] This shaping circuit reduces the signal edge rise time from approximately 1 ns for the original LVDS signal to less than 300 ps, ​​thereby reducing the trigger timing jitter caused by comparator input noise from approximately 5 ps to 1.5 ps. Simultaneously, impedance matching eliminates signal reflections, further reducing edge glitches and distortion.

[0089] 3. Internal calibration path of the controllable delay waveform generator

[0090] In addition to the main delay chain (e.g., a tapped delay chain consisting of 64 inverters, with each stage having a delay of approximately 10 ps), the controllable delay waveform generator also has a bypass calibration path. This path is extremely short (<1 mm), representing the minimum physical delay achievable by the test circuit.

[0091] Some embodiments of this application provide the following multiple methods for determining calibration values.

[0092] (a) Calibration method based on switching measurement and polynomial fitting

[0093] In some embodiments of this application, the controllable delay waveform generator 130 operates in two modes: a normal test mode and a calibration mode. For example... Figure 3As shown, the calibration path 132 is connected in parallel with the input of the main delay chain 131, and the output is combined to a two-way switch 133. The control terminal of the two-way switch 133 is connected to the control output terminal of the test computer 170 for switching between two modes.

[0094] In calibration mode, the test computer 170 controls the two-to-one switch 133 to connect the common output terminal COM and the second input terminal IN2, so that the shaped start signal is sent to the bypass calibration path 132 through the signal distribution node, and output after passing through PCB traces and high-speed analog switches. The test computer 170 measures the delay time of the start signal after passing through the bypass calibration path 132 and records it as the calibration value at the current temperature. Because the physical length of the bypass calibration path 132 is extremely short (<5mm), its temperature drift is negligible (<0.1ps / ℃). It reflects the temperature-dependent delay of the comparator, driver, and high-speed analog switch inside the controllable delay waveform generator at the current temperature.

[0095] Before formal testing, a full-temperature-range offline calibration procedure was performed: the integrated test PCB board was placed inside a programmable temperature control chamber 160, and the temperature was maintained at 10℃ increments within a range of -40℃ to 125℃ for 15 minutes at each temperature point. Delayed measurements were then performed under the calibration mode described above, and the calibration values ​​at each temperature point were recorded. The test computer 170 performed a cubic polynomial fitting on the 18 collected data points to obtain the temperature drift model:

[0096]

[0097] The coefficients a, b, c, and d are stored in the configuration file of the test computer 170.

[0098] During the formal testing phase (online application), the test computer 170 reads the current temperature fed back by the programmable temperature control box 160. The temperature drift model parameters a, b, c, and d are read from the configuration file and substituted into the above model to calculate the calibration value at the current temperature. The original time interval of the i-th measurement of the TDC under test. Compared with the actual time interval The relationship between them is: .

[0099] (ii) Calibration method based on simultaneous measurement of difference and linear fitting

[0100] In other embodiments of this application, a different calibration method is provided. Unlike the previous embodiments where the start signal is switched to the bypass calibration path and its absolute delay is measured, this embodiment sends the start signal to both the main delay chain 131 and the bypass calibration path 132 simultaneously and measures the time difference between the two outputs.

[0101] Specifically, in this embodiment, the trigger input of the controllable delay waveform generator 130 is connected to a signal distribution node, which is simultaneously connected to the input of the main delay chain 131 and the input of the bypass calibration path 132, allowing the same start signal to be transmitted along both paths simultaneously. The outputs of the main delay chain 131 and the bypass calibration path 132 are respectively connected to the two inputs of a time interval measurement unit (this time interval measurement unit can be an additional measurement channel inside the TDC under test, or a high-precision time-to-digital converter inside the test computer 170). This time interval measurement unit measures the time difference between the first pulse output by the main delay chain 131 and the second pulse output by the bypass calibration path 132. Since the physical length of the bypass calibration path 132 is extremely short, its delay is much smaller than the delay of the main delay chain 131 and can be ignored. Therefore, this time difference is the inherent delay value of the main delay chain 131 at the current temperature.

[0102] Before formal testing, a full-temperature calibration procedure was performed: the integrated test PCB board was placed inside a programmable temperature control chamber 160, and the steps of simultaneously measuring the time difference between the two outputs were repeated at multiple preset temperature points (e.g., -40℃, 25℃, 85℃, 125℃), recording the inherent delay value of the main delay chain 131 at each temperature point. The test computer 170 then fitted a linear model of the inherent delay of the main delay chain 131 as a function of temperature based on the collected data points.

[0103]

[0104] Where D0 is the inherent delay value at room temperature T0, and k is the temperature drift coefficient. D0 and k are stored in the configuration file of the test computer 170.

[0105] During the formal testing phase, the test computer 170 read the current temperature fed back by the programmable temperature control box 160. Substituting into the above linear model, the intrinsic delay value of the main delay chain 131 at the current temperature is calculated. This value is then subtracted from the original measurement time interval of the TDC under test as a calibration value to eliminate the error introduced by the test circuit's own delay due to temperature drift.

[0106] (III) Explanation of the commonalities and applicable scope of the two embodiments

[0107] Both calibration methods achieve the same goal—to obtain the inherent delay value of the test circuit at different temperatures and subtract it from the measurement result of the TDC under test, thereby eliminating the measurement error introduced by the temperature drift of the test circuit. The core difference between the two lies in:

[0108] The first embodiment (switching measurement) switches to the bypass calibration path via a two-to-one switch and measures its absolute delay. Combined with a cubic polynomial fitting model, it is suitable for scenarios with high calibration accuracy requirements and where the test computer has polynomial operation capabilities. Its advantages are high model fitting accuracy and the fact that only a two-to-one switch is needed for hardware implementation.

[0109] The second embodiment (simultaneous measurement of difference) directly obtains the inherent delay value of the main delay chain by simultaneously measuring the time difference between the outputs of the main delay chain and the bypass calibration path. Combined with a linear fitting model, it is suitable for scenarios with relatively abundant hardware resources (which can provide additional time interval measurement channels) and a small amount of calibration work. Its advantages are that the calibration process is intuitive and the model parameters are few.

[0110] Those skilled in the art can choose either of the two methods above to achieve full-temperature calibration based on actual hardware configuration and accuracy requirements, or combine the two methods (for example, using scheme A for high-precision direct measurement during offline calibration, and switching to scheme B for rapid calculation using the calibrated model during mass production online testing). All of these fall within the scope of protection of this application.

[0111] 4. Closed-loop correction algorithm

[0112] In some embodiments of this application, the test computer acquires the raw code values ​​output by the TDC. Then, make the correction according to the following formula:

[0113]

[0114] in: The actual time interval (true value) of the TDC under test is represented by LSB, which is the time resolution of the TDC itself (unit: ps). The temperature drift calculated based on the temperature drift model calibrated in step 3 at the current temperature. The inherent delay of the test circuit itself.

[0115] With this correction, the additional delay error introduced by the test circuit across the entire temperature range (-40℃ to 125℃) is controlled within ±3ps, and repeatability (based on the standard deviation of 10 measurements) is better than 1ps. In some other embodiments, the correction of the original code value based on the calibration value involves obtaining the calibration value at the current temperature. The raw code value obtained by the time-to-digital converter under test. Convert to time units to obtain the original time interval. Where LSB is the time resolution of the time-to-digital converter under test; from the original time interval Subtract the calibration value from the middle To obtain the actual time interval:

[0116] The actual performance parameters of the time-to-digital converter under test are determined based on the actual time interval.

[0117] It should be noted that the internal calibration path of the controllable delay waveform generator mentioned in point three above can directly use the waveform generator to generate adjustable delay waveforms.

[0118] Third, it is adapted to high and low temperature environment testing to achieve reliability verification of TDC timing parameters across the entire temperature range.

[0119] To achieve the effect described in the third point above, the following specific technical means are provided based on the concept of the above embodiments of this application:

[0120] 1. Fully integrated test circuit and temperature chamber adaptation design

[0121] The reference clock module, signal shaping and matching module, controllable delay waveform generator, and the TDC chip under test are all mounted on a single 8cm × 12cm PCB board. The entire board can be placed directly onto the tray of a standard high and low temperature test chamber (such as the ESPEC GPR-2 chamber, with internal effective dimensions of 30cm × 30cm × 25cm). The PCB board has four mounting holes for securing it to the internal support frame of the chamber using nylon supports, preventing vibration interference.

[0122] In terms of PCB layout, the controllable delay waveform generator, which generates a large amount of heat, and the temperature-sensitive reference clock module are placed on opposite sides of the board, with thermal isolation slots installed on the ground plane to reduce thermal coupling. No components are placed on top of the board to obstruct the airflow of the temperature chamber, ensuring temperature uniformity.

[0123] 2. Linkage control of temperature control modules (an example of a temperature control module is a programmable temperature control box).

[0124] The temperature control module uses a programmable high and low temperature test chamber with a temperature control range of -45℃ to 130℃, a temperature control accuracy of ±0.5℃, and a heating / cooling rate of ≥5℃ / min. The chamber connects to the test computer via an RS485 interface and communicates using the Modbus RTU protocol.

[0125] Test the computer's preset temperature profile, for example:

[0126] Step 1: Keep warm at 25℃ for 10 minutes, then perform the test.

[0127] Step 2: Maintain temperature at 85℃ for 15 minutes, then perform the test.

[0128] Step 3: Keep warm at 125℃ for 15 minutes, then perform the test. Step 4: Keep warm at -40℃ for 20 minutes, then perform the test.

[0129] Step 5: Incubate at 25℃ for 10 minutes, then perform a regression test (to verify reversibility).

[0130] At the end of each heat preservation stage, the programmable temperature control box sends a "temperature stable" flag to the test computer. Only after the computer receives the flag can it start the TDC test process to ensure that all measurements are performed in a thermal equilibrium state.

[0131] 3. Real-time calibration mechanism for the temperature drift of the test circuit itself.

[0132] The controllable delay waveform generator has an internal bypass calibration path, which consists of three extremely short PCB traces (total length <5mm) and a high-speed analog switch (such as Maxim's MAX4544). The calibration path is connected in parallel with the input of the main delay chain and in series with the output of a two-to-one switch.

[0133] Before the formal test begins at each temperature point, execute the following calibration subroutine:

[0134] Step 1: Switch the two-way switch to the calibration path.

[0135] Step 2: Send a narrow pulse with a width of 1ns to the controllable delay waveform generator.

[0136] Step 3: Measure the delay time of the pulse after it passes through the calibration path, and record it as D_cal_raw.

[0137] Step 4: Since the physical length of the calibration path is known and extremely short (<5mm), its own temperature drift is negligible (<0.1ps / ℃). Therefore, D_cal_raw mainly reflects the temperature-related delay of the comparator and driver inside the waveform generator.

[0138] Step 5: Switch the switch back to "Main Delay Chain" to officially begin the TDC test.

[0139] In actual testing, TDC No. The original time interval of the measurement Compared with the actual time interval The relationship between them is: ,in, This is the delay value measured at the current temperature for this calibration path.

[0140] 4. Offline calibration and online compensation of temperature drift model

[0141] Before using the newly manufactured test board for the first time, perform a full-temperature calibration procedure:

[0142] Place the test plate in an incubator and maintain the temperature at 10°C increments within the range of -40°C to 125°C for 15 minutes at each temperature point. Then, execute the calibration subroutine described above and record the results. ;

[0143] The collected data points (18 points in total) were fitted with a cubic polynomial to obtain the model:

[0144]

[0145] The coefficients a, b, c, and d (for example, the measured value is a = 2.1 × 10⁻) 5 b=1.3×10⁻³, c=2.8×10⁻², d=1250 (units are ps / ℃³, ps / ℃², ps / ℃, ps respectively) are stored in the configuration file of the test computer.

[0146] In actual testing, the computer reads the temperature fed back from the incubator in real time. Substitute into the model to calculate Then, the original output code value of each TDC is corrected according to the formula in Section 3.

[0147] 5. Complete test procedure for full-temperature reliability verification

[0148] Combining the above methods, the automated process for full-temperature range testing is as follows:

[0149] (1) Power on the system and initialize the test board and temperature chamber; (2) Heat the temperature chamber to 25°C and maintain the temperature for 10 minutes; (3) Execute the calibration subroutine and record the data. (25℃); (4) Perform TDC parameter tests (resolution, INL, DNL, ​​maximum range, etc.) and record the original data; (5) Correct the original data using the temperature drift model and output a room temperature test report; (6) Instruct the computer to raise the temperature of the chamber to 85℃ and repeat (2)-(5); (7) Instruct the temperature of the chamber to raise the temperature to 125℃ and repeat (2)-(5); (8) Instruct the temperature of the chamber to drop to -40℃ and repeat (2)-(5); (9) Instruct the temperature of the chamber to return to 25℃ and repeat (2)-(5) to verify whether the performance can be recovered (whether the high temperature / low temperature causes permanent damage); (10) Output a comprehensive test report for the entire temperature range, including the key TDC parameters and temperature drift curves at each temperature point.

[0150] In other words, the signal shaping and matching module of this proposed embodiment amplifies and shapes the low-dropout LVDS signal of the signal under test into a signal with a larger swing (for example, the technical means adopted in this application is to use a voltage comparator such as TLV3501 or a higher precision TLV3602 to convert the LVDS small signal into a 1.8V / 3.3V level), and shapes and impedance-matches the output edge to ensure that when the waveform generator samples the start signal, there is edge jitter due to the trigger threshold being too low (for example, the technical means adopted in this application is to use an adjustable threshold comparator circuit to convert the differential to single-ended or directly connect the signal to the P terminal for amplification, and to ensure that the signal transmission in the coaxial cable of the circuit board will not produce severe signal reflection through back-end impedance matching). The reference clock module: performs debouncing processing on the signal generated by the waveform generator to generate a more stable clock signal for the chip under test to sample and obtain low-jitter time measurement data. The temperature control module: is linked with the test circuit to realize controllable temperature change in the temperature range of -40℃ to 125℃, and is used to test the TDC temperature drift characteristics. The improvement of this application lies in the fact that all modules (signal shaping, waveform generator, clock chip, and chip under test) are on the same board, in the same temperature chamber, and share the same reference clock. The test computer can pre-calibrate the delay drift of the test circuit itself at various temperatures (e.g., by measuring the inherent delay of the waveform generator through an internal calibration path). During actual testing, the computer subtracts the contribution of the test circuit in real time based on the current temperature, thereby obtaining the true performance of the chip under test (TDC). In the original solution, because the external delay generator and the chip under test are not in the same temperature chamber, do not use the same clock, and the path length is uncertain and varies with temperature, it is impossible to achieve this level of accuracy correction.

[0151] It is not difficult to understand that, in some embodiments of this application, based on the above-described parameter testing circuit, the TDC parameter testing method includes the following steps:

[0152] Step S101: Power on the system and initialize the modules (reference clock module, signal shaping and matching module, controllable delay waveform generator) and programmable temperature control box on the integrated test PCB board.

[0153] Step S102: Place the integrated test PCB board inside the programmable temperature control chamber so that the test circuit and the TDC under test are in the same temperature environment; set the initial temperature of the programmable temperature control chamber to room temperature (e.g., 25°C), and after the internal temperature of the temperature control chamber reaches the set value and stabilizes, execute the subsequent test steps.

[0154] Step S103: The test computer controls the controllable delay waveform generator to output a series of stepped delay excitation signals from 0 to max Time (i.e., the delay time of the stop signal relative to the start signal gradually increases according to the preset step amount, covering the entire range) based on the maximum measurable time interval (max Time) of the TDC under test, as the time interval measurement excitation of the TDC under test.

[0155] Step S104: Under each step delay excitation, the TDC under test measures the time interval between the start signal and the stop signal and outputs the corresponding raw code value; the test computer synchronously acquires the raw code value output by the TDC under test.

[0156] Step S105: The test computer calculates the time resolution, differential nonlinearity (DNL), integral nonlinearity (INL), and accuracy error of the TDC under test based on the original code values ​​corresponding to each step delay collected.

[0157] Step S106: The test computer commands the programmable temperature control box to switch to multiple preset temperature points in sequence (e.g., -40℃, 25℃, 85℃, 125℃). After the TDC under test reaches thermal equilibrium at each temperature point for a preset time, steps S103 to S105 are repeated to obtain the original code value and parameter calculation results at each temperature point.

[0158] Step S107: The test computer uses the calibration path delay values ​​measured at each temperature point. Fit a temperature drift model (e.g., a cubic polynomial model) of the inherent delay of the test circuit as a function of temperature. ).

[0159] Step S108: The test computer performs closed-loop correction on the raw code values ​​collected at each temperature point according to the temperature drift model, eliminates the error introduced by the delay of the test circuit itself with temperature drift, and obtains the true performance parameters of the TDC under test at each temperature point.

[0160] Step S109: The test computer outputs a comprehensive test report covering the entire temperature range, including the time resolution, differential nonlinearity (DNL), integral nonlinearity (INL), accuracy error, and temperature drift characteristic curves of the TDC under test at each temperature point.

[0161] The stepped delay excitation generation method used in this application, although utilizing the delay triggering function of the waveform generator, differs from existing technical solutions in that: existing technical solutions only have an independent controllable delay waveform generator as an external instrument, and the waveform generated by it has jitter in the time domain, which usually requires the use of windowed FIR filters to eliminate jitter components; while in this application, the controllable delay waveform generator and the TDC under test share the same low-temperature drift and low-jitter reference clock module, eliminating relative phase drift. Furthermore, the controllable delay waveform generator, the signal shaping and matching module, and the TDC under test are integrated on the same PCB board and placed inside a temperature-controlled chamber. With the real-time calibration and closed-loop correction algorithm of the bypass calibration path, the delay error and temperature drift of the signal link are fundamentally reduced, and high-precision test results can be obtained without the need for additional filtering methods.

[0162] Some embodiments of this application provide an all-flash storage system, including: a storage controller comprising a system-on-a-chip as described above; a plurality of non-volatile solid-state drives (SSDs); wherein the DMA controller is configured to perform data migration and backup operations between different SSDs in automatic read / write mode.

[0163] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0164] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0165] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0166] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application. It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0167] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0168] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A parameter testing circuit for a time-to-digital converter, characterized in that, The parameter testing circuit includes: The signal shaping and matching module has an input terminal used to receive the start signal output by the time-to-digital converter under test; A controllable delay waveform generator, with its input terminal connected to the output terminal of the signal shaping and matching module, is used to generate a stop signal with a controllable delay relative to the start signal, and output the stop signal to the stop signal input terminal of the time-to-digital converter under test; The reference clock module has its output terminal connected to the reference clock input terminal of the controllable delay waveform generator and the sampling clock input terminal of the time-to-test digital converter, respectively, and is used to provide the same clock signal to the controllable delay waveform generator and the time-to-test digital converter. The reference clock module, the signal shaping and matching module, and the controllable delay waveform generator are all located on the same printed circuit board.

2. The parameter testing circuit as described in claim 1, characterized in that, The signal shaping and matching module includes: A differential amplifier is connected to the start signal output terminal of the time-to-digital converter under test and the output terminal of the reference clock module, respectively, and is used to convert the differential signal output by the time-to-digital converter under test into a single-ended signal. The first comparator, connected to the output of the differential amplifier, is used to shorten the edge rise time of the single-ended signal and perform level conversion.

3. The parameter testing circuit as described in claim 2, characterized in that, The signal shaping and matching module further includes: An adjustable threshold voltage circuit is connected to the reference voltage input terminal of the first comparator to provide an adjustable comparison threshold voltage. An impedance matching resistor is connected to the output of the first comparator to achieve impedance matching with the input of the controllable delay waveform generator.

4. The parameter testing circuit as described in any one of claims 1-3, characterized in that, The controllable delay waveform generator includes: a main delay chain and a bypass calibration path; The main delay chain includes a tapped delay chain composed of multiple inverters, used to generate adjustable delay pulse signals; The bypass calibration path is a PCB trace path; The input terminal of the bypass calibration path is connected in parallel with the input terminal of the main delay chain to receive the same start signal; the output terminal of the main delay chain and the output terminal of the bypass calibration path are respectively connected to the first input terminal and the second input terminal of the two-to-one switch, and the common output terminal of the two-to-one switch serves as the output terminal of the controllable delay waveform generator.

5. The parameter testing circuit as described in claim 1, characterized in that, The parameter testing circuit also includes: A programmable temperature control box, wherein the printed circuit board is disposed inside the programmable temperature control box, for the purpose of placing the parameter testing circuit and the time-to-be-tested digital converter in the same temperature environment; The control and data processing module is communicatively connected to the controllable delay waveform generator, and is used to send a delay step control signal to the controllable delay waveform generator and receive the digital code value output by the time-to-measure digital converter; the control and data processing module is also used to communicate with the programmable temperature control box, receive the temperature value fed back by the programmable temperature control box, and correct the digital code value according to the temperature value.

6. A method for testing parameters of a time-to-digital converter, executed by the parameter testing circuit according to any one of claims 1 to 5, characterized in that, The parameter testing method includes: The programmable temperature control box can adjust the ambient temperature of the printed circuit board to several different preset temperature values. During the isothermal phase at each preset temperature value, obtain the calibration value of the inherent delay of the parameter test circuit itself at the current temperature; The controllable delay waveform generator is controlled to generate a stop signal with a progressive delay relative to the start signal, wherein the start signal comes from the time-to-digital converter under test, and the progressive delay means that the delay time of the stop signal relative to the start signal gradually increases according to a preset step amount; The time-to-measure digital converter is driven to measure the time interval between the start signal and the stop signal to obtain the raw code value, wherein the raw code value is used to characterize the digital mapping result of the physical time interval between the start signal and the stop signal; The original code value is corrected based on the calibration value to eliminate the error introduced by the delay of the parameter test circuit itself due to temperature drift, so as to obtain the true performance parameters of the time-to-digital converter under test.

7. The parameter testing method as described in claim 6, characterized in that, The step of correcting the original code value based on the calibration value includes: The calibration value is subtracted from the original time interval measured by the time-to-digital converter under test to obtain the true time interval of the time-to-digital converter under test, thereby correcting the measurement results.

8. The parameter testing method as described in claim 6, characterized in that, Before controlling the controllable delay waveform generator to generate a stop signal with a progressive delay relative to the start signal, the method further includes: The original start signal is generated by the time-to-be-tested digital converter. After the original start signal is level-converted, edge-shaped and impedance-matched by the signal shaping and matching module, it is sent to the trigger input terminal of the controllable delay waveform generator. The controllable delay waveform generator generating a stop signal with a progressive delay relative to the start signal includes: The controllable delay waveform generator uses the clock provided by the reference clock module as a reference clock, and in response to the start signal, generates a stop signal with adjustable delay and outputs it to the time-to-measure digital converter.

9. The parameter testing method as described in claim 6, characterized in that, During the isothermal phase at each preset temperature value, a calibration value reflecting the inherent delay of the parameter testing circuit at the current temperature is obtained, including: Read the current temperature fed back by the programmable temperature control box ; Substituting the current temperature into the temperature drift model, the delay value at the current temperature is calculated and used as the calibration value for the inherent delay of the parameter test circuit corresponding to the current temperature.

10. The parameter testing method according to claim 9, characterized in that, Before substituting the current temperature into the temperature drift model to calculate the delay value at the current temperature, the parameter testing method further includes: Within a preset temperature range, with predetermined temperature steps, after holding at each temperature point for a predetermined time, a calibration step is performed, the calibration step including: Switch the two-way switch inside the controllable delay waveform generator to the bypass calibration path; Send a first pulse to the controllable delay waveform generator; The delay time of the first pulse after passing through the bypass calibration path is measured and recorded as the delay value at the current temperature point. ; After completing the measurements at all temperature points, the delay values ​​at each temperature point are used as a basis. By performing a polynomial fit on the following functional expression, the temperature drift model of calibration delay as a function of temperature is obtained: The parameters a, b, c, and d of the temperature drift model are stored in a configuration file.

11. The parameter testing method according to claim 8, characterized in that, The original code value is corrected based on the calibration value: Obtain the calibration value at the current temperature. ; The raw code value measured by the time-to-measure digital converter Convert to time units to obtain the original time interval. , where LSB is the time resolution of the time-to-digital converter under test; From the original time interval Subtract the calibration value from the middle To obtain the actual time interval: ； The actual performance parameters of the time-to-digital converter under test are determined based on the actual time interval.

Images