Fast wave envelope control method, cascade control system and storage medium

Abstract

The application discloses a quick wave blocking control method, a cascade control system and a storage medium, and comprises the following steps: when a first controller judges a fault signal, the fault signal indicating that a normal data packet received from any first link judges a communication fault, a wave blocking data packet is generated according to the fault signal, and the first controller sends the wave blocking data packet to each second controller connected thereto, wherein the data packet structure of the wave blocking data packet at least comprises a packet header section and a data content section arranged in sequence, and the wave blocking data packet is provided with a wave blocking identifier in the packet header section; any second controller receives a data packet, analyzes the packet header section in the data packet, and when the packet header section has the wave blocking identifier, the received data packet is the wave blocking data packet, the wave blocking data packet is first sent to a third controller connected thereto, and then the data content section in the wave blocking data packet is analyzed, so that the wave blocking response time is greatly shortened, the system is ensured to be stably and reliably operated, and the maintenance cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of communication technology for cascaded energy storage systems, and particularly to a fast wave blocking control method, a cascaded control system, and a storage medium. Background Technology

[0002] Cascaded energy storage systems typically include multiple cascaded arms and a cascaded control system. Cascaded arms are composed of multiple power units connected sequentially, while the cascaded control system adopts a multi-level communication architecture. The cascaded control system typically includes multiple levels such as control boards, arm boards, adapter boards, and power control boards. The control board is connected to multiple arm boards one-to-one through multiple sets of communication links. The arm boards are connected to multiple adapter boards one-to-one through multiple sets of communication links. The adapter boards are then connected to multiple power control boards one-to-one through multiple sets of communication links. The power control boards are connected to the power units one-to-one. The communication links typically have uplink and downlink communication links.

[0003] During normal operation, the boards transmit data packets at a fixed communication cycle (e.g., 50 microseconds). The data packets are used to carry control instructions such as PWM instructions or operating status information such as status monitoring.

[0004] When any communication link fails or a board malfunctions, after detecting the communication fault, feedback data packets need to be transmitted upwards level by level. Each level needs to parse the data packets and transmit them upwards, which takes approximately one complete communication cycle. Finally, the control board sends out blocking commands layer by layer to control each power control board to stop outputting PWM modulation waves and stop the operation of each power unit. For example, when any bridge arm board detects a communication fault, the entire process needs to go through: bridge arm board → control board → bridge arm board → adapter board → power control board. Theoretically, it should take at least four communication cycles, but in reality, due to factors such as software scheduling, interrupt response, and task priority, it will take longer.

[0005] During this delay, the current output by the cascaded energy storage system may reach several times the rated value due to the continuous increase in inductor current, exceeding the short-circuit withstand capability of power devices such as IGBTs or MOSFETs, leading to device burnout and significantly increasing maintenance costs. Summary of the Invention

[0006] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a fast wave blocking control method and a cascaded control system and storage medium to shorten the wave blocking response time, ensure stable and reliable system operation, and reduce maintenance costs.

[0007] According to a first aspect of the present invention, a fast blocking control method is applied to a cascaded control system. The cascaded control system includes at least a plurality of first controllers, a plurality of second controllers, and a plurality of third controllers. The first controllers and the second controllers, as well as the second controllers and the third controllers, are connected via communication link groups. Each communication link group includes a first link and a second link, both capable of transmitting data. The first controllers, second controllers, and third controllers communicate by transmitting normal data packets to achieve control or information feedback actions. The normal data packet structure includes at least a header segment and a data content segment arranged sequentially. The fast blocking control method includes... The process includes: when the first controller determines a fault signal, which indicates a communication failure based on normal data packets received from any first link, a blocking data packet is generated according to the fault signal. The first controller sends the blocking data packet to each connected second controller. The data packet structure of the blocking data packet includes at least a header segment and a data content segment set sequentially. The header segment of the blocking data packet contains a blocking identifier. Each second controller receives a data packet, parses the header segment of the data packet, and if the header segment contains a blocking identifier, the received data packet is a blocking data packet. The blocking data packet is first sent to the connected third controller, and then the data content segment of the blocking data packet is parsed.

[0008] The fast wave blocking control method according to embodiments of the present invention has at least the following beneficial effects: This invention provides a fast blocking control method. During normal operation, the first, second, and third controllers transmit normal data packets to achieve control or information feedback actions. When any controller detects a fault signal, taking the first controller as an example, it generates a blocking data packet and sends it to any connected controller, such as the second controllers. Since the blocking data packet has a blocking identifier in its header, the second controller parses the blocking data packet sequentially. The blocking identifier can be obtained during the header parsing, eliminating the need for full parsing of the blocking data packet, and the blocking data packet can be sent out to the third controllers. Thus, each of the first, second, and third controllers can send blocking data packets after being triggered, and the transmission between any two controllers does not consume the entire communication cycle, significantly shortening the blocking response time, ensuring stable and reliable system operation, and reducing maintenance costs.

[0009] According to some embodiments of the present invention, the fast blocking control method further includes: when a second controller determines a fault signal, the fault signal indicating a communication failure in the second link with any one of the first controllers, a blocking data packet is generated based on the fault signal; the second controller sends the blocking data packet to each of the connected first controllers and each of the connected third controllers; each of the first controllers receives the data packet, parses the header segment of the data packet, and if the header segment contains a blocking identifier, the received data packet is a blocking data packet; the blocking data packet is first sent to other connected second controllers, and then the data content segment of the blocking data packet is parsed; wherein, the other connected second controllers are all second controllers other than the second controller that sent the blocking data packet.

[0010] According to some embodiments of the present invention, the first controller sending the sealing data packet to each of the connected second controllers, or the second controller sending the sealing data packet to each of the connected first controllers and each of the connected third controllers, includes: sending N sealing data packets, with a first interval time between two adjacent sealing data packets.

[0011] According to some embodiments of the present invention, the first controller sending the sealing data packets to each of the connected second controllers, or the second controller sending the sealing data packets to each of the connected first controllers and each of the connected third controllers, includes: sending K sealing data packets, with a first interval time between two adjacent sealing data packets; after a second interval time, sending M sealing data packets, with a first interval time between two adjacent sealing data packets, wherein the second interval time is greater than the first interval time.

[0012] According to some embodiments of the present invention, after receiving a blocking data packet and determining that the packet header segment contains a blocking identifier by parsing the packet header segment of the blocking data packet, a blocking confirmation signal is formed and sent to the first controller or the second controller that sent the blocking data packet; after receiving the blocking confirmation signal, the first controller or the second controller stops sending the blocking data packet.

[0013] According to some embodiments of the present invention, the data packet structure of the normal data packet further includes a data length segment and a check segment, and the data content segment of the normal data packet includes control signal content or operating status content. In the data packet structure of the normal data packet, the header segment, data length segment, data content segment, and check segment are arranged sequentially. The data packet structure of the blocking data packet further includes a data length segment and a check segment, and the data content segment of the blocking data packet includes a fault address segment, a fault type segment, and an extended content segment. The header segment, data length segment, fault address segment, fault type segment, extended content segment, and check segment are arranged sequentially.

[0014] According to some embodiments of the present invention, a first value is set in the header segment of the normal data packet, and a second value is set in the header segment of the blocked data packet, wherein the second value is different from the first value to define the blocked identifier.

[0015] According to the cascaded control system of the second aspect of the present invention, the fast wave blocking control method disclosed in any of the above embodiments is executed.

[0016] The cascaded control system according to embodiments of the present invention has at least the following beneficial effects: The cascaded control system of the present invention applies the fast blocking control method disclosed in any of the above embodiments. Each first controller, second controller and third controller can send blocking data packets after being triggered. Moreover, the transmission between any two controllers does not require the entire communication cycle, which greatly shortens the blocking response time, ensures the stable and reliable operation of the system and reduces maintenance costs.

[0017] According to some embodiments of the present invention, when the third controller is a power controller, the power controller is used to connect to the controlled end of the power unit in the cascaded bridge arm. The normal data packet received by the power controller includes control signal content. The power controller outputs a PWM modulation wave according to the control signal content to control the operation of the power unit. When the power controller receives a blocked data packet and determines that there is a blocked identifier in the packet header segment by parsing the packet header segment in the blocked data packet, it stops outputting the PWM modulation wave.

[0018] According to a third aspect of the present invention, a computer-readable storage medium stores a computer program, characterized in that, when executed by a processor, the computer program implements the fast wave blocking control method disclosed in any of the above embodiments.

[0019] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the principle structure of one embodiment of the cascaded control system of the present invention; Figure 2 This is a first flowchart of one embodiment of the fast wave blocking control method of the present invention; Figure 3 This is a second flowchart of one embodiment of the fast wave blocking control method of the present invention.

[0021] Figure label: Control board 100; bridge arm board 200; adapter board 300; power control board 400; power unit 500; communication link group 800. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0024] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0026] like Figure 1 , 2 As shown, the fast blocking control method according to a first aspect of the present invention is applied to a cascaded control system. The cascaded control system includes at least a plurality of first controllers, a plurality of second controllers, and a plurality of third controllers. The first controllers and the second controllers, as well as the second controllers and the third controllers, are connected via communication link groups. Each communication link group includes a first link and a second link, both capable of transmitting data. The first controllers, second controllers, and third controllers transmit normal data packets to achieve control or information feedback actions. The structure of the normal data packet includes at least a header segment and a data content segment arranged sequentially. The fast blocking control method includes: S610. When the first controller determines that a fault signal is detected, the fault signal indicates that a communication fault is detected from the normal data packet received from any first link. Then, a blocking data packet is generated according to the fault signal. The first controller sends the blocking data packet to each connected second controller. The data packet structure of the blocking data packet includes at least a header segment and a data content segment set in sequence. The header segment of the blocking data packet is set with a blocking identifier. S620. Any second controller receives a data packet, parses the header segment of the data packet, and if the header segment contains a blocking identifier, the received data packet is a blocking data packet. First, the blocking data packet is sent to the connected third controller, and then the data content segment of the blocking data packet is parsed.

[0027] In a cascaded control system, there are usually multiple levels, including control boards, bridge arm boards, adapter boards, and power control boards. The control boards are connected to multiple bridge arm boards one-to-one through multiple sets of communication links. The bridge arm boards are connected to multiple adapter boards one-to-one through multiple sets of communication links. The adapter boards are then connected to multiple power control boards one-to-one through multiple sets of communication links. The power control boards are connected to the power units one-to-one.

[0028] It is understandable that a cascaded control system may also include a fourth controller or even more, with the third and fourth controllers connected via a communication link group 800. The fourth controller may also execute a fast wave blocking control method.

[0029] The control board 100, bridge arm plate 200, adapter plate 300, and power control board 400 can all be any one of the first controller, second controller, third controller, and fourth controller. For example, the control board 100 can be the first controller, the bridge arm plate 200 can be the second controller, the adapter plate 300 can be the third controller, and the power control board 400 can be the fourth controller; or, the control board 100 can be the fourth controller, the bridge arm plate 200 can be the third controller, the adapter plate 300 can be the second controller, and the power control board 400 can be the first controller; or, the control board 100 can be the first controller, one of the bridge arm plates 200 can be the second controller, and the other bridge arm plate 200 can be the third controller. These are not all listed here. The communication link group 800 can be composed of a data bus, which can integrate multiple transmission links, including a first link and a second link. The first link and the second link can be an uplink communication link and a downlink communication link, respectively. For example, if the first link is an uplink communication link, then the second link is a downlink communication link, and if the first link is a downlink communication link, then the second link is an uplink communication link.

[0030] In the case where the first controller detects a fault signal, it can determine whether a fault has occurred by receiving normal data packets and then verifying the integrity of the data packets, or by detecting the continuity of the link transmission signal.

[0031] In some embodiments of the present invention, a first value is set in the header segment of the normal data packet, and a second value is set in the header segment of the blocked data packet. The second value is different from the first value to define the blocked identifier.

[0032] The header segments of normal data packets and blocking data packets are typically 1 byte long. 0x01 represents the first value of the header segment of normal data packets, and 0x02 represents the second value of the header segment of blocking data packets, thus defining the blocking identifier. If the controller parses the different values ​​of the header segments, it can quickly determine that it is a blocking data packet.

[0033] Furthermore, other header segment values ​​can be defined, for example, 0x03 indicates an emergency shutdown and 0x04 indicates a system self-test request, so that the terminal controller can quickly execute the corresponding operation.

[0034] Understandably, if the communication cycle between the controllers is 50 microseconds, in this application, the time it takes for the second controller to receive the data packet, parse the packet header, and determine that it is a blocking data packet is approximately 10 microseconds. When the third controller receives the data packet, parses the packet header, and determines that it is a blocking data packet, it takes only about 20 microseconds. Compared to the traditional 100 microseconds for two complete cycles, the time is significantly shortened.

[0035] This invention provides a fast blocking control method. During normal operation, the first, second, and third controllers transmit normal data packets to achieve control or information feedback actions. When any controller detects a fault signal, taking the first controller as an example, it generates a blocking data packet and sends it to any connected controller, such as the second controllers. Since the blocking data packet has a blocking identifier in its header, the second controller parses the blocking data packet sequentially. The blocking identifier can be obtained during the header parsing, eliminating the need for full parsing of the blocking data packet, and the blocking data packet can be sent out to the third controllers. Thus, each of the first, second, and third controllers can send blocking data packets after being triggered, and the transmission between any two controllers does not consume the entire communication cycle, significantly shortening the blocking response time, ensuring stable and reliable system operation, and reducing maintenance costs.

[0036] In some embodiments of the present invention, such as Figure 3 As shown, the fast wave blocking control method also includes: S710. When the second controller determines that a fault signal has occurred, the fault signal indicates that a communication failure has occurred in the second link with any of the first controllers. Then, a sealing data packet is generated according to the fault signal, and the second controller sends the sealing data packet to each of the connected first controllers and each of the connected third controllers. S720. Any first controller receives a data packet, parses the header segment of the data packet, and if the header segment contains a blocking identifier, the received data packet is a blocking data packet. The blocking data packet is first sent to other connected second controllers, and then the data content segment of the blocking data packet is parsed. The other connected second controllers are all the second controllers other than the second controller that sent the blocking data packet.

[0037] It is understandable that the solution in this application adopts a multi-point triggering method for sending sealing data packets. After any controller detects a fault signal and generates a sealing data packet, it can send the sealing data packet to all other controllers connected to that controller.

[0038] When the first controller receives the blocking data packet sent by the second controller, after parsing the blocking identifier in the packet header, it can send the blocking data packet to each second controller other than the second controller that sent the blocking data packet, as well as other connected controllers.

[0039] When the third controller is a terminal controller, such as a power control board, the output of the PWM modulation wave stops after the packet header segment has a blocking indicator.

[0040] In some embodiments of the present invention, the first controller sending the sealing data packet to each of the connected second controllers, or the second controller sending the sealing data packet to each of the connected first controllers and each of the connected third controllers, includes: sending N sealing data packets, with a first interval time between two adjacent sealing data packets.

[0041] To ensure that the sealing data packets can be completely received by the receiving controller, so that the sealing data packets can be transmitted stably, specifically, N can be 2, 3, 5, 10, etc., and the first interval time can be 10 microseconds, 20 microseconds, etc., which can be set by the user according to the actual situation.

[0042] To prevent the transmission of sealing data packets from failing to be accurately delivered when the communication link group is occupied, in some embodiments of the present invention, the first controller sends the sealing data packets to each connected second controller, or the second controller sends the sealing data packets to each connected first controller and each connected third controller, including: Send K sealing data packets, with a first interval between each two adjacent sealing data packets; After the second interval, M more sealing data packets are sent. The first interval is between two adjacent sealing data packets. The second interval is longer than the first interval.

[0043] After sending multiple blocking data packets at the first interval, pause for the second interval. If the communication link group was occupied in the early stage, the second interval can wait for the communication link group to return to an idle state before sending multiple blocking data packets again. Specifically, K can be 3, 5, etc., M can be 2, 3, etc., the first interval can be 10 microseconds, 20 microseconds, etc., and the second interval can be 40, 50 microseconds.

[0044] In some embodiments of the present invention, after receiving the blocking data packet and determining that the packet header segment contains a blocking identifier by parsing the packet header segment of the blocking data packet, a blocking confirmation signal is formed and sent to the first controller or the second controller that sent the blocking data packet; after receiving the blocking confirmation signal, the first controller or the second controller stops sending the blocking data packet.

[0045] It is understandable that when a blocking data packet is received and the blocking identifier is found in the packet header segment by parsing the packet header segment, a blocking confirmation signal is also sent to the first or second controller that sent the blocking data packet while sending the blocking data packet to other connected controllers. This indicates that the blocking data packet has been received and the corresponding blocking action has been triggered. The first or second controller responsible for sending the blocking data packet does not need to continue sending blocking data packets, thus reducing redundancy.

[0046] In some embodiments of the present invention, the data packet structure of the normal data packet further includes a data length segment and a check segment, and the data content segment of the normal data packet includes control signal content or running status content. In the data packet structure of the normal data packet, the header segment, data length segment, data content segment and check segment are arranged in sequence. The data length segment is 1 byte, the data content segment includes control signal content such as PWM duty cycle and running status content such as status information, and the check segment is 2 bytes, which is used for data verification of normal data packets.

[0047] The packet structure of the blocking data packet also includes a data length segment and a check segment. The data content segment of the blocking data packet includes a fault address segment, a fault type segment, and an extended content segment. The packet header segment, data length segment, fault address segment, fault type segment, extended content segment, and check segment are set in sequence.

[0048] The data length segment is 1 byte, the data content segment includes the fault source address, fault type, etc., and can also record extended information through the fault type segment. The check segment is 2 bytes and is used for data verification of the blockade data packet.

[0049] Specifically, the fault address field is 2 bytes. When any controller determines that a fault triggers the rapid blocking step, it writes its unique identifier in the system (such as hierarchical code + board ID) into this field. Other controllers, upon receiving the data, can optionally record this address for the host computer to quickly locate the initial fault point. If the blocking data packet is forwarded from a higher level, this field retains the address of the original triggerer, and the forwarding controller must not overwrite it. The fault type field is 1 byte, indicating the specific reason for triggering the blocking, for example: 0x01: communication link interruption; 0x02: output overcurrent; 0x03: board overtemperature; 0x04: power supply undervoltage / overvoltage; 0x05: driver fault; 0x06: core logic CRC error; 0x07~0xFF: reserved for user customization; the extended content field is 2 bytes, for supporting the development of other functions. For example: Bit 0: extended packet type indicator (0=current version, 1=extended version); Bits 1~7: reserved, the remaining bytes can be used to carry extended information such as timestamps and fault severity levels.

[0050] Once the fault is cleared, the host computer sends a reset data packet through the control board. The header value of the reset data packet can be 0x03. The reset data packet uses the same forwarding mechanism as the PWM blocking data packet and is quickly sent to each controller, enabling the PWM modulation waveform of the terminal controller (power controller) to be enabled again.

[0051] According to the cascaded control system of the second aspect of the present invention, the fast wave blocking control method disclosed in any of the above embodiments is executed.

[0052] The cascaded control system of the present invention applies the fast blocking control method disclosed in any of the above embodiments. Each first controller, second controller and third controller can send blocking data packets after being triggered. Moreover, the transmission between any two controllers does not require the entire communication cycle, which greatly shortens the blocking response time, ensures the stable and reliable operation of the system and reduces maintenance costs.

[0053] In some embodiments of the present invention, when the third controller is a power controller, the power controller is used to connect to the controlled end of the power unit 500 in the cascaded bridge arm. The normal data packet received by the power controller includes control signal content. The power controller outputs a PWM modulation wave according to the control signal content to control the operation of the power unit 500. When the power controller receives a blocking data packet and finds that there is a blocking identifier in the packet header segment by parsing the packet header segment in the blocking data packet, it stops outputting the PWM modulation wave.

[0054] According to a third aspect of the present invention, a computer-readable storage medium stores a computer program, characterized in that, when executed by a processor, the computer program implements the energy storage calibration control method disclosed in any of the above embodiments.

[0055] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0056] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0057] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0058] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0059] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0060] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0061] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

[0062] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0063] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A fast wave-blocking control method is applied to a cascaded control system, which includes at least several first controllers, several second controllers, and several third controllers. The first controllers and second controllers, as well as the second controllers and third controllers, are connected via communication links. The communication link group includes a first link and a second link, both capable of transmitting data. The first controller, the second controller, and the third controller communicate by transmitting normal data packets to achieve control or information feedback actions. The normal data packet structure includes at least a header segment and a data content segment arranged sequentially. The fast blocking control method includes: When the first controller determines a fault signal, which indicates a communication failure based on the normal data packets received from any first link, a blocking data packet is generated according to the fault signal. The first controller sends the blocking data packet to each connected second controller. The data packet structure of the blocking data packet includes at least a header segment and a data content segment set sequentially. The header segment of the blocking data packet is equipped with a blocking identifier. Any second controller receives a data packet, parses the header segment of the data packet, and if the header segment contains a blocking identifier, the received data packet is a blocking data packet. The blocking data packet is first sent to the connected third controller, and then the data content segment of the blocking data packet is parsed.

2. The fast wave blocking control method according to claim 1, characterized in that, Also includes: When the second controller determines a fault signal, which indicates a communication failure in the second link with any of the first controllers, it generates a sealing data packet based on the fault signal and sends the sealing data packet to each of the connected first controllers and each of the connected third controllers. Any first controller receives a data packet, parses the header segment of the data packet, and if the header segment contains a blocking identifier, the received data packet is a blocking data packet. The blocking data packet is first sent to other connected second controllers, and then the data content segment of the blocking data packet is parsed. The other connected second controllers are all the second controllers other than the second controller that sent the blocking data packet.

3. The fast wave blocking control method according to claim 1, characterized in that, The first controller sending the sealing data packet to each of the connected second controllers, or the second controller sending the sealing data packet to each of the connected first controllers and each of the connected third controllers, includes: Send N sealing wave data packets, with a first interval between each pair of adjacent sealing wave data packets.

4. The fast wave blocking control method according to claim 1, characterized in that, The first controller sending the sealing data packet to each of the connected second controllers, or the second controller sending the sealing data packet to each of the connected first controllers and each of the connected third controllers, includes: Send K sealing data packets, with a first interval between each two adjacent sealing data packets; After the second interval, M more sealing data packets are sent. The first interval is between two adjacent sealing data packets. The second interval is longer than the first interval.

5. The fast wave blocking control method according to claim 3 or 4, characterized in that, After receiving the blocking data packet and parsing the packet header segment to find that the packet header segment contains a blocking identifier, a blocking confirmation signal is generated and sent to the first controller or the second controller that sent the blocking data packet. After receiving the blocking confirmation signal, the first or second controller stops sending blocking data packets.

6. The fast wave blocking control method according to claim 1, characterized in that, The data packet structure of the normal data packet also includes a data length segment and a check segment. The data content segment of the normal data packet includes control signal content or operating status content. In the data packet structure of the normal data packet, the header segment, data length segment, data content segment and check segment are set in sequence. The packet structure of the blocking data packet also includes a data length segment and a check segment. The data content segment of the blocking data packet includes a fault address segment, a fault type segment, and an extended content segment. The packet header segment, data length segment, fault address segment, fault type segment, extended content segment, and check segment are set in sequence.

7. The fast wave blocking control method according to claim 1, characterized in that, A first value is set in the header segment of the normal data packet, and a second value is set in the header segment of the blocked data packet. The second value is different from the first value to define the blocked identifier.

8. A cascaded control system, characterized in that, Perform the fast blocking control method as described in any one of claims 1 to 7.

9. The cascaded control system according to claim 8, characterized in that, When the third controller is a power controller, the power controller is used to connect to the controlled end of the power unit in the cascaded bridge arm. The normal data packet received by the power controller includes control signal content. The power controller outputs a PWM modulation wave according to the control signal content to control the operation of the power unit. When the power controller receives the PWM modulation data packet and determines that the packet header segment contains a PWM identifier by parsing the packet header segment of the PWM modulation data packet, it stops outputting the PWM modulation wave.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the fast wave blocking control method according to any one of claims 1 to 7.

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