Control system architecture for micro- and nanoscale real-time motion control

Abstract

The application discloses a control system architecture for micro-nano real-time motion control, comprising a function module and a system bus; the system bus comprises a signaling / status bus, a data exchange bus and a servo synchronization interrupt bus; the signaling / status bus is used for system configuration issuing and system state information reporting; the data exchange bus is used for system real-time data receiving and sending; and the servo synchronization interrupt bus is used for system control period timing interrupt, and realizes timing information transmission in the form of direct interrupt. The application adopts the signaling / status bus and the data exchange bus architecture, simplifies the servo synchronization mechanism, trims redundant functions, simplifies the system bottom design, improves the processing performance of key nodes, realizes a higher servo interrupt period, and enables the system architecture to be applied to more precise real-time motion control.

Description

Technical Field

[0001] This invention belongs to the field of motion control system technology, specifically relating to a control system architecture for real-time motion control at the micro-nano level. Background Technology

[0002] Currently, general-purpose motion control systems suffer from problems such as insufficient computing power, low data exchange rate, closed underlying drivers, insufficient peripheral interfaces, and excessive redundant functions when applied to micro- and nano-level motion control scenarios, making it difficult to meet the motion control requirements of lithography machine wafer scanners.

[0003] General motion control systems typically employ a VME bus architecture, such as Figure 1 As shown, its main control CPU is a PowerPC with a maximum clock speed of 1.2GHz, a 4-core (e500mc) 32-bit architecture; the digital signal processor is a TI DSP with a maximum clock speed of 800MHz and 8 cores; the main high-speed data bus is SRIO x1, under the control of the system timing synchronization signal, the various boards in the system perform high-speed data interaction based on this bus.

[0004] The micro / nano real-time motion control software designed based on this general-purpose motion control system primarily performs data computations on two nodes: the CPU and the DSP. The CPU mainly handles process scheduling and flow control based on the host computer's control, while the DSP performs real-time motion control calculations. The CPU has a relatively low clock speed, core count, and bit width, resulting in low real-time computing performance. It exchanges data with other parts of the system only through a single 5Gbps SRIO x1 high-speed data interface, leading to a low data exchange rate. The DSP, in addition to handling real-time motion control calculations, also performs routine drive control and corresponding data interaction processing for the two upstream and downstream SRIO x1 interfaces. The simultaneous operation of these two data interfaces and real-time motion control calculations increases the complexity of DSP resource scheduling and reduces computational performance.

[0005] The high-speed data exchange between components within the general-purpose system, as well as the external sensor data acquisition and drive data transmission, all utilize the SRIO x1 data bus with a line rate of 5Gbps, meaning a theoretical peak bus bandwidth of 500M bytes. The core data exchange network designed around the SRIO switching chip, such as... Figure 2 As shown, the surrounding nodes are all devices with processor architectures such as CPUs and DSPs (Von Neumann or Harvard architecture). In actual data exchange, data processing efficiency is closely related to real-time resource scheduling. When performing real-time calculations simultaneously, data exchange efficiency drops significantly. Furthermore, this system architecture often uses time-division multiplexing mechanisms to implement various resource scheduling, which is poorly adaptable to data exchange scenarios with sudden large data volumes, often resulting in occasional errors or data loss, and low system stability.

[0006] When the system acquires sensor data and sends driver data to external systems, it also affects the system's I / O performance, reducing one of the important indicators of the control system—control bandwidth. Furthermore, the PowerPC and DSP underlying drivers of general-purpose systems are secondary encapsulated function libraries with closed source code, making problem tracking, analysis, and resolution difficult. This also hinders the development of customized optimization functions, becoming a bottleneck for the application.

[0007] The motion control system of a lithography machine requires the integration of various sensors, including position, speed, image, force, and photoelectric sensors. The number of these sensors is also significant, resulting in a severe shortage of general-purpose system peripheral interfaces. Furthermore, the shared memory space allocated to each interface within the DSP is a fixed value and cannot be modified, leading to poor overall system interface scalability. Additionally, the general-purpose system design prioritizes versatility across various application scenarios, resulting in many redundant system functions that can be removed, consuming CPU resources and impacting system performance.

[0008] Considering the above factors, the servo control cycle of the real-time motion control system built on the general motion control system can only reach 5kHz. However, in the micro-nano real-time motion control scenario, the servo control cycle needs to be higher, and the general motion control system can no longer be optimized to meet the needs of micro-nano real-time motion control of lithography machines. Summary of the Invention

[0009] The purpose of this invention is to provide a control system architecture for real-time motion control at the micro-nano level, so as to solve the problems of insufficient computing power and low data exchange rate of general motion control systems when applied to real-time motion control systems at the micro-nano level.

[0010] This invention is achieved through the following technical solution: A control system architecture for real-time motion control at the micro- and nano-scale, including functional modules and a system bus; The functional modules include a lower-level master computer, a motion control module, an SRIO switching module, a clock synchronization module, a position data analysis module, and an interferometer signal acquisition module. The lower-level master control computer receives the control strategy from the lithography machine master control computer and reports motion control status information and data; the motion control module receives sensor data, performs real-time motion control calculations, and generates control data; the SRIO exchange module is used for real-time data exchange between modules; the clock synchronization module is used for system synchronization control; the position data analysis module receives the data collected by the interferometer signal acquisition module, performs real-time position analysis, and sends the analysis results to the motion control module; the interferometer signal acquisition module is used to acquire the workpiece stage position data of the interferometer. The system bus includes a signaling / status bus, a data exchange bus, and a servo synchronization interrupt bus; The signaling / status bus adopts a VME-VPX hybrid architecture and is used for issuing system configurations and reporting system status information; the data exchange bus communicates based on the SRIO bus and is used for receiving and sending real-time system data; the servo synchronization interrupt bus is used for timed interrupts of the system control cycle, realizing the transmission of timing information in a direct interrupt manner.

[0011] In some embodiments, an interferometer signal acquisition module on a VME bus and an interferometer signal acquisition module on a VPX bus are simultaneously connected to the system. The interferometer signal acquisition module on the VME bus is connected to the position data analysis module via the VME extended protocol P2Bus interface, and the interferometer signal acquisition module on the VPX bus is connected to the position data analysis module via the SRIOx4 interface.

[0012] In some embodiments, for VME register read and write operations, the VME bus protocol is parsed in the FPGA logic of the position data analysis module to extract the register operation type, address, and data. The register read operation is mapped to an SRIO N_READ transaction frame, the read return operation is mapped to an SRIO RESPONSE transaction frame, and the register write operation is mapped to an SRIO N_WRITE transaction frame. For VME interrupt operations, they are mapped to an SRIO DOORBELL transaction frame.

[0013] In some embodiments, the functional characteristics and status information of VME devices and VPX devices are defined using configuration / status registers. The addresses of the registers of VME devices and VPX devices are uniformly mapped to the PCIE address space of the lower-level master computer using the "base address + offset address" method, so that the lower-level master computer can access VME devices and VPX devices through PCIE read and write.

[0014] In some embodiments, an interrupt vector register is defined in the FPGA of the lower-level master computer, and each bit in the interrupt vector register represents a VME device or a VPX device. At the moment of servo synchronization interruption, the FPGA of the lower-level master computer detects the interrupt vector register. When it finds that the corresponding bit position is not zero, it initiates a PCIE-MSI interrupt to the CPU of the lower-level master computer. After receiving the PCIE-MSI interrupt, the CPU reads the interrupt vector register and processes the interrupt request of each device bit by bit.

[0015] In some embodiments, the lower-level master computer is connected to the FPGA of the motion control module and the position data analysis module through an SRIO exchange module. One SRIO port of the DSP of the motion control module and the position data analysis module is used for data exchange with the FPGA, and the other ports are used for real-time motion control.

[0016] In some embodiments, within the SRIO address space of the CPU of the lower-level master computer, an independent address space segment is uniformly allocated for each SRIO peripheral using the method of "base address + offset address".

[0017] In some embodiments, the servo synchronization interrupt bus defines two modes: internal synchronization and external synchronization. In internal synchronization mode, the local system generates a servo synchronization interrupt internally; in external synchronization mode, the local system receives servo synchronization interrupts from other real-time control systems.

[0018] In some embodiments, in the servo synchronous interrupt bus, an interrupt cycle is defined as a servo cycle, and each servo cycle is divided into two time slices: one for real-time data calculation and the other for data exchange. The proportion of the two time slices is configured, and the configuration of the proportion of the time slices is set to be unmodifiable during system operation.

[0019] In some embodiments, in internal synchronization mode, a servo synchronization interrupt is generated based on a local crystal oscillator clock source; in external synchronization mode, an external input is received as a servo synchronization interrupt.

[0020] Compared with the prior art, the present invention has the following advantages and beneficial effects: This invention adopts a signaling / status bus and data exchange bus architecture, simplifies the servo synchronization mechanism, removes redundant functions, simplifies the underlying system design, improves the processing performance of key nodes, and achieves a higher servo interrupt cycle, enabling the system architecture to be applied to more precise real-time motion control.

[0021] The system architecture of this invention can be applied to the motion control system of a lithography machine wafer scanner, which has multiple sensor and driver access capabilities, multi-machine synchronization capabilities, high control precision, and strong interference suppression capabilities. This enables the key process of high-performance motion control in the wafer scanner, accurately controlling the movement of the wafer and mask, thereby achieving wafer fabrication with smaller transistor feature sizes. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A block diagram of the VME bus architecture used in a general motion control system.

[0024] Figure 2 This is a block diagram of the SRIO x1 bus architecture for a general motion control system.

[0025] Figure 3 This is a system architecture block diagram of an embodiment of the present invention.

[0026] Figure 4 This is a block diagram of the functional modules in the system architecture of an embodiment of the present invention.

[0027] Figure 5 This is a block diagram of the signaling / status bus structure in the system architecture of an embodiment of the present invention.

[0028] Figure 6 This is a block diagram of the data exchange bus structure in the system architecture of an embodiment of the present invention.

[0029] Figure 7 This is a block diagram of servo synchronization control in the system architecture of an embodiment of the present invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, specific embodiments of this application will be described in further detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining this application and not for limiting it. It should also be noted that, for ease of description, only the parts relevant to this application are shown in the drawings, not all of them. Before discussing exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe operations (or steps) as sequential processes, many of these operations can be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations can be rearranged. The process can be terminated when its operation is completed, but may also have additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0031] This invention addresses the needs of real-time motion control in micro- and nano-scale scenarios. It aims to provide a control system architecture for real-time motion control in micro- and nano-scale scenarios without changing or with minimal changes to the application layer software. This architecture improves system computing performance, data interaction, and system control bandwidth, while being compatible with various sensors and controller peripherals and capable of accessing the data acquisition module of the new generation VPX interferometer.

[0032] By redefining the signaling / status bus architecture, the system retains the access capabilities of the original VME architecture while enabling access and control of the next-generation VPX interferometer data acquisition module.

[0033] By redefining the architecture of the data exchange bus to improve the real-time data exchange bandwidth of the system and adding a data read-in port for the data acquisition module of the new generation VPX interferometer, the data exchange load of the DSP can be reduced to free up resources for real-time control calculations, reduce the DSP scheduling complexity, and thus improve real-time computing performance.

[0034] This invention can be applied to the motion control system of a lithography machine wafer scanner, which has multiple sensor and driver access capabilities, multi-machine synchronization capabilities, high control precision, and strong interference suppression capabilities, to achieve the key process of high-performance motion control in the wafer scanner, to accurately control the movement of the wafer and the mask, and thus realize wafer fabrication with smaller transistor feature sizes.

[0035] like Figure 3 As shown, in some embodiments of the present invention, the system architecture includes functional modules and a system bus.

[0036] The system bus includes a signaling / status bus, a data exchange bus, and a servo synchronization interrupt bus; The signaling / status bus is an information bus for system configuration distribution and status reporting of various parts of the system. It exchanges information through register read and write and is a bidirectional full-duplex bus. The data exchange bus is a high-speed real-time data receiving and transmitting bus. It transmits data in the form of data frames with address information. Each node caches data by directly accessing memory addresses. It is a bidirectional full-duplex bus. The servo synchronous interrupt bus is a timer interrupt bus for the system control cycle. It transmits timing information in a direct interrupt manner and is a unidirectional bus.

[0037] like Figure 4 As shown, the functional modules include a lower-level master computer, a motion control module, an SRIO switching module, a clock synchronization module, a position data analysis module, and an interferometer signal acquisition module.

[0038] The lower-level master computer is used to receive the control strategy from the lithography machine master computer and report motion control status information and data to realize the control of each functional process.

[0039] The motion control module is used to receive sensor data, perform real-time motion control calculations, and generate control data.

[0040] The SRIO switching module is used to achieve high-speed real-time data exchange.

[0041] The clock synchronization module is used for system synchronization control and provides a time reference.

[0042] The position data analysis module receives the data acquired by the interferometer signal acquisition module, performs real-time position analysis, and sends the analysis results to the motion control module.

[0043] The interferometer signal acquisition module (VME / VPX) is used to acquire the stage position data of the multi-axis interferometer and report it to the position data analysis module. The interferometer signal acquisition module includes both VME bus-based and VPX bus-based modules.

[0044] In applications of micro- and nano-scale real-time motion control, the system architecture of this invention can collect more types and dimensions of sensor information to achieve more complex real-time motion control algorithms, control more motion peripherals and motion dimensions, and complete motion control processes with higher precision, stronger real-time performance, and more complex control details.

[0045] In some embodiments, the signaling / status bus is extended using a VME-VPX hybrid architecture, such as... Figure 5 As shown, a VPX bus is added to the system architecture, and the corresponding interface is defined through the SRIO x4 protocol. This interface is then connected to the slot of the position data analysis module via the backplane.

[0046] The interferometer signal acquisition module and the position data analysis module on the VME bus are connected via the VME extended protocol P2Bus interface; the position data analysis module and the interferometer signal acquisition module on the VPX bus are connected via the SRIO x4 interface. The SRIO x4 interface is connected to the corresponding onboard FPGA, realizing the physical interface expansion from VME bus to VPX bus.

[0047] The system adopts a VME / VPX hybrid architecture, which realizes a standard modular design. This allows the system architecture to simultaneously connect to both VME and VPX standard boards, and also enables the system architecture to be compatible with the connection of interferometer signal acquisition cards using the VPX bus.

[0048] In some embodiments, for the signaling / status bus, the VME to VPX (SRIO x4) protocol extension is performed based on the FPGA.

[0049] For VME register read and write operations, the VME bus protocol is parsed in the FPGA logic of the position data analysis module to extract the register operation type, address, and data. Register read operations are mapped to SRIO N_READ transaction frames, read return operations are mapped to SRIO RESPONSE transaction frames, and register write operations are mapped to SRIO N_WRITE transaction frames. For VME interrupt operations, they are mapped to SRIO DOORBELL transaction frames.

[0050] Based on the above mapping relationship, the VME bus operation required for motion control is extended to the SRIO basic protocol.

[0051] In some embodiments, for the signaling / status bus, the configuration / status space of VME / VPX devices is uniformly planned based on the PCIE protocol.

[0052] The functional characteristics and status information of all VME and VPX devices are defined using a configuration / status register approach. The register list for each device is implemented by the FPGA logic in the VME bus access plug-in section of each module.

[0053] All register addresses are mapped to the PCIE address space of the lower-level master computer PowerPC using the "base address + offset address" method, enabling the CPU of the lower-level master computer to access all VME and VPX devices in the system through PCIE read and write.

[0054] The FPGA of the lower-level master computer parses the PCIe protocol, extracts the register operation type, address and data, and converts them into the corresponding VME / VPX read and write operations of the device, so as to realize the unified planning of the configuration / state space of the VME / VPX device based on the PCIe protocol.

[0055] In some embodiments, the FPGA of the lower-level host computer performs PCIE protocol parsing to realize the mapping from PCIE-MSI interrupt to VME interrupt.

[0056] An interrupt vector register is defined in the FPGA of the lower-level master computer. Each bit in the interrupt vector register represents a VME device or VPX device. When a device in the system initiates an interrupt, the corresponding bit is set to zero. At the time of the servo synchronization interrupt, the FPGA of the lower-level master computer checks the interrupt vector register. If it finds that the value is not zero, it sends a PCIE-MSI interrupt to the CPU. After receiving the PCIE-MSI interrupt, the CPU reads the interrupt vector register and processes the interrupt request of each device bit by bit, realizing VME / VPX interrupt mapping based on PCIE.

[0057] In some embodiments, the architecture and bandwidth expansion of the data exchange bus are redefined; specifically, refer to Figure 6 The SRIO switching module serves as the data exchange center of the system architecture. Except for the CPU, all other first-level switching nodes are implemented using an FPGA. The FPGA is used for data exchange between upper and lower levels, as well as with peripherals. One SRIO port of the DSP is used for data exchange with the FPGA, while the other ports are used for real-time motion control.

[0058] Based on the actual controlled data flow, the CPU's SRIO bus width is designed to be x2, the FPGA's SRIO bus width is designed to be x4, and the SRIO bus interface width with peripherals is adjusted according to the peripheral situation, with a maximum width of x4.

[0059] An address-based data exchange bus architecture is adopted, with FPGA as the data exchange node. By leveraging its pipelined parallel processing advantages, the real-time data exchange bandwidth is improved, the data exchange load of DSP is reduced, thereby freeing up resources for real-time motion control calculations, reducing DSP scheduling complexity, and improving real-time computing performance.

[0060] In some embodiments, the data space of VME / VPX devices is uniformly planned for the data exchange bus.

[0061] Within the CPU's SRIO address space, each SRIO peripheral is allocated an independent address space segment using the "base address + offset address" method.

[0062] The size of each address space segment is defined independently by the device driver software, depending on the peripheral device. During system initialization, the CPU scans the entire device list to determine the address space allocation for each peripheral.

[0063] By adopting an address-based data exchange design, devices with processor architectures (Von Neumann or Harvard architecture) such as CPUs and DSPs in the system can directly acquire or send various types of data through memory read and write, thereby improving the overall computing performance and real-time data exchange efficiency of the real-time control system.

[0064] In some embodiments, peripheral interface protocol extensions are performed for the data exchange bus.

[0065] Based on the SRIO frame format, a unified intra-frame data payload field format is defined to standardize the data communication of all peripherals; the definition of the data payload field format is shown in Table 1.

[0066] Table 1. Standardized Sensor / Actuator Data Payload Field Format Definition

[0067] Data sampled by each sensor is processed using fixed-point encoding, with a minimum bit width of 32 bits. Integer and fractional bit widths can be customized based on the specific sensor. The SRIO protocol supports a maximum data payload of 256 bytes, meaning each data frame can transmit data from 63 channels of sensors / drivers. When the number of sensor channels exceeds 63, the data is transmitted in multiple frames, with the SRIO addresses of these frames remaining contiguous to ensure logical address contiguousness when the data is finally written to the DSP's shared memory space. When the number of driver data channels exceeds 63, the driver data, calculated in real-time, can be directly written to the DSP's contiguous shared memory space. After being read by the driver layer, it is divided into multiple data frames, with the SRIO addresses of these frames serving as the starting addresses of the memory data blocks.

[0068] By defining the data payload format for peripheral access, more types and dimensions of sensor information can be collected in micro- and nano-scale real-time motion control scenarios. This enables the control of more motion peripherals and motion dimensions, thereby achieving motion control with higher precision, stronger real-time performance, and more complex control details.

[0069] In some embodiments, a system synchronization mechanism is planned for the servo synchronization interrupt bus, and servo synchronization is defined.

[0070] like Figure 7 It defines two modes: internal synchronization and external synchronization. In internal synchronization mode, the local system generates a servo synchronization interrupt internally. In external synchronization mode, the local system receives servo synchronization interrupts from other real-time control systems. This interrupt is a periodic interrupt.

[0071] The system has both a synchronization signal output and an input port. Servo synchronization interrupts generated by the local system or received from external sources are distributed to various parts of the local system for use, and are also output to the outside of the system for use by other systems, so as to achieve multi-system synchronization.

[0072] In some embodiments, a system synchronization mechanism is planned to divide the servo cycle time slices.

[0073] An interrupt cycle is defined as a servo cycle. Each servo cycle is divided into two time slices: one for real-time data calculation and the other for data exchange.

[0074] During system initialization, the proportions of the two time slices are configured, and this configuration is prohibited from being modified during system operation until the system is finished.

[0075] In some embodiments, the system servo synchronization mechanism is implemented by the FPGA logic of the clock synchronization module according to the configuration.

[0076] In internal synchronization mode, a servo synchronization interrupt is generated based on the local crystal oscillator clock source; in external synchronization mode, external input is received as the servo synchronization interrupt. The local system's servo synchronization interrupt distribution is achieved through backplane transmission. Each module's FPGA receives the servo synchronization interrupt from the backplane and performs timing according to the configuration, dividing the time into time slices to control the synchronous operation of each component on the backplane. Simultaneously, the clock synchronization module outputs the servo synchronization interrupt through both single-ended and differential ports on the panel for use by other systems.

[0077] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications or equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A control system architecture for real-time motion control at the micro-nano level, characterized in that, Includes functional modules and system bus; The functional modules include a lower-level master computer, a motion control module, an SRIO switching module, a clock synchronization module, a position data analysis module, and an interferometer signal acquisition module. The lower-level master control computer is used to receive the control strategy from the lithography machine master control computer and report motion control status information and data; the motion control module is used to receive sensor data, perform real-time motion control calculations, and generate control data; the SRIO exchange module is used for real-time data exchange between modules; the clock synchronization module is used for system synchronization control; the position data analysis module is used to receive the data collected by the interferometer signal acquisition module, perform real-time position analysis, and send the analysis results to the motion control module. The interferometer signal acquisition module is used to acquire the workpiece stage position data of the interferometer; The system bus includes a signaling / status bus, a data exchange bus, and a servo synchronization interrupt bus; The signaling / status bus adopts a VME-VPX hybrid architecture and is used for issuing system configurations and reporting system status information; the data exchange bus communicates based on the SRIO bus and is used for receiving and sending real-time system data; the servo synchronization interrupt bus is used for timed interrupts of the system control cycle, realizing the transmission of timing information in a direct interrupt manner.

2. The control system architecture for real-time motion control at the micro-nano level according to claim 1, characterized in that, The system simultaneously connects to both the VME bus interferometer signal acquisition module and the VPX bus interferometer signal acquisition module. The VME bus interferometer signal acquisition module is connected to the position data analysis module via the VME extended protocol P2Bus interface, while the VPX bus interferometer signal acquisition module is connected to the position data analysis module via the SRIO x4 interface.

3. The control system architecture for real-time motion control at the micro-nano level according to claim 1, characterized in that, For VME register read and write operations, the VME bus protocol is parsed in the FPGA logic of the position data analysis module to extract the register operation type, address, and data. Register read operations are mapped to SRIO N_READ transaction frames, read return operations are mapped to SRIO RESPONSE transaction frames, and register write operations are mapped to SRIO N_WRITE transaction frames. For VME interrupt operations, they are mapped to SRIO DOORBELL transaction frames.

4. The control system architecture for real-time motion control at the micro-nano level according to claim 1, characterized in that, The functional characteristics and status information of VME and VPX devices are defined using configuration / status registers. The addresses of the registers of VME and VPX devices are uniformly mapped to the PCIE address space of the lower-level master computer using the "base address + offset address" method, so that the lower-level master computer can access VME and VPX devices through PCIE read and write.

5. The control system architecture for real-time motion control at the micro-nano level according to claim 1, characterized in that, The FPGA of the lower-level master computer has an interrupt vector register defined, and each bit in the interrupt vector register represents a VME device or VPX device. At the moment of servo synchronization interruption, the FPGA of the lower-level master computer detects the interrupt vector register. When it finds that the corresponding bit position is not zero, it initiates a PCIE-MSI interrupt to the CPU of the lower-level master computer. After receiving the PCIE-MSI interrupt, the CPU reads the interrupt vector register and processes the interrupt request of each device bit by bit.

6. The control system architecture for real-time motion control at the micro-nano level according to claim 1, characterized in that, The lower-level master computer is connected to the FPGA of the motion control module and the position data analysis module through the SRIO exchange module. One SRIO port of the DSP of the motion control module and the position data analysis module is used for data exchange with the FPGA, and the other ports are used for real-time motion control.

7. The control system architecture for real-time motion control at the micro-nano level according to claim 1, characterized in that, Within the SRIO address space of the CPU of the lower-level master computer, an independent address space segment is uniformly allocated for each SRIO peripheral using the method of "base address + offset address".

8. The control system architecture for real-time motion control at the micro-nano level according to claim 1, characterized in that, The servo synchronization interrupt bus defines an internal synchronization mode and an external synchronization mode. In the internal synchronization mode, the local system generates a servo synchronization interrupt internally. In the external synchronization mode, the local system receives servo synchronization interrupts from other real-time control systems.

9. The control system architecture for real-time motion control at the micro-nano level according to claim 8, characterized in that, In the servo synchronous interrupt bus, an interrupt cycle is defined as a servo cycle. Each servo cycle is divided into two time slices: one for real-time data calculation and the other for data exchange. The proportion of the two time slices is configured, and the configuration of the proportion of the time slices is set to be unmodifiable during system operation.

10. The control system architecture for real-time motion control at the micro-nano level according to claim 9, characterized in that, In internal synchronization mode, a servo synchronization interrupt is generated based on the local crystal oscillator clock source; in external synchronization mode, external input is received as a servo synchronization interrupt.

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