A reconfigurable DDS waveform generation system and method based on Zynq
Patent Information
- Application Number
- CN202611127573.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-28
- Publication Date
- 2026-10-27
AI Technical Summary
另一方面，若将波形生成、控制和接口驱动功能过多地集中在可编程逻辑侧实现，虽然能够获得较高的输出速率，但往往需要占用较多的逻辑、存储和时钟管理资源，灵活性也相对不足
[0040]本发明利用Zynq的异构结构，将波形生成和人机交互控制放在处理系统中完成，将高速相位累加、波表读取和DAC驱动放在可编程逻辑中完成，既保证了高速连续输出，又提高了波形参数配置的灵活性；并通过AXI-Lite地址映射方式写入波表和频率控制字，简化了PS与PL之间的数据交互；再利用4096点波表和32位相位累加器实现较细的频率调节粒度；并能通过串口屏输入参数实现正弦波、三角波、方波、锯齿波、复合波和扫频信号的在线切换，适用于嵌入式信号源、教学实验平台和可重构测试仪器等场景。
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Figure CN122984871A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital signal source and programmable logic control technology, specifically relating to a reconfigurable DDS waveform generation system and method based on Zynq. Background Technology
[0002] The statements in this section are merely background information relating to this disclosure, and these statements may constitute prior art. In the process of developing this invention, the inventors discovered at least the following problems in the prior art.
[0003] Existing FPGA-based DDS waveform generators typically embed wavetables in ROM or implement fixed waveforms in hardware logic. If changes to waveform type, amplitude, or composite relationships are needed, it often requires regenerating the stored file or re-synthesizing and configuring the logic, making debugging and use inflexible. For scenarios such as teaching experiments, embedded instruments, and portable signal sources, users also want to change the output frequency, amplitude, duty cycle, and sweep range in real time through simple human-machine interfaces such as serial port displays. Relying solely on processor software to output waveforms is insufficient to reliably meet the continuous sampling requirements of high-speed DACs.
[0004] Furthermore, existing processor-based software waveform generation schemes typically rely on the processor to handle waveform data calculation, updates, and output control. When multiple waveform switching, frequency sweep output, or high update rates are required, the processor needs to frequently participate in wavetable generation, data transfer, and interface control, which can lead to a significant real-time processing burden, thus affecting system response efficiency and output stability. On the other hand, while concentrating waveform generation, control, and interface driving functions excessively on the programmable logic side can achieve higher output rates, it often requires substantial logic, memory, and clock management resources, resulting in relatively insufficient flexibility.
[0005] Therefore, the main problem addressed by this invention is how to design a DDS waveform generation system and method to simultaneously solve the problems of insufficient waveform updates, heavy real-time output burden on the processor, and high programmable logic resource consumption in existing DDS waveform generators. Summary of the Invention
[0006] In view of the above problems, the purpose of this invention is to solve some of the problems in the prior art, or at least alleviate these problems.
[0007] A Zynq-based reconfigurable DDS waveform generation system includes:
[0008] A serial port screen is used to input waveform control parameters and send parameter frames.
[0009] The Zynq processing system is used to receive the parameter frame, parse the waveform control parameters, and generate a digital wavetable and frequency control word.
[0010] The AXI-Lite interface is used to write the digital wavetable and frequency control word into programmable logic;
[0011] A programmable logic wavetable storage module is used to store the digital wavetable;
[0012] The phase accumulation DDS module is used to perform phase accumulation according to the frequency control word and generate a wavetable read address;
[0013] The AD9744 digital-to-analog converter driver module is used to read the digital wavetable according to the wavetable read address and generate parallel data output to drive the AD9744 to output analog waveforms.
[0014] Furthermore, the waveform control parameters include one or more of the following: waveform type, output frequency, output amplitude, square wave duty cycle, waveform superposition coefficient, sweep start frequency, sweep end frequency, and sweep step speed; the parameter frame includes a frame header, parameter data, and a frame tail; the digital wavetable includes a sine wavetable, a triangular wavetable, a square wavetable, a sawtooth wavetable, and a composite wavetable; the sine wavetable is generated based on discrete sampling of a sine function, the triangular wavetable is generated based on linear rising and linear falling relationships, the square wavetable is generated based on duty cycle parameters, the sawtooth wavetable is generated based on linear ramp relationships, and the composite wavetable is generated by normalizing and superimposing the superposition coefficients of multiple basic waveforms; the parallel data includes 14-bit digital waveform data and a sampling clock.
[0015] Furthermore, the Zynq processing system includes a serial port interrupt receiving unit, a parameter parsing unit, a wavetable generation unit, and a control word calculation unit. The serial port interrupt receiving unit is used to receive the parameter frames sent by the serial port screen. The parameter parsing unit is used to determine the control type based on the frame header of the parameter frames. The wavetable generation unit is used to generate a digital wavetable, which is a discrete wavetable of sine waves, triangle waves, square waves, sawtooth waves, or composite waves. The depth of the discrete wavetable is 4096 points. The wavetable data is converted into 14-bit unsigned digital codes adapted to the AD9744 input range based on the output amplitude and stored in the least significant bits of the 32-bit AXI write data. The control word calculation unit generates a frequency control word based on the target output frequency and the sampling clock frequency. The sampling clock frequency is 150MHz.
[0016] Furthermore, the address space of the AXI-Lite interface includes a wavetable address area, a frequency control word address, and a start flag address; the wavetable address area is used to store a 4096-point digital wavetable in address order; the frequency control word address is used to store the DDS frequency control word; the start flag address is used to indicate that the wavetable writing is complete and to allow the programmable logic to start or continue output; the programmable logic wavetable storage module is a dual-port RAM, its first port is connected to the AXI-Lite writing logic and the processing system writes wavetable data, and its second port is connected to the phase accumulation DDS module and reads wavetable data under the sampling clock; the phase accumulation DDS module includes a 32-bit frequency control... The AD9744 frequency control word register includes a frequency control word register, a 32-bit phase accumulator, and an address truncation unit. The frequency control word register receives the frequency control word. The phase accumulator accumulates the frequency control word in each sampling clock cycle. The address truncation unit takes the high 12 bits of the accumulated phase value as the read address of the 4096-point wavetable. The AD9744 digital-to-analog converter driver module includes an output register and a clock output terminal. The output register latches the low 14 bits of the wavetable read data at a 150MHz sampling clock and outputs the low 14 bits of data to the data input terminal of the AD9744. At the same time, the clock output terminal outputs the 150MHz sampling clock as the operating clock of the AD9744.
[0017] A method using the aforementioned Zynq-based reconfigurable DDS waveform generation system includes the following steps:
[0018] It receives waveform control parameters input from the serial port screen and sends parameter frames to the Zynq processing system via the serial port;
[0019] Generate a corresponding digital wavetable based on the waveform control parameters and calculate the frequency control word;
[0020] The digital wavetable, frequency control word, and start flag are written into the programmable logic via the AXI-Lite bus;
[0021] In the programmable logic, phase accumulation is performed based on the frequency control word to generate the wavetable read address;
[0022] The digital wavetable is read according to the wavetable read address and 14-bit parallel data is output to drive the AD9744, thereby obtaining the target analog waveform.
[0023] Furthermore, the parameter frame includes a frame header, parameter data, and a frame tail; generating a corresponding digital wavetable and calculating the frequency control word based on the waveform control parameters includes the following steps:
[0024] The frame header identification control command is used to obtain control parameters from the parameter data; the control command includes selecting a sine wave, triangle wave, square wave, sawtooth wave, composite wave, or frequency sweep mode; the control parameters include frequency, amplitude, duty cycle, superposition coefficient, or frequency sweep range.
[0025] Upon receiving a waveform selection command, a 4096-point digital wavetable is generated according to the set wavetable depth, converted into a 14-bit unsigned digital code adapted to the AD9744 input range, and stored in the least significant bits of the 32-bit AXI write data; the digital wavetable includes a sine wavetable, a triangle wavetable, a square wavetable, a sawtooth wavetable, and a composite wavetable.
[0026] The frequency control word is calculated based on the target output frequency; where the sampling clock frequency is Fclk and the output frequency is Fout, the frequency control word Fword can be expressed as Fword = Fout × 2^32 / Fclk; the sampling clock frequency is 150MHz, and the target output frequency is converted into a 32-bit frequency control word and then written into the frequency control word register on the programmable logic side.
[0027] Furthermore, the digital wavetables generated by the processing system include sine wavetables, triangular wavetables, square wavetables, sawtooth wavetables, and composite wavetables. Sine wavetables are generated based on discrete sampling of a sine function, triangular wavetables are generated based on linear rising and falling relationships, square wavetables are generated based on duty cycle parameters, sawtooth wavetables are generated based on linear ramp relationships, and composite wavetables are generated by normalizing and superimposing the superposition coefficients of multiple basic waveforms.
[0028] The specific steps are as follows: For sine wave mode, the processing system generates a sine wave table based on the sampled values of the sine function within one cycle; for triangle wave mode, the processing system generates a triangle wave table based on the linear rise in the first half of the cycle and the linear fall in the second half of the cycle; for square wave mode, the processing system determines the number of high and low level duration points based on the duty cycle parameter and generates a square wave table; for sawtooth wave mode, the processing system generates a sawtooth wave table based on the linear ramp relationship; for composite wave mode, the processing system generates a composite wave table based on the superposition coefficient of the basic waveform; for frequency sweep mode, the processing system generates a wave table of the default waveform and writes it into the dual-port RAM, and then updates the frequency control word at a set step speed between the frequency sweep start frequency and the frequency sweep end frequency.
[0029] Furthermore, the digital wavetable, frequency control word, and start flag are written into the programmable logic via the AXI-Lite bus, including the following steps:
[0030] When a write operation is initiated by the AXI-Lite slave receiving and processing system, the address decoding unit maps the continuous address starting from the base address to the wavetable address area, maps the 4096th word address to the frequency control word address, and maps the 4097th word address to the start flag address.
[0031] During the waveform update process, the processing system first writes the 4096-point digital wavetable into the wavetable address area in ascending order of the wavetable address, then writes the frequency control word into the frequency control word address, and finally writes the valid flag into the start flag address.
[0032] Once the start flag is valid, the phase accumulation DDS module will begin or continue performing table lookup output at a 150MHz sampling clock.
[0033] Furthermore, in the programmable logic, phase accumulation is performed based on the frequency control word to generate the wavetable read address, including the following steps:
[0034] In each sampling clock cycle, the phase accumulator adds its current value to the frequency control word to obtain a new phase accumulation value;
[0035] The address truncation unit takes the high 12 bits of the new phase accumulation value as the read address of the second port of the dual-port RAM; the dual-port RAM outputs the wavetable data corresponding to the address.
[0036] Furthermore, reading the digital wavetable according to the wavetable read address and outputting 14-bit data to drive the AD9744 includes the following steps:
[0037] The output register latches the lower 14 bits of the wavetable data at the corresponding address and outputs them to the data input terminal of the AD9744; at the same time, the 150MHz sampling clock is used as the operating clock of the AD9744 and output to the data input terminal of the AD9744.
[0038] AD9744 outputs analog waveforms.
[0039] The present invention has the following beneficial effects:
[0040] This invention utilizes the heterogeneous architecture of Zynq, placing waveform generation and human-machine interaction control within the processing system, while high-speed phase accumulation, wavetable reading, and DAC driving are implemented in the programmable logic, ensuring both high-speed continuous output and improved flexibility in waveform parameter configuration. Furthermore, it simplifies data interaction between the PS and PL by writing the wavetable and frequency control word using AXI-Lite address mapping. A finer frequency adjustment granularity is achieved using a 4096-point wavetable and a 32-bit phase accumulator. Online switching between sine, triangle, square, sawtooth, composite, and swept signals can be realized via serial port input parameters, making it suitable for embedded signal sources, teaching experimental platforms, and reconfigurable test instruments. Attached Figure Description
[0041] Figure 1 This is a schematic diagram of the overall structure of the Zynq-based reconfigurable DDS waveform generation system provided by the present invention;
[0042] Figure 2 This is a schematic diagram of the programmable logic DDS module structure provided by the present invention;
[0043] Figure 3 This is a flowchart of waveform update and output control provided by the present invention. Detailed Implementation
[0044] The present invention will be further described below with reference to the accompanying drawings. The embodiments of the present invention are only used to illustrate the present invention and not to limit the present invention. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the technical concept of the present invention should be included within the scope of the present invention.
[0045] To address the aforementioned shortcomings, it is necessary to propose a collaborative DDS waveform generation scheme in which the processing system is responsible for waveform parameter analysis and wavetable generation, while the programmable logic is responsible for high-speed phase accumulation and DAC driving.
[0046] like Figure 1 As shown, the reconfigurable DDS waveform generation system provided in this embodiment includes a serial port screen, a Zynq processing system, an AXI-Lite interface, Zynq programmable logic, and an AD9744 digital-to-analog converter. The serial port screen sends parameter frames to the Zynq processing system via a serial port. The parameter frames include a frame header, parameter data, and a frame trailer. The processing system identifies control commands based on the frame header, such as selecting a sine wave, triangle wave, square wave, sawtooth wave, composite wave, or sweep frequency mode, and obtains control parameters such as frequency, amplitude, duty cycle, superposition coefficient, or sweep frequency range from the parameter data.
[0047] Upon receiving a waveform selection command, the processing system generates a 4096-point digital wavetable based on the set wavetable depth. For a sine wave, the system generates the wavetable according to the sine function sampling values within one cycle; for a triangular wave, it generates the wavetable based on a linear rise in the first half of the cycle and a linear fall in the second half; for a square wave, it determines the number of high and low level durations based on the duty cycle parameter; for a sawtooth wave, it generates the wavetable based on a linear ramp relationship; and for a composite wave, it generates a composite wavetable based on the superposition coefficients of basic waveforms such as sine, triangular, and square waves. The generated wavetable data is converted into 14-bit unsigned digital codes adapted to the AD9744 input range.
[0048] The processing system also calculates the frequency control word based on the target output frequency. Let the sampling clock frequency be Fclk and the output frequency be Fout, then the frequency control word Fword can be expressed as Fword = Fout × 2^32 / Fclk. In this embodiment, the sampling clock frequency is 150MHz, therefore the processing system converts the target frequency into a 32-bit frequency control word and writes it to the frequency control word register on the programmable logic side.
[0049] like Figure 2 As shown, the programmable logic side includes an AXI-Lite slave device, an address decoding unit, a dual-port RAM, a frequency control word register, a start flag register, a 32-bit phase accumulator, an address truncation unit, and an output register. When the AXI-Lite slave device receives a write operation initiated by the processing system, the address decoding unit maps consecutive addresses starting from the base address to the wavetable address area, maps the 4096th word address to the frequency control word address, and maps the 4097th word address to the start flag address. The wavetable address area stores 4096 points of wavetable data, the frequency control word address stores the DDS frequency control word, and the start flag address indicates that the wavetable and control parameters have been written. Through this address partitioning method, the processing system can complete waveform reconstruction using memory-mapped write operations without reconfiguring the programmable logic.
[0050] During waveform update, the processing system first writes the 4096-point wavetable into the wavetable address area sequentially, then writes the frequency control word into the frequency control word address, and finally writes a valid flag to the start flag address. After the start flag is valid, the phase accumulation DDS module starts or continues to perform table lookup output under a 150MHz sampling clock.
[0051] The dual-port RAM has its first port connected to the AXI-Lite write logic and its second port connected to the DDS read logic. The DDS read logic includes a 32-bit phase accumulator, which accumulates the frequency control word at a 150MHz sampling clock and takes the high 12 bits of the accumulated phase value as the 4096-point wavetable read address.
[0052] The specific working process of the phase accumulation DDS module is as follows:
[0053] In each sampling clock cycle, the phase accumulator adds its current value to the frequency control word to obtain a new phase accumulator value; the address truncation unit takes the high 12 bits of the phase accumulator value as the read address of the second port of the dual-port RAM; the dual-port RAM outputs the wavetable data corresponding to the address; the output register latches the low 14 bits of the wavetable data and outputs it to the data input terminal of the AD9744. Due to the use of a 32-bit phase accumulator and a 4096-point wavetable, this embodiment can achieve finer frequency control granularity with limited wavetable capacity.
[0054] In frequency sweep mode, the processing system generates a wavetable of default waveforms and writes it to the dual-port RAM. Then, it updates the frequency control word at a set step speed between the sweep start frequency and the sweep end frequency. The programmable logic side can change the output frequency without rewriting the wavetable, thus achieving continuous frequency sweep output.
[0055] In square wave mode, the processing system determines the number of sampling points corresponding to high and low levels within one cycle based on the duty cycle parameter and generates the corresponding wavetable. By changing the duty cycle parameter, the system can output square wave signals with different duty cycles. In composite wave mode, the processing system generates a composite wavetable based on the superposition coefficients of different basic waveforms, thereby outputting a composite waveform that meets the test requirements.
[0056] The system described in this embodiment can be implemented using Zynq-7000 series devices. The processing system runs a bare-metal program to complete serial port reception, parameter parsing, wavetable generation, and AXI-Lite write operations. The programmable logic generates a 150MHz sampling clock through a clock module and outputs 14-bit parallel data and the sampling clock to the AD9744 through external pins. It should be understood that the sampling clock frequency, wavetable depth, DAC bit width, and waveform type can all be adjusted according to specific applications, and these equivalent changes still fall within the protection scope of this invention.
[0057] This invention enables online reconstruction output of sine waves, triangle waves, square waves, sawtooth waves, composite waves, and frequency sweep signals without reconfiguring the FPGA. It has advantages such as simple structure, flexible parameter updates, low PL resource consumption, programmable output frequency, and convenient human-machine interaction control.
[0058] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various equivalent substitutions, improvements, or combinations made without departing from the concept of the present invention should be included within the scope of protection defined by the claims of the present invention.
Claims
1. A Zynq-based reconfigurable DDS waveform generation system, characterized in that, include: A serial port screen is used to input waveform control parameters and send parameter frames. The Zynq processing system is used to receive the parameter frame, parse the waveform control parameters, and generate a digital wavetable and frequency control word. The AXI-Lite interface is used to write the digital wavetable and frequency control word into programmable logic; A programmable logic wavetable storage module is used to store the digital wavetable; The phase accumulation DDS module is used to perform phase accumulation according to the frequency control word and generate a wavetable read address; The AD9744 digital-to-analog converter driver module is used to read the digital wavetable according to the wavetable read address and generate parallel data output to drive the AD9744 to output analog waveforms.
2. The Zynq-based reconfigurable DDS waveform generation system according to claim 1, characterized in that, The waveform control parameters include one or more of the following: waveform type, output frequency, output amplitude, square wave duty cycle, waveform superposition coefficient, sweep start frequency, sweep end frequency, and sweep step speed; the parameter frame includes a frame header, parameter data, and a frame tail; the digital wavetable includes a sine wavetable, a triangular wavetable, a square wavetable, a sawtooth wavetable, and a composite wavetable; the sine wavetable is generated based on discrete sampling of a sine function, the triangular wavetable is generated based on linear rising and linear falling relationships, the square wavetable is generated based on duty cycle parameters, the sawtooth wavetable is generated based on linear ramp relationships, and the composite wavetable is generated by normalizing and superimposing the superposition coefficients of multiple basic waveforms; the parallel data includes 14-bit digital waveform data and a sampling clock.
3. The Zynq-based reconfigurable DDS waveform generation system according to claim 1 or 2, characterized in that, The Zynq processing system includes a serial port interrupt receiving unit, a parameter parsing unit, a wavetable generation unit, and a control word calculation unit. The serial port interrupt receiving unit receives the parameter frames sent by the serial port screen. The parameter parsing unit determines the control type based on the frame header of the parameter frames. The wavetable generation unit generates a digital wavetable, which is a discrete wavetable of a sine wave, triangle wave, square wave, sawtooth wave, or composite wave. The depth of the discrete wavetable is 4096 points. The wavetable data is converted into 14-bit unsigned digital codes adapted to the AD9744 input range based on the output amplitude and stored in the least significant bits of the 32-bit AXI write data. The control word calculation unit generates a frequency control word based on the target output frequency and the sampling clock frequency. The sampling clock frequency is 150MHz.
4. The Zynq-based reconfigurable DDS waveform generation system according to claim 1, characterized in that, The address space of the AXI-Lite interface includes a wavetable address area, a frequency control word address, and a start flag address. The wavetable address area is used to store a 4096-point digital wavetable in address order. The frequency control word address is used to store the DDS frequency control word. The start flag address is used to indicate that the wavetable writing is complete and to allow the programmable logic to start or continue output. The programmable logic wavetable storage module is a dual-port RAM. Its first port is connected to the AXI-Lite writing logic and the processing system writes the wavetable data. Its second port is connected to the phase accumulation DDS module and reads the wavetable data under the sampling clock. The phase accumulation DDS module includes a 32-bit frequency control word register. The AD9744 wavetable includes a frequency control word register, a 32-bit phase accumulator, and an address truncation unit. The frequency control word register receives the frequency control word. The phase accumulator accumulates the frequency control word in each sampling clock cycle. The address truncation unit takes the high 12 bits of the accumulated phase value as the read address of the 4096-point wavetable. The AD9744 digital-to-analog converter driver module includes an output register and a clock output terminal. The output register latches the low 14 bits of the wavetable read data at a 150MHz sampling clock and outputs the low 14 bits to the data input terminal of the AD9744. Simultaneously, the clock output terminal outputs the 150MHz sampling clock as the operating clock of the AD9744.
5. A method using the Zynq-based reconfigurable DDS waveform generation system according to any one of claims 1 to 4, characterized in that, Includes the following steps: It receives waveform control parameters input from the serial port screen and sends parameter frames to the Zynq processing system via the serial port; Generate a corresponding digital wavetable based on the waveform control parameters and calculate the frequency control word; The digital wavetable, frequency control word, and start flag are written into the programmable logic via the AXI-Lite bus; In the programmable logic, phase accumulation is performed based on the frequency control word to generate the wavetable read address; The digital wavetable is read according to the wavetable read address and 14-bit parallel data is output to drive the AD9744, thereby obtaining the target analog waveform.
6. The method according to claim 5, characterized in that, The parameter frame includes a frame header, parameter data, and a frame tail; generating a corresponding digital wavetable based on the waveform control parameters and calculating the frequency control word includes the following steps: The frame header identification control command is used to obtain control parameters from the parameter data; the control command includes selecting a sine wave, triangle wave, square wave, sawtooth wave, composite wave, or frequency sweep mode; the control parameters include frequency, amplitude, duty cycle, superposition coefficient, or frequency sweep range. Upon receiving a waveform selection command, a 4096-point digital wavetable is generated according to the set wavetable depth, converted into a 14-bit unsigned digital code adapted to the AD9744 input range, and stored in the least significant bits of the 32-bit AXI write data; the digital wavetable includes a sine wavetable, a triangle wavetable, a square wavetable, a sawtooth wavetable, and a composite wavetable. The frequency control word is calculated based on the target output frequency; where the sampling clock frequency is Fclk and the output frequency is Fout, the frequency control word Fword can be expressed as Fword = Fout × 2^32 / Fclk; the sampling clock frequency is 150MHz, and the target output frequency is converted into a 32-bit frequency control word and then written into the frequency control word register on the programmable logic side.
7. The method according to claim 6, characterized in that, The steps for generating a digital wave table are as follows: For the sine wave mode, the processing system generates a sine wave table based on the sine function sampling values within one cycle; for the triangular wave mode, the processing system generates a triangular wave table based on the relationship of linear increase in the first half of the cycle and linear decrease in the second half of the cycle. For square wave mode, the processing system determines the number of high and low level duration points based on the duty cycle parameter and generates a square wave table; For the sawtooth wave mode, the processing system generates a sawtooth wave table according to a linear ramp relationship; For composite wave mode, the processing system generates a composite wave table based on the superposition coefficient of the basic waveform; for frequency sweep mode, the processing system generates a wave table of the default waveform and writes it into the dual-port RAM, and then updates the frequency control word at a set step speed between the frequency sweep start frequency and the frequency sweep end frequency.
8. The method according to claim 5, characterized in that, The digital wavetable, frequency control word, and start flag are written into the programmable logic via the AXI-Lite bus, including the following steps: When a write operation is initiated by the AXI-Lite slave receiving and processing system, the address decoding unit maps the continuous address starting from the base address to the wavetable address area, maps the 4096th word address to the frequency control word address, and maps the 4097th word address to the start flag address. During the waveform update process, the processing system first writes the 4096-point digital wavetable into the wavetable address area in ascending order of wavetable address, then writes the frequency control word into the frequency control word address, and finally writes the valid flag into the start flag address. Once the start flag is valid, the phase accumulation DDS module will begin or continue performing table lookup output at a 150MHz sampling clock.
9. The method according to claim 6, characterized in that, In programmable logic, phase accumulation is performed based on the frequency control word to generate the wavetable read address, including the following steps: In each sampling clock cycle, the phase accumulator adds its current value to the frequency control word to obtain a new phase accumulation value; The address truncation unit takes the high 12 bits of the new phase accumulation value as the read address of the second port of the dual-port RAM; the dual-port RAM outputs the wavetable data corresponding to the address.
10. The method according to claim 9, characterized in that, Reading the digital wavetable according to the wavetable read address and outputting 14-bit data to drive the AD9744 includes the following steps: The output register latches the lower 14 bits of the wavetable data at the corresponding address and outputs them to the data input terminal of the AD9744; at the same time, the 150MHz sampling clock is used as the operating clock of the AD9744 and output to the data input terminal of the AD9744. AD9744 outputs analog waveforms.