Method for synchronizing multi-channel signals and test machine
Patent Information
- Application Number
- CN202610838673.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-10
- Publication Date
- 2026-10-27
AI Technical Summary
上电后通道之间产生不同的延时，难以满足高精度测试需求
[0052]上述多通道信号同步方法、测试机、计算机可读存储介质和计算机程序产品中，采用优化的相位插值调整方案，实现多通道信号同步调节。即，针对板卡中每个通道，对从其缓冲单元中读数据的时钟信号进行相位插值的过程中，会统计分析缓冲区状态随相位插值的变化规律（简称相位插值变化规律），从而通过PMA复位的方式，使得每个通道对应的相位插值变化规律都满足目标类型，在所有通道对应的相位插值变化规律都满足目标类型的情况下，能实现多通道信号同步对齐。
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Figure CN122984875A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor testing technology, and in particular to a multi-channel signal synchronization method and testing machine. Background Technology
[0002] In the field of semiconductor testing, the high-speed transceiver inside the resource board of the test machine sends test signals to the corresponding device under test (DUT).
[0003] After power-on initialization, the phase deviation between channels of a high-speed transceiver is random and usually quite large; for example, the maximum measured deviation is approximately 24 microseconds (UI). Different delays occur between channels after power-on, making it difficult to meet the requirements of high-precision testing. Summary of the Invention
[0004] Therefore, it is necessary to provide a multi-channel signal synchronization method, a test machine, a computer-readable storage medium, and a computer program product to address the aforementioned technical problems.
[0005] In a first aspect, this application provides a multi-channel signal synchronization method, the method comprising:
[0006] For each channel in the resource board, based on the buffer state of the buffer unit in the channel, the clock signal used to read data from the buffer unit is phase interpolated;
[0007] The adjustment step size is obtained based on the difference between the second interpolation cumulative value and the first interpolation cumulative value; the first interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has not reached half-full state for multiple consecutive clock cycles; the second interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has reached half-full state for multiple consecutive clock cycles.
[0008] If the adjustment step size is greater than the average adjustment step size, the Physical Media Adaptor (PMA) module in the channel is reset, and the adjustment step size is recalculated until the adjustment step size is less than or equal to the average adjustment step size, at which point the reset stops.
[0009] The target interpolation cumulative value is determined based on the second interpolation cumulative value and the first interpolation cumulative value at the time of stop reset, and the clock signal is phase interpolated according to the target interpolation cumulative value.
[0010] In one embodiment, if the half-full signal of the buffer unit is low, the buffer state is not half-full; if the half-full signal of the buffer unit is high, the buffer state is half-full.
[0011] When the adjustment step size is less than or equal to the average adjustment step size, the phase adjustment change curve corresponding to the channel is of type one; when the adjustment step size is greater than the average adjustment step size, the phase adjustment change curve is of type two; wherein, the phase adjustment change curve refers to the curve of the duty cycle of the half-full signal of the buffer unit in the channel changing with the interpolated cumulative value of the clock signal.
[0012] When the phase adjustment change curves for each channel are all of type 1, after performing phase interpolation for each channel according to the target interpolation cumulative value, the signals of each channel are synchronized and aligned.
[0013] In one embodiment, one of the half-full state and the state not reaching half-full is referred to as the first state, and the other is referred to as the second state;
[0014] Based on the buffer state of the buffer unit in the channel, phase interpolation is performed on the clock signal used to read data from the buffer unit, including:
[0015] If the buffer state is in the first state for N consecutive clock cycles, the clock signal is phase interpolated in the first direction with a step length until the buffer state has a second state for N consecutive clock cycles.
[0016] Continue to perform phase interpolation of the clock signal in the second direction with the second step size until the buffer state is in the first state for M consecutive clock cycles, and record the first current interpolation cumulative value; the second step size is less than the first step size; the second direction is opposite to the first direction;
[0017] Continue to perform phase interpolation of the clock signal in the first direction with the second step size until the buffer state is in the second state for M consecutive clock cycles, and record the second current interpolation cumulative value; where M and N are both integers greater than or equal to 2; the second current interpolation cumulative value is different from the first current interpolation cumulative value, and is one of the second interpolation cumulative value and the first interpolation cumulative value, respectively.
[0018] In one embodiment, the method further includes:
[0019] If the buffer state is not always in the first state for N consecutive clock cycles, the clock signal is phase interpolated in the second direction with a third step size until the buffer state is always in the first state for N consecutive clock cycles.
[0020] In one embodiment, the first state is not half-full, the first direction is positive, the second state is half-full, the second direction is negative, the first current interpolation cumulative value is the first interpolation cumulative value, and the second current interpolation cumulative value is the second interpolation cumulative value.
[0021] In one embodiment, the first state is a half-full state with the first direction being reversed, the second state is a state that has not reached half-full with the second direction being forward, the first current interpolation cumulative value is the second interpolation cumulative value, and the second current interpolation cumulative value is the first interpolation cumulative value.
[0022] In one embodiment, before performing phase interpolation on the clock signal used to read data from the buffer unit based on the buffer state of the buffer unit in the channel, the method further includes:
[0023] Check if the buffer state is abnormal;
[0024] In the event of an abnormal buffer state, the channel is PMA reset until the buffer state returns to normal.
[0025] After the buffer state returns to normal, the clock signal used to read data from the buffer unit is phase interpolated based on the buffer state of the buffer unit in the channel.
[0026] In one embodiment, the buffer unit in the channel has a corresponding status register; detecting whether the buffer status is abnormal includes:
[0027] Detect the level of the preset bit in the status register;
[0028] If the level indicates that the buffer cell is full or empty, then the buffer cell's buffer state is determined to be abnormal.
[0029] In one embodiment, determining the target interpolation cumulative value based on the second interpolation cumulative value at the time of stop reset and the first interpolation cumulative value includes:
[0030] Determine the second interpolation cumulative value and the first interpolation cumulative value when the reset stops;
[0031] The target interpolation cumulative value is determined based on the average of the determined second interpolation cumulative value and the determined first interpolation cumulative value.
[0032] In one embodiment, after each phase interpolation, the interpolation accumulation value is updated, and the buffer state for multiple consecutive clock cycles under the updated interpolation accumulation value is counted.
[0033] Determine the second interpolation cumulative value and the first interpolation cumulative value at the time of stopping reset, including:
[0034] After the reset is stopped, the buffer state based on the buffer cell in the channel is re-executed, and the clock signal used to read data from the buffer cell is phase interpolated.
[0035] Based on the buffer state of multiple consecutive clock cycles under the interpolation cumulative value after each phase interpolation, the second interpolation cumulative value and the first interpolation cumulative value at the time of stop reset are determined.
[0036] In one embodiment, determining the second interpolation cumulative value and the first interpolation cumulative value at the time of stopping reset includes:
[0037] The second interpolation cumulative value and the first interpolation cumulative value calculated during the last reset are used as the second interpolation cumulative value and the first interpolation cumulative value when the reset stops.
[0038] In one embodiment, the average adjustment step size is the average of multiple adjustment step sizes calculated by performing multiple PMA resets on the channel in advance; before performing phase interpolation on the clock signal used to read data from the buffer unit based on the buffer state of the buffer unit in the channel, the method further includes:
[0039] For each channel in the resource board, perform multiple PMA resets on the channel;
[0040] Calculate the adjustment step size after each PMA reset, and determine the average adjustment step size based on the calculated adjustment step size.
[0041] The calculation of the adjustment step size after each PMA reset includes:
[0042] After each PMA reset, the clock signal is phase interpolated based on the buffer state of the buffer unit in the channel;
[0043] The adjustment step size is obtained based on the difference between the fourth interpolation cumulative value and the third interpolation cumulative value; the third interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has not reached half-full state for multiple consecutive clock cycles; the fourth interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has reached half-full state for multiple consecutive clock cycles.
[0044] Secondly, this application also provides a multi-channel signal synchronization device, which includes:
[0045] The phase interpolation unit is used to perform phase interpolation on the clock signal used to read data from the buffer unit for each channel in the resource board, based on the buffer state of the buffer unit in the channel.
[0046] The adjustment step size calculation unit is used to obtain the adjustment step size based on the difference between the second interpolation cumulative value and the first interpolation cumulative value; the first interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has not reached half-full state for multiple consecutive clock cycles; the second interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has reached half-full state for multiple consecutive clock cycles.
[0047] The reset unit is used to reset the Physical Media Adaptor (PMA) unit in the channel if the adjustment step size is greater than the average adjustment step size, and recalculate the adjustment step size until the adjustment step size is less than or equal to the average adjustment step size, at which point the reset stops.
[0048] The phase interpolation unit is also used to determine the target interpolation cumulative value based on the second interpolation cumulative value and the first interpolation cumulative value when the reset is stopped, and to perform phase interpolation on the clock signal according to the target interpolation cumulative value.
[0049] Thirdly, this application also provides a test machine, which includes a resource board; the resource board includes a main control module, which is used to execute the steps in the method involved in the first aspect above.
[0050] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the steps of the method described in the first aspect above.
[0051] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the method described in the first aspect above.
[0052] The aforementioned multi-channel signal synchronization method, test machine, computer-readable storage medium, and computer program product employ an optimized phase interpolation adjustment scheme to achieve multi-channel signal synchronization adjustment. Specifically, for each channel on the board, during the phase interpolation process of the clock signal reading data from its buffer unit, the change pattern of the buffer state with the phase interpolation (referred to as the phase interpolation change pattern) is statistically analyzed. Then, through a PMA reset, the phase interpolation change pattern for each channel is ensured to meet the target type. When the phase interpolation change patterns for all channels meet the target type, multi-channel signal synchronization alignment can be achieved.
[0053] Specifically, when performing multi-channel signal synchronization adjustment based on phase interpolation, the adjustment step size formed by each channel during the current phase interpolation process can be calculated. Comparing this current adjustment step size with the average adjustment step size allows determination of whether the current phase interpolation change pattern of each channel conforms to the target type. That is, if the current adjustment step size is greater than or equal to the average adjustment step size, it indicates a non-compliance, and a PMA reset is performed until the adjustment step size is less than the average adjustment step size. If the current adjustment step size is less than the average adjustment step size, it indicates a compliance, and the cumulative interpolation values of the two critical states can be directly found based on the current phase interpolation statistical analysis results. This determines the final target cumulative interpolation value. Each channel performs phase interpolation on the clock signal according to its corresponding target cumulative interpolation value, effectively achieving multi-channel signal synchronization alignment. Attached Figure Description
[0054] Figure 1 This is a schematic diagram of the clock link of the test machine system in one embodiment;
[0055] Figure 2 Here is a system architecture diagram of the test machine in one embodiment;
[0056] Figure 3 This is a flowchart illustrating a multi-channel signal synchronization method in one embodiment;
[0057] Figure 4 This is a schematic diagram of the phase adjustment change curve of the first type in one embodiment;
[0058] Figure 5 This is a schematic diagram of the phase adjustment change curve of the second type in one embodiment;
[0059] Figure 6 Here is a flowchart of the phase interpolation steps in one embodiment;
[0060] Figure 7 This is a structural block diagram of a multi-channel signal synchronization device in one embodiment;
[0061] Figure 8 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0062] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by those skilled in the art. The technical terms used herein are for the purpose of describing specific examples and are not intended to limit the scope of protection of this application.
[0063] Figure 1 The middle arrow indicates the direction of the clock link in the test system. For example... Figure 1 As shown, the base clock is input to each resource board from the reference clock source, meaning that the clocks input to each channel are from the same source. However, in resource boards using high-speed transceivers (such as digital boards), the phase deviation (skew) between each high-speed transceiver channel (i.e., high-speed channel) after power-on is random, and the skew is usually large. Figure 1 The conversion channel is used to perform level conversion on the signal output from the high-speed channel before outputting it to the device under test (DUT). In the embodiments of this application, the channel refers to the high-speed channel, and the schemes or methods in the embodiments of this application aim to achieve signal synchronization alignment between multiple high-speed channels.
[0064] Some solutions employ phase interpolator (PI) technology to achieve high-precision phase adjustment, thereby enabling accurate alignment between multiple channels. PI technology can dynamically adjust the sampling or transmission clock phase of each channel with fine time steps, achieving an adjustment resolution of UI / 64. Through this PI technology, the phase skew between channels can be effectively reduced.
[0065] Now combined Figure 2 The diagram illustrates the system architecture of the test machine, illustrating the principles of PI technology. It should be understood that... Figure 2 This is for illustrative purposes only and should not be construed as limiting the modules in the test machine. The modules in the test machine can be... Figure 2 Based on this, we can make adaptive additions and deletions.
[0066] like Figure 2 As shown, the test machine includes a main control module and resource boards. The main control module, also known as a user logic module, can specifically be an FPGA, CPU, MCU, etc. The test machine may include one or more resource boards. Figure 2 This example only illustrates one resource board. Resource boards can include digital boards, power supply boards, etc.
[0067] The resource board includes a transmit module (TX), a phase-locked loop (PLL) module (e.g., CPLL or QPLL), and a clock delivery module. These three modules can be collectively referred to as the signal transmission module. For example, the signal transmission module can be a gigabit transmitter (GTH).
[0068] The transmit module (TX) includes a PI control module (PIC) and a physical media adapter layer module (PMA). The PIC includes a phase interpolator controller (TX Phase Interpolator Controller) and a buffer unit. The buffer unit is used to buffer pattern data (i.e., pattern data, also known as test vector data or waveform data), and the buffer unit can be a phase-adjusted first-in-first-out buffer (PMA). The PMA includes a phase interpolator (TX Phase Interpolator) and a frequency divider unit. The clock delivery module includes a clock unit BUFG_GT and a clock frequency divider unit BUFG_GT_dv. The clock unit BUFG_GT has a frequency multiplication function.
[0069] When the test machine inputs a common base clock (also called a reference clock, refclk) into the resource board, the write clock of the PIC's buffer unit can be determined based on the input base clock. For example... Figure 2As shown, the base clock is input to the clock unit BUFG_GT, which has a frequency multiplication function. Therefore, a higher frequency clock signal can be obtained based on the clock unit BUFG_GT, denoted as the PCS high-speed clock. Furthermore, the PCS high-speed clock is used as the write clock for the PIC's buffer unit. Based on this write clock, the code pattern data is written to the PIC's buffer unit for buffering. For example, the same base clock can be output to the resource board from the clock buffer module of the test machine.
[0070] For example, the code pattern data written to the buffer unit of the PIC can be generated under the control of the main control module. Figure 2 As shown, the clock divider unit BUFG_GT_dv in the clock transmission module divides the input base clock to obtain a lower frequency clock signal, which can be denoted as the PCS low-speed clock. The main control module can use this PCS low-speed clock to drive the generation of code pattern data. The generated code pattern data can be stored in the storage module (not shown in the figure), and when it needs to be written to the PIC's buffer unit, the code pattern data is sent to the PIC's buffer unit.
[0071] In addition, when a base clock of the same origin is input into the resource board, the phase-locked loop module outputs a clock signal (i.e., the initial read clock) for reading pattern data from the buffer unit of the PIC based on the input base clock.
[0072] The phase interpolator in the PMA (Phase-Locked Loop Module) interpolates the phase of the clock signal output from the PLL module, determining the final read clock based on the interpolated clock signal. It should be understood that the clock signal output from the PLL module is obtained by multiplying the base clock, thus belonging to a higher-frequency, high-speed clock. Therefore, the clock signal obtained by phase interpolation using the phase interpolator in the PMA can be called the PMA high-speed clock. Further, the PMA high-speed clock is divided using a frequency divider, and the divided PMA low-speed clock is used as the final read clock for the PIC's buffer unit. Subsequently, the buffered code data can be read from the buffer unit based on this final read clock.
[0073] In some examples, the phase interpolation controller configures the parameters of the PMA according to the control commands sent by the main control module. The phase interpolator in the PMA performs phase interpolation on the clock signal output by the phase-locked loop module according to the parameters configured by the phase interpolation controller.
[0074] Specifically, for each channel of the resource board, the main control module can perform forward phase interpolation processing on the clock signal output by the phase-locked loop module according to the buffer state of the buffer unit of each channel. Forward phase interpolation processing stops when the buffer state first changes from "not half-full" to "half-full" (i.e., the data in the buffer unit first reaches the preset capacity), and the cumulative interpolation value A is recorded as the critical state where the buffer state remains "not half-full" for multiple consecutive clock cycles. In the embodiments of this application, the cumulative interpolation value refers to the cumulative adjustment value of the phase of the clock signal (i.e., the read clock of the buffer unit), or the cumulative number of PI adjustments. PI is the adjustment unit for a single phase adjustment, meaning one PI is adjusted each time.
[0075] Taking a 128-clock-cycle period as an example, where the high and low levels (1 / 0) of the half_full signal indicate whether the buffer has reached a half-full state, the interpolation cumulative value A is equivalent to the critical state interpolation cumulative value that makes the half_full signal of the buffer state all 0 within 128 clock cycles. If positive phase interpolation is continued based on the interpolation cumulative value A, the buffer state will change from "not reaching a half-full state" to "half-full state" for the first time - that is, the half_full signal of the buffer state will change from 0 to 1 for the first time.
[0076] Furthermore, the clock signal output by the phase-locked loop module is subjected to reverse phase interpolation until the buffer state is detected to change from "half-full" to "not half-full" (i.e., the data in the buffer unit has not reached the preset capacity). The cumulative interpolation value B of the reverse phase interpolation is recorded—that is, the cumulative interpolation value of the critical state that makes the buffer state half-full for multiple consecutive clock cycles.
[0077] Similarly, referring to the example above, the interpolation cumulative value B is equivalent to the critical state interpolation cumulative value that makes the half_full signal of the buffer state all 1 for 128 clock cycles. That is, at the previous interpolation cumulative value B, the half_full signal of the buffer state is not all 1 for 128 clock cycles; it is only at the interpolation cumulative value B that the half_full signal of the buffer state is all 1 for 128 clock cycles.
[0078] Furthermore, after recording the interpolation cumulative value B, the clock signal output by the phase-locked loop module is subjected to reverse phase interpolation processing until the target phase interpolation is reached and then the interpolation is stopped; wherein, the target phase interpolation is calculated based on the interpolation cumulative value A and the interpolation cumulative value B.
[0079] It should be understood that the phase of the read clock in the internal buffer unit of the transmit module TX is random. Forward phase interpolation essentially increases the period of the read clock, while reverse phase interpolation essentially shortens the period of the read clock. By adjusting the frequency of the read clock in the buffer unit through phase interpolation, the position of the pointer in the buffer unit is changed. Therefore, the above-mentioned PI technology can achieve multi-channel phase alignment and, to a certain extent, achieve signal synchronization of multiple channels on various boards.
[0080] However, while the aforementioned PI technology can significantly reduce the maximum skew between channels, there is still room for optimization. Through in-depth research, the inventors of this application have proposed an optimized and improved phase interpolation adjustment scheme for the PI technology to further reduce inter-channel skew. For example, assuming that the traditional PI technology can reduce the maximum inter-channel skew to D (unit: ps), the improved phase interpolation adjustment scheme of this application can control the inter-channel skew within D / 2 (unit: ps). This significantly improves the synchronization performance of multi-channel high-speed transceivers and more effectively achieves multi-channel signal synchronization adjustment.
[0081] Specifically, the inventors of this application conducted an in-depth study on the phase interpolation variation patterns corresponding to each channel of the resource board. They discovered that the phase interpolation variation patterns for each channel of the resource board generally fall into two types. When the phase interpolation variation patterns for all channels are of the target type, the inter-channel skew can be effectively reduced further. For example, the inter-channel skew can be reduced from D to within D / 2 (unit: ps). The phase interpolation variation pattern refers to the change in the buffer state corresponding to the buffer unit of the channel as the phase interpolation is adjusted. Taking the half-full signal representing the buffer state as an example, the phase interpolation variation pattern can be the change in the duty cycle of the half-full signal as the cumulative interpolation value changes.
[0082] The inventors of this application discovered through further research that when the physical media adapter module (PMA) corresponding to a channel is reset, and then the phase interpolator in the reset PMA is used to perform phase interpolation on the clock signal (i.e., the initial read clock) used to read data from the buffer unit of that channel, the phase interpolation variation pattern may change. Therefore, by resetting the PMA corresponding to each channel, the phase interpolation variation pattern of each channel can be gradually made to conform to the target type.
[0083] Therefore, for each channel in the resource board, during the phase interpolation process of the clock signal (i.e., the initial read clock) reading data from its buffer unit, the change law of the buffer state with the phase interpolation (i.e., the phase interpolation change law) is statistically analyzed. Through PMA reset, the phase interpolation change law for each channel is ensured to meet the target type. When the phase interpolation change law for all channels meets the target type, inter-channel skew can be significantly reduced, achieving multi-channel signal synchronization and alignment more effectively and efficiently. For more detailed processing, please refer to the descriptions of multi-channel signal synchronization methods in the following embodiments.
[0084] like Figure 3 As shown, in some embodiments, a multi-channel signal synchronization method is provided, which is executed by a test machine (e.g., the main control module of the test machine), and specifically includes the following steps:
[0085] S31 performs phase interpolation on the clock signal used to read data from the buffer unit for each channel in the resource board, based on the buffer state of the buffer unit in the channel.
[0086] Each channel of the resource board has a corresponding transmit module; therefore, each channel also has a corresponding buffer unit (e.g., the buffer unit in the PIC of the transmit module). When the multi-channel signal synchronization adjustment process is formally initiated, for each channel on the resource board, based on the buffer state of the buffer unit in the channel, phase interpolation is performed on the clock signal used to read data from the buffer unit (i.e., the read clock). The clock signal used to read data from the buffer unit is output by the phase-locked loop module. The specific processing of phase interpolation is described above and will not be repeated here.
[0087] S32, the adjustment step size is obtained based on the difference between the second interpolation cumulative value and the first interpolation cumulative value; the first interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has not reached half-full state for multiple consecutive clock cycles; the second interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has reached half-full state for multiple consecutive clock cycles.
[0088] It should be understood that the specific number of consecutive clock cycles can be preset according to requirements. For example, 128 clock cycles.
[0089] During phase interpolation, two critical state interpolation cumulative values are recorded: the first interpolation cumulative value (i.e., interpolation cumulative value A mentioned above) and the second interpolation cumulative value (i.e., interpolation cumulative value B mentioned above). Then, the adjustment step size is obtained based on the difference between the second and first interpolation cumulative values. For example, the adjustment step size C = interpolation cumulative value B - interpolation cumulative value A.
[0090] S33, if the adjustment step size is greater than the average adjustment step size, reset the Physical Media Adaptor (PMA) module in the channel and recalculate the adjustment step size until the adjustment step size is less than or equal to the average adjustment step size, then stop resetting.
[0091] In some examples, the average step size can be a preset empirical value.
[0092] In other examples, the average adjustment step size can be the average of multiple adjustment step sizes calculated by performing multiple PMA resets on the channel beforehand. That is, before the formal multi-channel signal synchronous adjustment (detectable as formal adjustment processing), during the data preparation phase, for each channel in the resource board, multiple PMA resets are performed on the channel beforehand. After each PMA reset, the clock signal used to read data from the buffer unit is phase interpolated, and the adjustment step size is calculated based on the phase interpolation statistical analysis results. The adjustment step size refers to the difference between the interpolated cumulative values of two critical states (i.e., the interpolated cumulative values when the buffer state of the buffer unit in the channel is exactly half-full or exactly not half-full within multiple clock cycles). Thus, based on the multiple adjustment step sizes calculated after multiple PMA resets, the average adjustment step size corresponding to the channel is obtained. The number of PMA resets during the data preparation phase can be preset according to actual needs.
[0093] In some examples, prior to step S31, the method further includes: an adjustment step average calculation step, specifically including: performing multiple PMA resets on each channel in the resource board; calculating the adjustment step size after each PMA reset, and determining the average adjustment step size based on the calculated adjustment step size; wherein, calculating the adjustment step size after each PMA reset includes: performing phase interpolation on the clock signal based on the buffer state of the buffer unit in the channel after each PMA reset; obtaining the current adjustment step size based on the difference between the fourth interpolation cumulative value and the third interpolation cumulative value; the third interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that is not half-full for multiple consecutive clock cycles; the fourth interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that is half-full for multiple consecutive clock cycles. It should be understood that, in order to distinguish the data preparation stage from the formal adjustment processing, the interpolation cumulative values of the two critical states in the data preparation stage are denoted as the third interpolation cumulative value and the fourth interpolation cumulative value, but this does not impose any other limitations.
[0094] After obtaining the average adjustment step size, for each channel, the adjustment step size calculated for that channel in step S32 (i.e., the adjustment step size calculated for that channel in the formal adjustment process) is compared with the average adjustment step size. It should be understood that the average adjustment step size calculated based on the adjustment step size after multiple PMA resets must lie between the adjustment step sizes under the two possible types. If the adjustment step size is greater than the average adjustment step size, it indicates that the current phase interpolation change pattern of that channel does not conform to the target type (the target type can be as follows). Figure 4 The first type shown), but another type that converges more slowly (such as the first type shown). Figure 5 (As shown in the second type below), the PMA corresponding to that channel can be reset, and steps S31 to S32 can be re-executed after the PMA reset to recalculate the adjustment step size until the adjustment step size is less than or equal to the average adjustment step size. It should be understood that if the adjustment step size is less than or equal to the average adjustment step size, it indicates that the current phase interpolation change pattern of the channel conforms to the target type, and the PMA reset for that channel should be stopped.
[0095] In some embodiments, if the half-full signal of the buffer unit (i.e., the half_full signal) is low (i.e., the half_full level is 0), the buffer state is not half-full; if the half-full signal of the buffer unit is high (i.e., the half_full level is 1), the buffer state is half-full.
[0096] The phase interpolation variation pattern for each channel can be characterized by the phase adjustment variation curve for that channel. The phase adjustment variation curve refers to the curve showing how the duty cycle of the half-full signal of the buffer unit in the channel changes with the cumulative interpolation value of the read clock (i.e., the clock signal used to read data from the buffer unit).
[0097] When the adjustment step size is less than or equal to the average adjustment step size, the phase adjustment change curve corresponding to the channel is of type I. Figure 4 Used to illustrate the phase adjustment change curve of the first type.
[0098] When the adjustment step size is greater than the average adjustment step size, the phase adjustment change curve is of the second type. Figure 5 Used to illustrate the phase adjustment change curve of the second type.
[0099] The duty cycle of a half-full signal refers to the number of times the buffer unit's half-full signal is high within a preset number of clock cycles. Taking a preset number of clock cycles of 64k (i.e., 64000) clock cycles as an example... Figure 4When the phase interpolation cumulative value is approximately 32, the duty cycle of the half-full signal is exactly 0, meaning that the half-full signal is high for 0 consecutive clock cycles (i.e., all high levels). When the phase interpolation cumulative value is approximately 40, the duty cycle of the half-full signal is approximately 15000, meaning that the half-full signal is 1 for 15000 clock cycles out of 64000 clock cycles, hence the high-level count is 15000. When the phase interpolation cumulative value reaches 68, the duty cycle of the half-full signal stabilizes—reaches its maximum. That is, when the phase interpolation cumulative value is 68, the half-full signal is high for 64000 consecutive clock cycles, hence the high-level count is 64000.
[0100] Figure 5 When the interpolated cumulative value of the mid-phase is approximately 10⁸, the duty cycle of the half-full signal reaches stability.
[0101] from Figure 4 As can be seen from the phase adjustment change curve of the first type, as the cumulative interpolation value of the phase gradually increases, the number of half_full high levels within 64k cycles (clock cycles) shows an approximately linear increase without obvious steps and fast convergence speed, indicating that the phase interpolation adjustment response is good and can quickly lock the center of the data eye.
[0102] from Figure 5 As can be seen, in the first type of phase adjustment curve, as the interpolation cumulative value gradually increases, the number of half_full high-level times within 64k cycles exhibits a clear step-like change, with a distinct transition plateau. This nonlinear behavior leads to a significant decrease in convergence speed.
[0103] Therefore, the first type is the target type that can achieve channel synchronization more effectively and efficiently. That is, when the phase adjustment change curve corresponding to each channel is of the first type, after performing phase interpolation for each channel according to the target interpolation cumulative value, the signals of each channel can be quickly and effectively synchronized and aligned.
[0104] S34: Determine the target interpolation cumulative value based on the second interpolation cumulative value and the first interpolation cumulative value when the reset is stopped, and perform phase interpolation on the clock signal according to the target interpolation cumulative value.
[0105] It should be understood that, for each channel, stopping the PMA reset for that channel indicates that the current phase interpolation change pattern of that channel conforms to the target type, thus allowing the determination of the second interpolation cumulative value and the first interpolation cumulative value at the time of stopping the reset. Furthermore, based on the average of the determined second interpolation cumulative value and the determined first interpolation cumulative value, the target interpolation cumulative value is determined; and phase interpolation of the clock signal is performed according to the target interpolation cumulative value.
[0106] In some embodiments, after each phase interpolation, the interpolation accumulation value is updated, and the buffer state for multiple consecutive clock cycles under the updated interpolation accumulation value is statistically analyzed. After stopping the PMA reset, if phase interpolation is performed based on the PMA after the last reset, the current phase interpolation change pattern of the channel can conform to the target type. Therefore, after stopping the PMA reset, step S31 can be re-executed to perform phase interpolation on the clock signal used to read data from the buffer unit based on the buffer state of the buffer unit in the channel. That is, the phase interpolator in the PMA after reset is used to perform phase interpolation on the read clock of the buffer unit. Then, based on the buffer state for multiple consecutive clock cycles under the interpolation accumulation value after each phase interpolation, the second interpolation accumulation value and the first interpolation accumulation value at the time of stopping the reset are determined.
[0107] In other embodiments, since steps S31 and S32 have already been executed when determining whether to stop the PMA reset—that is, the second interpolation cumulative value and the first interpolation cumulative value at the time of the last PMA reset have already been calculated—and the adjustment step size determined by the difference between the two is less than or equal to the average adjustment step size, it is determined that the reset can be stopped. Therefore, the second interpolation cumulative value and the first interpolation cumulative value calculated at the time of the last reset can be cached. After stopping the PMA reset, the second interpolation cumulative value and the first interpolation cumulative value calculated at the time of the last reset can be directly used as the second interpolation cumulative value and the first interpolation cumulative value at the time of stopping the reset, without having to re-execute steps S31 and S32, thus saving computational resources.
[0108] The above method employs an optimized phase interpolation adjustment scheme to achieve synchronous adjustment of multi-channel signals. Specifically, for each channel on the board, during the phase interpolation process of the clock signal reading data from its buffer unit, the phase interpolation change pattern is statistically analyzed. Then, through PMA reset, the phase interpolation change pattern for each channel is ensured to meet the target type. When the phase interpolation change pattern for all channels meets the target type, synchronous alignment of multi-channel signals can be achieved.
[0109] In some embodiments, one of the states being half-full and not half-full is designated as the first state, and the other as the second state. For example... Figure 6 As shown, in this embodiment, step S31 (referred to as the "phase interpolation step") includes:
[0110] S311: If the buffer state is in the first state for N consecutive clock cycles, perform phase interpolation of the clock signal in the first direction with a step length until the buffer state has a second state for N consecutive clock cycles.
[0111] S312, continue to perform phase interpolation of the clock signal in the second direction with the second step size until the buffer state is in the first state for M consecutive clock cycles, and record the first current interpolation cumulative value; the second step size is less than the first step size; the second direction is opposite to the first direction.
[0112] S313, continue to perform phase interpolation of the clock signal in the first direction with the second step size until the buffer state is in the second state for M consecutive clock cycles, and record the second current interpolation cumulative value; where M and N are both integers greater than or equal to 2; the second current interpolation cumulative value is different from the first current interpolation cumulative value, and is one of the second interpolation cumulative value and the first interpolation cumulative value respectively.
[0113] In Example 1, the first state is not yet half-full, and the first direction is positive. The second state is half-full, and the second direction is negative. The first current interpolation cumulative value is the first interpolation cumulative value (i.e., the interpolation cumulative value A of the critical state that makes the buffer state not yet half-full for M consecutive clock cycles); the second current interpolation cumulative value is the second interpolation cumulative value (i.e., the interpolation cumulative value B of the critical state that makes the buffer state half-full for M consecutive clock cycles).
[0114] Taking the half-full signal as an example to represent the buffer state of a buffer unit:
[0115] In Example 1, step S311 includes: for each channel, if the half_full level of the buffer unit corresponding to the channel is all low (i.e. all 0) for N consecutive clock cycles, perform forward phase interpolation on the clock signal (i.e., read clock) used to read data from the buffer unit with a step size (e.g., step size 15, i.e., adjust 15 PI each time) until the half_full level of the buffer unit is high (i.e., there is 1 or not all 0) for N consecutive clock cycles, and stop the forward phase interpolation.
[0116] Step S312 includes: continuing to perform reverse phase interpolation on the read clock corresponding to the buffer unit with a second step size (e.g., step size 1, i.e., adjusting 1 PI each time) until the half_full level of the buffer unit is low (i.e., all 0) for M consecutive clock cycles, and recording the current interpolation cumulative value (i.e., the first current interpolation cumulative value). In this case, the first current interpolation cumulative value is the first interpolation cumulative value.
[0117] Step S313 includes: continuing to perform forward phase interpolation on the read clock corresponding to the buffer unit with a second step size (such as step size 1) until the half_full level of the buffer unit is high (i.e. all 1) for M consecutive clock cycles, and recording the current interpolation cumulative value (i.e. the second current interpolation cumulative value).
[0118] Combination Figure 4 To explain Example 1 above, assume that initially the half_full level is 0 for multiple clock cycles, with the first step size being 15 and the second step size being 1. In step S311, forward phase interpolation (i.e., increasing PI) is performed first with a step size of 15. Assuming the cumulative interpolation value of 45 is found first, reverse phase interpolation (i.e., decreasing PI) is performed with a step size of 1, thus gradually finding the cumulative interpolation value A (i.e., 32) of the critical state. Then, referring to the cumulative interpolation value A of the critical state, fine-grained forward phase interpolation is performed with a step size of 1 to find another critical point—the cumulative interpolation value B of the critical state.
[0119] In Example 2, the first state is a half-full state with the first direction being reversed, the second state is not yet half-full with the second direction being forward, the first current interpolation cumulative value is the second interpolation cumulative value (i.e., the interpolation cumulative value B of the critical state that makes the buffer state half-full for M consecutive clock cycles); the second current interpolation cumulative value is the first interpolation cumulative value (i.e., the interpolation cumulative value A of the critical state that makes the buffer state not yet half-full for M consecutive clock cycles).
[0120] Taking the half-full signal as an example to represent the buffer state of a buffer unit:
[0121] In Example 2, step S311 includes: for each channel, if the half_full level of the buffer cell corresponding to the channel is all high (i.e. all 1) for N consecutive clock cycles, reverse phase interpolation is performed on the clock signal (i.e., the read clock) used to read data from the buffer cell with a first step size (e.g., step size 15) until the half_full level of the buffer cell is low (i.e., there is 0 or not all 1) for N consecutive clock cycles, and then the reverse phase interpolation is stopped.
[0122] Step S312 includes: continuing to perform forward phase interpolation on the read clock corresponding to the buffer unit with a second step size (such as step size 1) until the half_full level of the buffer unit is high (i.e. all 1) for M consecutive clock cycles, and recording the current interpolation cumulative value (i.e. the first current interpolation cumulative value).
[0123] Step S313 includes: continuing to perform reverse phase interpolation on the read clock corresponding to the buffer unit with a second step size (such as step size 1) until the half_full level of the buffer unit is low (i.e. all 0) for M consecutive clock cycles, and recording the current interpolation cumulative value (i.e. the second current interpolation cumulative value).
[0124] Combination Figure 5 To explain Example 2 above, assuming that the half_full level is 1 for multiple clock cycles initially, in step S311, reverse phase interpolation (i.e., decrementing PI) is first performed with a step size of 15. Assuming the cumulative interpolation value of 100 is found, forward phase interpolation (i.e., increasing PI) is then performed with a step size of 1, gradually finding the cumulative interpolation value B (e.g., 108) of the critical state. Then, referring to the cumulative interpolation value B of the critical state, fine-grained reverse phase interpolation is performed with a step size of 1 to find another critical point—the cumulative interpolation value A of the critical state.
[0125] In the above scheme, the interpolated cumulative value processed in step S311 is near the interpolated cumulative value of the critical state (i.e., the critical point). This is equivalent to first using a larger step size to find the vicinity of the critical point, and then, in step S312, using a smaller step size to perform finer-grained phase interpolation in the opposite direction, thereby finding the critical point more accurately. Based on the already found critical point, further interpolation can be performed to find another critical point more accurately.
[0126] In some embodiments, if the buffer state is not always in the first state over N consecutive clock cycles, the clock signal is phase interpolated in the second direction with a third step size until the buffer state is always in the first state over N consecutive clock cycles. The third step size may be equal to or different from the first or second step size.
[0127] In some embodiments, before step S31, it is also possible to detect whether the buffer state is abnormal. For example, the buffer unit in the channel has a corresponding status register, and the level on the preset bit of the status register can be detected (for example, the bufstatus[1] level, that is, the level on the bit with index 1 of the status register); if the level indicates that the buffer unit is full or empty, it is determined that the buffer state of the buffer unit is abnormal; otherwise, it is determined that the buffer state of the buffer unit is normal.
[0128] In the event of an abnormal buffer state, the channel is PMA reset until the buffer state returns to normal. After the buffer state returns to normal, step S31 is executed to perform phase interpolation on the clock signal used to read data from the buffer unit based on the buffer state of the buffer unit in the channel.
[0129] In some embodiments, taking M=128, N=8, first step length=15, second step length=1, third step length=15, first direction is positive, second direction is negative, and the preset bit is the first bit as an example, the steps of the multi-channel signal synchronization method are illustrated, specifically including the following steps:
[0130] 1. After receiving the tx_sync_en synchronization PI alignment signal, proceed to step 2.
[0131] 2. For each channel, check the level of bufstatus[1]. If bufstatus[1] is 0, it means that the buffer status of the corresponding buffer unit is normal, and then proceed to step 3. Otherwise, if bufstatus[1] is 1, it means that the buffer unit is full or empty, and the buffer status is abnormal. Then perform a PMA reset for the channel until the level of bufstatus[1] is low (i.e., 0).
[0132] 3. Detect the half_full level of the buffer unit corresponding to the channel. If the half_full level is all 0 within 8 clock cycles, proceed to step 4. Otherwise (i.e., the half_full level is not all 0 within 8 clock cycles), perform reverse phase interpolation on the read clock corresponding to the buffer unit with a step size of 15 (i.e., the third step size) until the half_full level is all 0 within 8 clock cycles.
[0133] 4. Increase PI in steps of 15 (i.e., the first step size) (i.e., perform positive phase interpolation on the read clock corresponding to the buffer unit) until the half_full level is not all 0 (or there is 1) within 8 clock cycles.
[0134] 5. Continue to subtract PI from the read clock corresponding to the buffer unit with a step size of 1 (i.e., the second step size) (i.e., perform reverse phase interpolation) until the half_full level is 0 for 128 clock cycles. Record the PI value at this time as A (i.e., the current interpolation cumulative value A).
[0135] 6. Continue to increase PI by a step size of 1 (i.e., the second step size) (i.e., perform positive phase interpolation on the read clock corresponding to the buffer unit) until the half_full level is 1 for 128 clock cycles. Record the PI value at this time as B (i.e., the current interpolation cumulative value B). Adjust the step size to C=BA.
[0136] 7. Perform PMA reset on the channel 16 times. After each PMA reset, repeat steps 2 to 6, and count a total of 16 adjustment steps C.
[0137] 8. Calculate the average value of the adjustment step size C for 16 adjustments to obtain the average adjustment step size. Use this average adjustment step size as the criterion for judging the type of subsequent curves.
[0138] It should be understood that the process of calculating the average adjustment step size belongs to the data preparation stage.
[0139] 9. In the formal adjustment process, for each channel, steps 2 to 6 are executed to obtain the adjustment step size C corresponding to each channel in the formal adjustment process.
[0140] 10. Compare the adjustment step size C corresponding to each channel in the formal adjustment process with the average adjustment step size. If the adjustment step size C ≤ the average adjustment step size, the phase adjustment change curve corresponding to that channel is determined to be of type one (i.e., target type). If the adjustment step size C > the average adjustment step size, it means that the phase adjustment change curve corresponding to that channel is not type one but type two. Then, perform PMA reset on that channel until the subsequent adjustment step size C ≤ the average adjustment step size.
[0141] 11. If the phase adjustment change curves of all channels on the resource board are of type 1, then repeat steps 3 to 6 for all channels to obtain the interpolation cumulative value A and interpolation cumulative value B for each channel; calculate the target interpolation cumulative value = (B+A) / 2.
[0142] 12. For each channel, perform PI adjustment control (i.e., phase interpolation) on the read clock of the buffer unit of that channel so that the current interpolation cumulative value reaches (B+A) / 2, thereby completing the multi-channel signal synchronization alignment.
[0143] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. At least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the steps or stages of other steps.
[0144] Based on the same inventive concept, this application also provides a multi-channel signal synchronization device for implementing the above-mentioned method. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more embodiments of the multi-channel signal synchronization device provided below can be found in the limitations of the multi-channel signal synchronization method described above, and will not be repeated here.
[0145] like Figure 7As shown, in one embodiment, a multi-channel signal synchronization device is provided, the device comprising:
[0146] Phase interpolation unit 702 is used to perform phase interpolation on the clock signal used to read data from the buffer unit for each channel in the resource board, based on the buffer state of the buffer unit in the channel.
[0147] For example, the phase interpolation unit 702 is located within the main control module of the test machine. Based on the buffer state of the buffer unit in the channel, the phase interpolation unit 702 in the main control module sends control commands to the phase interpolation controller in the PIC. The phase interpolation controller configures the parameters of the PMA according to the control commands sent by the main control module. The phase interpolator in the PMA performs phase interpolation on the clock signal output by the phase-locked loop module according to the parameters configured by the phase interpolation controller.
[0148] The adjustment step size calculation unit 704 is used to obtain the adjustment step size based on the difference between the second interpolation cumulative value and the first interpolation cumulative value; the first interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has not reached half-full state for multiple consecutive clock cycles; the second interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has reached half-full state for multiple consecutive clock cycles.
[0149] The reset unit 706 is used to reset the Physical Media Adaptor (PMA) unit in the channel if the adjustment step size is greater than the average adjustment step size, and recalculate the adjustment step size until the adjustment step size is less than or equal to the average adjustment step size, and then stop the reset.
[0150] For example, the reset unit 706 in the main control module can send a reset command to the PMA corresponding to the channel to achieve PMA reset.
[0151] The phase interpolation unit 702 is also used to determine the target interpolation cumulative value based on the second interpolation cumulative value and the first interpolation cumulative value when the reset is stopped, and to perform phase interpolation on the clock signal according to the target interpolation cumulative value.
[0152] In some embodiments, one of the half-full state and the state not reaching half-full is denoted as the first state, and the other is denoted as the second state; the phase interpolation unit 702 is further configured to, when the buffer state is in the first state for N consecutive clock cycles, perform phase interpolation of the clock signal in the first direction with a first step length until the buffer state has a second state for N consecutive clock cycles; continue to perform phase interpolation of the clock signal in the second direction with a second step length until the buffer state is in the first state for M consecutive clock cycles, and record the first current interpolation cumulative value; the second step length is less than the first step length; the second direction is opposite to the first direction; continue to perform phase interpolation of the clock signal in the first direction with a second step length until the buffer state is in the second state for M consecutive clock cycles, and record the second current interpolation cumulative value; wherein, M and N are both integers greater than or equal to 2; the second current interpolation cumulative value and the first current interpolation cumulative value are different, and are one of the second interpolation cumulative value and the first interpolation cumulative value, respectively.
[0153] In some embodiments, the phase interpolation unit 702 is further configured to perform phase interpolation of the clock signal in a second direction with a third step size when the buffer state is not always in the first state within N consecutive clock cycles, until the buffer state is always in the first state within N consecutive clock cycles.
[0154] In some embodiments, the device further includes:
[0155] An anomaly detection unit (not shown in the figure) is used to detect whether the buffer state is abnormal. If the buffer state is abnormal, the channel is PMA reset until the buffer state returns to normal. After the buffer state returns to normal, the phase interpolation unit 702 is notified to perform phase interpolation on the clock signal used to read data from the buffer unit based on the buffer state of the buffer unit in the channel.
[0156] In some embodiments, the buffer unit in the channel has a corresponding status register; the anomaly detection unit is also used to detect the level on a preset bit of the status register; if the level indicates that the buffer unit is full or empty, the buffer state of the buffer unit is determined to be abnormal.
[0157] In some embodiments, the phase interpolation unit 702 is further configured to determine a second interpolation cumulative value and a first interpolation cumulative value when the reset is stopped; and to determine a target interpolation cumulative value based on the average of the determined second interpolation cumulative value and the determined first interpolation cumulative value.
[0158] In some embodiments, after each phase interpolation, the interpolation cumulative value is updated, and the buffer state for multiple consecutive clock cycles under the updated interpolation cumulative value is counted.
[0159] The phase interpolation unit 702 is also used to re-execute the phase interpolation of the clock signal used to read data from the buffer unit based on the buffer state of the buffer unit in the channel after the stop reset; and to determine the second interpolation cumulative value and the first interpolation cumulative value at the time of the stop reset based on the buffer state of the buffer for multiple consecutive clock cycles under the interpolation cumulative value after each phase interpolation.
[0160] In some embodiments, the phase interpolation unit 702 is further configured to use the second interpolation cumulative value and the first interpolation cumulative value calculated during the last reset as the second interpolation cumulative value and the first interpolation cumulative value when the reset stops.
[0161] In some embodiments, the reset unit 706 is further configured to perform multiple PMA resets on each channel in the resource board;
[0162] The adjustment step size calculation unit 704 is also used to calculate the adjustment step size after each PMA reset;
[0163] The phase interpolation unit 702 is also used to perform phase interpolation on the clock signal based on the buffer state of the buffer unit in the channel after each PMA reset; and to obtain the adjustment step size for this time based on the difference between the fourth interpolation cumulative value and the third interpolation cumulative value; the third interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has not reached half-full state for multiple consecutive clock cycles; the fourth interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has reached half-full state for multiple consecutive clock cycles;
[0164] The device also includes:
[0165] The step size mean calculation unit (not shown in the figure) is used to determine the mean adjustment step size based on the adjustment step size calculated in each iteration.
[0166] Each unit in the aforementioned multi-channel signal synchronization device can be implemented entirely or partially through software, hardware, or a combination thereof. These units can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each unit.
[0167] In one embodiment, a computer device is provided, which may be a test machine or the main control module of a test machine. The internal structure diagram of the computer device may be as follows: Figure 8As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external devices via a network connection. When the computer program is executed by the processor, it implements a multi-channel signal synchronization method.
[0168] Those skilled in the art will understand that Figure 8 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0169] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the embodiments of this application.
[0170] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the embodiments of this application.
[0171] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. The processors involved in the embodiments provided in this application can be general-purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited thereto.
[0172] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
Claims
1. A multi-channel signal synchronization method, characterized in that, The method includes: For each channel in the resource board, based on the buffer state of the buffer unit in the channel, the clock signal used to read data from the buffer unit is phase interpolated; The adjustment step size is obtained based on the difference between the second interpolation cumulative value and the first interpolation cumulative value; the first interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has not reached half-full state for multiple consecutive clock cycles; the second interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has reached half-full state for multiple consecutive clock cycles. If the adjustment step size is greater than the average adjustment step size, the Physical Media Adaptor (PMA) module in the channel is reset, and the adjustment step size is recalculated until the adjustment step size is less than or equal to the average adjustment step size, at which point the reset stops. The target interpolation cumulative value is determined based on the second interpolation cumulative value and the first interpolation cumulative value at the time of stop reset, and the clock signal is phase interpolated according to the target interpolation cumulative value.
2. The method according to claim 1, characterized in that, If the half-full signal of the buffer unit is low, the buffer state is not half-full; if the half-full signal of the buffer unit is high, the buffer state is half-full. When the adjustment step size is less than or equal to the average adjustment step size, the phase adjustment change curve corresponding to the channel is of the first type; When the adjustment step size is greater than the average adjustment step size, the phase adjustment change curve is of the second type; wherein, the phase adjustment change curve refers to the curve of the duty cycle of the half-full signal of the buffer unit in the channel changing with the interpolated cumulative value of the clock signal; When the phase adjustment change curves corresponding to each channel are all of the first type, after performing phase interpolation on each channel according to the target interpolation cumulative value, the signals of each channel are synchronized and aligned.
3. The method according to claim 1, characterized in that, One of the half-full state and the state that is not half-full is designated as the first state, and the other is designated as the second state. The step of performing phase interpolation on the clock signal used to read data from the buffer unit based on the buffer state of the buffer unit in the channel includes: If the buffer state is in the first state for N consecutive clock cycles, the clock signal is phase interpolated in the first direction with a first step length until the buffer state exists in the second state for N consecutive clock cycles. The clock signal is further interpolated in a second direction with a second step size until the buffer state is in the first state for M consecutive clock cycles, and the first current interpolation cumulative value is recorded; the second step size is smaller than the first step size; the second direction is opposite to the first direction; The clock signal is further interpolated in the first direction using the second step size until the buffer state is in the second state for M consecutive clock cycles. The second current interpolation cumulative value is recorded. M and N are both integers greater than or equal to 2. The second current interpolation cumulative value is different from the first current interpolation cumulative value and is one of the second interpolation cumulative value and the first interpolation cumulative value, respectively.
4. The method according to claim 3, characterized in that, The method further includes: If the buffer state is not always in the first state within N consecutive clock cycles, the clock signal is phase interpolated in the second direction with a third step size until the buffer state is always in the first state within N consecutive clock cycles.
5. The method according to claim 3 or 4, characterized in that, The first state is not half full, and the first direction is positive. The second state is half full, and the second direction is negative. The first current interpolation cumulative value is the first interpolation cumulative value; the second current interpolation cumulative value is the second interpolation cumulative value. or, The first state is a half-full state, and the first direction is reverse. The second state is a state that has not reached half-full, and the second direction is forward. The first current interpolation cumulative value is the second interpolation cumulative value; the second current interpolation cumulative value is the first interpolation cumulative value.
6. The method according to claim 1, characterized in that, The buffer unit in the channel has a corresponding status register; Before performing phase interpolation on the clock signal used to read data from the buffer unit based on the buffer state of the buffer unit in the channel, the method further includes: Detect the level of a preset bit in the status register; If the level indicates that the buffer unit is full or empty, the buffer state of the buffer unit is determined to be abnormal, and the channel is PMA reset until the buffer state returns to normal. After the buffer state returns to normal, the buffer state based on the buffer unit in the channel is used to perform phase interpolation on the clock signal used to read data from the buffer unit.
7. The method according to claim 1, characterized in that, After each phase interpolation, the interpolation cumulative value is updated, and the buffer state for multiple consecutive clock cycles under the updated interpolation cumulative value is counted. The step of determining the target interpolation cumulative value based on the second interpolation cumulative value at the time of stopping reset and the first interpolation cumulative value includes: After stopping the reset, the buffer state based on the buffer unit in the channel is re-executed to perform phase interpolation on the clock signal used to read data from the buffer unit; Based on the buffer state over multiple consecutive clock cycles following each phase interpolation, the second interpolation cumulative value and the first interpolation cumulative value at the time of stop reset are determined. The target interpolation cumulative value is determined based on the average of the determined second interpolation cumulative value and the determined first interpolation cumulative value.
8. The method according to claim 1, characterized in that, The step of determining the target interpolation cumulative value based on the second interpolation cumulative value at the time of stopping reset and the first interpolation cumulative value includes: The second interpolated cumulative value and the first interpolated cumulative value calculated during the last reset are used as the second interpolated cumulative value and the first interpolated cumulative value at the time of stopping the reset. The target interpolation cumulative value is determined based on the average of the determined second interpolation cumulative value and the determined first interpolation cumulative value.
9. The method according to claim 1, characterized in that, The average adjustment step size is the average of multiple adjustment step sizes calculated by performing multiple PMA resets on the channel in advance; before performing phase interpolation on the clock signal used to read data from the buffer unit based on the buffer state of the buffer unit in the channel, the method further includes: For each channel in the resource board, perform multiple PMA resets on the channel; Calculate the adjustment step size after each PMA reset, and determine the average adjustment step size based on the calculated adjustment step size. The calculation of the adjustment step size after each PMA reset includes: After each PMA reset, the clock signal is phase interpolated based on the buffer state of the buffer unit in the channel; The adjustment step size is obtained based on the difference between the fourth interpolation cumulative value and the third interpolation cumulative value; the third interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has not reached half-full state for multiple consecutive clock cycles; the fourth interpolation cumulative value is the interpolation cumulative value that makes the buffer state a critical state that has reached half-full state for multiple consecutive clock cycles.
10. A testing machine, characterized in that, The test machine includes a resource board; the resource board includes a main control module, which is used to execute the steps of the method according to any one of claims 1 to 9.