Power supply control system and server

Abstract

The present disclosure provides a power supply control system and a server, the power supply control system comprising: a control component configured to send an enable signal to a power supply component when detecting that the server is powered on; the power supply component connected with the control component, configured to generate a power supply state signal in response to the enable signal and send the power supply state signal to the control component; wherein the control component is further configured to acquire register information of the power supply component when the power supply state signal indicates an abnormality, determine a power supply abnormality type according to the register information, and send an off signal to the power supply component.

Description

Technical Field

[0001] This disclosure relates to the field of servers, and more particularly to a power control system and a server. Background Technology

[0002] When the power supply chip's load fails, all chip enablements are disabled, and only the Voltage Regulator Module Power-Good Signal (VR PG) or an alarm signal is recorded in the server log. Furthermore, since the power supply chip's fault information is stored in registers, immediately disabling the chip when its load fails will result in the loss of this information after power-down. This makes it impossible to obtain detailed error information about the power supply chip, hindering the analysis and troubleshooting of the server. Summary of the Invention

[0003] In view of this, the present disclosure provides a power control system and a server.

[0004] One aspect of this disclosure provides a power control system, including: a control component configured to send an enable signal to a power component when a server is detected to be powered on; and a power component connected to the control component configured to generate a power status signal in response to the enable signal and send the power status signal to the control component; wherein the control component is further configured to acquire register information of the power component, determine the type of power abnormality based on the register information, and send a shutdown signal to the power component when the power status signal indicates an abnormality.

[0005] According to embodiments of this disclosure, the power supply component includes: at least one power supply unit, each power supply unit being connected to a control component; the control component is configured to, upon detecting that the server is powered on, sequentially send an enable signal to at least one power supply unit according to a preset timing logic, and, in response to a power status signal indicating an abnormality returned from any power supply unit, obtain register information of the abnormal power supply unit via an integrated circuit bus, determine the power abnormality type based on the register information, and send a shutdown signal to the abnormal power supply unit.

[0006] According to embodiments of this disclosure, each power supply unit includes: a fuse and a voltage regulator, the fuse and the voltage regulator being respectively connected to a control component, and the fuse being electrically connected to the voltage regulator; the fuse is configured to output a power supply voltage to the voltage regulator in response to a first enable signal from the control component, generate a first power status signal according to first operating parameters, and send the first power status signal to the control component; the first operating parameters include at least one of the output voltage, output current, and internal temperature of the fuse; the voltage regulator is configured to convert the power supply voltage to a target voltage and output it to a load in response to a second enable signal from the control component, generate a second power status signal according to second operating parameters, and send the second power status signal to the control component; the second operating parameters include the output voltage of the voltage regulator.

[0007] According to embodiments of this disclosure, a power supply component includes at least one register, the value of a set flag bit in the register being used to indicate the state of the power supply component. The power status signal includes a power-good signal and an alarm signal. The control component is further configured to: in response to a power-good signal indicating an anomaly, locate an abnormal power supply unit in the power supply component by querying a hardware mapping table; the hardware mapping table indicates the correspondence between the pin numbers of the power-good signal and the power supply units in the power supply component; in response to an alarm signal indicating an anomaly, locate the abnormal power supply unit in the power supply component by sending an alarm response address command; the alarm response address command is used to cause the abnormal power supply unit to return a corresponding device address to the control component; obtain register information of the abnormal power supply unit and determine the power anomaly type by parsing the register information; save the power anomaly type and register information, and send a shutdown signal to the abnormal power supply unit.

[0008] According to embodiments of this disclosure, the control component is further configured to: determine whether to restore power supply based on the type of power supply abnormality; wherein the power supply abnormality type includes at least one of: transient overcurrent, transient undervoltage, overtemperature warning, input undervoltage, overvoltage latch, continuous overcurrent latch, short circuit latch, and power supply damage; and determine to restore power supply when the power supply abnormality type is at least one of transient overcurrent, transient undervoltage, overtemperature warning, and input undervoltage.

[0009] According to embodiments of this disclosure, the control component is further configured to: send an enable signal to the power supply component again when it is determined that power is restored; complete the power-on of the server in response to all power status signals received from the power supply component indicating normal operation; and maintain the power supply component off in response to any power status signal received from the power supply component indicating abnormal operation and the number of times the enable signal is sent to the power supply component again is greater than a predetermined threshold.

[0010] According to embodiments of this disclosure, it further includes: a management component configured to read register information from a target storage area of ​​the control component in a polling or interrupt manner, and generate a power management log based on the register information.

[0011] According to embodiments of this disclosure, it further includes: an access control component connected to the management component, the control component, and the power component via an integrated circuit bus C, configured to disconnect the communication between the management component and the power component and the control component during the process of the control component reading the register information of the power component via the integrated circuit bus C, and to restore the communication between the management component and the power component and the control component after the control component has finished reading the register information of the power component.

[0012] According to embodiments of this disclosure, the buffer output enable terminal of the control component is connected to the access control component; the control component is further configured to, during the upgrade of the management component, output an enable signal with a first level via the buffer output enable terminal to disconnect the communication between the management component and the power component and the control component, and, upon completion of the upgrade of the management component, output an enable signal with a second level via the buffer output enable terminal to restore the communication between the management component and the power component and the control component.

[0013] In one embodiment, the first level is a high level and the second level is a low level.

[0014] In another embodiment, the first level is low and the second level is high.

[0015] Another aspect of this disclosure provides a server, including: a power supply unit configured to provide a power supply voltage; a control component configured to send an enable signal to the power supply component when the server is detected to be powered on; and a power supply component connected to the control component and the power supply unit, configured to generate a power status signal in response to the enable signal and send the power status signal to the control component; wherein the control component is further configured to acquire register information of the power supply component, determine the power abnormality type based on the register information, and send a shutdown signal to the power supply component when the power status signal indicates an abnormality.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0017] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0018] Figure 1A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0019] Figure 2 A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0020] Figure 3 A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0021] Figure 4 A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0022] Figure 5 A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0023] Figure 6 A schematic diagram of the power control system structure according to an embodiment of the present disclosure is shown.

[0024] Figure 7 A flowchart illustrating the power control process performed by a control component according to an embodiment of the present disclosure is shown schematically.

[0025] Figure 8 A schematic block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0026] The embodiments of this disclosure will now be described with reference to the accompanying drawings. Various details of the embodiments of this disclosure are included to aid understanding and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0028] All terms used herein, including technical and scientific terms, have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0029] When using expressions such as "at least one of A, B, and C," the meaning should generally be interpreted according to the understanding of someone skilled in the art. For example, "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C. Similarly, when using expressions such as "at least one of A, B, or C," the meaning should generally be interpreted according to the understanding of someone skilled in the art. For example, "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C.

[0030] It should also be noted that the directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the directions in the accompanying drawings and are not intended to limit the scope of protection of this disclosure. Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure.

[0031] In server power supply technologies, there are typically power supply components for regulating input voltage or isolating multiple power paths included in the server, as well as control components for enabling the power supply components and receiving power state information from the power supply components.

[0032] In related technologies, in response to the control component detecting an abnormal power supply state, the control component will disable the enable of all power supply components and cut off the input voltage of all power supply components. The data in the registers of the power supply components will be cleared after the input voltage is cut off. As a result, after the power supply component malfunctions, the control component cannot obtain the information contained in the registers of the power supply components, which in turn makes it impossible to locate the abnormal power supply components in the server power supply. This makes it difficult to locate the fault in the server power supply and makes it impossible to obtain the internal fault state information of the power chip before power-off.

[0033] Based on this, the present disclosure provides a power control system and server, which, when a power component malfunctions, is configured to acquire the register information of the power component, and then send a shutdown signal to the power component after acquiring the register information, so as to realize the reading of the register information of the power component when the power component malfunctions and the location and detection of the malfunction based on the register information.

[0034] Figure 1 A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0035] like Figure 1 As shown, the power control system of this embodiment may include a control component 110 and a power component 120.

[0036] The control component 110 can be electrically connected to each power supply unit 121 via an enable signal line EN and a power status signal line P. The enable signal line EN is used by the control component 110 to send an enable signal to the power supply unit 121, and the power status signal line P is used by the power supply unit 121 to return a power status signal to the control component 110.

[0037] Control component 110 is configured to send an enable signal to power component 120 upon detecting that the server has been powered on. The enable signal can be used to control the power component 120 to start or stop operation. Server power-on indicates that the server, which has a deployed power control system, is connected to AC power.

[0038] The control component 110 may be, for example, a field-programmable gate array (FPGA) or a complex programmable logic device (CPLD). The control component 110 can control the power supply component 120 to turn on or off by sending an enable signal to the power supply component 120.

[0039] Power supply component 120 can be used to regulate input voltage or to isolate multiple circuits or components included in the server. Power supply component 120 is connected to control component 110 and can be configured to generate a power status signal in response to an enable signal and send the power status signal to the control component. The power status signal indicates whether power supply component 120 is in a normal or abnormal state. Power supply component 120 can return a high-level signal to indicate a normal power status signal and a low-level signal to indicate an abnormal power status signal. The high-level signal can be, for example, 3.3V, 3.5V, or 3.6V, and the low-level signal can be, for example, 0.3V, 0.4V, or 0.6V.

[0040] The power supply component 120 may include registers for recording the power supply status of the power supply component 120 in the current or recent time period and information that caused the abnormal state when it was in an abnormal state.

[0041] The power supply component 120 may be, for example, a voltage regulator module or an electronic fuse (eFues).

[0042] The control component 110 is also configured to acquire register information of the power component 120 when the power status signal indicates an abnormality, determine the type of power abnormality based on the register information, and send a shutdown signal to the power component 120.

[0043] The register information of power supply component 120 may include information such as the type of power supply abnormality generated by power supply component 120 when an abnormality occurs. For example, when an abnormality occurs, power supply component 120 may send a power status signal indicating the abnormality to control component 110, and simultaneously save the determined information including the type of power supply abnormality into the register of power supply component 120. After receiving the power status signal indicating the abnormality, control component 110 sends a shutdown signal to power supply component 120 that sent the power status signal, so that the abnormal power supply component 120 is turned off.

[0044] According to embodiments of this disclosure, the control component 110, upon receiving a power status signal indicating an abnormality, acquires register information of the power component and determines the power abnormality type in the register information. This enables the control component 110 to acquire the register information of the power component 120 that sent the abnormality indication when the power component 120 malfunctions, thereby obtaining the power abnormality type of the power component. In addition to acquiring the power status signal indicating the presence of a power component malfunction, the control component 110 can also acquire information on the power abnormality type, providing rich data support for analyzing and locating power component malfunctions and improving the effectiveness of analyzing and locating power component malfunctions.

[0045] Figure 2 A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0046] like Figure 2 As shown, the power control system of this embodiment may include a control component 110 and a power component 120. The power component 120 includes at least one power supply unit 121.

[0047] In embodiments of this disclosure, each power supply component 120 may include at least one power supply unit 121, and an abnormal power status signal may be generated by any of the power supply components 121 included in the power supply component 120 and returned to the control component 110.

[0048] The control component 110 can be electrically connected to each power supply unit 121 via an enable signal line EN and a power status signal line P. The enable signal line EN is used by the control component 110 to send an enable signal to the power supply unit 121, and the power status signal line P is used by the power supply unit 121 to return a power status signal to the control component 110.

[0049] Furthermore, the control component 110 can also be electrically connected to each power supply unit 121 via an integrated circuit bus C. The integrated circuit bus C can be used by the power supply unit 121 to return register information to the control component 110.

[0050] According to an embodiment of the present disclosure, the control component 110 is configured to, upon detecting that the server is powered on, sequentially send an enable signal to at least one power supply unit 121 according to a preset timing logic, and in response to a power status signal indicating an abnormality returned from any power supply unit 121, obtain the register information of the abnormal power supply unit via the integrated circuit bus C, determine the power abnormality type based on the register information, and send a shutdown signal to the abnormal power supply unit.

[0051] The preset timing logic characterization control component 110 sends enable signals to at least one power supply unit 121 in the power supply component 120 in the order and time interval of the signal, thereby realizing the power-on timing control of at least one power supply unit 121.

[0052] For example, if the power supply assembly 120 includes a power supply unit 121, the preset timing logic representation control assembly 110 can be configured to send an enable signal to the power supply unit 121 through the enable signal line EN when it determines at any time that an instruction to send an enable signal to the power supply unit 121 is required.

[0053] For example, if the power supply component 120 includes two power supply units 121, each including a power supply unit for supplying power to the basic logic circuits of the motherboard and a power supply unit for supplying power to the central processing unit, and the timing logic indicates that an enable signal is first sent to the power supply unit for supplying power to the basic logic circuits of the motherboard, and an enable signal is sent to the power supply unit for supplying power to the central processing unit after a 10-millisecond delay, then the control component 110 can, according to the preset timing logic, when it is necessary to send an enable signal to the two power supply units 121, first send an enable signal to the power supply unit for supplying power to the basic logic circuits of the motherboard through the enable signal line EN, and after a 10-millisecond delay, send an enable signal to the power supply unit for supplying power to the central processing unit through the enable signal line EN.

[0054] For example, if the power supply assembly 120 includes three power supply units 121, each power supply unit 121 includes a power supply unit for supplying power to the basic logic circuits of the motherboard, a power supply unit for supplying power to the central processing unit, and a power supply module for supplying power to the input / output circuits of the memory module. The control assembly 110 can, according to a preset timing logic, first send an enable signal to the power supply unit supplying power to the basic logic circuits of the motherboard. After detecting a normal power status signal returned by that power supply unit, it sends an enable signal to the power supply module supplying power to the input / output circuits of the memory module. After detecting a normal power status signal returned by that power supply unit, it sends an enable signal to the power supply unit supplying power to the central processing unit.

[0055] It is understood that the preset timing logic may include, in addition to the order and time interval of the control component 110 sending enable signals to at least one power supply unit 121 in the power supply component 120, other information for power-on control of at least one power supply unit 121. For example, it may also include the delay of the power supply unit 121 outputting voltage after receiving the enable signal, the time required for the power supply unit 121 to rise the voltage from 0 to the target voltage, and the delay of the power supply unit 121 returning a power state signal indicating normal operation to the control component 110 after outputting the target voltage.

[0056] The control component 110 can use the integrated circuit bus C to poll the registers corresponding to at least one power supply unit 121 to obtain the register information of at least one power supply unit 121. The register information may include the operating parameters of the power supply unit 121 when an abnormality occurs and the type of power supply abnormality.

[0057] It is understandable that the register information of at least one power supply unit 121 can be stored in the same register, and the register information of different power supply units 121 can be distinguished by different storage areas or different power supply unit identifiers. At least one power supply unit 121 may also have its own corresponding register, and the register information of each power supply unit 121 is stored in its respective corresponding register.

[0058] According to embodiments of this disclosure, the control component 110 monitors at least one power supply unit 121. When any power supply unit 121 returns a power status signal indicating an abnormality, the control component 110 obtains the register information of the abnormal power supply unit via the integrated circuit bus C. After obtaining the register information, the control component 110 sends a shutdown signal to the abnormal power supply unit to prevent data loss due to power failure. This allows the control component to read the register information of the power supply unit 121 when an abnormality occurs, determine the type of power supply abnormality, and analyze and locate the abnormality. Furthermore, when a power supply unit 121 returns a power status signal indicating an abnormality, the control component 110 can read the register information of the abnormal power supply unit indicated by the abnormality via the integrated circuit bus C, eliminating the need to read the register information of all power supply units 121. This reduces the amount of data that needs to be read and analyzed when the power supply component 121 malfunctions. In addition, after obtaining the register information of the abnormal power supply unit, the control component 110 sends a shutdown signal to the abnormal power supply unit to enable power-off only for the abnormal power supply unit, so that the other power supply units in at least one power supply unit 121 other than the abnormal power supply unit are normally powered on, reducing the impact on the server.

[0059] Figure 3 A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0060] like Figure 3 As shown, the power control system of this embodiment may include a control component 110 and a power component 120. The power component 120 includes at least one power supply unit 121, and each power supply unit 121 includes at least one of a fuse E and a voltage regulator VR.

[0061] In some embodiments, each power supply unit 121 may include at least one of a fuse E and a voltage regulator VR. The fuse E and the voltage regulator VR are respectively connected to a control component, and the fuse is electrically connected to the voltage regulator.

[0062] The fuse E is configured to output a power supply voltage to the voltage regulator VR in response to a first enable signal from the control component 110, generate a first power status signal based on a first operating parameter, and send the first power status signal to the control component 110.

[0063] The fuse E is used to isolate and protect the power path, quickly melting in the event of a short circuit or overcurrent to protect components in the server.

[0064] The first operating parameter is the circuit parameter used by the fuse device E to determine the circuit in which the fuse device is located. For example, the first operating parameter may include at least one of the output voltage, output current and internal temperature of the fuse device E.

[0065] The first power status signal is a signal determined by the fuse E based on the first operating parameters after receiving the first enable signal, indicating the operating status of the circuit in which the fuse E is located. For example, if the fuse E detects that its temperature is within a preset temperature range, it returns a first power status signal indicating normal operation to the control component 110; if the fuse E detects that its temperature exceeds the preset temperature range, it returns a first power status signal indicating abnormality to the control component 110.

[0066] The voltage regulator VR is configured to convert the power supply voltage to a target voltage and output it to the load in response to a second enable signal from the control component 110, generate a second power status signal according to second operating parameters, and send the second power status signal to the control component 110; the second operating parameters include the output voltage of the voltage regulator VR.

[0067] In one example, the power supply assembly 120 may include eight power supply units 121, of which two power supply units 121 are fuses E and six power supply units 121 are voltage regulators VR.

[0068] The second power status signal is a signal determined by the voltage regulator VR based on the second operating parameters after receiving the second enable signal, indicating the operating status of the circuit containing the fuse device E. For example, if the second operating parameter is an output voltage of 1.05V for the voltage regulator VR, and the voltage regulator VR detects an output voltage of 1.05V, it returns a second power status signal indicating normal operation to the control component 110; if the voltage regulator VR detects an output voltage of 12V, it returns a second power status signal indicating abnormal operation to the control component 110.

[0069] The fuse E and the voltage regulator VR can be connected in series, with the fuse E located at the power input terminal and the voltage regulator VR following the fuse E. The control component 110 sends enable signals in the following sequence: first enable signal followed by second enable signal. For example, in response to receiving the first enable signal, the fuse E controls its internal switch to turn on and outputs the input 12V power supply voltage to the voltage regulator VR connected in series with the fuse E, serving as the input voltage for the voltage regulator VR. In response to receiving the second enable signal, the voltage regulator VR converts the 12V input voltage to a target voltage of 1.05V, serving as the input voltage for the load.

[0070] According to embodiments of this disclosure, by configuring each power supply unit 121 to include at least one of a fuse E and a voltage regulator VR, the power supply unit 121 can perform isolation or voltage regulation operations on the input voltage, thereby isolating and protecting different circuit components in the power supply system and converting the input voltage into the target voltage of the load in the power supply system. Furthermore, the control component 110 sends a first enable signal and a second enable signal to the fuse E and the voltage regulator VR respectively, thereby controlling the components included in the power supply unit 121 respectively. Moreover, by using the first power status signal and the second power status signal returned by the fuse E and the voltage regulator VR respectively, the control component 110 can accurately determine the operating status of the fuse E and the voltage regulator VR in the power supply unit 121. Upon receiving an abnormal power status signal, it can determine whether the abnormality is due to the fuse E or the voltage regulator VR by judging whether the power status signal is the first power status signal or the second power status signal, thus improving the accuracy of abnormality location.

[0071] According to embodiments of this disclosure, the power supply component 120 includes at least one register REG, the value of a set flag bit in register REG being used to indicate the state of the power supply component 120, and the power status signals including a power good signal and an alarm signal. The control component 110 is further configured to: in response to a power good signal indicating an abnormality, locate the abnormal power supply unit in the power supply component 120 by querying a hardware mapping table.

[0072] The power supply assembly 120 includes at least one of the fuse E and the voltage regulator VR, which can each correspond to a register REG. The register REG is used to temporarily store the state of the corresponding fuse E or voltage regulator VR after the power supply system is powered on.

[0073] Different bits in register REG can be used to store different power component information. At least one bit in the register can be set to represent a setting flag. For example, if register REG can be used to store 16 bits of data, the 16th bit of register REG can be set as a setting flag. If the setting flag is 1, it indicates that the power component 120 corresponding to the register is in good condition, and a normal power good signal is returned to the control component 110. If the setting flag is 0, it indicates that the power component corresponding to the register is abnormal, and an abnormal power good signal is returned to the control component 110.

[0074] Multiple bits of data in the register information can be used to represent different power supply fault types. For example, if the REG register can store 16 bits of data, bits 15 and 16 can be set as flag bits. Bit 15 indicates whether there is an overvoltage condition in the power supply component, and bit 16 indicates whether there is an overcurrent condition. If the value of bit 15 or bit 16 is detected as 1, a power supply good signal indicating an fault is returned; if the values ​​of bit 15 and bit 16 are both detected as 0, a power supply good signal indicating normal operation is returned.

[0075] The pins of the fuse E and voltage regulator VR in each power supply assembly 120 can be electrically connected to the control assembly 110 via the power good signal line P and the alarm signal line A. The signals received by the control assembly 110 via the power good signal line or the alarm signal line carry pin numbers.

[0076] Understandable Figure 3 The number of power good signal lines P can be multiple. Each power good signal line P is used to connect the control component 110 to the pins of different fuses E or voltage regulators VR, so that the fuses E or voltage regulators VR can return a power good signal to the control component 110. Multiple power components 120 can share a single alarm signal line A, which is used by the power component 120 to return an alarm signal to the control component 110.

[0077] The hardware mapping table establishes a predetermined correspondence between pin numbers indicating a power-good signal and power supply units 121 in the power supply assembly 120. Upon receiving a power-good signal carrying a pin number, the control assembly 110 can use the hardware mapping table to determine the corresponding power supply unit 121. For example, the preset hardware mapping table includes pins 1, 2, 3, and 4, where pin 1 corresponds to fuse 1, pin 2 corresponds to voltage regulator 1, pin 3 corresponds to fuse 2, and pin 4 corresponds to voltage regulator 2. If the control assembly 110 receives a low-level power-good signal indicating an abnormality, and the pin number carried by this power-good signal is pin 2, then the control assembly 110 can determine that voltage regulator 1 is the abnormal power supply unit.

[0078] In response to an alarm signal indicating an anomaly, the abnormal power supply unit in power supply component 120 is located by sending an alarm response address command. The alarm response address command is used to cause the abnormal power supply unit to return the corresponding device address to the control component. The register information of the abnormal power supply unit is obtained, and the power anomaly type is determined by parsing the register information. The power anomaly type and register information are saved, and a shutdown signal is sent to the abnormal power supply unit.

[0079] Multiple power supply units 121 can share a single alarm signal line A to send signals to the control component 110. When a power supply unit 121 detects an anomaly, it actively sends an alarm signal to the control component 110 via alarm signal line A. Upon receiving the alarm signal, the control component 110 sends an Alert Response Address (ARA) command to all power supply units 121. The ARA command instructs the abnormal power supply unit that sent the alarm signal to return its device address to the control component, enabling the control component 110 to identify the abnormal power supply unit based on the returned device address. After receiving the device address and identifying the abnormal power supply unit, the control component 110 reads the register information of the REG register corresponding to the abnormal power supply unit and determines the power supply anomaly type based on at least one set flag bit in the register information.

[0080] The control component 110 obtains the power failure type and register information, and can save the power failure type and register information to a preset storage area.

[0081] According to an embodiment of this application, the abnormal power supply unit that sends the abnormal power supply good signal is located by querying a hardware mapping table based on the pin number of the abnormal power supply good signal. Furthermore, the device address of the abnormal power supply unit that receives the alarm response address signal is obtained by sending an alarm response address signal. This enables the location of the abnormal power supply unit that sends both the abnormal power supply good signal and the alarm signal.

[0082] The control component 110 can also restore power to power supply units that experience occasional and recoverable abnormal power supply.

[0083] According to embodiments of this application, power supply abnormality types may include at least one of the following: transient overcurrent, transient undervoltage, overtemperature warning, input undervoltage, overvoltage latch, continuous overcurrent latch, short circuit latch, and power supply failure.

[0084] Transient overcurrent characterizes the condition where the load current of power supply unit 121 briefly exceeds the overcurrent protection threshold and then recovers. For example, the surge current that occurs when the server powers on can cause a power supply anomaly that triggers transient overcurrent in power supply unit 121.

[0085] A transient undervoltage condition where the output voltage briefly drops below the undervoltage protection threshold and then recovers on its own. For example, if the CPU load suddenly increases, the feedback loop of the CPU's voltage regulator VR takes some time to respond, causing the output voltage to drop momentarily, but then recover to the set value.

[0086] The over-temperature warning indicates a power supply abnormality where the temperature of the power supply unit 121 exceeds a preset temperature threshold but does not reach the over-temperature protection trigger point. For example, the central processing unit may experience a situation where the temperature of the processor's power supply unit 121 rises to the warning temperature range due to continuous high load operation, but does not reach the temperature range that triggers the over-temperature protection shutdown.

[0087] Input undervoltage is a fault in which the input voltage of power supply unit 121 is lower than the lower limit of its normal operating range. For example, a situation where the input voltage of power supply unit 121 drops significantly due to intermittent fluctuations in the input voltage.

[0088] Overvoltage latching occurs when a hardware fault triggers the power supply unit 121, causing the output voltage to exceed the overvoltage protection threshold and triggering hardware latching. During hardware latching, the power supply unit 121 enters a fault-locked state, which can only be exited after the server sends a recovery command or a power-down restart is performed.

[0089] Short-circuit latching is triggered by a short circuit between the output terminal of power supply unit 121 and ground. Short-circuit latching is mainly triggered by physical damage to the load equipment of the power supply unit.

[0090] The power supply failure is a hardware failure caused by the power supply unit 121 being blown or broken down, and the power supply unit 121 needs to be replaced.

[0091] For power supply anomalies that are briefly triggered and can recover on their own, such as transient overcurrent, transient undervoltage, overtemperature warning, and input undervoltage, the control component can perform a power restoration operation.

[0092] Control component 110 is also configured to determine whether to restore power supply based on the type of power supply anomaly. Power supply restoration is determined if the power supply anomaly type is at least one of transient overcurrent, transient undervoltage, overtemperature warning, and input undervoltage.

[0093] Understandably, different power supply anomaly types can correspond to different power supply recovery strategies. For example, for power supply anomalies such as transient overcurrent and transient undervoltage, the corresponding power supply recovery strategy can be set to restore power supply after waiting for 100 milliseconds; for power supply anomalies such as overtemperature warning, the corresponding power supply recovery strategy can be set to poll the temperature of power supply unit 121 and restore power supply when the temperature of power supply unit 121 is lower than a preset temperature threshold; for power supply anomalies such as input undervoltage, the corresponding power supply recovery strategy can be set to restore power supply after the input voltage stabilizes.

[0094] When the control component 110 detects that the power supply abnormality of the power supply unit 121 is any one of transient overcurrent, transient undervoltage, overtemperature warning or input undervoltage, it can perform a power supply restoration operation based on the power supply restoration strategy corresponding to the power supply abnormality type.

[0095] If the control component 110 detects multiple power supply anomalies in the power supply unit 121, including transient overcurrent, transient undervoltage, overtemperature warning, or input undervoltage, the control component 110 can be configured to perform a power supply recovery operation if the power supply recovery requirements of the power supply recovery strategy corresponding to each of the multiple power supply anomaly types are met. For example, if the control component 110 detects that the power supply anomaly in the power supply unit 121 includes transient overcurrent and overtemperature warning, the control component 110 can restore power supply after waiting for 100 milliseconds and determining that the temperature of the power supply unit 121 is below a preset temperature threshold. As another example, if the control component 110 detects that the power supply anomaly in the power supply unit 121 includes transient overcurrent, overtemperature warning, and input undervoltage, the control component 110 can restore power supply after waiting for 100 milliseconds, determining that the temperature of the power supply unit 121 is below a preset temperature threshold, and determining that the input voltage is stable.

[0096] The control component 110 can restore power after a preset delay once it has determined that power can be restored.

[0097] For long-term power anomalies caused by hardware, such as overvoltage latch, continuous overcurrent latch, short circuit latch, and power supply failure, the control component 110 restores power supply only after receiving an anomaly recovery command.

[0098] According to embodiments of this disclosure, by determining whether the abnormality of the abnormal power supply unit can be self-recovered in a short time based on the type of power abnormality, and restoring power to the abnormal power supply unit if it is determined that the abnormality can be self-recovered in a short time, power is restored to the abnormal power supply unit. This achieves power restoration for intermittent and recoverable abnormal power supply units, avoiding the need for maintenance of power supply units due to intermittent failures, reducing the number of server maintenance operations, and ensuring the stability of server operation. Furthermore, in the event of a long-term failure due to hardware failure, no power restoration operation is performed, avoiding the situation where repeatedly powering the abnormal power supply unit with hardware failure would affect other normal power supply units 121, thus protecting other power supply units and components in the server.

[0099] After the control component 110 restores the power supply to the intermittent and recoverable abnormal power supply unit, it can send an enable signal to the power supply component 120 to determine whether the power supply component 120 is working properly.

[0100] According to embodiments of this disclosure, the control component 110 is further configured to send an enable signal to the power supply component 120 again upon determining that power supply has been restored. The control component 110 sends an enable signal to the power supply component 120 to obtain power status signals returned by each power supply unit 121 in the power supply component 120 after determining that the abnormal power supply unit is temporarily abnormal and can automatically recover, or after a hardware-faulted abnormal power supply unit has been replaced or repaired.

[0101] If all power status signals received from the power supply component 120 indicate that the power supply is normal, it is determined that there is no abnormal power supply unit in the power supply component 120, and power supply is restored to complete the power-on of the server.

[0102] In response to receiving any power status signal indicating an abnormality from the power supply component 120, and the number of times an enable signal is sent to the power supply component 120 again exceeds a predetermined threshold, the power supply component 120 is kept off.

[0103] If any power status signal received from the power supply component 120 indicates an abnormality, it is determined whether the number of times an enable signal has been sent to the power supply component 120 is greater than a predetermined threshold. If the number of times an enable signal has been sent to the power supply component 120 is less than or equal to the predetermined threshold, then the enable signal continues to be sent to the power supply component 120.

[0104] If the number of times the enable signal is sent to the power supply component 120 exceeds a predetermined threshold, it is determined that there is an abnormal power supply unit in the power supply component 120 that cannot be automatically restored in a short time, and the power supply component 120 is kept off.

[0105] For example, the predetermined threshold is 5 times. When control component 110 receives a power-good signal indicating an abnormality and determines that the power abnormality type of the abnormal power supply unit returning the signal is a transient overcurrent, it sends a shutdown signal to the power assembly 120 including the abnormal power supply unit. After waiting for a preset time, control component 110 sends an enable signal to the power assembly 120 including the abnormal power supply unit again. If a power-good signal indicating an abnormality is received, the operation of waiting for the preset time and sending an enable signal to the power assembly 120 including the abnormal power supply unit is repeated. If control component 110 sends no more than 5 enable signals to the power assembly 120 including the abnormal power supply unit, and still receives a power-good signal indicating an abnormality, it continues to send enable signals. If control component 110 receives a power-good signal indicating an abnormality and has already sent 6 enable signals to the power assembly 120 including the abnormal power supply unit, the power assembly 120 remains off.

[0106] According to embodiments of this disclosure, for power supply units exhibiting transient overcurrent, transient undervoltage, overtemperature warning, and input undervoltage that are briefly triggered and self-recovering, power supply is restored after the power supply unit recovers to normal operation by repeatedly sending an enable signal a preset threshold number of times. Furthermore, if the power supply unit fails to recover after repeatedly sending the enable signal a preset threshold number of times, the sending of the enable signal is stopped, and the power component 120 remains off, avoiding the waste of system resources caused by continuously sending enable signals and preventing repeated sending of enable signals from affecting other power supply units.

[0107] Figure 4 A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0108] like Figure 4 As shown, the power control system of this embodiment may include a control component 110, a power component 120, a management component 130, and an access control component 140. The power component 120 includes at least one power supply unit 121, which includes at least one of a fuse E and a voltage regulator VR. The control component 110 can be electrically connected to each power supply unit 121 via an enable signal line EN, a power status signal line P, an alarm signal line A, and an integrated circuit bus C. The enable signal line EN is used by the control component 110 to send an enable signal to the power supply unit 121, and the power status signal line P is used by the power supply unit 121 to return a power status signal to the control component 110. The alarm signal line A can be used by the power supply unit 121 to return an alarm signal to the control component, and the integrated circuit bus C can be used by the power supply unit 121 to return register information to the control component 110.

[0109] According to embodiments of this disclosure, management component 130 is configured to read register information from the target storage area of ​​control component in a polling or interrupt manner, and generate power management log based on the register information.

[0110] Management component 130 is used to obtain the status of at least one power supply unit 121 in power supply component 120 and generate a power management log. The power management log can be provided to server maintenance personnel, who can optimize and maintain the server based on the power management log. Management component 130 may have an independent processor, memory, network interface, and standby power supply. Even when control component 110 and power supply component 120 are powered down in the server, management component 130 can still read the target storage area of ​​control component 110 and generate a power management log. Management component 130 may be, for example, a Baseboard Management Controller (BMC).

[0111] The management component 130 can use a polling method to periodically access the target storage area and obtain the operating status of the power component 120 obtained by the control component 110 from the register information during the current polling cycle.

[0112] The control component 110 can send an interrupt signal to the management component 130 after each time register information is written to the target storage area, so that the management component 130 can read the target storage area in a timely manner. For example, after the control component 110 receives a power abnormality type of long-term failure caused by hardware failure, the management component 130 writes the register information of the abnormal power supply unit to the target storage area and sends an interrupt signal. In response to receiving the interrupt signal, the management component reads the register information in the target storage area and generates a power management log.

[0113] For example, when control component 110 receives a power status signal indicating normal operation or a power abnormality type of at least one of transient overcurrent, transient undervoltage, overtemperature warning, and input undervoltage, management component 130 polls the target storage area at 1-second intervals to obtain updated register information in the target storage area and generates a power management log. In response to control component 110 receiving an abnormality indication and the power abnormality type including at least one of overvoltage latch, continuous overcurrent latch, short circuit latch, and power supply failure, control component 110 obtains the register information of the abnormal power supply unit, writes the register information to the target storage area, and sends an interrupt signal to management component 130. In response to receiving the interrupt signal, management component 130 immediately accesses the target storage area and obtains the register information of the abnormal power supply unit, generates a power management log based on the register information of the abnormal power supply unit, and stores it on the server's hard drive.

[0114] According to embodiments of this disclosure, the management component 130 can read register information in the target storage unit and generate a power management log when the control component 110 and power component 120 in the server are powered down. This improves the stability of generating a power management log that includes register information of the power supply unit 121 and mitigates the loss of register information due to power-down of the control component 110 and power component 120. Furthermore, by employing both polling and interrupt methods to read register information and generate the power management log, the power management log is periodically updated, and when there is a need to generate the power management log promptly, the register information in the target storage area is read immediately to generate the power management log, improving the continuity and timeliness of power management log generation.

[0115] In some embodiments, the management component 130 may be electrically connected to the control component 110 and the power supply component 120 via the integrated circuit bus C.

[0116] Figure 5 A schematic block diagram of a power control system according to an embodiment of the present disclosure is shown.

[0117] like Figure 5 As shown, the power control system of this embodiment may include a control component 110, a power component 120, a management component 130, and an access control component 140. The power component 120 includes at least one power supply unit 121, which includes at least one of a fuse E and a voltage regulator VR. The control component 110 can be electrically connected to each power supply unit 121 via an enable signal line EN, a power status signal line P, an alarm signal line A, and an integrated circuit bus C. The enable signal line EN is used by the control component 110 to send an enable signal to the power supply unit 121, and the power status signal line P is used by the power supply unit 121 to return a power status signal to the control component 110. The alarm signal line A can be used by the power supply unit 121 to return an alarm signal to the control component, and the integrated circuit bus C can be used by the power supply unit 121 to return register information to the control component 110.

[0118] It should be understood that only one component is allowed to perform an access or write operation on the integrated circuit bus C. To avoid read / write errors and bus conflicts caused by the management component 130 reading the target memory area while the control component 110 is reading the register information of the power supply component 120 and writing the register to the target memory area, the power control system may also include an access control component 140. The access control component 140 is used to prevent the control component 110 and the management component 130 from being connected to the integrated circuit bus C simultaneously.

[0119] According to an embodiment of this application, the access control component 140 is connected to the management component 130, the control component 110, and the power component 120 via the integrated circuit bus C. It is configured to disconnect the communication between the management component 130 and the power component and the control component 110 during the process of the control component 110 reading the register information of the power component 120 via the integrated circuit bus C, and to restore the communication between the management component 130 and the power component 120 and the control component 110 after the control component 110 has finished reading the register information of the power component 120.

[0120] Access control component 140 can be a buffer used to control the connection status of management component 130 and control component 110 with integrated circuit bus C. If it is detected that control component 110 reads the register information of power component 120 via integrated circuit bus C and writes the register information into the target storage area, the connection between management component 130 and integrated circuit bus C is disconnected. If control component 110 does not read the register information of power component 120, the connection between management component 130 and integrated circuit bus C is restored.

[0121] For example, during the process of reading the register information of the power supply component 120 via the integrated circuit bus C, the control component 110 can send a first signal to the access control component 140 to cause the management component 130 to disconnect from the integrated circuit bus C, and after reading the register information of the power supply component 120, send a second signal to the access control component 140 to restore the connection between the management component 130 and the integrated circuit bus C.

[0122] According to embodiments of this disclosure, by setting an access control component 140, the connection between the management component 130 and the integrated circuit bus C is disconnected when the control component 110 uses the integrated circuit bus C, and the connection between the management component 130 and the integrated circuit bus C is restored when the control component 110 does not use the integrated circuit bus C. This allows the control component 110 and the management component 130 to share the integrated circuit bus C and avoids bus conflicts and read / write conflicts, reducing the probability of erroneous recording, improving the reliability of register reading, and increasing the accuracy of abnormal recording.

[0123] In some embodiments, the buffer output enable terminal of the control component 110 is connected to the access control component 140.

[0124] According to an embodiment of this disclosure, the control component 110 is further configured to, during the upgrade of the management component 130, output an enable signal with a first level via the buffer output enable terminal to disconnect the communication between the management component 130 and the power component 120 and the control component 110, and, upon completion of the upgrade of the management component 130, output an enable signal with a second level via the buffer output enable terminal to restore the communication between the management component 130 and the power component 120 and the control component 110.

[0125] An enable signal with a first level is a signal from control component 110 instructing access control component 140 to disconnect management component 130 from power supply component 120 and control component 110. An enable signal with a first level is a signal from control component 110 instructing access control component 140 to resume communication between management component 130 and power supply component 120 and control component 110.

[0126] In one embodiment, the first level is a high level and the second level is a low level.

[0127] In another embodiment, the first level is low and the second level is high.

[0128] The buffer output enable terminal of the control component 110 can be an input / output pin of the control component 110, used to send an enable signal to the access control component 140 to control the on / off state of the access control component 140.

[0129] The upgrade of management component 130 means that management component 130 performs a firmware upgrade based on the firmware upgrade operation. If, during the upgrade process of management component 130, there is a situation where it sends erroneous instructions to other components connected to integrated circuit bus C or interferes with the communication of other components.

[0130] Upon receiving an enable signal with a first level, access control component 140 controls the disconnection of management component 130 from power supply component 120 and control component 110. For example, access control component 140 controls management component 130 to disconnect from integrated circuit bus C.

[0131] Control component 110 can determine whether the firmware upgrade program of management component 130 has ended based on whether the server has completed the firmware upgrade program. After determining that the firmware upgrade program of management component 130 has ended, control component 110 sends an enable signal with a second level to access control component 140. Upon receiving the enable signal with the second level, access control component 140 controls the restoration of communication between management component 130, power supply component 120, and control component 110. For example, access control component 140 controls management component 130 to restore its connection to the integrated circuit bus C.

[0132] According to embodiments of this disclosure, by configuring the control component 110 to send an enable signal with a first level and an enable signal with a second level to the access control component 140 via the buffer output enable terminal, the communication between the management component 130 and the power component 120 and the control component 110 can be controlled to disconnect and resume, thereby achieving flexible control of the buffer via a single buffer output enable terminal. Furthermore, by controlling the disconnection of communication between the management component 130 and the power component 120 and the control component 110 during the unstable state of the management component 130 upgrade, the control component 110 avoids interference to the power component 120 and the control component 110 during the upgrade process of the management component 130. Moreover, after the management component 130 upgrade is completed, the control component 110 outputs an enable signal with a second level to the access control component 140 via the buffer output enable terminal, resuming communication between the management component 130 and the power component 120 and the control component 110, thus achieving automatic restoration of the connection between the management component 130 and the power component 120 and the control component 110 after the upgrade.

[0133] Figure 6 A schematic diagram of the power control system structure according to an embodiment of the present disclosure is shown.

[0134] like Figure 6As shown, the power control system may include a control component 110, a power supply component 120, a management component 130, and an access control component 140. The power supply component 120 includes at least one power supply unit 121, which includes at least one of a fuse E and a voltage regulator VR. The power supply component 120 includes eight power supply units 121, of which two power supply units 121 are fuses E1 and E2, and six power supply units 121 are voltage regulators VR1, VR2, VR3, VR4, VR5, and VR6.

[0135] The control component 110 can be electrically connected to each power supply unit 121 via an enable signal line EN, a power status signal line P, an alarm signal line A, and an integrated circuit bus C. The enable signal line EN is used by the control component 110 to send an enable signal to the power supply unit 121; the power status signal line P is used by the power supply unit 121 to return a power status signal to the control component 110; the alarm signal line A is used by the power supply unit 121 to return an alarm signal to the control component; and the integrated circuit bus C is used by the power supply unit 121 to return register information to the control component 110.

[0136] Understandable Figure 6 In the integrated circuit bus C, line 1 and line 2, represented by dashed lines, can either exist. If line 2 does not exist, then access control component 140 also does not exist.

[0137] The control component 110 can send enable signals to each of the eight power supply units 121 according to a preset timing logic. The preset timing logic indicates that the order in which the enable signals are sent, from first to last, is E1, VR1, E2, VR2, VR3, VR4, VR5, and VR6. After receiving the enable signal, each power supply unit 121 returns a power good signal to the control component 110 through the power status signal line P.

[0138] When line 1 exists in the integrated circuit bus C, after the control component 110 receives a power good signal or alarm signal indicating an abnormality, the control component 110 can obtain the power supply unit 121 register information that returned the power good signal or alarm signal through the integrated circuit bus C, and write the register information into the target storage area of ​​the control component 110.

[0139] The management component 130 can poll the target storage area at 1-second intervals to obtain updated register information in the target storage area and generate a power management log.

[0140] When line 2 exists in the integrated circuit bus C, during the process of the control component 110 reading the register information of the power supply component 120 via the integrated circuit bus C, a first signal can be sent to the access control component 140 to cause the management component 130 to disconnect from the integrated circuit bus C. After reading the register information of the power supply component 120, a second signal is sent to the access control component 140 to restore the connection between the management component 130 and the integrated circuit bus C. When the management component 130 is disconnected from the integrated circuit bus C, it cannot obtain information about the target memory area. When the management component 130 is connected to the integrated circuit bus C, it can obtain information about the target memory area at 1-second intervals.

[0141] Figure 7 A flowchart illustrating the power control process performed by a control component according to an embodiment of the present disclosure is shown.

[0142] exist Figure 7 In this configuration, control component 110 is a Field-Programmable Gate Array (FPGA), and power supply unit 121 includes a fuse E and a voltage regulator VR. Voltage regulator VR1 is present to power the central processing unit; its integrated circuit bus address is 0x48, and its overcurrent protection threshold is set to 40A. The power-good signal consists of a Voltage Regulator Module Power-Good Signal (VR PG) and an Alert signal.

[0143] When the S710 is in operation and the server is powered on, the FPGA detects the power-on event and begins working according to the preset timing logic. It sends a first enable signal to the fuses E in each power supply unit 121, so that the fuses E output the 12V input voltage to the subsequent voltage regulator VR. Then, the FPGA sends a second enable signal to at least one voltage regulator VR according to the timing logic, so that the voltage regulator VR steps down the input voltage and outputs the resulting output voltage to the CPU, memory, and other load components.

[0144] When operating the S720, the FPGA monitors for the presence of a PG signal or Alert signal (indicating an anomaly) after sending the first and second enable signals to determine if there is an abnormality in the power supply components. If no abnormality is found, the power-on operation will continue the next time the server is powered on.

[0145] If a transient overcurrent exceeding 40A is detected in voltage regulator VR1, voltage regulator VR1 records the transient overcurrent power supply anomaly type in the register information and returns an Alert signal. Then, operation S730 is executed.

[0146] In operation S730, if the FPGA detects that the voltage regulator VR1 has an abnormal PG signal or Alert signal, the FPGA sends an alarm response address command to all voltage regulators VR. After the voltage regulator VR1 returns the integrated circuit bus address 0x48, operation S740 is executed.

[0147] When operating the S740, poll all registers or the abnormal power register. The FPGA can read the register information of the voltage regulator VR1 by accessing the integrated circuit bus address 0x48.

[0148] When operating the S750, after the FPGA obtains the register information of the voltage regulator VR1, it powers off the voltage regulator VR1.

[0149] In operation S760, the FPGA determines whether the power supply anomaly type of voltage regulator VR1 is a recoverable power supply anomaly type based on the register information of voltage regulator VR1. If it is determined that the power supply anomaly type of voltage regulator VR1 is transient overcurrent, which is a recoverable power supply anomaly type, then operation S770 is executed.

[0150] In operation S770, it is further determined whether the number of retry power-on attempts for the voltage regulator VR1 has exceeded 3. If it has not exceeded 3, operation S380 is executed.

[0151] In operation S780, the FPGA controls the voltage regulator VR1 to power on again and continues to monitor for any abnormalities in the power supply components. If it is determined that the power supply abnormality type of the voltage regulator VR1 is not a recoverable power supply abnormality type or the number of retries to power on the voltage regulator VR1 exceeds 3, then operation S790 is executed.

[0152] The S790 is operated to maintain the voltage regulator VR1 in a de-energized state and wait for the maintenance personnel to intervene.

[0153] Figure 8 A schematic block diagram of an electronic device 800 according to an embodiment of the present disclosure is shown.

[0154] like Figure 8 As shown, the electronic device 800 of this embodiment includes a power supply unit 810, a control component 110, and a power supply component 120.

[0155] The power supply unit 810 is configured to provide power voltage to the control assembly 110 and the power supply assembly 120.

[0156] Control component 110 is configured to send an enable signal to power component when the server is detected to be powered on.

[0157] The power supply assembly 120, connected to the control assembly and the power supply unit, is configured to generate a power status signal in response to an enable signal and send the power status signal to the control assembly.

[0158] The control component is also configured to acquire the register information of the power component when the power status signal indicates an abnormality, determine the type of power abnormality based on the register information, and send a shutdown signal to the power component.

[0159] Electronic device 800 may be, for example, a server equipped with a power supply unit 810, a control component 110, and a power supply component 120. The power supply unit 810 may be, for example, a server power supply, the control component 110 may be, for example, a field-programmable gate array (FPGA), and the power supply component 120 may include, for example, a fuse and a voltage regulation module.

[0160] In server scenarios, multiple sets of fuses E and voltage regulators VR are required for power conversion or isolation of the CPU, BMC and the entire board power supply. The enable control of the power chips of the fuses E and voltage regulators VR is implemented by CPLD as the control component 110.

[0161] When the load of the power chip fails, the board needs to be powered down to protect it and prevent it from being burned out. The faulty power chip will shut down the output PG signal and output voltage. After the CPLD detects the abnormal PG signal, it will immediately read the register information of the faulty chip and write it to the target storage area, and then disable the faulty chip.

[0162] BMC will use a polling method to read the register information in the target memory area and update the server log according to the register information, so that the server log includes the register information of the power chip that caused the abnormality due to the VR PG signal / Alert signal.

[0163] Server power supplies, field-programmable gate arrays (FPGAs), fuses, and voltage regulator modules can be located, for example, within the server's power supply or mainboard. When the server power supply provides the power voltage and the fuse or voltage regulator module experiences at least one of the following power supply anomalies: transient overcurrent, transient undervoltage, overtemperature warning, input undervoltage, overvoltage latch, continuous overcurrent latch, short circuit latch, or power supply failure, the FPGA promptly acquires the register information of the power supply components and sends a shutdown signal to the malfunctioning fuse or voltage regulator module based on the type of power supply anomaly.

[0164] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0165] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0166] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A power supply control system, comprising: The control component is configured to send an enable signal to the power supply component when the server is detected to be powered on. A power supply component, connected to the control component, is configured to generate a power status signal in response to the enable signal and send the power status signal to the control component. The control component is further configured to, when the power status signal indicates an abnormality, acquire the register information of the power component, determine the power abnormality type based on the register information, and send a shutdown signal to the power component.

2. The system according to claim 1, wherein the power supply component comprises: At least one power supply unit, each power supply unit being connected to the control component; The control component is configured to, upon detecting that the server is powered on, sequentially send enable signals to at least one power supply unit according to a preset timing logic, and, in response to a power status signal indicating an anomaly returned from any power supply unit, obtain register information of the abnormal power supply unit via the integrated circuit bus, determine the power anomaly type based on the register information, and send a shutdown signal to the abnormal power supply unit.

3. The system according to claim 2, wherein each power supply unit comprises: A fuse and a voltage regulator, wherein the fuse and the voltage regulator are respectively connected to the control component, and the fuse and the voltage regulator are electrically connected; The fuse is configured to, in response to a first enable signal from the control component, output a power supply voltage to the voltage regulator, generate a first power status signal based on a first operating parameter, and send the first power status signal to the control component; The first operating parameter includes at least one of the output voltage, output current and internal temperature of the fuse device; The voltage regulator is configured to, in response to a second enable signal from the control component, convert the power supply voltage to a target voltage and output it to the load, generate a second power status signal according to second operating parameters, and send the second power status signal to the control component; the second operating parameters include the output voltage of the voltage regulator.

4. The system of claim 1, wherein the power supply component includes at least one register, the value of a set flag bit of the register is used to indicate the state of the power supply component, the power status signal includes a power good signal and an alarm signal, and the control component is further configured to: In response to the power good signal indicating an abnormality, the abnormal power supply unit in the power supply component is located by querying the hardware mapping table. The hardware mapping table indicates the correspondence between the pin numbers of the power good signal and the power supply units in the power supply assembly; In response to the alarm signal indicating an abnormality, the abnormal power supply unit in the power supply assembly is located by sending an alarm response address command; The alarm response address command is used to cause the abnormal power supply unit to return the corresponding device address to the control component; Obtain the register information of the abnormal power supply unit, and determine the power supply abnormality type by parsing the register information; Save the power supply fault type and the register information, and send a shutdown signal to the faulty power supply unit.

5. The system according to claim 1, wherein the control component is further configured to: Determine whether to restore power based on the type of power failure; wherein... The power supply abnormality types include at least one of the following: transient overcurrent, transient undervoltage, overtemperature warning, input undervoltage, overvoltage latch, continuous overcurrent latch, short circuit latch, and power supply failure; If the power supply abnormality type is at least one of transient overcurrent, transient undervoltage, overtemperature warning, and input undervoltage, power supply is restored.

6. The system according to claim 5, wherein the control component is further configured to: Once it is determined that power has been restored, an enable signal is sent to the power supply component again; Upon receiving power status signals from the power supply components indicating normal operation, the server is powered on. In response to receiving any power status signal indicating an abnormality from the power supply component, and the number of times an enable signal is sent to the power supply component again exceeds a predetermined threshold, the power supply component remains off.

7. The system according to claim 1, further comprising: The management component is configured to read the register information from the target storage area of ​​the control component using a polling or interrupt-driven approach, and generate a power management log based on the register information.

8. The system according to claim 7, further comprising: An access control component, connected to the management component, the control component, and the power component via an integrated circuit bus, is configured to disconnect the communication between the management component and the power component and the control component while the control component is reading the register information of the power component via the integrated circuit bus, and to restore the communication between the management component and the power component and the control component after the control component has finished reading the register information of the power component.

9. The system according to claim 8, wherein the buffer output enable terminal of the control component is connected to the access control component; The control component is further configured to, during the upgrade of the management component, output an enable signal with a first level via the buffer output enable terminal to disconnect the communication between the management component and the power component and the control component, and, upon completion of the upgrade of the management component, output an enable signal with a second level via the buffer output enable terminal to restore the communication between the management component and the power component and the control component.

10. A server, comprising: The power supply unit is configured to provide power voltage; The control component is configured to send an enable signal to the power supply component when the server is detected to be powered on. A power supply component, connected to the control component and the power supply unit, is configured to generate a power status signal in response to the enable signal and send the power status signal to the control component. The control component is further configured to, when the power status signal indicates an abnormality, acquire the register information of the power component, determine the power abnormality type based on the register information, and send a shutdown signal to the power component.

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