Adaptive nand operation suspension scheduling method and device based on proportional equal division

Abstract

The application discloses a self-adaptive NAND operation suspension scheduling method and device based on proportional equal division, which divides the total busy time of programming / erasing operation into multiple suspension intervals in proportion, sets a suspension check point at the end of each suspension interval, calculates a suspension allowance score by a constructed cost function, and triggers suspension only when the suspension allowance score exceeds a dynamic threshold; dynamically calculates the maximum suspension number allowed by current operation according to the real-time physical busy time of a logic unit, and dynamically corrects the subsequent suspension interval by using an EWMA predictor according to the remaining busy time after each recovery; obtains a prediction probability by a Markov predictor before a read request arrives, and initiatively initiates pre-suspension when the prediction probability is greater than a preset threshold; compensates the busy time for the erasing operation, introduces a temperature drift compensation coefficient to correct a busy time base value, and guarantees the system stability under abnormal scenes by a hardware watchdog and a timeout hierarchical degradation strategy.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive storage control technology, and in particular to an adaptive NAND operation suspension scheduling method and apparatus based on proportional equal distribution. Background Technology

[0002] In NAND Flash storage systems, programming and erasing operations take significantly longer than reading operations. For example, in a three-cell NAND flash memory, programming typically takes 1 to 3 milliseconds, erasing takes 5 to 8 milliseconds, while reading takes only about 50 to 100 microseconds. When a programming or erasing operation is in progress, if the host initiates a read request, traditional solutions offer two approaches: waiting for completion or suspending and resuming. Passively waiting for the programming or erasing operation to finish before executing the read command leads to a significant deterioration in read latency, failing to meet the read latency quality of service (QoS) requirements of solid-state drives. Utilizing the suspension and resumption mechanism defined by the NAND interface, the currently time-consuming programming or erasing operation is paused, a high-priority read request is inserted, and the suspended operation is resumed after the read operation is completed.

[0003] However, existing suspend scheduling schemes generally suffer from the following defects and shortcomings: Suspension checkpoints use fixed periods or fixed numbers, failing to consider significant timing parameter differences between different NAND manufacturers and generations; they lack dynamic adaptation, failing to dynamically adjust the suspension interval based on the actual busy time of programming or erasing caused by wear and temperature changes during actual operation of each logic cell, resulting in intervals that are too close or too far apart; they lack fine-grained dual-layer gating of the number of reads during a single suspension and the total number of reads within the entire busy cycle, easily causing programming or erasing operations to be frequently suspended and "starved," or read request overflow and timeout; and they are mixed in operation types, failing to effectively distinguish the different suspension characteristics of programming and erasing operations, and failing to adapt to timing parameters from multiple manufacturers, making erasing operations prone to failure after multiple suspensions. Summary of the Invention

[0004] The purpose of this invention is to address the problems in existing NAND suspend scheduling, such as the inability to guarantee latency service quality due to fixed checkpoints, lack of differentiation between programming and erasure suspends, lack of dynamic adaptive gating based on real-time physical state, and lack of systematic adaptation to timing parameters from multiple vendors. This invention proposes a proportionally distributed adaptive NAND operation suspend scheduling method and apparatus. By dynamically and proportionally dividing busy time windows, introducing predictive decision-making based on multi-physical dimension feedback, and implementing a hardware-coordinated timeout grading and degradation mechanism, this invention aims to maximize the effective utilization of NAND media and extend the lifespan of solid-state drives while strictly guaranteeing host read latency service quality.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: The adaptive NAND operation suspension scheduling method based on proportional distribution includes the following: Divide the total busy time of programming or erasing operations into multiple suspension intervals proportionally, and set a suspension checkpoint at the end of each suspension interval. Based on the real-time physical busy time of the logic unit, the maximum number of suspensions allowed for the current programming or erasing operation is dynamically calculated and used as a constant upper limit for the number of suspensions during the current operation. For the erase operation, the busy time compensation is dynamically added based on the number of suspensions after each recovery. For the busy time drift caused by wear, the suspension interval is dynamically corrected based on EWMA. The prediction probability is obtained based on the Markov predictor. When the prediction probability is greater than the preset threshold, a pre-suspend trigger signal is actively issued. At each suspension checkpoint, a suspension allowance score is calculated based on a cost function, and suspension is allowed only if the suspension allowance score exceeds a dynamic threshold. Introduce a temperature drift compensation coefficient to correct the busy time base value of programming or erasure operations based on real-time temperature; The watchdog timer monitors the execution timeout of suspended commands and implements a tiered degradation strategy based on the severity of the timeout.

[0006] More preferably, the total busy time of the programming or erasing operation is divided into multiple suspension intervals proportionally, as follows: Obtain the total busy time base value T_BUSY_BASE_COMP after temperature and wear compensation; Get the maximum number of suspensions allowed for the current operation, MAX_SSPD_CNT; The suspension interval T_SSPD_INTRVL is calculated using the following formula: T_SSPD_INTRVL=T_BUSY_BASE_COMP / (MAX_SSPD_CNT+1); The total busy time is divided into (MAX_SSPD_CNT+1) equal parts on the time axis. The length of each part is the suspension interval, and the end point of each suspension interval is set as the suspension check point. The suspension check window is the width of the interval around the suspension check point. The suspension check window is equal to the suspension interval in value. Suspension is allowed only within the suspension check window.

[0007] More preferably, the dynamic calculation of the maximum number of suspensions allowed for the current programming or erasing operation is performed in the following manner: Read the real-time physical busy clock cycle count value T_BUSY_ACTUAL of the current logic unit; Read the currently active suspension interval T_SSPD_INTRVL_CURRENT; The maximum number of suspensions, ADAPTIVE_MAX_CNT, is calculated using the following formula: ADAPTIVE_MAX_CNT=(T_BUSY_ACTUAL / T_SSPD_INTRVL_CURRENT)-1; If ADAPTIVE_MAX_CNT > 0, then the maximum number of times the current operation can be suspended is MAX_SSPD_CNT = ADAPTIVE_MAX_CNT; if ADAPTIVE_MAX_CNT ≤ 0, then suspension is disabled and MAX_SSPD_CNT = 0. The maximum number of suspensions is calculated once when the current programming or erasure command is initiated, and serves as a constant upper limit during the operation.

[0008] More preferably, the dynamic addition of busy time compensation for the number of suspensions is performed in the following manner: Busy time compensation is enabled only when the operation type is erase; Let cur_suspend_count be the cumulative number of suspensions that have occurred in the current operation; If cur_suspend_count equals the maximum number of suspensions MAX_SSPD_CNT, and the logic unit is still busy after resumption, then: Temporarily increment the maximum number of suspensions MAX_SSPD_CNT by 1, allowing one more suspension; The compensation time is equal to the currently effective suspension interval T_SSPD_INTRVL_CURRENT; Update the total busy time T_BUSY_TOTAL using the following formula: T_BUSY_TOTAL=T_BUSY_BASE_COMP+(cur_suspend_count×T_SSPD_INTRVL_CURRENT)+T_WAIT_RESUME; Where T_BUSY_BASE_COMP represents the busy time base value after temperature and wear compensation, and T_WAIT_RESUME is the hardware firmware interaction overhead time.

[0009] More preferably, the EWMA-based dynamic correction of the suspension interval includes: After each recovery operation is completed, the read logic unit returns the actual remaining busy time T_REM before it becomes idle; Get the currently used suspension interval T_SSPD_INTRVL_OLD and the remaining suspension count; The suspension interval T_SSPD_INTRVL_NEW is dynamically adjusted using the following formula: T_SSPD_INTRVL_NEW = α × T_SSPD_INTRVL_OLD + (1-α) × (T_REM / (remaining number of suspensions + 1)); Where T_SSPD_INTRVL_NEW is the updated suspension interval, and α is the smoothing factor; Write T_SSPD_INTRVL_NEW to the proportional equal timer, update the proportional equal timer register, and determine whether the recovery operation is complete. If yes, return; otherwise, continue to execute the suspended checkpoint trigger.

[0010] More preferably, the step of obtaining the prediction probability based on the Markov predictor, and actively issuing a pre-suspend trigger signal when the prediction probability is greater than a preset threshold, includes: If the interval between the two most recent read request suspensions is less than a preset threshold, then the suspension interval is marked as a dense state; otherwise, it is marked as a sparse state. Update the state transition count table for each new read request; The predicted probability P_ij of transitioning from state i to state j is expressed as: P_ij=cnt_ij / (cnt_iD+cnt_iS), Where, cnt_ij is the actual number of times the transition from state i to state j occurs, and cnt_iD and cnt_iS represent the total number of transitions from the current state i to the dense state and the sparse state, respectively. When the current programming or erasure operation is in a non-suspended state and has not yet reached the suspension checkpoint, the average dense or average sparse duration is estimated starting from the current state. Based on the current state and the transition matrix, the predicted probability of entering the dense state within a predetermined time period in the future is calculated. If the predicted probability is greater than the preset threshold, a pre-suspend signal is triggered, and the process jumps to the suspended state. After each read response is completed, update the history arrival interval buffer and state transition count.

[0011] More preferably, the suspension allowance score S_Score is calculated based on the cost function using the following formula: S_Score=[Q_read(urgency)×W_read_weight] / [Q_pe(progress)×W_pe_weight+ε]; Where Q_read(urgency) is the urgency coefficient calculated based on the maximum wait timeout of read requests in the current pending queue; W_read_weight is the current host read bandwidth weight; Q_pe(progress) is the reciprocal of the time elapsed for the current programming or erasing operation; W_pe_weight is the current host write bandwidth weight; and ε is a constant. The dynamic threshold K is dynamically adjusted according to the write amplification factor, and the gating decision is as follows: Suspension is only allowed if S_Score > K.

[0012] More preferably, the introduction of a temperature drift compensation coefficient, which corrects the busy time base value of the programming or erasing operation based on real-time temperature, is implemented in the following manner: Read the real-time temperature TEMP_curr output from the SSD's onboard temperature sensor; Obtain the busy time base value T_BUSY_BASE and the temperature drift compensation coefficient β before compensation; The compensated busy time base value T_BUSY_BASE_COMP is calculated using the following formula: T_BUSY_BASE_COMP=T_BUSY_BASE×(1+β×(25℃-TEMP_curr)).

[0013] More preferably, the step of monitoring the execution timeout of the suspend command through a watchdog timer and implementing a graded degradation strategy based on the severity of the timeout is as follows: Each time a suspend command is issued, the watchdog timer loads a preset timeout value and starts counting down; if a suspend response is received before the timeout value, the watchdog timer is reset to zero; otherwise, a timeout interrupt is triggered. The tiered downgrade strategy includes: Level 1 downgrade: If the suspend command times out without confirmation, immediately resend the suspend command and shorten the suspend interval. Level 2 degradation: If the cumulative retries fail after reaching a preset number of attempts, the suspension operation on the logical unit is abandoned, the physical address of the logical unit is filled into the exception block table, and background data migration is triggered after the current programming or erasure operation is completed. Level 3 degradation means that when the status query command times out without response, the channel link layer of the logical unit is directly reset and the connection is re-established. The watchdog timeout automatically records the retry count. The first timeout triggers Level 1 degradation. If the timeout occurs again after Level 1 degradation, the retry count is incremented. When the retry count reaches a preset number, Level 2 degradation is triggered. If the timeout occurs during the status query phase, Level 3 degradation is triggered directly.

[0014] In another aspect, this invention proposes a proportionally evenly distributed adaptive NAND operation suspension scheduling device for executing the proportionally evenly distributed adaptive NAND operation suspension scheduling method. The device is integrated into the suspension scheduling hardware engine within the channel processor of the SSD controller. The device includes: A proportional timer, counting at the main clock cycle, is used to generate evenly distributed suspend checkpoints; An 18-state finite state machine is used for process control, including suspending, reading, resuming, and querying states. The adaptive control logic module includes an EWMA predictor, an adaptive maximum number of times calculation unit, and a temperature compensation unit, which performs dynamic correction of the suspension interval, calculation of the maximum number of suspensions, and temperature drift compensation of the busy time base value. The Markov predictor has a built-in read arrival density prediction module. It predicts the arrival density of read requests and compares the obtained prediction probability with a preset threshold to trigger suspension in advance. Cost function calculator, used to calculate the allowed suspension score; Watchdog timer and tiered degradation controller are used for independent timeout monitoring and execution of tiered degradation strategies; Registers store basic parameter configurations for different NAND manufacturers or generations.

[0015] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention divides the total busy time of programming or erasing into uniform check windows using a proportional equalization formula, ensuring that read insertion opportunities are completely controllable. The maximum read latency is strictly limited within the suspension interval and read execution time, significantly improving read tail latency and exhibiting high uniformity and low latency jitter. By introducing EWMA-based dynamic interval correction and adaptive maximum suspension count calculation, it can perfectly track the physical time changes caused by NAND wear and aging, eliminating the need for manual parameter tuning and achieving full lifecycle adaptation. By using a Markov predictor to achieve proactive pre-suspension, it upgrades the traditional passive response to active defense, fundamentally eliminating the command transmission latency overhead of the suspension command itself. Through multi-dimensional cost function gating decision-making, it comprehensively considers read urgency, write bandwidth pressure, and remaining erase / write time, avoiding the starvation of programming or erase / write operations due to unilateral pursuit of read performance, thus improving the overall steady-state throughput of the solid-state drive. Through temperature drift compensation and watchdog graded degradation strategies, the scheduling algorithm can maintain deterministic service quality under high temperature, low temperature, and NAND physical anomaly scenarios, greatly enhancing the product's environmental adaptability and reliability. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the collaborative data flow between the intelligent decision enhancement layer and the scheduling layer in an embodiment of the present invention; Figure 2 This is a schematic diagram of the state transition path of the 18-state finite state machine in this embodiment of the invention; Figure 3 This is a schematic diagram of the proportionally evenly distributed hanging interval in an embodiment of the present invention; Figure 4 This is a flowchart of the adaptive maximum number of suspensions and EWMA dynamic correction in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the specific embodiments of this invention will be described in detail below with reference to the accompanying drawings. These embodiments are merely preferred examples of this invention, used to aid in understanding the inventive concept, and do not constitute a limitation on the scope of protection.

[0018] To ensure consistency in terminology throughout the text, the following terms are defined: Programming (P): The operation of writing data to NAND pages.

[0019] Erase (E): The operation that erases a NAND block to a state of all "1"s.

[0020] Read (R): The operation of reading data from a NAND page.

[0021] Suspend (SSPD): Pauses the currently executing programming or erasing operation in order to insert a read operation.

[0022] Resume (RSUM): Resumes a suspended programming or erasing operation after the read is complete.

[0023] Channel Processor (CHP): The back-end hardware processing unit in the SSD controller responsible for managing a single NAND channel, and is the core execution entity of this invention.

[0024] A logical cell (Die) is the smallest physical unit in NAND flash memory that can perform operations independently. Each die has its own state machine.

[0025] Busy time base value before temperature compensation (T_BUSY_BASE): The busy time base value experienced by the programming or erasing operation from the start to the physical completion before temperature compensation.

[0026] Temperature-compensated busy time base value (T_BUSY_BASE_COMP): The busy time base value for programming or erasing operations after temperature compensation.

[0027] Suspension Interval (T_SSPD_INTRVL): The time length between two adjacent suspension checkpoints on the busy timeline.

[0028] Suspend Checkpoint: A pre-defined point on the timeline at which a suspension request is allowed to be initiated.

[0029] Suspend Check Window: A tiny time window centered on the checkpoint. Suspension judgments and operations are performed within this window. In this scheme, the window width is equal to the suspension interval.

[0030] This embodiment proposes a proportionally distributed adaptive NAND operation suspension scheduling device, integrated into the suspension scheduling hardware engine within the Channel Processor (CHP) of the SSD controller. Its physical components include: The proportional divider timer is a reloadable decrementing counter that counts in cycles of the master clock and is used to generate evenly distributed suspend checkpoints.

[0031] An 18-state finite state machine (FSM) enables complete process control for suspending, reading, resuming, and querying status.

[0032] The adaptive control logic module includes an EWMA predictor, an adaptive maximum count calculation unit, and a temperature compensation unit. As the core computing engine of the intelligent decision enhancement layer, the adaptive control logic module is responsible for collecting the physical state (actual busy time) and environmental parameters (temperature) of the logic units in real time. Based on this dynamic feedback information, through the internally integrated EWMA predictor, adaptive maximum count calculation unit, and temperature compensation unit, it performs dynamic correction of the suspension interval, adaptive calculation of the maximum suspension count, and temperature drift compensation of the busy time base value, respectively. Finally, it outputs the optimized scheduling parameters (such as the updated suspension interval and maximum suspension count) to the basic scheduling layer, realizing closed-loop, real-time, and human-intervention-free adaptive adjustment of the suspension scheduling strategy.

[0033] The Markov predictor has a built-in lightweight read arrival density prediction module. It predicts the arrival density (dense or sparse) of read requests and compares the obtained prediction probability with a preset threshold to trigger suspension in advance.

[0034] Cost function calculator, calculates the allowed suspension score in real time.

[0035] Watchdog timers and tiered degradation controllers are used for independent timeout monitoring and execution of tiered degradation strategies.

[0036] The register stores basic parameter configurations such as busy time base value and temperature drift compensation coefficient for different NAND manufacturers or generations.

[0037] The aforementioned physical components together form a closed-loop adaptive scheduling system through the basic scheduling layer and the intelligent decision enhancement layer.

[0038] The basic scheduling layer consists of proportionally distributed timing and an 18-state finite state machine, which is responsible for initiating suspension at fixed time points and executing standard suspension or recovery procedures. The intelligent decision enhancement layer consists of an adaptive control logic module, a Markov predictor, a cost function calculator, a watchdog timer, and a hierarchical degradation controller. It is responsible for dynamically adjusting the timer's overload value (suspend interval), the maximum number of suspends, and whether to allow jumping to the suspend state.

[0039] Figure 1 This diagram illustrates the collaborative data flow between the intelligent decision enhancement layer and the scheduling layer of an adaptive NAND operation suspension scheduling device based on proportional distribution. The input layer sends real-time temperature values ​​measured by temperature sensors, current write ratio statistics of read / write bandwidth, maximum wait timeout statistics of the read queue, time elapsed for programming / erasing progress, and read arrival history (128-item circular buffer) to the intelligent decision enhancement layer. In the intelligent decision enhancement layer, the temperature compensation unit corrects the busy time base value, the Markov predictor second-order state model generates a pre-suspension trigger based on the read arrival history, and the cost function calculator generates a suspension allowance score by combining the urgency coefficient and the erase / write progress. After gating decision-making, the finite state machine is enabled. The basic scheduling layer is responsible for the 18-state finite state machine of process control. The integrated checkpoint trigger, pre-suspend trigger and gating enable signal send operation commands to the logic unit (Die) of the execution layer to execute NAND operations. The remaining busy time after recovery is fed back to the EWMA predictor to dynamically correct the next suspension interval. At the same time, the Markov history is updated. The proportionally distributed timer generates evenly distributed suspension checkpoints. The watchdog independently monitors timeouts and triggers hierarchical degradation, forming a fully closed-loop adaptive scheduling.

[0040] It should be noted that the intelligent decision enhancement layer does not contain a physical hardware watchdog. The watchdog is located inside the channel processor, but its timeout threshold and degradation strategy are controlled by this layer. Its decision results are applied to the basic scheduling layer by modifying registers and control signals.

[0041] The Channel Processor (CHP), serving as the carrier of this device, manages one or more dies. Each die executes operations independently. The Channel Processor routes suspend commands to specific dies via die selection signals and receives their status feedback. The relationship between the device and the dies is as follows: the device is the scheduling and decision-making center within the Channel Processor, and the dies are the scheduled execution objects. This device does not contain the NAND dies themselves but relies on the busy / idle status signals of the dies and temperature sensor inputs.

[0042] The aforementioned 18-state finite state machine (FSM) contains 18 defined state codes, covering the complete control flow from the start of programming / erasing to the end. This embodiment explicitly lists all 18 states and transition logic, and their state codes are shown in Table 1.

[0043] Table 1 Status Code Table

[0044] State transition path of an 18-state finite state machine: Combining Table 1 and Figure 2 Starting from state 0: IDLE (idle), if a write command is received from the host, it jumps to state 1: REQ_PROG (initiating a programming request) or state 2: REQ_ERASE (initiating an erase request), and then enters state 3: RESP_CMD (waiting for a command response). Die accepts the command. Once Die enters the busy state, the proportional sharing timer starts. When the proportional sharing timer reaches the suspension interval and the cost function gating decision condition is met, it jumps to state 4: REQ_SSPD (initiating a suspension request), and then enters state 5: RESP_SSPD (waiting for a suspension response). If the response is successful, the process proceeds to state 7: REQ_READ0 initiates a normal read request; state 8: REQ_READ1 initiates an MPI first read request; state 9: REQ_READ2 initiates an MPI internal read request. States 7, 8, and 9 are selected according to read type priority, and then proceed through the corresponding response states in sequence: state 10: RESP_READ0 waits for a normal read response; state 11: RESP_READ1 waits for an MPI first read response; state 12: RESP_READ2 waits for an MPI internal read response. After the read is completed, the process jumps to state 13: REQ_RSUM initiates a recovery request. After the recovery command is issued, the process returns to state 14: RESP_RSUM waits for recovery to complete. After recovery is complete, jump to state 15: REQ_STS to initiate a status query to check the Die status. If the query returns to state 16: RESP_STS_BUSY and returns busy, then re-enter the suspended waiting loop (i.e., return to wait for the next suspended checkpoint); if the query returns an exception, then return to state 17: RESP_STS_FAIL and the query returns failure, then exception handling is triggered; if it returns idle (i.e. programming / erasing complete), then return to state 0: IDLE.

[0045] If a suspension failure response is received in state 5: RESP_SSPD, the process jumps to state 6: RESP_SSPD_FAIL suspension failure handling. In this state, the failure count is recorded and subsequent suspensions are prevented within the current operation cycle. Then, the process jumps to state 15: REQ_STS and keeps querying the Die status until the operation is completed.

[0046] Based on the above description of the adaptive NAND operation suspension scheduling device based on proportional distribution, this embodiment further proposes an adaptive NAND operation suspension scheduling method based on proportional distribution, which includes the following: This invention does not use fixed values, but instead designs a family of register parameters that can be configured during compilation. For different NAND vendors and generations, the parameters are burned into read-only memory (ROM) during the firmware compilation stage, and then loaded into internal registers by the channel processor after power-on.

[0047] Detailed configuration method: Define a set of structures for each NAND manufacturer or generation, including: program_time_base[N] is an array of program busy time base values ​​(unit: number of clock cycles). N is the number of segments, with a default value of 1.

[0048] erase_time_base[M], erases the busy time base value array (M is similar).

[0049] segment_boundary[ ], segment page address boundary (if applicable).

[0050] suspend_fail_mask, a bitmap, indicates which segments are forcibly prevented from being suspended (suspending failure-prone segments).

[0051] During power-on initialization, the channel processor matches the corresponding structure based on the NAND ID and writes the base value into the overload register of the proportional equalization timer.

[0052] For particles with programmable segmentation characteristics (such as some Micron TLCs with three word line levels), this solution configures three independent program_time_base[0..2], corresponding to the low, middle and high segments of the word line respectively.

[0053] The first segment (lower segment) is prone to suspension failure due to physical characteristics. Therefore, bit 0 of `suspend_fail_mask` is configured to be 1, indicating that when programming operations are in this segment, the forced suspension failure flag is in effect. That is, no suspension is allowed in this segment. Although the proportional equalization timer continues to run, it does not trigger a suspension request until the second segment is entered, after which the suspension capability is restored. This is a special instance under a multi-vendor differentiated configuration framework, where its configuration parameters and general base values ​​are stored in the same structure.

[0054] This invention achieves a uniform distribution of hanging inspection points along the busy time axis through proportional equalization, the geometric meaning of which is as follows: Figure 3As shown, the total busy time of a complete programming or erasing operation is evenly divided into (MAX_SSPD_CNT+1) equal parts on the time axis. The length of each part is the suspension interval (T_SSPD_INTRVL). The end point of each suspension interval is set as the suspension checkpoint. The width of the interval around the suspension checkpoint is the suspension check window. The suspension check window is numerically equal to the suspension interval, and suspensions are allowed to be initiated within the suspension check window.

[0055] Obtain the total busy time base value T_BUSY_BASE_COMP after temperature and wear compensation; Get the maximum number of suspensions allowed for the current operation, MAX_SSPD_CNT; The formula for calculating the hanging interval with equal proportions is as follows: T_SSPD_INTRVL=T_BUSY_BASE_COMP / (MAX_SSPD_CNT+1) Wherein, T_BUSY_BASE_COMP represents the busy time base value after temperature and wear compensation, in units of main frequency clock cycles; MAX_SSPD_CNT is the maximum number of suspensions allowed for this operation (fixed configuration or adaptive calculation).

[0056] The division result is rounded down (using integer division to truncate) to ensure that the suspended checkpoint does not exceed the busy time range. This formula divides the total time evenly, so each suspended interval is equal, achieving an even distribution of suspended intervals. The (N+1) suspended check windows correspond to the (N+1) suspended check intervals, and the end point of each suspended check window is the suspended checkpoint.

[0057] The process of adaptive maximum suspension count and dynamic EWMA correction is as follows: Figure 4 As shown, this process is a complete decision-making path from reading the actual busy time, calculating the maximum number of temporary suspensions, to using the remaining time of the previous recovery to weighted update the next suspension interval.

[0058] Using the adaptive maximum count calculation unit, when adaptive mode (ENABLE_ADAPTIVE_MAX_SSPD_CNT) is enabled, the maximum number of suspensions no longer uses a fixed configuration. Instead, at the beginning of each programming or erasing operation, the channel processor dynamically calculates the maximum number of suspensions allowed for the current programming or erasing operation based on the real-time physical busy time of the logic unit (Die). This calculation serves as a constant for the number of suspensions during the current operation. The process is as follows: At the beginning of each programming or erasing operation, read the real-time physical busy clock cycle count value T_BUSY_ACTUAL of the current Die (i.e., the measured time from when the command is issued to when the Die returns the busy flag).

[0059] Read the currently effective suspension interval T_SSPD_INTRVL_CURRENT (EWMA correction has been taken into account), determine whether adaptive mode is enabled, if not enabled, use a fixed number of suspensions to perform programming or erasure operations, if adaptive mode is enabled, proceed to the next step.

[0060] The dynamic calculation formula for the adaptive maximum number of suspensions is as follows: ADAPTIVE_MAX_CNT=(T_BUSY_ACTUAL / T_SSPD_INTRVL_CURRENT)-1; Division uses integer division and rounds down; where ADAPTIVE_MAX_CNT represents the maximum number of suspensions allowed for the current programming or erasure operation, calculated dynamically and adaptively.

[0061] If ADAPTIVE_MAX_CNT > 0, then the maximum number of times this operation can be suspended is this value, MAX_SSPD_CNT = ADAPTIVE_MAX_CNT; if ADAPTIVE_MAX_CNT ≤ 0, then suspension is prohibited (MAX_SSPD_CNT = 0), and programming or erasure operations are performed.

[0062] The maximum number of suspensions is calculated once when the current programming or erasure command is initiated, serving as a constant upper limit during the operation.

[0063] For erase operations, to make the total completion time of the erase operation more accurate through busy time compensation and to avoid failure, the erase operation requires additional charge neutralization time after each resumption. Therefore, the busy time compensation algorithm for the number of suspensions in this invention only takes effect when the operation type is erase. After each resumption, busy time compensation is dynamically added based on the number of suspensions that have occurred. The specific rules of the busy time compensation algorithm for erase operations are as follows: Let cur_suspend_count be the cumulative number of suspensions that have occurred in the current operation (the number of suspensions that have occurred from the start of the operation until it has been successfully suspended is the cumulative number of suspensions that have occurred in the current operation cycle, not all historical counts).

[0064] If cur_suspend_count = maximum number of suspensions (MAX_SSPD_CNT), meaning the maximum allowed number has been reached, and Die is still busy after resumption, indicating that additional time is needed, then: Temporarily increment MAX_SSPD_CNT by 1 to allow one more suspension; The compensation time is equal to the currently effective suspension interval T_SSPD_INTRVL_CURRENT; Update the total busy time T_BUSY_TOTAL using the following formula: T_BUSY_TOTAL=T_BUSY_BASE_COMP+(cur_suspend_count×T_SSPD_INTRVL_CURRENT)+T_WAIT_RESUME.

[0065] T_WAIT_RESUME is the hardware firmware interaction overhead time (including command transmission and status polling delays), which is a pre-measured fixed value (e.g., 5μs) and stored in clock cycles.

[0066] To track the busy time drift caused by NAND wear, this invention integrates an EWMA predictor (exponentially weighted moving average model, EWM) into the channel processor. After each recovery operation is completed, the channel processor reads the actual remaining busy time T_REM before the Die returns to idle (i.e., the time from recovery completion to the Die busy flag being removed).

[0067] If T_REM is very short (e.g., <50μs), it indicates that the reserved suspension interval is too long, and the next suspension interval should be shortened. If T_REM is relatively long, it indicates that the reserved suspension interval is insufficient, and the next suspension interval should be increased.

[0068] Get the currently used suspension interval T_SSPD_INTRVL_OLD, and the remaining number of suspensions for the current operation; The formula for dynamically adjusting the suspension interval based on EWMA is as follows: T_SSPD_INTRVL_NEW = α × T_SSPD_INTRVL_OLD + (1 - α) × (T_REM / (remaining number of pending attempts + 1)) Wherein, T_SSPD_INTRVL_NEW is the updated suspension interval, which will be written to the proportional equalization timer for subsequent suspension checkpoints; T_SSPD_INTRVL_OLD is the currently used suspension interval; α is the smoothing factor, configured by a hardware register (within the range of 0.5 to 0.9), and expressed as a fixed-point decimal (e.g., 0.75 corresponds to a shift operation).

[0069] Remaining number of suspensions = Current maximum number of suspensions - Number of suspensions that have occurred.

[0070] Then, T_SSPD_INTRVL_NEW is written to the proportional averaging timer, updating the proportional averaging timer register. It then checks if the recovery operation is complete; if yes, it returns; otherwise, it continues executing the suspended checkpoint trigger, implementing a cyclical operation of suspending, reading requests, and recovery. This EWMA predictor is updated once after each suspended checkpoint, ensuring that the suspension interval dynamically changes with physical time.

[0071] The Markov predictor proposed in this invention employs a second-order state model, simplifying the read request arrival pattern into two states: dense (D) and sparse (S). The hardware implementation does not involve complex matrix operations; instead, it utilizes a counter and comparator within the Markov predictor. By using the Markov predictor, probability calculations are not performed through complex multiply-accumulate or matrix operation units. The prediction logic is completed using a counter and a comparator that compares the probability values ​​with a preset threshold, resulting in minimal hardware overhead and significantly reducing the latency of suspended command transmission (approximately 5~10 μs).

[0072] The specific implementation steps of the read request advance pre-suspend mechanism based on Markov chains are as follows: The prediction probability is obtained using the read arrival density prediction module of a Markov predictor. 1. State Definition: The channel processor maintains a 128-entry historical arrival interval circular buffer, counted by the main clock frequency. If the interval between the two most recent read request suspends is less than a preset threshold (e.g., 30μs), the suspend interval is marked as dense state D; otherwise, it is marked as sparse state S. The aforementioned dense state (D) and sparse state (S) are called the arrival density of the read request.

[0073] 2. Transition probability update: For each new read request, update the state transition counter table and maintain two counters, including a transition counter and a state dwell time counter. The transition counter is used to record the number of transitions between states to calculate the transition probability; the state dwell time counter is used to record the duration for which the system stays in the same state (dense or sparse).

[0074] The state transition count table is as follows: cnt_DtoD: Represents the number of times a state transitions from a dense state (D) to a dense state (D).

[0075] cnt_DtoS: Represents the number of times the state transitions from dense state (D) to sparse state (S).

[0076] cnt_StoD: Represents the number of times the state transitions from a sparse state (S) to a dense state (D).

[0077] cnt_StoS: Represents the number of transitions from sparse state (S) to sparse state (S).

[0078] When an actual transfer occurs, the corresponding counter increments by 1, saturating to its maximum value of 255; The predicted probability P_ij of transitioning from state i to state j is expressed as: P_ij=cnt_ij / (cnt_iD+cnt_iS), Wherein, cnt_ij is the actual number of times the transition from state i to state j occurs, and cnt_iD and cnt_iS represent the total number of transitions from the current state i (which can be D or S) to dense (D) and sparse (S) states, respectively.

[0079] In actual comparisons, multiplication is used to avoid division, such as determining whether cnt_DtoD > (cnt_DtoD + cnt_DtoS) * threshold / 100.

[0080] 3. Predictive Decision-Making: When the current programming or erasing operation is in a non-suspended state and the proportional distribution timer has not yet reached the suspension checkpoint, the Markov predictor, starting from the current state, estimates the average dense or average sparse duration using the state dwell time counter. Based on the current state (D or S) and the transition matrix, it calculates the predicted probability P_ij of entering a dense state within the next 200μs. If the predicted probability is greater than a preset threshold (e.g., >70%), it determines that "the dense arrival state is about to be entered," triggering a pre-suspension. That is, before the current programming or erasing operation reaches the suspension checkpoint, a pre-suspension trigger signal is actively sent to the 18-state finite state machine. Even if the read queue is empty, it jumps to the suspended state REQ_SSPD. The pre-suspension is actively initiated before the current programming or erasing operation reaches the suspension checkpoint, and a zero-delay response can be given once a read request arrives.

[0081] The transition matrix is ​​a 2×2 matrix consisting of four transition probabilities: P = |P_DD,P_DS|×|P_SD,P_SS|, Wherein, P_DD = cnt_DtoD / (cnt_DtoD+cnt_DtoS); P_DS = cnt_DtoS / (cnt_DtoD+cnt_DtoS), and so on.

[0082] The predicted probability of entering a dense state within the next 200μs is not directly equal to P_SD or P_DD. Instead, it requires combining the dwell time of the current state (i.e. how long the current state has lasted) and the state transition probability to calculate the predicted probability of a state transition (from S to D, or remaining in D) occurring within the next 200μs time window.

[0083] After each read response is completed, the historical arrival interval circular buffer and transition count are updated, and the second-order state model is updated to achieve continuous self-learning.

[0084] This invention utilizes a cost function calculator to construct a real-time cost function as a hard indicator for whether a jump from IDLE or RESP_CMD to REQ_SSPD is allowed. The cost function calculator is located in the intelligent decision enhancement layer, and its inputs include read queue timeout information, host read / write bandwidth statistics, and the time elapsed for current programming or erasing.

[0085] At each suspension checkpoint, a suspension allowance score, S_Score, is calculated based on a multi-dimensional cost function using the following formula: S_Score=[Q_read(urgency)×W_read_weight] / [Q_pe(progress)×W_pe_weight+ε]

[0086] Wherein, Q_read(urgency) is the urgency coefficient (selectable from 0 to 10) calculated based on the maximum waiting timeout of read requests in the current pending queue; W_read_weight is the current host read bandwidth weight (real-time statistics); Q_pe(progress) is the reciprocal of the time elapsed for the current programming or erasing operation, reflecting the remaining workload of the programming or erasing operation; W_pe_weight is the current host read / write bandwidth weight. If the read pressure is high, this weight is increased to suppress suspending; ε is a constant to prevent division by zero errors.

[0087] The gating rule for the above cost function gating decision is: a suspension operation is only allowed when S_Score > K (K is a dynamic threshold that is adjusted with the write amplification factor). The cost function calculator outputs an enable signal one clock cycle before each suspension checkpoint.

[0088] Onboard temperature sensors are standard in existing SSDs, typically integrated near the controller or NAND flash memory. NAND programming and erasing times are extremely sensitive to operating temperature; they slow down at low temperatures due to reduced electron mobility and speed up at high temperatures. This invention uses the output of the onboard temperature sensor as an input signal, incorporating it into the compensation logic of the channel processor. While the onboard temperature sensor itself is not part of the device, the device includes a temperature compensation calculation unit responsible for reading the onboard temperature sensor's output. Based on the real-time temperature (TEMP_curr), it introduces a temperature drift compensation coefficient to correct the busy time base value for programming or erasing operations. The temperature compensation formula is as follows: T_BUSY_BASE_COMP=T_BUSY_BASE×(1+β×(25℃-TEMP_curr)) Where T_BUSY_BASE represents the busy time base value before compensation, T_BUSY_BASE_COMP is the busy time base value after compensation, and β is the temperature drift compensation coefficient, stored in read-only memory (ROM). The value of β can be 0.001 ~ 0.005, ensuring that the result of (1 + β × (25℃ - TEMP_curr)) is positive in any operating temperature range, such as -40℃ to 125℃.

[0089] The watchdog timer is an independent timer within the channel processor and is not a physical module of the intelligent decision enhancement layer. However, its timeout threshold and degradation strategy are configured by the intelligent decision enhancement layer. The watchdog timer monitors the execution timeout of suspended commands and executes a graded degradation strategy based on the severity of the timeout, as follows: Timeout trigger: Each time a suspend command is issued, the watchdog timer loads a preset timeout value (e.g., 200μs) and starts counting down; if a suspend response is received before the timeout value, the watchdog timer is reset to zero; otherwise, an interrupt is triggered.

[0090] The degradation strategy response selection mechanism of the tiered degradation controller is as follows: Level 1 downgrade (timeout without confirmation): Immediately resend the suspension command and shorten the suspension interval to 50% of the current value (to accelerate the next suspension preemption).

[0091] Level 2 degradation: If the cumulative retries fail after reaching the preset number (3 retries and still fail), the suspension operation on the die is abandoned, the physical address of the die is filled into the exception block table, and the background data migration is triggered after the current programming / erasing operation is completed.

[0092] Level 3 degradation (status query timeout, i.e. no response after REQ_STS) directly resets the channel link layer of the die and re-establishes the connection.

[0093] After the watchdog timeout, the hardware automatically records the retry count. The first timeout triggers Level 1 degradation; if a Level 1 degradation occurs (retransmission) and then times out again, the retry count is incremented by 1. When the retry count exceeds a preset number, Level 2 degradation is triggered; if the timeout occurs during the status query phase (independent of the suspend timeout), Level 3 degradation is triggered directly. Level 3 degradation is the highest level and is not affected by the retry count.

[0094] In another embodiment of the present invention, taking a mainstream manufacturer's TLC NAND (with a total programming time base value configured as 1500μs) as an example, the operation process of the adaptive NAND operation suspension scheduling method based on proportional equal distribution is briefly described.

[0095] Step 1, during the system power-on initialization phase, the channel processor loads the corresponding compile-time parameters from the read-only memory: Maximum number of suspensions = 2, basic suspension interval = 1500μs / (2+1) = 500μs.

[0096] Step 2: The host sends a write command, the channel processor enters the REQ_PROG state, and begins programming operations. The internal busy counter starts to increment.

[0097] Step 3: When the internal timer reaches 500μs, if the read request queue is detected to be non-empty, the 18-state finite state machine transitions to REQ_SSPD. After issuing a suspend command, the watchdog timer loads a 200μs timeout value.

[0098] Step 4: If the suspension is successful, proceed to REQ_READ0 to perform a read operation. After the read operation is completed, check if the number of reads during a single suspension (num_reads_during_suspend) is less than 16; if it is less, initiate a resumption (REQ_RSUM).

[0099] Step 5: After recovery is complete, recalculate the remaining suspend interval (using the EWMA dynamic interval correction formula, with α set to 0.75) and update the reload register of the proportional equalization timer.

[0100] Step 6: Repeat steps 3-5 until the programming is complete or the total number of reads reaches the upper limit of 512.

[0101] In another embodiment of the present invention, taking the enhanced implementation under extreme high temperature and burst read scenarios as an example, the operation process of the adaptive NAND operation suspension scheduling method based on proportional distribution is briefly described; when the internal temperature sensor of the solid-state drive detects that the temperature has risen to 70°C: 1. Temperature compensation is activated. The channel processor reads the β temperature drift compensation coefficient (e.g., 0.002 / ℃) and corrects the programming base value to 1500μs×(1+0.002×45)=1635μs. The suspension interval is automatically increased accordingly to avoid programming failure due to excessive suspension at high temperatures.

[0102] 2. Markov prediction intervenes. At this time, the host suddenly experiences a large number of 4K random reads, detecting a shortening arrival interval, and the state transition matrix converges towards a denser state. Before the current programming operation reaches the suspension checkpoint, the Markov predictor outputs a probability of 85% > the threshold of 70%, triggering active pre-suspension.

[0103] 3. Cost function decision: In the proactive pre-suspend process, the cost function calculator reads the urgency coefficient Q_read=8 (close to timeout), the current read and write bandwidth weights are low W_pe_weight=0.3, and the calculated S_Score is much greater than the dynamic threshold K, so suspension is allowed.

[0104] 4. Watchdog protection: If the current suspension fails to receive confirmation due to an internal NAND anomaly, a watchdog overflow triggers a first-level degradation (retry). If no response is received after 1ms, a second-level degradation is triggered, marking the die (logical unit) as abnormal, forcibly jumping to the recovery state, and initiating background data migration. Throughout the entire anomaly handling process, the host's read requests are responded to normally by other normal dies, and the overall system read latency QoS remains unaffected.

[0105] Through the collaborative operation of the two application scenarios described above, it can be seen that the adaptive NAND operation suspension scheduling method based on proportional distribution of the present invention can realize the end-to-end closed-loop adaptive scheduling from physical perception, intelligent prediction, cost decision-making to anomaly fallback.

[0106] To verify the effectiveness of the proportionally distributed adaptive NAND operation suspension scheduling method proposed in this invention, thorough simulation verification was conducted on a Verilog HDL-based SSD controller simulation platform. Multi-scenario tests were also performed using typical industry-standard TLC NAND Flash models (referencing parameters from Western Digital, Micron, Yangtze Memory, and other manufacturers). The simulation environment was: controller clock speed 800MHz, multi-channel multi-die parallel architecture, and FIO tools were used on the host side to generate mixed read / write loads. The main simulation parameters are as follows: NAND type: TLC NAND, programming time base value 1500μs, erase time base value 6000μs.

[0107] Maximum number of suspensions: dynamically calculated in adaptive mode (baseline 2~5 times).

[0108] Comparison with benchmark: Option A (existing technology): Uses fixed-cycle suspension inspection (inspection once every 500μs), with a fixed maximum number of suspensions of 3, no temperature / wear compensation, and no cost function gating.

[0109] Solution B (Solution of this invention): Enables proportional equal-division suspension interval, EWMA dynamic correction suspension interval, temperature correction compensation, cost function gating and erase compensation algorithm.

[0110] Test load: 70% sequential write and 30% random read (mixed load); extreme scenario is continuous burst of 4K random reads (read-intensive).

[0111] The key performance indicators are compared in Table 2, showing the test results for read latency quality of service (QoS) and write operation fairness (unit: µs).

[0112] Table 2. Results of Read Latency Quality of Service (QoS) and Write Operation Fairness Tests

[0113] The results show that, under bursty read-intensive scenarios, the P99 read latency (320μs) of the present invention is reduced by about 82.7% compared with the prior art (1850μs), and the maximum read latency is strictly controlled within 750μs (less than 2 suspend intervals). The read latency is improved, which proves the deterministic control capability of the proportionally evenly distributed window on the tail latency.

[0114] Existing technologies, lacking dynamic gating, frequently suspend during burst reads, leading to programming / erase completion times increasing by up to 210%, which easily triggers write timeouts. This invention achieves write operation fairness through cost function gating and double-layer read counting, controlling the P / E completion time extension rate to within 22%, effectively preventing P / E starvation.

[0115] Temperature correction compensation verification: The tests were conducted at low temperature (-20°C), normal temperature (25°C), and high temperature (85°C). The temperature drift compensation coefficient β = 0.002 / °C was set in the NAND characteristic simulator (i.e., programming time is shortened at high temperature and lengthened at low temperature). Table 3 below compares the effectiveness of suspend scheduling at different temperatures.

[0116] Table 3 Comparison of suspension scheduling effectiveness at different temperatures

[0117] Results analysis: At room temperature, the hanging interval deviation rate of both schemes was 0% at 25℃, indicating comparable performance and verifying the correctness of the reference configuration.

[0118] In low-temperature scenarios (-20°C), the physical programming time increased from 1500μs to 1635μs. Solution A rigidly adhered to a 375μs interval, resulting in an actual suspension interval smaller than the ideal value (408.75μs), leading to overly frequent suspension checks. This caused programming operations to be repeatedly suspended before fully recovering, causing the failure rate to soar to 8.5%. Solution B uses a temperature correction compensation formula: T_BUSY_BASE_COMP=T_BUSY_BASE×(1+β×(25℃-TEMP_curr)) =1500×(1+0.002×(45))≈1635

[0119] The new baseline value of 1635 was calculated in real time, and the suspension interval was dynamically corrected to 408.75μs, resulting in a sharp drop in the failure rate to 0.2%.

[0120] In high-temperature scenarios (85°C), the physical programming time is reduced to 1320μs, and the ideal suspension interval should be 330μs. Solution A still uses 375μs, resulting in an actual suspension interval greater than the ideal value, causing delayed responses to read requests, with read latency P99 exceeding 1ms and severely degrading service quality. Solution B dynamically adjusts the suspension interval to 330μs, ensuring that read requests are always inserted promptly at the next window boundary, and keeping read P99 stably below 200μs, verifying the robustness of the full-temperature-range adaptive solution of this invention.

[0121] Adaptive maximum suspension count (based on EWMA) aging tracking test: The physical characteristic of NAND flash memory that programming time gradually increases with the number of erase / write (P / E) cycles was simulated (the setting was increased from an initial 1500 μs to a final 1800 μs). The changing trends of the adaptive maximum suspension count and the actual number of read insertions in this invention are recorded in Table 4.

[0122] Table 4. Trends in Adaptive Maximum Suspension Count and Actual Read Insertion Count

[0123] The results analysis showed that as the NAND flash memory ages, this invention predicts the correction interval through EWMA and dynamically calculates the maximum number of hangs (gradually decreasing from 3 to 1). This "adaptive degradation" strategy ensures that read operations still enjoy a uniform insertion window, while avoiding permanent failure of P / E operations due to excessively long P / E physical times and too many hangs, significantly extending the performance of the solid-state drive at the end of its lifespan.

[0124] Comparison of erase operation compensation algorithms: Table 5 shows the comparison of the completion of the erase operation in a continuous suspension scenario. The erase base value was set to 6ms, and a maximum of 2 suspensions were allowed.

[0125] Table 5 Comparison of erase operation completion in continuous suspension scenarios

[0126] Results Analysis: This invention dynamically adds compensation busy time based on the number of suspensions in the Resume response processing, making the total completion time of the erase operation more accurate, reducing the erase failure rate from 5.2% to 0.1%, while ensuring a high response rate for read requests.

[0127] Based on the above experimental data, the adaptive NAND operation suspension scheduling method and device based on proportional distribution proposed in this invention significantly outperforms existing fixed-interval suspension schemes in all key indicators. Read latency QoS determinism is improved by more than 80% (maximum read latency is reduced from milliseconds to microseconds); P / E starvation is prevented (under extreme read loads, P / E completion time extension is reduced from 210% to 22%); strong environmental adaptability (suspend failure rate <0.3% and no read latency exceeding limits in high / low temperature / aging scenarios); and erase operation reliability is improved (erase failure rate reduced from 5.2% to 0.1%).

[0128] Although the steps in the above embodiments are described in the above order, those skilled in the art will understand that in order to achieve the effect of this embodiment, different steps do not need to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple variations are all within the protection scope of this invention.

[0129] Those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of the invention and form different embodiments. For example, in the claims of this invention, any of the claimed embodiments can be used in any combination.

[0130] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, the word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed PC.

[0131] The technical solution of the present invention has been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it should be noted that the parts not covered in this invention are the same as or can be implemented using existing technology. It will be readily understood by those skilled in the art that the scope of protection of this invention is obviously not limited to these specific embodiments. Without departing from the principles of this invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions resulting from these changes or substitutions will all fall within the scope of protection of this invention.

Claims

1. An adaptive NAND operation suspension scheduling method based on proportional equal distribution, characterized in that, Includes the following: Divide the total busy time of programming or erasing operations into multiple suspension intervals proportionally, and set a suspension checkpoint at the end of each suspension interval. Based on the real-time physical busy time of the logic unit, the maximum number of suspensions allowed for the current programming or erasing operation is dynamically calculated and used as a constant upper limit for the number of suspensions during the current operation. For the erase operation, the busy time compensation is dynamically added based on the number of suspensions after each recovery. For the busy time drift caused by wear, the suspension interval is dynamically corrected based on EWMA. The prediction probability is obtained based on the Markov predictor. When the prediction probability is greater than the preset threshold, a pre-suspend trigger signal is actively issued. At each suspension checkpoint, a suspension allowance score is calculated based on a cost function, and suspension is allowed only if the suspension allowance score exceeds a dynamic threshold. Introduce a temperature drift compensation coefficient to correct the busy time base value of programming or erasure operations based on real-time temperature; The watchdog timer monitors the execution timeout of suspended commands and implements a tiered degradation strategy based on the severity of the timeout.

2. The adaptive NAND operation suspension scheduling method based on proportional equal distribution according to claim 1, characterized in that, The total busy time of programming or erasing operations is divided proportionally into multiple suspension intervals, as follows: Obtain the total busy time base value T_BUSY_BASE_COMP after temperature and wear compensation; Get the maximum number of suspensions allowed for the current operation, MAX_SSPD_CNT; The suspension interval T_SSPD_INTRVL is calculated using the following formula: T_SSPD_INTRVL=T_BUSY_BASE_COMP / (MAX_SSPD_CNT+1); The total busy time is divided into (MAX_SSPD_CNT+1) equal parts on the time axis. The length of each part is the suspension interval, and the end point of each suspension interval is set as the suspension check point. The suspension check window is the width of the interval around the suspension check point. The suspension check window is equal to the suspension interval in value. Suspension is allowed only within the suspension check window.

3. The adaptive NAND operation suspension scheduling method based on proportional equal distribution according to claim 1, characterized in that, The dynamic calculation of the maximum allowed number of suspensions for the current programming or erasure operation is performed in the following manner: Read the real-time physical busy clock cycle count value T_BUSY_ACTUAL of the current logic unit; Read the currently active suspension interval T_SSPD_INTRVL_CURRENT; The maximum number of suspensions, ADAPTIVE_MAX_CNT, is calculated using the following formula: ADAPTIVE_MAX_CNT=(T_BUSY_ACTUAL / T_SSPD_INTRVL_CURRENT)-1; If ADAPTIVE_MAX_CNT > 0, then the maximum number of times the current operation can be suspended is MAX_SSPD_CNT = ADAPTIVE_MAX_CNT; if ADAPTIVE_MAX_CNT ≤ 0, then suspension is disabled and MAX_SSPD_CNT = 0. The maximum number of suspensions is calculated once when the current programming or erasure command is initiated, and serves as a constant upper limit during the operation.

4. The adaptive NAND operation suspension scheduling method based on proportional equal distribution according to claim 1, characterized in that, The dynamic addition of busy time compensation for the number of suspensions is implemented in the following manner: Busy time compensation is enabled only when the operation type is erase; Let cur_suspend_count be the cumulative number of suspensions that have occurred in the current operation; If cur_suspend_count equals the maximum number of suspensions MAX_SSPD_CNT, and the logic unit is still busy after resumption, then: Temporarily increment the maximum number of suspensions MAX_SSPD_CNT by 1, allowing one more suspension; The compensation time is equal to the currently effective suspension interval T_SSPD_INTRVL_CURRENT; Update the total busy time T_BUSY_TOTAL using the following formula: T_BUSY_TOTAL=T_BUSY_BASE_COMP+(cur_suspend_count×T_SSPD_INTRVL_CURRENT)+T_WAIT_RESUME; Where T_BUSY_BASE_COMP represents the busy time base value after temperature and wear compensation, and T_WAIT_RESUME is the hardware firmware interaction overhead time.

5. The adaptive NAND operation suspension scheduling method based on proportional equal distribution according to claim 1, characterized in that, The EWMA-based dynamic correction of the suspension interval includes: After each recovery operation is completed, the read logic unit returns the actual remaining busy time T_REM before it becomes idle; Get the currently used suspension interval T_SSPD_INTRVL_OLD and the remaining suspension count; The suspension interval T_SSPD_INTRVL_NEW is dynamically adjusted using the following formula: T_SSPD_INTRVL_NEW = α × T_SSPD_INTRVL_OLD + (1-α) × (T_REM / (remaining number of suspensions + 1)); Where T_SSPD_INTRVL_NEW is the updated suspension interval, and α is the smoothing factor; Write T_SSPD_INTRVL_NEW to the proportional equal timer, update the proportional equal timer register, and determine whether the recovery operation is complete. If yes, return; otherwise, continue to execute the suspended checkpoint trigger.

6. The adaptive NAND operation suspension scheduling method based on proportional equal distribution according to claim 1, characterized in that, The step of obtaining the prediction probability based on a Markov predictor, and actively issuing a pre-suspend trigger signal when the prediction probability is greater than a preset threshold, includes: If the interval between the two most recent read request suspensions is less than a preset threshold, then the suspension interval is marked as a dense state; otherwise, it is marked as a sparse state. Update the state transition count table for each new read request; The predicted probability P_ij of transitioning from state i to state j is expressed as: P_ij=cnt_ij / (cnt_iD+cnt_iS), Where, cnt_ij is the actual number of times the transition from state i to state j occurs, and cnt_iD and cnt_iS represent the total number of transitions from the current state i to the dense state and the sparse state, respectively. When the current programming or erasure operation is in a non-suspended state and has not yet reached the suspension checkpoint, the average dense or average sparse duration is estimated starting from the current state. Based on the current state and the transition matrix, the predicted probability of entering the dense state within a predetermined time period in the future is calculated. If the predicted probability is greater than the preset threshold, a pre-suspend signal is triggered, and the process jumps to the suspended state. After each read response is completed, update the history arrival interval buffer and state transition count.

7. The adaptive NAND operation suspension scheduling method based on proportional equal distribution according to claim 1, characterized in that, The suspension allowance score S_Score is calculated based on the cost function using the following formula: S_Score=[Q_read(urgency)×W_read_weight] / [Q_pe(progress)×W_pe_weight+ε]; Where Q_read(urgency) is the urgency coefficient calculated based on the maximum wait timeout of read requests in the current pending queue; W_read_weight is the current host read bandwidth weight; Q_pe(progress) is the reciprocal of the time elapsed for the current programming or erasing operation; W_pe_weight is the current host write bandwidth weight; and ε is a constant. The dynamic threshold K is dynamically adjusted according to the write amplification factor, and the gating decision is as follows: Suspension is only allowed if S_Score > K.

8. The adaptive NAND operation suspension scheduling method based on proportional equal distribution according to claim 1, characterized in that, The temperature drift compensation coefficient is introduced to correct the busy time base value of the programming or erasure operation based on the real-time temperature, as follows: Read the real-time temperature TEMP_curr output from the SSD's onboard temperature sensor; Obtain the busy time base value T_BUSY_BASE and the temperature drift compensation coefficient β before compensation; The compensated busy time base value T_BUSY_BASE_COMP is calculated using the following formula: T_BUSY_BASE_COMP=T_BUSY_BASE×(1+β×(25℃-TEMP_curr)).

9. The adaptive NAND operation suspension scheduling method based on proportional equal distribution according to claim 1, characterized in that, The method of monitoring the execution timeout of suspended commands using a watchdog timer and implementing a tiered degradation strategy based on the severity of the timeout is as follows: Each time a suspend command is issued, the watchdog loads the preset timeout value and starts a countdown; If a pending response is received before the timeout value, the watchdog timer is reset to zero; otherwise, a timeout interrupt is triggered. The tiered downgrade strategy includes: Level 1 downgrade: If the suspend command times out without confirmation, immediately resend the suspend command and shorten the suspend interval. Level 2 degradation: If the cumulative retries fail after reaching a preset number of attempts, the suspension operation on the logical unit is abandoned, the physical address of the logical unit is filled into the exception block table, and background data migration is triggered after the current programming or erasure operation is completed. Level 3 degradation means that when the status query command times out without response, the channel link layer of the logical unit is directly reset and the connection is re-established. The watchdog timeout automatically records the retry count. The first timeout triggers Level 1 degradation. If the timeout occurs again after Level 1 degradation, the retry count is incremented. When the retry count reaches a preset number, Level 2 degradation is triggered. If the timeout occurs during the status query phase, Level 3 degradation is triggered directly.

10. A proportionally-based adaptive NAND operation suspension scheduling device, used to execute the proportionally-based adaptive NAND operation suspension scheduling method as described in any one of claims 1-9, wherein the device is integrated into a suspension scheduling hardware engine in the channel processor inside the SSD controller, characterized in that, The device includes: A proportional timer, counting at the main clock cycle, is used to generate evenly distributed suspend checkpoints; An 18-state finite state machine is used for flow control, including suspending, reading, resuming, and querying states. The adaptive control logic module includes an EWMA predictor, an adaptive maximum number of times calculation unit, and a temperature compensation unit, which performs dynamic correction of the suspension interval, calculation of the maximum number of suspensions, and temperature drift compensation of the busy time base value. The Markov predictor has a built-in read arrival density prediction module. It predicts the arrival density of read requests and compares the obtained prediction probability with a preset threshold to trigger suspension in advance. Cost function calculator, used to calculate the allowed suspension score; Watchdog timer and tiered degradation controller are used for independent timeout monitoring and execution of tiered degradation strategies; Registers store basic parameter configurations for different NAND manufacturers or generations.

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