A multi-path synchronous low-delay I2S and PCIe high-speed audio data interaction architecture and implementation method

Abstract

The application discloses a multi-path synchronous low-delay I2S and PCIe high-speed audio data interaction architecture and an implementation method, and belongs to the technical field of audio data interaction. The interaction architecture comprises at least one I2S collection / sending IP core, an audio Codec channel group, a unified clock synchronization module, an AXI4 interconnection module, a PCIe DMA module and a host side processing module. The implementation method comprises the following steps: generating or distributing a shared clock, accessing the multi-path audio Codec channel group, converting in the I2S collection / sending IP core, frame synchronization alignment, FIFO buffering, AXI4 address mapping, XDMA C2H uploading, XDMA H2C issuing, host side processing and multi-IP core interrupt aggregation and reporting. The application can improve multi-channel audio synchronization, reduce end-to-end transmission delay, improve system bandwidth, expand capacity and host side management efficiency.

Description

Technical Field

[0001] This invention belongs to the field of audio data interaction technology, specifically relating to a multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture and implementation method. Background Technology

[0002] The I2S interface is a commonly used serial audio interface in digital audio systems. It typically includes a shared bit clock (BCLK), a shared left and right channel clock (LRCLK), a serial data line (SDATA), and an optional shared master clock (MCLK). In single-channel or low-channel scenarios, traditional I2S controllers can complete basic acquisition and playback. However, in scenarios such as multi-member airborne calls, professional recording and broadcasting, array microphones, smart cockpit voice front-ends, conference recording, and real-time voice algorithm processing, the system needs to simultaneously access multiple audio codecs and requires consistency in sampling frame boundaries, playback output times, channel order, and host-side processing latency among the audio channels.

[0003] In existing technologies, multi-channel I2S audio access typically suffers from the following problems: First, if multiple audio codecs are driven by different control links or independent clocks, sampling phase deviation, channel misalignment, cross-channel time drift, and synchronization playback errors are likely to occur. Second, if multiple I2S controllers are simply stacked repeatedly, it will increase the consumption of FPGA logic resources, on-chip interconnect resources, and register management resources. Third, multi-channel high-sampling-rate audio data needs to be continuously transferred between the FPGA and the host, and ordinary low-speed interfaces or non-unified buffer management methods cannot balance bandwidth, real-time performance, and jitter resistance. Fourth, when multiple I2S acquisition / transmission IP cores are deployed in the system, status signals and interrupt events are scattered, and the host-side software needs to manage multiple event sources, increasing the processing complexity of drivers and user-space applications.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture and implementation method.

[0006] To achieve the above objectives, the present invention provides the following technical solution: The implementation method of this multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture specifically includes the following steps: S1, the FPGA side generates or distributes shared LRCLK, shared BCLK and optional shared MCLK through a unified clock synchronization module; S2, connect the multiple I2S audio codec channel groups to the same I2S acquisition / transmission IP core, and enable the multiple audio codec channel groups to perform synchronous acquisition or synchronous playback based on a shared clock (a shared source LRCLK, a shared source BCLK, and an optional shared source MCLK generated or distributed by a unified clock synchronization module); S3, the I2S acquisition / transmission IP core performs serial-to-parallel conversion, frame synchronization detection, channel alignment, channel identification, and FIFO buffering on the I2S format SDATA output by each audio codec channel group; S4 maps the control register, status register, acquisition FIFO and transmission FIFO of the I2S acquisition / transmission IP core to the FPGA side address space through the AXI4 interface unit; S5, the PCIe DMA module moves the collected data to the host-side memory through the C2H channel based on AXI4 read / write transactions; S6, the PCIe DMA module transfers the data to be played from the host side to the FPGA side through the H2C channel, and writes it into the transmit FIFO of the target I2S acquisition / transmission IP core through the AXI4 interconnect module; S7, the host-side processing module performs synchronous recording, synchronous playback, encoding / decoding, voice algorithm, or data forwarding based on the I2S acquisition / transmission IP core number, channel number, audio channel identifier, and frame count.

[0007] Furthermore, when multiple I2S acquisition / transmission IP cores are deployed in parallel, the implementation method further includes: S8, an interrupt aggregation module is connected between the host-side processing module and the I2S acquisition / transmission IP cores, and the interrupt aggregation module uniformly aggregates the status and interrupt events of each I2S acquisition / transmission IP core and centrally reports them to the host-side processing module.

[0008] Furthermore, the implementation method need not be strictly executed in a linear order; the acquisition and playback links can be executed in parallel or independently.

[0009] Specifically, in the upload direction of the acquisition (e.g., S3 to S5 to S7), each audio codec channel group outputs I2S format SDATA under the constraints of shared source LRCLK and shared source BCLK; the I2S acquisition / transmission IP core performs serial-to-parallel conversion, frame boundary identification, and channel alignment on each SDATA, and writes multiple samples within the same sampling frame into the acquisition FIFO in a preset order; after the acquisition FIFO reaches the preset level, the number of complete frames, or the timed trigger condition, the AXI4 interface unit provides the acquired data to the AXI4 interconnect module according to the preset address mapping; the PCIe DMA module moves data from the FPGA-side DMA buffer or the mapped data area of ​​the I2S acquisition / transmission IP core to the host-side memory through the C2H channel based on AXI4 read / write transactions; after the host-side processing module reads the corresponding buffer, it restores the channel affiliation and time order of the multiple audio data according to the I2S acquisition / transmission IP core number, channel number, channel identifier, and frame count.

[0010] Specifically, in the playback direction (e.g., S7 to S6 to S3), the host-side processing module writes the multi-channel audio data to be played into the host-side transmission buffer; the PCIe DMA module moves the data to the corresponding address space on the FPGA side via the H2C channel; the AXI4 interconnect module writes the data into the transmission data area or transmission FIFO of the target I2S acquisition / transmission IP core according to the address mapping; the I2S acquisition / transmission IP core allocates the data to the corresponding output channel according to the channel number, channel identifier, and frame count, and performs parallel-to-serial conversion under the shared source LRCLK and shared source BCLK drivers, outputting I2S format SDATA to the corresponding audio codec channel group, thereby realizing multi-channel synchronous playback or low-latency feedback.

[0011] Specifically, the FIFO, AXI4, and PCIe DMA constitute the low-latency transmission link of this invention. The FIFO buffer is used to isolate the I2S clock domain from the AXI4 / PCIe clock domain, absorb short-term rate differences, and trigger DMA transfers through a water level threshold. The AXI4 interface unit is used to map the data buffer, control register, and status register of the I2S acquisition / transmission IP core to a unified address space, facilitating access by DMA and host-side software. The PCIe DMA module is used to perform high-speed C2H and H2C transfers between host memory and the FPGA-side address space. By setting the FIFO depth, water level threshold, AXI4 burst length, DMA buffer size, and host-side ring buffer length, a configuration balance can be achieved between low-latency calls and high-throughput recording.

[0012] Furthermore, this invention also provides an interactive architecture for implementing some or all of the above-described methods. This architecture includes at least one I2S acquisition / transmission IP core for synchronous access and output of multiple I2S audio data streams, an audio codec channel group connected to the I2S acquisition / transmission IP core, a unified clock synchronization module, an AXI4 interconnect module, a PCIe DMA module connected to the AXI4 interconnect module, and a host-side processing module that interacts with the PCIe DMA module. The host-side processing module interacts with the PCIe DMA module via a PCIe bus, driver, DMA buffer, or device node. The I2S acquisition / transmission IP core, unified clock synchronization module, AXI4 interconnect module, and PCIe DMA module are all configured within an FPGA.

[0013] Specifically, the audio codec channel group (audio codec channel group) is a combination of a set of physical channels (left and right channels) inside the codec chip (audio codec chip).

[0014] Furthermore, the unified clock synchronization module is used to provide a common clock to the audio codec channel group and / or the I2S acquisition / transmission IP core.

[0015] Specifically, the same-source clock includes a shared same-source LRCLK and a shared same-source BCLK. The shared same-source LRCLK is used to define the left and right channels or sampling frame boundaries, and the shared same-source BCLK is used to define the I2S serial bit transmission clock.

[0016] Furthermore, the same-source clock may optionally include a shared same-source MCLK, which is used to provide a sampling reference to the codec.

[0017] Specifically, through a unified clock synchronization module, multiple audio codec channels connected to the same I2S acquisition / transmission IP core can operate under the same frame boundary and bit clock. When multiple I2S acquisition / transmission IP cores are deployed in parallel, each I2S acquisition / transmission IP core can also generate multiple sets of I2S clocks with consistent phase or calibrable based on the same reference clock, thereby ensuring that the expanded multi-channel audio has a consistent synchronization reference.

[0018] Furthermore, the I2S acquisition / transmission IP core includes: The I2S receiver unit is used to convert multiple SDATA serial data into parallel audio samples. The I2S transmitting unit is used to convert the parallel audio samples into a serial data stream conforming to the I2S bus protocol and transmit it. The frame synchronization detection unit is used to identify the sampling frame boundary based on the shared source LRCLK; The channel alignment unit is used to align multiple samples within the same sampling period according to channel order. The channel identification unit is used to write the I2S acquisition / transmission IP core number, channel number, audio channel identifier, frame count, or time stamp into the sample data; Collect FIFO to cache data to be uploaded; Send a FIFO to cache the data to be played sent by the host; The AXI4 interface unit is used to connect the I2S acquisition / transmission IP core to the data path on the FPGA. And the status register.

[0019] Specifically, a single I2S acquisition / transmission IP core can be externally connected to 8 audio codecs or audio codec channel groups that support the I2S protocol.

[0020] Furthermore, when there are multiple I2S acquisition / transmission IP cores, these IP cores are deployed in parallel and connected to the AXI4 interconnect module via AXI4 interface units, sharing the same PCIe DMA module. These multiple I2S acquisition / transmission IP cores can share the same XDMA data channel or connect to different XDMA data channels. The total number of channel groups in the audio codec channel group can linearly expand with the number of I2S acquisition / transmission IP cores. The data areas of multiple I2S acquisition / transmission IP cores can be mapped to different AXI4 address segments. The host-side processing module can distinguish data from different I2S acquisition / transmission IP cores based on the address segment, I2S acquisition / transmission IP core number, or data frame header.

[0021] Furthermore, the interactive architecture also includes an interrupt aggregation module, which is configured within the FPGA. The interrupt aggregation module is used to uniformly collect the status and events of each I2S acquisition / transmission IP core in a multi-I2S acquisition / transmission IP core expansion scenario, and report them to the host-side processing module through interrupt signals and event status registers.

[0022] Specifically, the states and events include the acquisition FIFO reaching its water level, the transmission FIFO being underloaded, the acquisition FIFO overflowing, frame completion, frame count anomaly, clock anomaly, DMA completion, DMA error, and link state changes. The interrupt aggregation module masks, latches, prioritizes, and uniformly reports multiple event sources, and provides the host-side processing module with an event status register, an event clearing register, and an event source number register. Upon receiving the unified event notification, the host-side processing module can read the specific I2S acquisition / transmission IP core, the specific channel, and the specific exception type through the AXI4 mapping register, thereby reducing the complexity of software interrupt management in scenarios with multiple I2S acquisition / transmission IP cores.

[0023] Furthermore, the AXI4 interface unit organizes the control area, status area, data acquisition area, and data transmission area using an address mapping method, and supports burst read and write to adapt to the PCIe DMA module's access to the FPGA-side storage or peripheral address space.

[0024] Specifically, the PCIe DMA module acts as the AXI4 master device, and the I2S acquisition / transmission IP core acts as the AXI4 slave device. The I2S acquisition / transmission IP core receives access requests from the PCIe DMA module through the AXI4 slave interface of the AXI4 interface unit. In the address mapping space of the AXI4 slave interface, the control area and status area are used by the host or upper-level control logic to access the control register, status register, FIFO level register, channel configuration register, and interrupt mask register of the I2S acquisition / transmission IP core. The acquisition data area and transmission data area are used by the PCIe DMA module, which acts as the AXI4 master device, to directly read audio data in the acquisition FIFO through burst read / write, or to directly write data to be played to the transmission FIFO.

[0025] Optionally, the AXI4 interface unit further includes an AXI4 main interface, which is used to write audio data in the acquisition FIFO into the on-chip DMA buffer, or to read data to be played from the on-chip DMA buffer and write it into the transmission FIFO, so as to realize a local data transfer path.

[0026] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects: 1. This invention enables multiple audio codec channels under the same I2S acquisition / transmission IP core to have unified sampling frame boundaries and bit transmission beats by sharing the same LRCLK, the same BCLK, and the optional same MCLK; multiple I2S acquisition / transmission IP cores can be extended based on the same reference clock, thereby reducing the risk of cross-channel phase deviation and playback asynchrony.

[0027] 2. This invention employs a single I2S acquisition / transmission IP core capable of accessing eight audio codec channels, reducing redundant control links and lowering FPGA logic resource consumption and system routing complexity. Simultaneously, the I2S acquisition / transmission IP core utilizes an AXI4 interface, mapping control, status, acquisition data, and transmission data to a unified address space, facilitating interconnection with AXI4, PCIe DMA, register management, and host-side software access.

[0028] 3. This invention forms a low-latency link through FIFO level triggering, AXI4 burst read / write and PCIe DMA bidirectional transport, which can reduce the intermediate waiting and software intervention times of multi-channel audio from the I2S side to the host side and from the host side to the I2S side, thereby reducing end-to-end latency.

[0029] 4. This invention uses a PCIe DMA module to provide a high-speed C2H / H2C data channel, and the AXI4 interconnect supports multiple I2S acquisition / transmission IP core address mapping and burst access, which can adapt to multi-channel, high sampling rate, and high bit width audio continuous transmission, thereby improving the system's throughput.

[0030] 5. This invention allows multiple I2S acquisition / transmission IP cores to be connected in parallel to the AXI4 interconnect module. Each I2S acquisition / transmission IP core processes multiple audio codec channels, and the total number of channels can be expanded according to project needs, making it suitable for multiplexing in multi-channel audio platforms from small to large scale. The interrupt aggregation module uniformly reports the events and statuses of multiple I2S acquisition / transmission IP cores, and the host-side processing module can locate the event source through the event register, reducing the burden of scattered interrupt handling and software polling.

[0031] 6. This invention can be used in FPGA audio acquisition and processing boards, PCIe audio interface devices, airborne multi-member communication systems, professional recording and broadcasting systems, array pickup systems, intelligent cockpit voice front-ends, industrial acoustic acquisition terminals, and AI audio processing acceleration devices. Attached Figure Description

[0032] The accompanying drawings are incorporated in and form part of this specification, and together with the description serve to explain the principles of the invention.

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0034] Figure 1 This is a block diagram illustrating the principle of the multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture of the present invention. Figure 2 This is a flowchart of the method for implementing multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction according to the present invention; Figure 3 This is a schematic diagram of the low-latency bidirectional data link constructed by FIFO, AXI4 and PCIe DMA of the present invention. Detailed Implementation

[0035] Exemplary embodiments will now be described in detail. The embodiments described below are not representative of all embodiments consistent with this invention. Rather, they are merely examples consistent with some aspects of the invention as detailed in the appended claims.

[0036] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0037] Example 1 This embodiment provides an implementation method for a multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture, specifically including the following steps: S1, the FPGA side generates or distributes shared LRCLK and shared BCLK through a unified clock synchronization module; S2, connect multiple I2S audio codec channel groups to the same I2S acquisition / transmission IP core, and enable the multiple audio codec channel groups to perform synchronous acquisition or synchronous playback based on a shared clock; S3, the I2S acquisition / transmission IP core performs serial-to-parallel conversion, frame synchronization detection, channel alignment, channel identification, and FIFO buffering on the I2S format SDATA output by each audio codec channel group; S4 maps the control register, status register, acquisition FIFO and transmission FIFO of the I2S acquisition / transmission IP core to the FPGA side address space through the AXI4 interface unit; S5, the PCIe DMA module moves the collected data to the host-side memory through the C2H channel based on AXI4 read / write transactions; S6, the PCIe DMA module transfers the data to be played from the host side to the FPGA side through the H2C channel, and writes it into the transmit FIFO of the target I2S acquisition / transmission IP core through the AXI4 interconnect module; S7, the host-side processing module performs synchronous recording, synchronous playback, encoding / decoding, voice algorithm, or data forwarding based on the I2S acquisition / transmission IP core number, channel number, audio channel identifier, and frame count.

[0038] Furthermore, the implementation method need not be strictly executed in a linear order; the acquisition and playback links can be executed in parallel or independently.

[0039] like Figure 3 As shown, in the acquisition / upload link, audio data is written to the acquisition FIFO by the I2S acquisition / transmit IP core, and then transported to the host side via the AXI4 mapped data area and the C2H channel of PCIe DMA. In the playback / download link, data in the host-side transmit buffer is written to the FPGA-side AXI4 transmit data area via the H2C channel of PCIe DMA, then enters the transmit FIFO and is synchronously output by the I2S acquisition / transmit IP core. Low-latency parameter configurations are located between the uplink and downlink to uniformly explain the impact of FIFO water level threshold, AXI4 burst length, XDMA buffer, host ring buffer, and transport cycle on bidirectional link latency.

[0040] This embodiment is based on synchronous playback distribution using the AXI4 interface unit. The host-side processing module writes multiple channels of data to be played into the transmission buffer. The data frame includes the I2S acquisition / transmission IP core number, channel number, channel identifier, frame count, and audio sample. The PCIe DMA module moves the data to the FPGA-side AXI4 address space via the H2C channel. The AXI4 interconnect writes the data into the transmission FIFO of the target I2S acquisition / transmission IP core according to the address segment. The I2S acquisition / transmission IP core reads data frame by frame from the transmission FIFO based on the shared LRCLK and BCLK, and outputs SDATA to the corresponding audio codec channel group through the parallel-to-serial conversion unit, so that the multiple playback data are output at a unified frame boundary.

[0041] The interactive architecture based on the above implementation method includes at least one I2S acquisition / transmission IP core for synchronous access and output of multiple I2S audio data streams, an audio codec channel group connected to the I2S acquisition / transmission IP core, a unified clock synchronization module, an AXI4 interconnect module, a PCIe DMA module connected to the AXI4 interconnect module, and a host-side processing module that interacts with the PCIe DMA module. The host-side processing module interacts with the PCIe DMA module via a PCIe bus, driver, DMA buffer, or device node. The I2S acquisition / transmission IP core is configured within an FPGA.

[0042] This embodiment utilizes a single I2S acquisition / transmission IP core with a shared clock for eight-channel synchronous acquisition. Specifically, the FPGA is connected to the host via a PCIe bus interface. The FPGA internally deploys an I2S acquisition / transmission IP core, a unified clock synchronization module, an AXI4 interconnect module, and a PCIe DMA module. The unified clock synchronization module provides a shared source LRCLK, a shared source BCLK, and an optional shared source MCLK to the eight audio codec channel groups. The eight audio codec channel groups output I2S format SDATA at the same frame boundary. The I2S acquisition / transmission IP core performs serial-to-parallel conversion on the eight SDATA channels and determines the sampling frame to which the sample belongs based on the LRCLK edge. Subsequently, the channel alignment unit arranges multiple samples within the same sampling frame according to channel number and writes the sample, channel number, and frame count into the acquisition FIFO.

[0043] When the acquisition FIFO reaches the preset level, the I2S acquisition / transmit IP core provides readable data to the mapped data area through the AXI4 interface unit, or writes data to the DMA buffer. The PCIe DMA module reads the acquired data from the FPGA-side AXI4 address space through the C2H channel and moves it to the host-side circular buffer. After reading the data, the host-side processing module restores the sampling order based on the frame count and distinguishes the source of different audio codec channel groups based on the channel number, realizing multi-channel synchronous recording or real-time algorithm processing.

[0044] Example 2 Based on Example 1, this example provides a method for implementing a multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture, applicable to cases with more than 8 audio codec channel groups, and specifically includes the following steps: S8, The host-side processing module is connected to the I2S acquisition / transmission IP core via an interrupt aggregation module. The interrupt aggregation module aggregates the status and interrupt events of each I2S acquisition / transmission IP core and reports them to the host-side processing module.

[0045] like Figure 2 As shown, the process method in this embodiment includes shared clock generation or distribution, multi-channel codec access, serial-to-parallel conversion and frame synchronization alignment within the I2S acquisition / transmission IP core, FIFO buffering, AXI4 address mapping, XDMA C2H upload, XDMAH2C download, host-side processing, and interrupt aggregation and reporting of multiple I2S acquisition / transmission IP cores. S8 is used for event monitoring and unified reporting, and does not indicate that the clock is regenerated after the interrupt aggregation is completed; in continuous sampling or playback scenarios, the system enters the next data cycle and continues to run.

[0046] Based on the interactive architecture described above, multiple I2S acquisition / transmission IP cores can be deployed within the FPGA. Each I2S acquisition / transmission IP core is connected to an AXI4 interconnect via an AXI4 interface unit and mapped to different address segments. For example, the first I2S acquisition / transmission IP core corresponds to the first acquisition data area and the first transmission data area, and the second I2S acquisition / transmission IP core corresponds to the second acquisition data area and the second transmission data area. The host-side processing module can distinguish different IP cores by the IP core number in the address segment or data frame. Each IP core shares the same reference clock or multiple sets of I2S clocks with consistent phase are generated by a unified clock synchronization module, ensuring that the expanded multi-channel audio still maintains a synchronization reference.

[0047] Furthermore, the interactive architecture also includes an interrupt aggregation module configured within the FPGA. Multiple I2S acquisition / transmission IP cores generate events such as FIFO level, frame completion, acquisition overflow, playback underload, clock error, DMA completion, and link error. The interrupt aggregation module latches, masks, and prioritizes these events, then outputs a unified interrupt or event notification to the host-side processing module. Upon receiving an event, the host-side processing module reads the event source number register, event type register, and event status register from the interrupt aggregation module to locate the specific I2S acquisition / transmission IP core, the specific channel, and the error type. After processing, the host-side processing module clears the corresponding status using the event clear register.

[0048] like Figure 1 As shown, multiple audio codec channel groups operate under shared MCLK, BCLK, and LRCLK provided by a unified clock synchronization module. The I2S acquisition / transmission IP core completes serial-to-parallel / parallel-to-serial conversion, frame synchronization alignment, and channel FIFO buffering. The I2S acquisition / transmission IP core is connected to the AXI4 interconnect module and DMA buffer management unit through the AXI4 interface unit. The PCIe DMA module realizes high-speed bidirectional data transfer between the FPGA and the host-side processing module through the C2H / H2C data channel. For systems with multiple I2S acquisition / transmission IP cores expanded in parallel, the interrupt aggregation module uniformly reports the events and statuses of each IP core.

[0049] Example 3 Building upon Embodiment 1 or 2, this embodiment provides an application of a multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture. This embodiment can be integrated into FPGA audio acquisition and processing boards, PCIe audio interface devices, airborne multi-member call and voice recording systems, professional recording and broadcasting equipment, array microphones, conference recording systems, smart cockpit voice front-ends, industrial acoustic acquisition terminals, and AI audio processing acceleration devices. The FPGA side is responsible for deterministic timing synchronization, I2S acquisition / playback, FIFO buffering, and AXI4 / XDMA data transfer, while the host side is responsible for recording, playback, encoding / decoding, voice enhancement, voice recognition, or business logic processing.

[0050] In summary, this invention provides a multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture. Compared to conventional architectures, this invention, through parameter configuration, can achieve low-latency and high-throughput data transmission. For real-time call scenarios, the acquisition FIFO level can be set to a lower threshold to reduce the DMA transfer cycle and shorten the host-side ring buffer length, thereby reducing end-to-end latency. For long-duration multi-channel recording scenarios, the FIFO depth, AXI4 burst length, and host-side buffer capacity can be appropriately increased to improve throughput efficiency and jitter resistance. The system can also detect frame loss based on frame count, detect overflow or underload based on the FIFO status field, and handle these issues through resynchronization, silence filling, or error alarms.

[0051] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention.

[0052] It should be understood that the present invention is not limited to the content already described above, and various modifications and changes can be made without departing from its scope. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for implementing a multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture, characterized in that, The implementation method specifically includes the following steps: S1, the FPGA side generates or distributes shared LRCLK and shared BCLK through a unified clock synchronization module; S2, connect multiple I2S audio codec channel groups to the same I2S acquisition / transmission IP core, and enable the multiple audio codec channel groups to perform synchronous acquisition or synchronous playback based on a shared clock; S3, the I2S acquisition / transmission IP core performs serial-to-parallel conversion, frame synchronization detection, channel alignment, channel identification, and FIFO buffering on the I2S format SDATA output by each audio codec channel group; S4 maps the control register, status register, acquisition FIFO and transmission FIFO of the I2S acquisition / transmission IP core to the FPGA side address space through the AXI4 interface unit; S5, the PCIe DMA module moves the collected data to the host-side memory through the C2H channel based on AXI4 read / write transactions; S6, the PCIe DMA module transfers the data to be played from the host side to the FPGA side through the H2C channel, and writes it into the transmit FIFO of the target I2S acquisition / transmission IP core through the AXI4 interconnect module; S7, the host-side processing module performs synchronous recording, synchronous playback, encoding / decoding, voice algorithm, or data forwarding based on the I2S acquisition / transmission IP core number, channel number, audio channel identifier, and frame count.

2. The implementation method of the multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture according to claim 1, characterized in that, When multiple I2S acquisition / transmission IP cores are deployed in parallel, the implementation method further includes: S8, The host-side processing module is connected to the I2S acquisition / transmission IP core via an interrupt aggregation module. The interrupt aggregation module aggregates the status and interrupt events of each I2S acquisition / transmission IP core and reports them to the host-side processing module.

3. The implementation method of the multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture according to claim 1, characterized in that, In the acquisition and upload direction, each audio codec channel group outputs I2S format SDATA under the constraints of shared source LRCLK and shared source BCLK; the I2S acquisition / transmission IP core performs serial-to-parallel conversion, frame boundary identification, and channel alignment on each SDATA, and writes multiple samples within the same sampling frame into the acquisition FIFO in a preset order; after the acquisition FIFO reaches the preset level, the number of complete frames, or the timed trigger condition, the AXI4 interface unit provides the acquired data to the AXI4 interconnect module according to the preset address mapping; the PCIe DMA module moves data from the FPGA-side DMA buffer or the mapped data area of ​​the I2S acquisition / transmission IP core to the host-side memory through the C2H channel based on AXI4 read / write transactions; after the host-side processing module reads the corresponding buffer, it restores the channel affiliation and time order of the multiple audio data according to the I2S acquisition / transmission IP core number, channel number, channel identifier, and frame count.

4. The implementation method of the multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture according to claim 1, characterized in that, In the playback direction, the host-side processing module writes the multi-channel audio data to be played into the host-side transmission buffer; the PCIe DMA module moves the data to the corresponding address space on the FPGA side through the H2C channel; the AXI4 interconnect module writes the data into the transmission data area or transmission FIFO of the target I2S acquisition / transmission IP core according to the address mapping; the I2S acquisition / transmission IP core allocates the data to the corresponding output channel according to the channel number, channel identifier and frame count, and performs parallel-to-serial conversion under the shared source LRCLK and shared source BCLK drivers, outputting I2S format SDATA to the corresponding audio codec channel group, thereby realizing multi-channel synchronous playback or low-latency feedback.

5. A multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture, used to execute the implementation method according to any one of claims 1 to 4, characterized in that, It includes at least one I2S acquisition / transmission IP core for synchronous access and synchronous output of multiple I2S audio data, an audio codec channel group connected to the I2S acquisition / transmission IP core, a unified clock synchronization module and an AXI4 interconnect module, a PCIe DMA module connected to the AXI4 interconnect module, and a host-side processing module that interacts with the PCIe DMA module. The host-side processing module interacts with the PCIe DMA module via the PCIe bus, driver, DMA buffer, or device node. The I2S acquisition / transmission IP core, unified clock synchronization module, AXI4 interconnect module, and PCIe DMA module are all configured within the FPGA.

6. The multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture according to claim 5, characterized in that, The unified clock synchronization module is used to provide a common clock to the audio codec channel group and / or the I2S acquisition / transmission IP core; The shared clock sources include a shared LRCLK and a shared BCLK. The shared LRCLK is used to define the boundaries of the left and right channels or sampling frames, and the shared BCLK is used to define the I2S serial bit transmission clock.

7. The multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture according to claim 6, characterized in that, The I2S acquisition / transmission IP core includes: The I2S receiver unit is used to convert multiple SDATA serial data into parallel audio samples. The I2S transmitting unit is used to convert the parallel audio samples into a serial data stream conforming to the I2S bus protocol and transmit it. The frame synchronization detection unit is used to identify the sampling frame boundary based on the shared source LRCLK; The channel alignment unit is used to align multiple samples within the same sampling period according to channel order. The channel identification unit is used to write the I2S acquisition / transmission IP core number, channel number, audio channel identifier, frame count, or time stamp into the sample data; Collect FIFO to cache data to be uploaded; Send a FIFO to cache the data to be played sent by the host; The AXI4 interface unit is used to connect the I2S acquisition / transmission IP core to the data path on the FPGA. And the status register.

8. The multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture according to claim 7, characterized in that, When there are multiple I2S acquisition / transmission IP cores, the multiple I2S acquisition / transmission IP cores are deployed in parallel and connected to the AXI4 interconnect module through the AXI4 interface unit respectively, and share the same PCIe DMA module.

9. The multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture according to claim 8, characterized in that, It also includes an interrupt aggregation module, which is configured within the FPGA. The interrupt aggregation module is used to uniformly collect the status and events of each I2S acquisition / transmission IP core in a multi-I2S acquisition / transmission IP core expansion scenario, and report to the host-side processing module through interrupt signals and event status registers. The states and events include the acquisition FIFO reaching the water level, the transmission FIFO underload, the acquisition FIFO overflowing, frame completion, frame count abnormality, clock abnormality, DMA completion, DMA error, and link state change.

10. The multi-channel synchronous low-latency I2S and PCIe high-speed audio data interaction architecture according to claim 7, characterized in that, The AXI4 interface unit uses an address mapping method to organize the control area, status area, data acquisition area, and data transmission area, and supports burst read and write to adapt to the PCIe DMA module's access to the FPGA-side storage or peripheral address space. In this configuration, the PCIe DMA module acts as the AXI4 master device, and the I2S acquisition / transmission IP core acts as the AXI4 slave device. The I2S acquisition / transmission IP core receives access requests from the PCIe DMA module through the AXI4 slave interface of the AXI4 interface unit. In the address mapping space of the AXI4 slave interface, the control area and status area are used by the host or upper-level control logic to access the control register, status register, FIFO level register, channel configuration register, and interrupt mask register of the I2S acquisition / transmission IP core. The acquisition data area and transmission data area are used by the PCIe DMA module, acting as the AXI4 master device, to directly read audio data from the acquisition FIFO through burst read / write, or to directly write data to be played to the transmission FIFO.

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