Division method based on dynamic scaling between partitions and single-cycle floating-point divider

Abstract

The embodiment of the application provides a division operation method based on partition interval dynamic scaling and a single-cycle floating-point divider, and belongs to the technical field of digital integrated circuit design. The scheme parallelly unpacks a dividend and a divisor, separates a sign bit, a mantissa bit and an exponent bit, parallelly calculates a quotient sign bit, extracts a highest bit of the mantissa of the divisor as a control signal to realize partition interval dynamic mantissa scaling, obtains an original mantissa result through polynomial shift multiplication and addition operation, then judges an original mantissa overflow level, obtains a normalized mantissa through mantissa shift normalization processing, and simultaneously generates an overflow state signal; based on the overflow state, shift compensation is implemented on an original exponent difference value to obtain a compensated exponent; finally, the quotient sign bit, the normalized mantissa and the compensated exponent are spliced to output a floating-point division result. The application relies on a partition interval dynamic scaling mechanism to suppress polynomial truncation error, adopts an absolute value shift multiplication and addition tree to reduce hardware area, and the overall channel adopts pure combinational logic to realize single-cycle floating-point division operation.

Description

Technical Field

[0001] This application relates to the field of digital integrated circuit design technology, and in particular to a division operation method based on interval dynamic scaling and a single-cycle floating-point divider. Background Technology

[0002] Floating-point division is one of the most expensive basic arithmetic operations in digital integrated circuit design. Traditional IEEE 754 floating-point dividers (such as those based on the SRT algorithm or the Newton-Raphson iterative method) heavily rely on sequential state machines for multi-cycle iterations, making it difficult to achieve continuous throughput in a single clock cycle. To achieve single-cycle output, existing technologies typically use polynomial approximation algorithms to transform division into multiplication and addition operations, such as Taylor series expansion. However, this method has a fatal theoretical flaw: when the range of the dividend is large, the truncation error of the polynomial amplifies sharply at the boundaries. To meet accuracy requirements, it is necessary to calculate extremely high-order polynomials or introduce a large error-compensated lookup table (LUT). This results in hardware area and critical path latency still failing to meet the needs of high-density parallel computing, such as edge AI inference.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to propose a division operation method based on interval dynamic scaling and a single-cycle floating-point divider, which can achieve complete signed half-precision floating-point (FP16) single-cycle throughput with extremely low silicon wafer area, effectively reducing computational latency and improving area energy efficiency ratio.

[0005] To achieve the above objectives, one aspect of this application proposes a single-cycle floating-point divider based on interval dynamic scaling. The single-cycle floating-point divider includes an input register, a sign bit XOR operation unit, an interval mantissa data selector, an exponent dynamic compensation unit, a mantissa calculation unit, an abnormal data selector, and a result output register. The input register is used to receive and store dividend and divisor data, and to separate the dividend and divisor data into sign bit, exponent bit and mantissa bit, and to transmit the sign bit to the sign bit XOR operation unit, the mantissa bit to the interval mantissa data selector, and the exponent bit to the exponent dynamic compensation unit. The sign bit XOR operation unit is used to calculate the sign bit of the quotient result based on the sign bit. The segmented mantissa data selection is used to dynamically extract the temporary mantissas of the dividend and divisor in segments, using the highest bit of the divisor's mantissa as the selection control signal. The mantissa calculation unit is used to calculate the polynomial coefficients and perform polynomial shift multiplication and addition operations in combination with the temporary mantissa to obtain the original mantissa calculation result; The exponent dynamic compensation unit is used to calculate the original exponent difference based on the exponent bits of the dividend and divisor, and to perform shift compensation on the original exponent difference based on the overflow state of the original mantissa calculation result to obtain the compensation exponent. The abnormal data selector is used to output the division operation result based on the sign bit of the quotient result, the calculation result of the original mantissa, and the compensation exponent, and output it to the outside via the result output register.

[0006] In some embodiments, the input register includes a dividend input register and a divisor input register, and the interval mantissa data selector includes a first interval mantissa data selector and a second interval mantissa data selector; The dividend input register is used to receive external floating-point dividend data and perform latching and signal separation. The dividend is dynamically selected by interval through the first interval mantissa data selector, and the temporary mantissa of the dividend is output to the mantissa calculation unit. The divisor input register is used to receive external floating-point divisor data and perform latching and signal separation. The divisor is dynamically selected by interval via the second interval mantissa data selector, and the temporary mantissa of the divisor is output to the mantissa calculation unit.

[0007] In some embodiments, the input register is equipped with a division-by-zero error detection mechanism. The mechanism performs joint verification on the mantissa and exponent bits of the dividend and divisor. If either the dividend or the divisor satisfies the zero value condition, the risk of division by zero is directly determined, and an error flag signal is output to the error data selector.

[0008] In some embodiments, the sign bit XOR operation unit obtains the sign of the quotient result based on the XOR operation between the sign bit of the dividend and the sign bit of the divisor.

[0009] In some embodiments, in the interval mantissa data selector, when the highest bit level of the divisor mantissa is 0, the original mantissa of the dividend is directly extracted as the temporary mantissa of the dividend, and the original mantissa of the divisor is used as the temporary mantissa of the divisor; when the highest bit level of the divisor mantissa is 1, a unified shift and scaling operation is performed on the original mantissa of the dividend and the original mantissa of the divisor respectively to obtain the scaled mantissa of the dividend and the scaled mantissa of the divisor, and the scaled mantissa of the dividend is extracted as the temporary mantissa of the dividend, and the scaled mantissa of the divisor is used as the temporary mantissa of the divisor.

[0010] In some embodiments, the mantissa calculation unit includes a β coefficient calculator, an absolute value shift multiply-accumulate tree, and a constant accumulator; The β coefficient calculator is used to calculate polynomial coefficients based on the temporary mantissa output by the interval mantissa data selector, and to generate higher-order terms of the temporary mantissa of the divisor. The absolute value shift multiply-add tree is used to generate higher-order terms based on the temporary mantissa of the divisor, and in combination with the polynomial coefficients, to perform polynomial shift multiply-add operations based on the absolute value shift multiply-add tree to obtain a polynomial approximation. The constant accumulator is used to superimpose the polynomial fitting constant term onto the polynomial approximation to obtain the original mantissa calculation result.

[0011] In some embodiments, the single-cycle floating-point divider further includes an overflow detection unit, which is used to determine the mantissa overflow level of the original mantissa calculation result according to the overflow determination status bit, perform shift normalization processing on the mantissa based on the mantissa overflow level to obtain a normalized mantissa and an overflow status signal, output the normalized mantissa to an abnormal data selector, and output the overflow status signal to an exponential dynamic compensation unit.

[0012] In some embodiments, the two most significant bits of the original mantissa calculation result are extracted as overflow determination status bits, the mantissa overflow level of the original mantissa calculation result is determined based on the overflow determination status bits, and the mantissa overflow level is converted into a standardized overflow status signal for output.

[0013] In some embodiments, the mantissa overflow level includes a positive overflow level, a no overflow level, and a low-bit under-sizing level; if it is a positive overflow level, the normalization flag is mapped to -1, and the mantissa is shifted one bit to the right; if it is a no overflow level, the normalization flag is mapped to 0, and the mantissa remains in its original position; if it is a low-bit under-sizing level, the normalization flag is mapped to 1, and the mantissa is shifted one bit to the left to make up the difference.

[0014] To achieve the above objectives, another aspect of this application proposes a division operation method based on interval dynamic scaling, the division operation method comprising: Based on the input register, the floating-point number is received as the dividend and divisor, and the dividend and divisor are unpacked in parallel to separate the sign bit, mantissa bit and exponent bit. The sign bit XOR operation unit calculates the sign bit of the quotient result based on the sign bits of the dividend and the divisor; The highest bit of the divisor's mantissa is extracted by the mantissa calculation unit as a selection control signal. The temporary mantissas of the dividend and divisor are dynamically extracted in intervals, and the original mantissa calculation result is obtained by polynomial shift multiplication and addition operations. The dual overflow detection unit determines the mantissa overflow level of the original mantissa calculation result based on the overflow determination status bit, and performs shift normalization processing on the mantissa according to the mantissa overflow level to obtain the normalized mantissa and overflow status signal. The exponent dynamic compensation unit calculates the original exponent difference based on the exponent bits of the dividend and divisor, and performs shift compensation on the original exponent difference based on the overflow state signal to obtain the compensated exponent. The abnormal data selector outputs the division result based on the sign bit of the quotient result, the normalized mantissa, and the compensation exponent, and outputs it to the outside via the result output register.

[0015] The embodiments of this application include at least the following beneficial effects: This application provides a division operation method based on interval dynamic scaling and a single-cycle floating-point divider. This scheme unpacks the dividend and divisor floating-point numbers in parallel, separating the sign bit, mantissa bit, and exponent bit, realizing data path splitting. This allows the sign operation, mantissa operation, and exponent operation to be performed in parallel, eliminating the timing loss caused by serial processing, and providing an architectural foundation for the entire division path to achieve single-cycle operation. The sign bit of the quotient result is calculated based on the sign bits of the dividend and divisor; the sign calculation is performed in parallel with the mantissa and exponent operation branches, without waiting for the mantissa operation result, and does not occupy critical timing paths. The sign logic only uses a simple XOR combination circuit, with minimal hardware overhead, and can output the quotient sign bit in advance for the final splicing stage.

[0016] By extracting the highest bit of the divisor's mantissa as a partitioning control signal, the dividend and the temporary mantissa of the divisor are dynamically scaled to constrain the input interval of the second-order polynomial. On the one hand, the dynamic scaling mechanism solves the problem of exponential error explosion that occurs in the traditional fixed-interval second-order Taylor approximation when the mantissa of the divisor approaches 2.0. The maximum truncation error across the entire domain can be constrained to about 2ULP by relying solely on shifting hardware overhead, significantly widening the high-precision calculation interval. On the other hand, the polynomial operation adopts an absolute value shift multiply-accumulate tree architecture, converting signed multiplication into unsigned shift accumulation operation, avoiding the hardware area expansion defect of traditional two's complement multipliers, reducing the circuit size while ensuring calculation accuracy, and obtaining the original mantissa calculation result.

[0017] Due to the positive error caused by polynomial truncation, the original mantissa calculation result will deviate from the floating-point standard specification range. This solution extracts the two highest bits of the original mantissa to generate an overflow judgment status bit, divides the mantissa overflow level into three categories, drives the mantissa dynamic shifter to perform self-healing normalization, and handles the three working conditions of positive overflow, normal range, and under-specification respectively; at the same time, an overflow status signal is generated and fed forward to effectively correct the mantissa out-of-bounds problem, and outputs a normalized mantissa that meets the floating-point standard format, ensuring that the mantissa falls within the standard range of [1.0, 2.0).

[0018] The mantissa shift operation changes the exponent of the value. An overflow status signal maps the shifted offset to an exponent compensation value. The original exponent difference is synchronously corrected with the compensation value; that is, a right shift of the mantissa decrements the exponent by 1, a left shift increments the exponent by 1, and no shift leaves the exponent unchanged. This achieves coordinated correction of the mantissa and exponent, ensuring the floating-point value remains constant before and after the shift and avoiding computational deviations introduced by normalization. The quotient sign bit, normalized mantissa, and compensation exponent are concatenated according to standard floating-point bit order to output a standard format floating-point division result. Simultaneously, parallel validity checks are performed, identifying abnormal conditions such as division by zero, exponent overflow, and exponent underflow, and outputting an exception flag along with the result. Upper-level modules can distinguish between valid and invalid results based on the exception flag, improving the fault tolerance of the hardware system. The overall path uses pure combinational logic to implement single-cycle floating-point division, balancing computational accuracy, hardware overhead, and low latency, making it suitable for high-speed processors, AI accelerator chips, and other hardware scenarios. Attached Figure Description

[0019] Figure 1 This is an overall hardware block diagram of a single-cycle floating-point divider based on interval dynamic scaling provided in this application embodiment; Figure 2 This is a flowchart of a division operation method based on interval dynamic scaling provided in an embodiment of this application; Figure 3 This is a curve comparing the error between the interval dynamic shift scaling truncation of this application and the traditional second-order Taylor truncation.

[0020] The reference numerals in the attached diagram are as follows: Dividend input register 101, Divisor input register 102; Sign bit XOR operation unit 103; First interval mantissa data selector 104, Second interval mantissa data selector 105; β coefficient calculator 106; Absolute value shift multiply-add tree 107; Constant accumulator 108; Double overflow detection unit 109; Mantissa dynamic shifter 110; Exponent dynamic compensation unit 111; Abnormal data selector 112; Result output register 113. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0022] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0023] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0025] Existing floating-point dividers struggle to perform single-cycle division operations. While polynomial approximation algorithms convert division into multiplication-addition operations for single-cycle output, this introduces significant errors. Calculating extremely high-order polynomials to improve accuracy results in insufficient hardware area and critical path latency to meet the demands of high-density parallel computing. Therefore, this application provides a division method and a single-cycle floating-point divider based on interval dynamic scaling. By extracting the exponent and mantissa of the dividend and divisor, and utilizing low-cost hardware shift operations to perform interval dynamic scaling reduction on the divisor, truncation errors are forcibly suppressed. Furthermore, a unified second-order polynomial approximation algorithm, combined with an unsigned multiply-add array and extreme value overflow protection logic, transforms the division operation into a pure combinational logic feedforward multiply-add operation. This divider, when used in in-memory computing macro or edge neural network accelerators, can achieve complete signed half-precision floating-point (FP16) single-cycle throughput with extremely low silicon area, effectively reducing computational latency and improving area efficiency.

[0026] Please see Figure 1 The figure shown is an overall hardware block diagram of a single-cycle floating-point divider based on interval dynamic scaling provided in this application embodiment. The single-cycle floating-point divider includes: an input register, a sign bit XOR operation unit 103, an interval mantissa data selector, an exponent dynamic compensation unit 111, a mantissa calculation unit, an abnormal data selector 112, and a result output register 113.

[0027] The input register is used to receive and store the dividend and divisor data, and separate the dividend and divisor data into a sign bit, an exponent bit, and a mantissa bit, and transmit the sign bit to the sign bit XOR operation unit 103, the mantissa bit to the interval mantissa data selector, and the exponent bit to the exponent dynamic compensation unit 111.

[0028] In some embodiments, the input register includes a dividend input register 101 and a divisor input register 102, and the interval mantissa data selector includes a first interval mantissa data selector 104 and a second interval mantissa data selector 105. The dividend input register 101 is used to receive external floating-point dividend data and perform latching and signal separation. The dividend is dynamically selected by interval through the first interval mantissa data selector 104, and the temporary mantissa of the dividend is output to the mantissa calculation unit. The divisor input register 102 is used to receive external floating-point divisor data and perform latching and signal separation. The divisor is dynamically selected by interval via the second interval mantissa data selector 105, and the temporary mantissa of the divisor is output to the mantissa calculation unit.

[0029] This application implements single-cycle floating-point division based on interval dynamic scaling, second-order polynomial approximation, and pure combinational logic multiply-add tree. It externally inputs two 16-bit half-precision floating-point data pairs: dividend Q[15:0] and divisor A[15:0]. Dividend Q[15:0] is sent to dividend input register 101, and divisor A[15:0] is sent to divisor input register 102 for latching. This embodiment uses a 16-bit floating-point storage format, with the bit fields divided as follows: the sign bit Bit

[15] represents the sign of the floating-point number, with 0 representing a positive number and 1 representing a negative number; the exponent bits Bit[14:10] are 5-bit unsigned offset exponents used to represent the floating-point order of magnitude; and the mantissa bits Bit[9:0] are 10-bit decimal mantissas representing the significant floating-point value.

[0030] The dividend input register 101 and the divisor input register 102 separate the dividend and divisor signals respectively. The dividend Q[15:0] is split and outputs three independent signals, including the dividend sign bit Q

[15] , the dividend mantissa bit Q[9:0], and the dividend exponent bit Q[14:10]. The divisor A[15:0] is split and outputs four independent signals, including the divisor sign bit A

[15] , the divisor mantissa bit A[9:0], the divisor exponent bit A[14:10], and the highest bit of the divisor mantissa A[9].

[0031] In some embodiments, the input register is equipped with a division-by-zero error detection mechanism. The mechanism performs joint verification on the mantissa and exponent bits of the dividend and divisor. If either the dividend or the divisor satisfies the zero value condition, the risk of division by zero is directly determined, and an error flag signal is output to the error data selector 112.

[0032] This embodiment uses a division-by-zero error detection mechanism to jointly verify the mantissa bits Q[9:0] of the dividend, the exponent bits Q[14:10] of the dividend, the mantissa bits A[9:0] of the divisor, and the exponent bits A[14:10] of the divisor to determine whether the dividend and divisor are zero. Specifically, when Q[14:10] == 5'b00000 and Q[9:0] == 10'b0000000000, the dividend is determined to be zero; when A[14:10] == 5'b00000 and A[9:0] == 10'b0000000000, the divisor is determined to be zero. If any of the zero-value conditions are met, error = 1 is immediately raised; under other normal input conditions, error = 0.

[0033] The generated error flag signal is transmitted to the error data selector 112 as an error control signal. When error=1, that is, division by zero is detected, the error data selector 112 cuts off the normal operation data stream and selects to output a preset error result, such as infinity or NaN custom value. When error=0, the error data selector 112 selects the normal operation path to output the floating-point quotient obtained by splicing the sign bit, normalized mantissa, and compensation exponent.

[0034] In this embodiment, the entire division-by-zero detection uses pure combinational logic, which is executed in parallel with the dynamic scaling operation of the mantissa interval. This does not introduce additional clock cycles, maintains the single-cycle operation characteristics of the circuit, and does not disrupt the original feedforward hardware pipeline.

[0035] The sign bit XOR operation unit 103 is used to calculate the sign bit of the quotient result based on the sign bit.

[0036] In some embodiments, the sign bit XOR operation unit 103 obtains the sign bit of the quotient result based on the XOR operation between the sign bit of the dividend and the sign bit of the divisor.

[0037] In this embodiment, the sign bits of the divisor (Q

[15] ) and the sign bit of the divisor (A

[15] ) are sent to the sign bit XOR operation unit 103 for XOR operation. According to the rules of positive and negative division, when the two sign bits are at the same level, a low level is output, indicating that the quotient is positive; when the two sign bits are at different levels, a high level is output, indicating that the quotient is negative. The result output by the sign bit XOR operation unit 103 is the sign bit of the quotient result, and the sign bit of the quotient result is transmitted to the abnormal data selector 112 for final floating-point quotient data splicing.

[0038] Interval mantissa data selection is used to dynamically extract the temporary mantissas of the dividend and divisor in intervals, using the highest bit of the divisor's mantissa as the selection control signal.

[0039] In order to force the mantissa of the divisor to be suppressed within the low error range, this embodiment extracts the highest bit A[9] of the mantissa of the divisor as the selection control signal of the first interval mantissa data selector 104 and the second interval mantissa data selector 105. Based on the original mantissa of the dividend and the original mantissa of the divisor, the first interval mantissa data selector 104 and the second interval mantissa data selector 105 are driven to dynamically extract the temporary mantissa of the dividend and the temporary mantissa of the divisor, respectively, so as to realize the dynamic reduction of the mantissa interval and suppress the truncation error caused by the subsequent polynomial approximation.

[0040] In some embodiments, in the interval mantissa data selector, when the highest bit level of the divisor mantissa is 0, the original mantissa of the dividend is directly extracted as the temporary mantissa of the dividend, and the original mantissa of the divisor is used as the temporary mantissa of the divisor; when the highest bit level of the divisor mantissa is 1, a unified shift and scaling operation is performed on the original mantissa of the dividend and the original mantissa of the divisor respectively to obtain the scaled mantissa of the dividend and the scaled mantissa of the divisor, and the scaled mantissa of the dividend is extracted as the temporary mantissa of the dividend, and the scaled mantissa of the divisor is used as the temporary mantissa of the divisor.

[0041] The mantissa calculation unit is used to calculate the polynomial coefficients and perform polynomial shift multiplication and addition operations in combination with the temporary mantissa to obtain the original mantissa calculation result.

[0042] In some embodiments, the mantissa calculation unit includes a β coefficient calculator 106, an absolute value shift multiply-accumulate tree 107, and a constant accumulator 108; The β coefficient calculator 106 is used to calculate polynomial coefficients based on the temporary mantissa output by the interval mantissa data selector, and to generate higher-order terms of the divisor temporary mantissa.

[0043] Temporary mantissa of the dividend output by the interval mantissa data selector. Temporary mantissa of divisor A parallel input β coefficient calculator 106 reads two temporary mantissa values ​​and performs combinational logic operations based on an internally preset second-order reciprocal approximation polynomial model to solve for the polynomial coefficient β suitable for the current interval. This second-order reciprocal approximation polynomial model predetermines the polynomial basis form according to the interval containing the divisor; in this embodiment, it can be represented as follows: The circuit uses two temporary mantissas as input variables and employs pure combinational logic hardware to implement the mapping operation. First, a parallel comparison circuit is used to lock the polynomial constraints corresponding to the current scaling interval. Then, a polynomial solution path is built using multiple parallel multipliers and adders, substituting the temporary mantissas of the dividend. Temporary mantissa of divisor Unsigned fixed-point arithmetic is performed to solve for the polynomial coefficients β that fit the current mantissa interval in real time. These polynomial coefficients β are used to establish the polynomial mapping relationship for division operations, realizing the equivalent conversion of division operations to multiplication and addition operations. The entire solution process has no register feedback and requires no iteration. The operation delay is only the combinational logic transmission delay. The solved polynomial coefficients β are directly output to the absolute value shift multiplication and addition tree 107, providing coefficient input for the second-order polynomial multiplication and addition approximation.

[0044] The absolute value shift multiply-add tree 107 is used to generate higher-order terms based on the temporary mantissa of the divisor, and combined with the polynomial coefficients, to perform polynomial shift multiply-add operations based on the absolute value shift multiply-add tree to obtain polynomial approximations.

[0045] The polynomial coefficients β and the temporary mantissa of the divisor are fed into the absolute value shift multiply-accumulate tree 107. The absolute value shift multiply-accumulate tree 107 employs a pure combinatorial feedforward hardware structure, rapidly generating quadratic, quartic, and other higher-order terms of the temporary mantissa of the divisor through hardware shift operations. It then performs parallel multiplication operations between each term and the polynomial coefficients β, as well as multi-level accumulation operations, thus fully executing the second-order polynomial fitting operation and outputting a polynomial approximation value without a constant term. The entire operation has no iterative feedback loop, ensuring that the operation can be completed within a single cycle.

[0046] This embodiment transforms signed multiplication into unsigned shift-accumulate operations through absolute value preprocessing, significantly reducing the hardware area of ​​the multiply-accumulate circuit while retaining complete sign recovery logic, balancing hardware overhead and computational accuracy. Specifically, the terms of the temporary mantissa of the divisor and the polynomial coefficients β obtained by the β coefficient calculator 106 are fed into the absolute value shift-multiply-accumulate tree to perform polynomial shift-multiply-accumulate operations. First, the absolute value of the temporary mantissa of the divisor is extracted. Relying on Each bit's 0 / 1 state serves as a multiplexing control signal, conditionally selecting and staggering the coefficients β of the positive fixed-point polynomial. This replaces traditional large-scale hardware multipliers in performing unsigned multiplication and accumulation operations, simultaneously generating the polynomial required for the operation. Number of operations. After the unsigned operation is completed, read the temporary mantissa of the divisor. The original sign bit is used to determine whether to perform a two's complement conversion on the accumulated result to restore the numerical sign, and then the polynomial approximation is output. and polynomial components The approximate polynomial value without constant terms is obtained and transmitted to the constant accumulator 108. The entire operation is implemented based on an unsigned lightweight architecture, avoiding the hardware area expansion problem caused by negative two's complement multipliers, and uses pure combinational logic throughout to ensure that the operation is completed in a single cycle.

[0047] The constant accumulator 108 is used to superimpose the polynomial fitting constant term onto the polynomial approximation to obtain the original mantissa calculation result.

[0048] The polynomial approximation output by the absolute value shift multiply-add tree 107 is fed into the constant accumulator 108. The constant accumulator 108 has a built-in preset polynomial fitting constant term. The constant term is superimposed and compensated with the polynomial approximation through a hardware addition circuit to complete the constant component of the second-order approximation polynomial. Finally, the complete original mantissa calculation result is output and transmitted to the dual overflow detection unit 109 for overflow level determination. The original mantissa calculation result refers to the fixed-point operation result output by the constant accumulator 108 after superimposing the polynomial approximation with the polynomial fitting constant term. It represents the preliminary approximation of the mantissa of the division quotient. This value has not yet been adjusted for floating-point normalization and its value range is not constrained by [1.0, 2.0). It is the input data source for subsequent overflow level determination and mantissa shift processing.

[0049] In this embodiment, the numerical range is divided based on the highest digit of the divisor's mantissa. Different numerical ranges are matched with the same second-order polynomial architecture. The range of the independent variable is compressed only by dynamically scaling the mantissa. β is used as a proportionality coefficient to establish the mapping between the dividend, divisor, and reciprocal polynomials. This converts the division operation into the multiplication and addition form of "coefficient × divisor polynomial", avoiding direct division operations and providing a mathematical basis for single-cycle pure hardware feedforward calculation.

[0050] The single-cycle floating-point divider also includes an overflow detection unit 109. The overflow detection unit 109 is used to determine the mantissa overflow level of the original mantissa calculation result according to the overflow determination status bit, perform shift normalization processing on the mantissa based on the mantissa overflow level, obtain the normalized mantissa and overflow status signal, output the normalized mantissa to the abnormal data selector 112, and output the overflow status signal to the exponent dynamic compensation unit 111.

[0051] In some embodiments, the two highest bits of the original mantissa calculation result are extracted as overflow determination status bits. The overflow level of the original mantissa calculation result is determined based on the overflow determination status bits, and the overflow level of the mantissa is converted into a standardized overflow status signal and output to the exponential dynamic compensation unit 111.

[0052] Since polynomial truncation approximation introduces positive calculation errors, mantissa overflow problems are likely to occur when the theoretically calculated quotient value is close to the hardware fixed-point constant reference of 2.0 or 1.0. In this embodiment, the mantissa overflow level is quickly determined based on the highest two bits of the original mantissa calculation result, and the mantissa shift and exponent compensation logic are linked synchronously to realize real-time hardware self-healing correction. Pure combinational logic operation is used throughout the process, without introducing additional clock cycles, thus ensuring the single-cycle operation performance of the circuit.

[0053] Specifically, in this embodiment, the two highest bits of the original mantissa calculation result are extracted as overflow determination status bits, and the corresponding mantissa overflow level is obtained based on the overflow determination status bits. The mantissa overflow level is synchronously output as two control signals. One signal is sent to the mantissa dynamic shifter 110, which is used to perform left or right shift operations according to the mantissa overflow level to complete the mantissa normalization process and obtain the normalized mantissa. The other signal converts the mantissa overflow level into a normalized overflow status signal and transmits it to the exponent dynamic compensation unit 111 for subsequent exponent difference compensation calculation.

[0054] In some embodiments, the mantissa overflow level includes a positive overflow level, a no overflow level, and a low-bit under-sizing level; if it is a positive overflow level, the normalization flag is mapped to -1, and the mantissa is shifted one bit to the right; if it is a no overflow level, the normalization flag is mapped to 0, and the mantissa remains in its original position; if it is a low-bit under-sizing level, the normalization flag is mapped to 1, and the mantissa is shifted one bit to the left to make up the difference.

[0055] The original mantissa calculation result output by the constant accumulator 108 is sent to the dual overflow detection unit 109 for overflow determination. That is, the dual overflow detection unit 109 extracts the two highest bits of the original mantissa calculation result as overflow determination status bits to determine the mantissa overflow level. Then, the mantissa overflow level is sent as a control signal to the mantissa dynamic shifter 110 to perform mantissa self-healing normalization processing.

[0056] Specifically, if it's a positive overflow level (i.e., the original mantissa calculation result is detected to have an extreme positive overflow of 2.0, and the initial approximation of the quotient mantissa is greater than or equal to 2.0), then the normalization flag δ=-1, the mantissa is shifted one bit to the right to eliminate mantissa overflow, and the exponent compensation is corrected by -1. If it's a no-overflow level (i.e., the original mantissa calculation result is detected to be within the normal normalization range of [1.0, 2.0), and the initial approximation of the quotient mantissa is within the normal range), then the normalization flag δ=0, the mantissa remains in its original position, and the exponent is not compensated additionally. If it's a low-bit under-normalization level (i.e., the original mantissa calculation result is detected to be less than 1.0, and the initial approximation of the quotient mantissa is less than 1.0), then the normalization flag δ=+1, the mantissa is shifted one bit to the left to fill the standard normalization range, the exponent is not compensated additionally, and the exponent compensation is corrected by +1. Thus, it achieves mantissa shifting and normalization processing according to the mantissa overflow level to obtain a normalized mantissa, and simultaneously converts the overflow status signal containing exponent compensation according to the mantissa overflow level.

[0057] The exponent dynamic compensation unit 111 is used to calculate the original exponent difference based on the exponent bits of the dividend and divisor, and to perform shift compensation on the original exponent difference based on the overflow state of the original mantissa calculation result to obtain the compensation exponent.

[0058] Based on the dividend exponent and divisor exponent bits parsed from the input register, a subtraction circuit is used to subtract the divisor exponent from the dividend exponent to obtain the original exponent difference. Then, an overflow status signal output from the overflow detection unit 109 is received. This overflow status signal carries the exponent compensation amount (-1, 0, +1) corresponding to the normalization flag δ. The original exponent difference and the exponent compensation amount are added together to achieve exponent shift compensation. When the normalization flag δ = -1, the original exponent difference is decreased by 1; when the normalization flag δ = 0, the original exponent difference remains unchanged; when the normalization flag δ = 1, the original exponent difference is increased by 1. The final calculated output is the compensated exponent, which is then transmitted to the exception data selector 112 for concatenating the final floating-point result.

[0059] The abnormal data selector 112 is used to output the division operation result based on the sign bit of the quotient result, the original mantissa calculation result, and the compensation exponent, and output it to the outside via the result output register 113.

[0060] The system receives the sign bit of the quotient result obtained from the sign bit XOR operation unit 103, the normalized mantissa processed by the overflow detection unit 109, and the compensated exponent output by the exponent dynamic compensation unit 111. It then performs a bit concatenation operation according to the bit arrangement rules defined by the target floating-point data bit width. Specifically, the sign bit of the quotient result is placed at the highest sign bit position, the compensated exponent is filled into the exponent bit range after the sign bit of the quotient result, and the normalized mantissa is sequentially arranged in the lower mantissa range, combining to form a complete floating-point data format. The floating-point data is then validated. The validation logic identifies two types of abnormal conditions: first, the exponent, after compensation, exceeds the representable upper and lower limits of the floating-point format exponent, resulting in overflow or underflow; second, a division-by-zero anomaly is detected in the pre-process of the division operation. Once an anomaly is identified, an anomaly flag is simultaneously added and output along with the floating-point result for the upper-level circuit to determine whether the output value is valid. If no anomaly is detected, the concatenated standard floating-point division result is directly output.

[0061] Please see Figure 2 The diagram shows an optional flowchart of a division operation method based on interval dynamic scaling provided in this application embodiment. The division operation method includes: S1, based on the input register, receives floating-point numbers as dividend and divisor, and unpacks the dividend and divisor in parallel to separate the sign bit, mantissa bit and exponent bit; S2, the sign bit XOR operation unit 103 calculates the sign bit of the quotient result based on the sign bits of the dividend and the divisor; S3 extracts the highest bit of the divisor mantissa as a selection control signal through the mantissa calculation unit, dynamically extracts the temporary mantissas of the dividend and divisor in intervals, and obtains the original mantissa calculation result through polynomial shift multiplication and addition operations; S4, the dual overflow detection unit 109 determines the mantissa overflow level of the original mantissa calculation result according to the overflow determination status bit, and performs shift normalization processing on the mantissa according to the mantissa overflow level to obtain the normalized mantissa and overflow status signal. S5, the exponent dynamic compensation unit 111 calculates the original exponent difference based on the exponent bits of the dividend and divisor, and performs shift compensation on the original exponent difference based on the overflow state signal to obtain the compensation exponent; S6, the abnormal data selector 112 outputs the division result based on the sign bit of the quotient result, the normalized mantissa, and the compensation exponent, and outputs it to the outside via the result output register 113.

[0062] The core objective of this application is to solve the global accuracy collapse problem caused by the truncation of high-order terms in traditional polynomial approximation dividers. By proposing a novel interval dynamic scaling and polynomial truncation expansion algorithm, the divisor is dynamically reduced using extremely low-cost shift operations in digital circuits, so that the global accuracy can be satisfied by retaining only the extremely simplified polynomial down to the second-order term. This results in the construction of a pure feedforward, single-cycle, and extremely low-area hardware approximation divider.

[0063] Taking the FP16 format as an example, the sign bit in its operation is achieved by performing a logical XOR operation between the sign bits of the dividend and divisor; the exponent bit is achieved by subtracting the exponent bits of the dividend and divisor, and then performing shift compensation in conjunction with the normalization flag δ of the mantissa operation result. The core operation process of the mantissa bit is as follows: First, we perform algebraic transformations and series expansions on the division polynomial. The original division operation Q÷A=B is equivalent to (1+q)÷(1+a)=(1+b), where q, a, and b are the mantissas of Q, A, and B, respectively. The goal is to find the mantissa b of the quotient. Given (1+a)(1+b)=(1+q), through algebraic identities, we can obtain a+b+ab=q, and further derive b=qa-ab. Iteratively substituting this equation, we get b=qaa(qa-ab)=qaa(qa)+a2b. For ease of hardware implementation, we let the intermediate characteristic variable γ=qaa(qa). Then, the above equation can be rewritten in the form of an infinite series, expressed as: .

[0064] Then, dynamic scaling reduction is performed based on the highest-order bit of the divisor; in the hardware implementation, higher-order terms are truncated. The key is to reduce the area, combined with Figure 3 The error comparison curve shows that when the divisor's last digit a approaches 1.0, the error of this term is extremely large. In this embodiment, A=1.5 (i.e., the highest digit of the divisor's last digit) is used as the dividing point of the interval reduction. When A<1.5, i.e., a<0.5, the highest digit of the divisor's last digit A[9]=0, the higher-order term... The decay is extremely rapid. In this embodiment, we directly take n=2 for second-order truncation, and the approximate formula is: When A ≥ 1.5, i.e., a ≥ 0.5, if the term is truncated directly, the error term... This cannot be ignored. This embodiment introduces a scaling mechanism at the algorithm level, meaning that even if Q'=Q / 2 and A'=A / 2, the equation Q' / A'=B still holds. The scaled mantissa variables q'=(q-1) / 2 and a'=(a-1) / 2 are then extracted, and the intermediate feature variable γ'=q'-a'-a'(q'-a') is calculated. Since Q / 2 and A / 2 at the hardware level only represent a logical right shift of the connection (zero cost), the scaled variable |a'|<0.25, resulting in a sharp reduction in higher-order error terms, even when using the same second-order truncation formula. truncate higher-order terms It can also be safely discarded. In summary, regardless of the interval, the core architecture of this embodiment can be uniformly expressed as a second-order approximate polynomial. This allows for the use of a very simple multiply-accumulate path to cover the entire data range.

[0065] Subsequently, a hardware algebraic reconstruction and mapping of the entire positive number domain are performed to avoid negative numbers. In the pure mathematical derivation, the intermediate feature variable is γ = qaa(qa). During hardware mapping, since the relationship between the mantissa q of the dividend and the mantissa a of the divisor is unknown, directly calculating (qa) will produce a negative number, which will force the underlying layer to call a signed two's complement multiplier with high area consumption. To achieve unsigned computation across the entire data path, this embodiment proposes an algebraic reconstruction method, introducing a hardware baseline positive bias of 1.0, and constructing a hardware intermediate variable β = 1.0 - q + a for the entire positive number domain. Since q, a ∈ [0, 1.0), β is strictly greater than 0 under any data input, completely eliminating the negative number trap. At this time, the polynomial approximation is expressed as: .

[0066] Therefore, we can conclude that... .

[0067] Through the aforementioned identity transformation, this embodiment completely maps floating-point division into the data paths of pure addition and subtraction and unsigned multiplication, eliminating the dependence on negative two's complement conversion from the root of the algorithm.

[0068] Finally, hardware circuit mapping and boundary compensation are performed. Based on the reconstructed all-positive-number-domain approximation formula, the corresponding temporary mantissa of the dividend is extracted at the RTL level by using a multiplexer (MUX) combined with the determination of the highest bit of the divisor. With the temporary mantissa of the divisor (Complete the dynamically scaled mantissa). For the temporary mantissa of the divisor. For hardware pain points that may be negative, first extract their absolute value. A custom unsigned shift-and-add truncated multiply-add tree array is used to solve for the intermediate variable in the all-positive number field. and Then, the initial value of the mantissa of the quotient is obtained in the pure combinational addition and subtraction logic. Finally, with the aid of dual hardware overflow detection, dynamic carry-adaptive adjustment of the exponent and mantissa is realized, completing the fully pipelined feedforward output without any timing state machine.

[0069] Please see Figure 1 The diagram shows the overall hardware block diagram of the single-cycle floating-point divider of this application. It does not contain any D flip-flops (DFFs) or sequential state machines, and relies entirely on pure feedforward combinational logic gates to achieve single-cycle throughput. The single-cycle floating-point divider receives an external 16-bit floating-point number and performs single-cycle floating-point division based on interval dynamic scaling, second-order polynomial approximation, and pure combinational logic multiply-add tree. The input floating-point format is defined as follows: Bit

[15] represents the sign bit, Bit[14:10] represents the exponent bit, and Bit[9:0] represents the mantissa. The overall data flow is divided into a sign path, a mantissa operation path, an exponent compensation path, and an abnormal output selection path.

[0070] exist Figure 1 In the input register, the outputs are connected to the sign bit XOR operation unit 103, the interval mantissa data selector, and the exponent dynamic compensation unit 111, respectively; the output of the interval mantissa data selector is connected to the mantissa calculation unit, and the mantissa calculation unit, the double overflow detection unit 109, and the mantissa dynamic shifter 110 are connected in sequence; the outputs of the sign bit XOR operation unit 103, the mantissa dynamic shifter 110, and the exponent dynamic compensation unit 111 are all connected to the result output register 113 through the abnormal data selector 112.

[0071] The input registers include a dividend input register 101 and a divisor input register 102. The interval mantissa data selector includes a first interval mantissa data selector 104 and a second interval mantissa data selector 105. The output of the dividend input register 101 is connected to the first interval mantissa data selector 104, and the output of the divisor input register 102 is connected to the second interval mantissa data selector 105. The output of the second interval mantissa data selector 105 is also connected to an absolute value shift multiply-add tree 107.

[0072] The mantissa calculation unit includes a β coefficient calculator 106, a shift multiply-add tree 107, and a constant accumulator 108 connected in sequence. The input of the β coefficient calculator 106 is connected to the interval mantissa data selector, and the output of the constant accumulator 108 is connected to the double overflow detection unit 109. The output of the double overflow detection unit 109 is also connected to the exponential dynamic compensation unit 111.

[0073] Specifically, the dividend input register 101 receives an external 16-bit floating-point dividend Q[15:0] and splits it into three signals: the dividend sign bit Q

[15] , the dividend original mantissa Q[9:0], and the dividend original exponent Q[14:10]. The divisor input register 102 receives an external 16-bit floating-point divisor A[15:0] and splits it into four signals: the divisor sign bit A

[15] , the divisor original mantissa A[9:0], the divisor original exponent A[14:10], and the divisor mantissa most significant bit A[9]. The divisor mantissa most significant bit A[9] is used as an interval selection control signal.

[0074] The sign bit Q

[15] of the dividend and the sign bit A

[15] of the divisor are input into the sign bit XOR operation unit 103. After XOR operation by the XOR gate, the sign bit of the quotient result is obtained and sent to the end abnormal data selector 112.

[0075] In the first interval mantissa data selector 104 and the second interval mantissa data selector 105, the highest bit A[9] of the divisor mantissa is used as the selection control signal. The mantissas of the dividend and divisor are dynamically selected in intervals as temporary mantissas and input into the β coefficient calculator 106. At the same time, the mantissa of the divisor is input into the absolute value shift multiply-add tree 107. That is, when A[9]=0, the first interval mantissa data selector 104 directly extracts the original mantissa of the dividend as the temporary mantissa of the dividend. The second interval mantissa data selector 105 directly extracts the original mantissa of the divisor as the temporary mantissa of the divisor. When A[9]=1, the original mantissa of the dividend and the original mantissa of the divisor are shifted and scaled respectively to obtain the scaled mantissa of the dividend and the scaled mantissa of the divisor. The first interval mantissa data selector 104 extracts the scaled mantissa of the dividend as the temporary mantissa of the dividend. The second interval mantissa data selector 105 extracts the divisor scaling mantissa as the temporary mantissa of the divisor. .

[0076] Temporary mantissa of dividend And the temporary mantissa of the divisor Entering the β coefficient calculator 106, polynomial coefficients β are generated based on the polynomial approximation model, and the generated polynomial coefficients β are then fed into the absolute value shift multiply-add tree 107. (Divisor temporary mantissa) In the absolute value shift multiply-add tree 107, higher-order terms are generated through hardware shifting, such as... Then, a second-order polynomial multiplication and addition operation is performed with the polynomial coefficient β to obtain a polynomial approximation of the mantissa. ,Will The data is fed into constant accumulator 108. Constant accumulator 108 is used for polynomial approximation. By superimposing the constant term of the polynomial fitting, the complete second-order polynomial is evaluated, and the original mantissa calculation result is obtained and sent to the dual overflow detection unit 109.

[0077] The dual overflow detection unit 109 extracts the two most significant bits of the original mantissa calculation result as overflow determination status bits. Based on the determined mantissa overflow level, it generates three status flags: overflow, no overflow, and underflow. Simultaneously, it outputs two signals: one overflow status signal, input to the exponent dynamic compensation unit 111, and the other mantissa calculation result, input to the mantissa dynamic shifter 110. The mantissa dynamic shifter 110 uses the mantissa overflow level as a control signal, performs shift normalization processing on the mantissa according to the overflow status, and obtains a normalized mantissa, which is then sent to the abnormal data selector 112.

[0078] The exponent dynamic compensation unit 111 calculates the difference between the original exponent Q[14:10] of the dividend and the original exponent A[14:10] of the divisor to obtain the original exponent difference value. Based on the overflow status signal output by the dual overflow detection unit 109, the original exponent difference value is compensated by hardware ±1 / 0, and the compensation exponent is output and sent to the abnormal data selector 112.

[0079] The exception data selector 112 receives the sign bit of the quotient result output by the sign bit XOR operation unit 103, the normalized mantissa output by the mantissa dynamic shifter 110, and the compensation exponent output by the exponent dynamic compensation unit 111. It concatenates the sign bit, normalized mantissa, and compensation exponent to obtain a 16-bit floating-point quotient and sends this quotient to the result output register 113. Simultaneously, the exception data selector 112 uses the error flag as an exception control signal to output preset exceptions triggered by an error, such as division by zero, non-normalized number, or NaN. The normal or exception result output by the exception data selector 112 is then output to the external system via the result output register 113 to display the final division result.

[0080] Please see Figure 3 The figure shows a comparison curve of the error between the interval dynamic shift scaling truncation of this application and the traditional second-order Taylor truncation. The figure shows the relationship between the maximum truncation error of this scheme and the change of the divisor mantissa of the traditional second-order Taylor truncation scheme. The horizontal axis represents the actual value A of the divisor mantissa, with a value range of [1.0, 2.0]; the vertical axis represents the maximum truncation error, with the unit being ULP. Figure 3 The red dashed line represents the comparison scheme, namely the traditional second-order Taylor truncation algorithm without scaling; the blue solid line represents the scheme of this application, namely the interval dynamic shift scaling truncation scheme; the black dotted line is the hardware shift trigger boundary, corresponding to the threshold A=1.5.

[0081] For traditional second-order Taylor truncation schemes, when the mantissa A > 1.5, the maximum truncation error rapidly increases, exhibiting an exponential error explosion phenomenon, with the maximum error exceeding 1000 ULP, severely degrading computational accuracy; at the shift boundary A = 1.5, the error of the traditional scheme reaches approximately 10.7 ULP. This application's scheme employs an interval-based dynamic shift-scaling truncation strategy, triggering the shift-scaling mechanism at the threshold A = 1.5; when A ≥ 1.5, only 1 bit of hardware shift overhead is required to stably constrain the maximum truncation error to within approximately 2 ULP, completely eliminating the error explosion problem; in the A < 1.5 interval, the error curve of this application's scheme follows the same trend as the traditional scheme. The comparison shows that this application's scheme, through simple hardware shift-scaling, significantly suppresses the polynomial truncation error when the mantissa of the divisor approaches 2.0, effectively widening the effective input range of high-precision division, without increasing circuit complexity.

[0082] This application provides a division operation method based on interval dynamic scaling and a single-cycle floating-point divider. This scheme unpacks the dividend and divisor floating-point numbers in parallel, separating the sign bit, mantissa bit, and exponent bit, thus splitting the data path. This allows the sign operation, mantissa operation, and exponent operation to be performed in parallel, eliminating the timing loss caused by serial processing and providing an architectural foundation for single-cycle operation of the entire division path. The sign bit of the quotient result is calculated based on the sign bits of the dividend and divisor. The sign calculation is performed independently of the mantissa and exponent operation branches, without waiting for the mantissa operation result, and does not occupy critical timing paths. The sign logic only uses a simple XOR combination circuit, resulting in minimal hardware overhead and enabling the quotient sign bit to be output in advance for the final concatenation stage.

[0083] By extracting the highest bit of the divisor's mantissa as a partitioning control signal, the dividend and the temporary mantissa of the divisor are dynamically scaled to constrain the input interval of the second-order polynomial. On the one hand, the dynamic scaling mechanism solves the problem of exponential error explosion that occurs in the traditional fixed-interval second-order Taylor approximation when the mantissa of the divisor approaches 2.0. The maximum truncation error across the entire domain can be constrained to about 2ULP by relying solely on shifting hardware overhead, significantly widening the high-precision calculation interval. On the other hand, the polynomial operation adopts an absolute value shift multiply-accumulate tree architecture, converting signed multiplication into unsigned shift accumulation operation, avoiding the hardware area expansion defect of traditional two's complement multipliers, reducing the circuit size while ensuring calculation accuracy, and obtaining the original mantissa calculation result.

[0084] Due to the positive error caused by polynomial truncation, the original mantissa calculation result will deviate from the floating-point standard specification range. This solution extracts the two highest bits of the original mantissa to generate an overflow judgment status bit, divides the mantissa overflow level into three categories, drives the mantissa dynamic shifter to perform self-healing normalization, and handles the three working conditions of positive overflow, normal range, and under-specification respectively; at the same time, an overflow status signal is generated and fed forward to effectively correct the mantissa out-of-bounds problem, and outputs a normalized mantissa that meets the floating-point standard format, ensuring that the mantissa falls within the standard range of [1.0, 2.0).

[0085] The mantissa shift operation changes the exponent of the value. An overflow status signal maps the shifted offset to an exponent compensation value. The original exponent difference is synchronously corrected with the compensation value; that is, a right shift of the mantissa decrements the exponent by 1, a left shift increments the exponent by 1, and no shift leaves the exponent unchanged. This achieves coordinated correction of the mantissa and exponent, ensuring the floating-point value remains constant before and after the shift and avoiding computational deviations introduced by normalization. The quotient sign bit, normalized mantissa, and compensation exponent are concatenated according to standard floating-point bit order to output a standard format floating-point division result. Simultaneously, parallel validity checks are performed, identifying abnormal conditions such as division by zero, exponent overflow, and exponent underflow, and outputting an exception flag along with the result. Upper-level modules can distinguish between valid and invalid results based on the exception flag, improving the fault tolerance of the hardware system. The overall path uses pure combinational logic to implement single-cycle floating-point division, balancing computational accuracy, hardware overhead, and low latency, making it suitable for high-speed processors, AI accelerator chips, and other hardware scenarios.

[0086] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0087] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0088] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0089] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0090] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A single-cycle floating-point divider based on interval dynamic scaling, characterized in that, The single-cycle floating-point divider includes an input register, a sign bit XOR operation unit, a segmented mantissa data selector, an exponent dynamic compensation unit, a mantissa calculation unit, an exception data selector, and a result output register. The input register is used to receive and store dividend and divisor data, and to separate the dividend and divisor data into sign bit, exponent bit and mantissa bit, and to transmit the sign bit to the sign bit XOR operation unit, the mantissa bit to the interval mantissa data selector, and the exponent bit to the exponent dynamic compensation unit. The sign bit XOR operation unit is used to calculate the sign bit of the quotient result based on the sign bit. The segmented mantissa data selection is used to dynamically extract the temporary mantissas of the dividend and divisor in segments, using the highest bit of the divisor's mantissa as the selection control signal. The mantissa calculation unit is used to calculate the polynomial coefficients and perform polynomial shift multiplication and addition operations in combination with the temporary mantissa to obtain the original mantissa calculation result; The exponent dynamic compensation unit is used to calculate the original exponent difference based on the exponent bits of the dividend and divisor, and to perform shift compensation on the original exponent difference based on the overflow state of the original mantissa calculation result to obtain the compensation exponent. The abnormal data selector is used to output the division operation result based on the sign bit of the quotient result, the calculation result of the original mantissa, and the compensation exponent, and output it to the outside via the result output register.

2. The single-cycle floating-point divider according to claim 1, characterized in that, The input register includes a dividend input register and a divisor input register, and the interval mantissa data selector includes a first interval mantissa data selector and a second interval mantissa data selector. The dividend input register is used to receive external floating-point dividend data and perform latching and signal separation. The dividend is dynamically selected by interval through the first interval mantissa data selector, and the temporary mantissa of the dividend is output to the mantissa calculation unit. The divisor input register is used to receive external floating-point divisor data and perform latching and signal separation. The divisor is dynamically selected by interval via the second interval mantissa data selector, and the temporary mantissa of the divisor is output to the mantissa calculation unit.

3. The single-cycle floating-point divider according to claim 1, characterized in that, The input register is equipped with a division-by-zero error detection mechanism. The mechanism performs joint verification on the mantissa and exponent bits of the dividend and divisor. If either the dividend or the divisor satisfies the zero value condition, the risk of division by zero is directly determined, and an error flag signal is output to the error data selector.

4. The single-cycle floating-point divider according to claim 1, characterized in that, The sign bit XOR operation unit obtains the sign bit of the quotient result by performing an XOR operation between the sign bit of the dividend and the sign bit of the divisor.

5. The single-cycle floating-point divider according to claim 1, characterized in that, When the highest bit level of the divisor's mantissa is 0, the original mantissa of the dividend is directly extracted as the temporary mantissa of the dividend, and the original mantissa of the divisor is used as the temporary mantissa of the divisor. When the highest bit level of the divisor's mantissa is 1, a unified shift and scaling operation is performed on the original mantissa of the dividend and the original mantissa of the divisor respectively to obtain the scaled mantissa of the dividend and the scaled mantissa of the divisor. The scaled mantissa of the dividend is extracted as the temporary mantissa of the dividend, and the scaled mantissa of the divisor is used as the temporary mantissa of the divisor.

6. The single-cycle floating-point divider according to claim 1, characterized in that, The mantissa calculation unit includes a β coefficient calculator, an absolute value shift multiply-accumulate tree, and a constant accumulator; The β coefficient calculator is used to calculate polynomial coefficients based on the temporary mantissa output by the interval mantissa data selector, and to generate higher-order terms of the temporary mantissa of the divisor. The absolute value shift multiply-add tree is used to generate higher-order terms based on the temporary mantissa of the divisor, and in combination with the polynomial coefficients, to perform polynomial shift multiply-add operations based on the absolute value shift multiply-add tree to obtain a polynomial approximation. The constant accumulator is used to superimpose the polynomial fitting constant term onto the polynomial approximation to obtain the original mantissa calculation result.

7. The single-cycle floating-point divider according to claim 1, characterized in that, The single-cycle floating-point divider also includes an overflow detection unit. The overflow detection unit is used to determine the mantissa overflow level of the original mantissa calculation result according to the overflow determination status bit, perform shift normalization processing on the mantissa based on the mantissa overflow level to obtain the normalized mantissa and the overflow status signal, output the normalized mantissa to the abnormal data selector, and output the overflow status signal to the exponential dynamic compensation unit.

8. The single-cycle floating-point divider according to claim 7, characterized in that, The two most significant bits of the original mantissa calculation result are extracted as overflow determination status bits. The overflow level of the original mantissa calculation result is determined based on the overflow determination status bits, and the overflow level is converted into a standardized overflow status signal and output to the exponential dynamic compensation unit.

9. The single-cycle floating-point divider according to claim 7, characterized in that, The mantissa overflow level includes positive overflow level, no overflow level, and low-bit under-normalization level; if it is a positive overflow level, the normalization flag is mapped to -1, and the mantissa is shifted one bit to the right; If it is a no-overflow level, the normalization flag is mapped to 0, and the mantissa remains in its original position; if it is a low-bit under-normalization level, the normalization flag is mapped to 1, and the mantissa is shifted one bit to the left to make up the difference.

10. A division operation method based on interval dynamic scaling, applied to the single-cycle floating-point divider according to any one of claims 1 to 9, characterized in that, The division operation method includes: Based on the input register, the floating-point number is received as the dividend and divisor, and the dividend and divisor are unpacked in parallel to separate the sign bit, mantissa bit and exponent bit. The sign bit XOR operation unit calculates the sign bit of the quotient result based on the sign bits of the dividend and the divisor; The highest bit of the divisor's mantissa is extracted by the mantissa calculation unit as a selection control signal. The temporary mantissas of the dividend and divisor are dynamically extracted in intervals, and the original mantissa calculation result is obtained by polynomial shift multiplication and addition operations. The dual overflow detection unit determines the mantissa overflow level of the original mantissa calculation result based on the overflow determination status bit, and performs shift normalization processing on the mantissa according to the mantissa overflow level to obtain the normalized mantissa and overflow status signal. The exponent dynamic compensation unit calculates the original exponent difference based on the exponent bits of the dividend and divisor, and performs shift compensation on the original exponent difference based on the overflow state signal to obtain the compensated exponent. The abnormal data selector outputs the division result based on the sign bit of the quotient result, the normalized mantissa, and the compensation exponent, and outputs it to the outside via the result output register.

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