A hybrid multiple-precision arithmetic logic unit array processor

Abstract

The application discloses a kind of mixed multi-ary arithmetic logic unit array processor, belong to digital integrated circuit technical field.When the different data bits are used in different base (such as sixty base and decimal mixed) when computing task needs, standard binary array can only be simulated in binary.The application includes configurable base ALU unit array, each unit base is independently adjustable;Cross-base carry propagation circuit, the carry value of low-order unit to high-order unit is determined by the unit configuration base and is transmitted through carry line;Cross-base interconnection network, adjacent direct connection, row-column broadcast and diagonal exchange are supported;Runtime base reconfiguration controller, three configuration granularities of global, row or column, unit are supported, pipeline gap is completed switching;Mixed base data decomposition and reorganization unit, input data is decomposed and operated in parallel according to unit base and then reorganized and output.The application enables different units to run in different base simultaneously, and is suitable for mixed base parallel computing field.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit technology, and more specifically to a processor comprising an array of arithmetic logic units with multiple independently configurable bases, and a cross-base interconnect network. Background Technology

[0002] In existing processor architectures, the base of all arithmetic logic units is fixed in binary. Some reconfigurable array processors support runtime switching of unit operation functions—for example, switching the same arithmetic unit from addition to multiplication—but the arithmetic base of each unit remains fixed in binary.

[0003] However, the arithmetic radix of the above scheme is fixed during the synthesis or design phase, and cannot support multiple radixes simultaneously on the same hardware or dynamically switch radixes at runtime. Specifically, it includes the following limitations: (1) Fixed radix: The radix of a single ALU is fixed during synthesis and cannot be flexibly switched to other radixes (such as radix 3, radix 6, radix 7, etc.) on the same hardware. For application scenarios that require frequent switching between different modulus spaces, the fixed radix scheme requires multiple chips or multiple reconfigurations; (2) No hardware support for mixed radix operations: Periodic systems in the real world are often not based on a single radix (such as radix 3, radix 5, radix 6, radix 7, radix 10, etc., and existing processors cannot process mixed radixes in parallel on the same data path; (3) Lack of standardized interconnection schemes for array expansion: When multiple non-binary radix ALUs need to work together, there is a lack of standardized single interconnection schemes. The design complexity of inter-element data exchange, carry propagation and synchronization mechanisms increases linearly with the number of units when extended to arrays; (4) The radix reconfiguration of existing hybrid radix operation engines (such as hybrid radix engines for dedicated applications such as FFT) is limited to the overall engine level - all units are switched to the same radix at the same time, and different radixes cannot be configured independently for different units. Moreover, the carry propagation between units still follows fixed binary rules and lacks a cross-radix carry propagation mechanism. When adjacent ALU units are configured with different radixes, the carry value of the lower unit cannot be correctly passed to the higher unit according to its configured radix. Units with different radixes cannot directly participate in multi-unit joint operation and must first convert the results of each unit back to the same radix before completing the operation step by step.

[0004] In existing technologies, reconfigurable array processors (such as the PACT XPP architecture) support runtime switching of unit operation functions, but the arithmetic radix of each unit remains fixed as binary. The reconfiguration of the operation function of such reconfigurable arrays is achieved by changing data routing and opcode mapping, without involving the reconfiguration of the carry chain within the arithmetic unit. There is a fundamental difference between changing the radix and changing the operation function: the radix determines the comparison threshold of the carry chain, the upper limit of the modulo operation unit's range, and the cascading depth of the borrow logic; these are circuit topology characteristics of the arithmetic unit, not operation mapping characteristics. Therefore, existing reconfigurable array processors cannot process data in parallel with different radixes on the same data path; when non-binary modulo operations are required, multiple binary instructions must still be combined to complete the operation. Summary of the Invention

[0005] The technical problem to be solved by this invention is that the radix of existing arithmetic logic units is fixed in binary and cannot be switched, mixed radix operations require software simulation, and array expansion lacks standardized interconnection schemes.

[0006] To address the aforementioned technical problems, this invention provides a hybrid multi-base arithmetic logic unit array processor. Its core lies in enabling the same hardware to support parallel operations on multiple non-binary bases, joint operations on multiple units across bases, and dynamic switching at runtime through configurable bases, cross-base carry propagation circuits, and runtime base reconfiguration mechanisms.

[0007] The technical solution adopted in this invention is as follows:

[0008] A hybrid multi-base arithmetic logic unit array processor includes: a configurable radix ALU unit array containing multiple ALU units, each unit having an independent programmable arithmetic radix, and each unit including a radix configuration register, a structured opcode decoder, and a carry-shift chain; and a cross-radix carry propagation circuit, wherein when the array performs joint operations of multiple units, the carry value from the lower-order unit to the higher-order unit is determined by the configuration radix of the lower-order unit, and the carry value is not equal to a fixed binary 2. The carry line includes a radix encoding sub-line and a validity flag sub-line, the radix encoding sub-line transmitting the carry value, and its bit width is based on the maximum radix K_max supported by the array. The ceil(log2(K_max)) bit is defined as the valid flag sub-line, which is a single line and is pulled high when a carry is valid; a cross-radix interconnect network connects the data exchange structure of each ALU unit; a runtime radix reconfiguration controller supports three reconfiguration granularities: global, row or column, and cell level, and includes a finite state machine to complete radix switching between pipeline intervals without consuming additional operation clock cycles; a hybrid radix data decomposition and reconstruction unit decomposes binary inputs according to the radix of each unit at the front end and unifies multiple results into binary output at the back end; and an adaptive pipeline control unit dynamically adjusts the pipeline stages according to the array configuration.

[0009] Furthermore, the cross-radix interconnection network includes a direct interconnection channel between adjacent cells (supporting cross-cell transmission of carry / borrow), a row broadcast bus and a column broadcast bus (supporting simultaneous reception of the same operand by cells in the same row or column), and a diagonal data forwarding path (supporting indirect data exchange between non-adjacent cells).

[0010] Furthermore, the runtime radix reconfiguration controller includes a finite state machine, which includes a global reconfiguration state, a row or column reconfiguration state, and a cell-level reconfiguration state. After receiving an external radix reconfiguration instruction, the finite state machine replaces the value of the radix reconfiguration register of the specified ALU cell with the new configuration value during pipeline intervals. The switching process does not consume additional operation clock cycles.

[0011] Furthermore, the hybrid radix data decomposition and recombination unit includes a front-end decomposer and a back-end recombination unit; the front-end decomposer includes a multi-path radix encoding lookup table corresponding one-to-one with the ALU unit, decomposing the external binary input data into a multi-path hybrid radix representation according to the configured radix of each ALU unit, with each decomposition channel independent of each other, and each unit receiving the valid data segment of its corresponding radix; the back-end recombination unit unifies the operation results of each path into binary output according to their respective radix.

[0012] Furthermore, the adaptive pipeline control unit includes a multi-level pipeline stage register and a stage selector. The stage selector selects an active stage sequence from the pipeline stage register according to the array configuration. The stage sequence includes a data distribution stage (D, distributing input data to each ALU unit), a parallel operation stage (P, each unit independently performs configuration operations), a cross-radix interaction stage (C, inserted when cross-unit data exchange is required), and a reorganized output stage (R, unified output of results).

[0013] Beneficial effects: (1) Configurable radix enables a single chip to support multiple non-binary radix switching, eliminating the limitation of fixed radix after synthesis; (2) Hybrid radix parallel operation converts multi-step software simulation into single-cycle hardware completion, significantly reducing latency; (3) Standardized array interconnect scheme makes the expansion cost linearly related to the number of units, avoiding the quadratic growth of the full interconnect scheme - the design complexity increment is constant for each doubling of the number of units; (4) Runtime reconfiguration supports three granularities, enabling the same hardware to act as an accelerator for different radix structures at different operation stages; (5) Cross-radix carry propagation circuit enables ALU units with different radixes to directly participate in multi-unit joint operation, with the carry value determined by the radix configuration of the source unit and transmitted through the radix-encoded sub-line, eliminating the radix conversion overhead of the carry value in hybrid radix operation, and realizing true cross-radix hardware pipeline. Attached Figure Description

[0014] Figure 1This is the overall architecture diagram of the configurable radix ALU cell array of the present invention (100 is binary data input, 110 is front-end decomposer, 200 is ALU cell array, 210 is cross-radix interconnection network, 211 is carry line, 300 is back-end reassembler, 400 is binary result output, 600 is runtime radix reconfiguration controller, 610 is radix configuration instruction, and 700 is adaptive pipeline control unit).

[0015] Figure 2 The circuit structure diagram of a single configurable radix ALU unit of the present invention is shown below (500 is structured opcode, 510 is structured opcode decoder, 520 is configurable radix ALU core, 521 is radix configuration register, 522 is carry shift chain, 523 is configurable radix operation core, 530 is input data bus, 531 is carry input, and 540 is result output).

[0016] Figure 3 The state transition diagram of the radix reconfiguration controller during runtime of the present invention is as follows (610 is the radix reconfiguration instruction, 600 is the runtime radix reconfiguration controller, 620 is the global reconfiguration, 621 is the row or column reconfiguration, and 622 is the cell-level reconfiguration). Detailed Implementation

[0017] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings.

[0018] Example 1: N×M Configurable Radix Array

[0019] The array consists of N rows × M columns, totaling N × M ALU units (N≥1, M≥1), each unit can be independently configured with a radix. Taking a 3×3 array as an example, the nine units are addressed by rows and columns as ALU00~ALU22, and each unit is independently configured with the required radix. All units perform operations in parallel within the same clock cycle, exchanging intermediate results through a cross-radix interconnect network. Data path: Binary input data → Front-end decomposer segments data according to the radix of each unit → Parallel operation of each unit → Cross-radix interaction (carry transfer between adjacent units) → Back-end reassembler outputs binary results.

[0020] The interface signals of a single ALU unit include: clock CLK, reset RST, opcode OPCODE, input data DATA_IN, output data DATA_OUT, base configuration BASE_CFG, carry input CARRY_IN, carry output CARRY_OUT, and status flag FLAG.

[0021] Example 2: Runtime Radix Reconfiguration

[0022] During processor operation, the radix reconfiguration controller receives an external instruction to switch the radix of a certain ALU unit from its current value to another radix. The switching is completed during pipeline intervals (after the P stage ends and before the C stage begins), without consuming additional clock cycles. Adjacent units sense the radix change and automatically adjust the carry propagation protocol. There are three reconfiguration modes: (1) Global mode - a single instruction unifies all units to the same radix, which is suitable for scenarios where all units need to perform large-scale parallel operations with the same radix; (2) Row or column mode - specifying a row or column to be unified to a certain radix, which is suitable for multi-path independent multi-base pipelines; (3) Unit mode - configuring each unit independently, which is suitable for mixed scenarios where each unit processes different cycle components.

[0023] Example 3: N×M Scalable Array

[0024] The array supports scalability through standardized expansion interfaces—new cells connect to the existing interconnect network along the row or column direction, with addresses uniquely determined by row and column codes, requiring no modification to controller logic or data paths. The row broadcast bus allows cells in the same row to load operands from the same data source in parallel, while the column broadcast bus supports parallel aggregation and output of results.

[0025] The array's expansion interface includes three sets of parallel signal lines: address lines (consisting of row select lines and column select lines, with widths of ceil(log2(N)) bits and ceil(log2(M)) bits respectively), data lines (width equal to the ALU unit's data bit width), and control lines (including read / write enable, clock enable, and synchronous reset). During expansion, the address of the newly added unit is automatically mapped based on its row and column position, requiring no external address allocation—the unit is selected when it detects that both the row select line and column select line match its routing position. After expansion, the runtime radix reconfiguration controller enumerates all in-place units via broadcast; unconnected positions return a zero flag, and the controller automatically excludes them from subsequent operation scheduling. The expansion operation is completed during array idle or reset periods and does not affect the operational status of already configured units.

[0026] Example 4: Structured Opcode Mapping

[0027] Each ALU unit's opcode uses a 3-bit structured encoding (bit 2 distinguishes between arithmetic / bitwise operations, bit 1 distinguishes between size categories), allowing the decoder to directly map the opcode bit positions and implement it through bit selection logic, eliminating the need for storage resources such as lookup tables. The operation instruction extends the target address field before the opcode, with the address field width corresponding to the array size—the address line width of the extended interface is

[0025] , the row address is ceil(log2(N)) bits, the column address is ceil(log2(M)) bits, and the total instruction width is ceil(log2(N)) + ceil(log2(M)) + 3 bits. Taking a 3×3 array as an example: the address field is 4 bits (2 bits for row address, 2 bits for column address), and the instruction is in 7-bit format—bits [6:5] specify the target unit row number, bits [4:3] specify the target unit column number, and bits [2:0] are the operation type encoding. The nine units ALU00~ALU22 are uniquely addressed by row and column addresses. Broadcast writing does not occupy address encoding and is implemented through the row broadcast bus and column broadcast bus described in

[0024] .

[0028] Example 5: Cross-radix carry transfer

[0029] When the array performs multi-cell joint operations (such as multi-precision mixed radix addition), the carry from the lower-order cell to the higher-order cell is no longer fixed as a power of 2, but is determined by the radix of the source cell; the shift radix of the carry shift chain is dynamically provided by the radix configuration register of that cell. The carry propagation protocol is implemented through a dedicated carry line in the interconnect network—each cell outputs a carry signal to the adjacent higher-order cell at the end of the P phase, and the carry value is equal to the radix configured for that cell. During the C phase, when merging the carry, the higher-order cell uses the carry value as an additional addend in its own cell's operation.

[0030] The carry line ( Figure 1 (211) includes a radix-coded sub-line and a valid flag sub-line: the radix-coded sub-line has a width of ceil(log2(K_max)) bits, where K_max is the maximum radix supported by the array, and transmits the current carry value; the valid flag sub-line is a single line, pulled high when a carry is valid. After detecting that the valid flag is pulled high, the carry receiving unit adds the carry value to its local operand, and the overflow value of the addition result is passed as the carry output of this unit to the next higher-order unit, forming a carry propagation chain. The length of the carry propagation chain can be dynamically adjusted according to the array configuration, covering a maximum of N+M-1 units (N is the number of rows, M is the number of columns).

[0031] Example 6: FPGA Synthesis Results

[0032] Using the Tang Primer 20K (GW2A-LV18PG256C8 / I7) as the target platform, the parameterized ALU design underwent multi-radix synthesis testing using the GowinSynthesis tool (V1.9.12.03). The data bit width (WIDTH) was 8. The resource consumption for each radix was as follows: radix 3 consumed 99 LUTs, radix 5 consumed 141 LUTs, radix 8 consumed 64 LUTs, radix 10 consumed 140 LUTs, radix 16 consumed 67 LUTs, radix 32 consumed 61 LUTs, radix 64 consumed 63 LUTs, and radix 127 consumed 205 LUTs. Under each configuration, the number of registers equaled the data bit width (8 when WIDTH=8), the number of basic FPGA logic units was determined by the data bit width (47 when WIDTH=8), and the number of DSP units was always 1 (used for multiplication operations). The overall results show that the LUT consumption of a single configurable radix ALU unit is in the range of 61-205 (radix 2 is the least expensive within the measured radix range; radix excluding powers of 2 consumes more due to the increased logic depth of the comparison / modulus operation circuit). Radix configuration itself does not increase hardware overhead. Taking a 2×2 array as an example (four units configured as radix 5 / 3 / 6 / 10 respectively, including cross-radix carry chains, with WIDTH=8 per unit), the overall consumption is 437 LUTs, 36 registers, 87 FPGA basic logic units, and 1 DSP unit, accounting for approximately 3% of the total logic resources. The array size can be expanded to 3×3 and larger, and larger-scale arrays can be cascaded with multiple FPGAs. The above resource consumption indicates that the multi-radix array processor of this invention can be fully deployed on low-cost FPGAs without the need for high-performance processes or dedicated instruction set support—the manufacturing cost threshold is low, and mature processes such as 0.35μm and above can support it, providing hardware-level acceleration for non-binary arithmetic operations. In terms of timing performance, the synthesis process did not report any setup or hold time violations (no explicit clock frequency constraints were set).

[0033] Example 7: Parallel Processing of Hybrid Features

[0034] This embodiment provides an acceleration scheme for applying configurable radix arrays to parallel processing of hybrid features. In hybrid feature data, different channels have different numerical statistical characteristics—high-amplitude channels require a larger data range, medium-amplitude channels need a balance between range and accuracy, and low-amplitude channels focus on detail accuracy. Uniform bit-width processing leads to computational bottlenecks in high-amplitude channels and wasted bit-width in low-amplitude channels. This embodiment configures each ALU unit of the array as a dedicated processing channel with different radixes. The front-end decomposer distributes the input data to the corresponding unit according to the amplitude range, and each unit processes independently according to its configured radix. A cross-radix interconnection network undertakes the weighted summation task when the data from each channel enters the fusion stage. In parallel processing of hybrid features, multi-radix parallel processing effectively reduces single-frame processing latency.

[0035] This invention can be applied to: (1) Multi-radix arithmetic acceleration - supporting parallel processing of multiple non-binary arithmetic operations on a single chip; (2) Dynamic precision adjustable data path - dynamically switching the radix according to the computational requirements to balance computational precision and resource consumption; (3) Hybrid modular collaborative computing - arithmetic units of multiple radixes work collaboratively in the same data stream to eliminate the data transport overhead of cross-modal conversion; (4) Reconfigurable parallel processing - the same hardware can be reconfigured into a parallel accelerator with different radix structures at different computational stages.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A hybrid multi-level arithmetic logic unit array processor, characterized in that, Include: A configurable radix ALU cell array, consisting of multiple ALU cells, each ALU cell containing a radix configuration register that stores the radix configuration value of the cell; A cross-radix carry propagation circuit connects the multiple ALU units. When the ALU unit array performs multi-unit joint operations, the carry value from the lower unit to the higher unit is determined by the radix configuration value of the lower unit, and the carry value is not equal to a fixed binary 2. The cross-radix carry propagation circuit includes carry lines connecting adjacent ALU units. Each carry line includes a radix encoding sub-line and a valid flag sub-line. The radix encoding sub-line transmits the carry value, and its bit width is determined as ceil(log2(K_max)) bits according to the maximum radix K_max supported by the array. The valid flag sub-line is a single line that is pulled high when the carry is valid. After detecting that the valid flag is pulled high, the carry receiving unit adds the carry value to the local operand. The overflow value of the addition result is passed as the carry output of this unit to the next higher unit, forming a carry propagation chain. The mixed radix data decomposition and recombination unit includes a front-end decomposer and a back-end recombination unit. The front-end decomposer includes a multi-path radix encoding lookup table corresponding one-to-one with each ALU unit. The encoding method and output bit width of each lookup table are independently determined according to the configured radix of the corresponding ALU unit. The decomposition channels are independent of each other, and the external binary input data is decomposed into a multi-path mixed radix representation according to the configured radix of each ALU unit. The back-end recombination unit unifies the operation results of each path into binary output according to their respective radix. The runtime radix reconfiguration controller includes a finite state machine, which includes a global reconfiguration state, a row or column reconfiguration state, and a cell-level reconfiguration state. After receiving an external radix reconfiguration instruction, the finite state machine enters the corresponding state and replaces the radix reconfiguration register value of the specified ALU cell or cell group.

2. The processor according to claim 1, characterized in that, It also includes a cross-radius interconnection network that connects the data exchange paths between the multiple ALU units, including direct interconnection channels between adjacent units, row broadcast buses, column broadcast buses, and diagonal data forwarding paths.

3. The processor according to claim 1, characterized in that, The runtime cardinality reconfiguration controller supports three configuration granularities: global reconfiguration—all cells have a unified cardinality; row or column reconfiguration—cells in the same row or column have a unified cardinality; and cell-level reconfiguration—each cell has an independent cardinality.

4. The processor according to claim 1, characterized in that, The runtime radix reconfiguration controller replaces the value of the radix configuration register of a specified ALU unit with a new configuration value during pipeline gaps. The pipeline gap is the idle time window from the completion of the parallel computing phase to the start of the next pipeline phase. The switching process does not consume additional computing clock cycles.

5. The processor according to claim 1, characterized in that, The length of the carry propagation chain is dynamically adjusted according to the array configuration, and the maximum coverage length is the number of rows plus the number of columns of the array minus one.

6. The processor according to claim 1, characterized in that, Each ALU cell in the configurable radix ALU cell array further includes: The structured opcode decoder uses decoding logic that directly maps the positions of external opcode bits, and achieves decoding without the need for storage resources such as lookup tables through bit selection logic; The carry shift chain is dynamically provided by the radix configuration register of this unit.

7. The processor according to claim 1, characterized in that, It also includes an adaptive pipeline control unit, which includes a multi-level pipeline stage register and a stage selector. The stage selector selects the active stage sequence from the pipeline stage register according to the array configuration. The stages include: a data distribution stage—distributing input data to each ALU unit; a parallel operation stage—each unit independently performs configuration operations; a cross-radix interaction stage—inserted when cross-unit data exchange is required; and a recombined output stage—outputting the results uniformly.

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