Instruction execution method and apparatus, instruction translation method and apparatus, device, and medium

Abstract

The application discloses an instruction execution method and device, an instruction translation method and device, equipment and a medium. The instruction execution method comprises the following steps: obtaining target code, wherein the target code is obtained by inserting a preset instruction sequence before a first target instruction in the process of translating source code, and the first target instruction is used for requesting a condition bit; in the process of running the target code, in response to the fact that an instruction to be executed in the target code is the preset instruction sequence, determining a target storage address based on a target calculation type of a second target instruction, the second target instruction being used for requesting a condition bit; acquiring a target preset instruction having an association relationship with the target calculation type from the preset instruction sequence based on the target storage address; and running the target preset instruction to obtain a target condition bit requested by the first target instruction. The application solves the technical problem that the execution efficiency of the translated code is low due to the simulation of the condition bit calculation in the code translation process.

Description

Technical Field

[0001] This application relates to the field of processors, and more specifically, to an instruction execution method and apparatus, an instruction translation method and apparatus, a device, and a medium. Background Technology

[0002] Some CPU (Central Processing Unit) architectures, such as ARM and x86, have hardware condition bits. These condition bits directly reflect the state after instruction execution, such as carry, overflow, and zero, thereby improving conditional branching and data processing flow. However, when running code on architectures without hardware condition bit support, a binary translator is typically needed to simulate the condition bits.

[0003] When simulating condition bits using a binary translator, deferred computation can be achieved through function calls. This involves encapsulating complex condition bit calculations within a function. When an instruction to generate condition bits is encountered, the condition bits are not immediately calculated; instead, the necessary information for calculation is recorded, and the calculation is only performed when subsequent instructions require these condition bits. However, this method introduces additional function call overhead, including parameter passing, return value handling, and saving and restoring register states before and after the call. This reduces the execution efficiency of the translated code, impacting overall computational performance and user experience.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This application provides an instruction execution method and apparatus, an instruction translation method and apparatus, a device, and a medium to at least solve the technical problem that simulating condition bit calculations during code translation leads to low execution efficiency of the translated code.

[0006] According to one aspect of the embodiments of this application, an instruction execution method is provided, comprising: obtaining target code, wherein the target code is obtained by inserting a preset instruction sequence before a first target instruction during the translation of source code, the first target instruction being used to request the use of a condition bit, the preset instruction sequence containing at least a plurality of preset instructions, different preset instructions being used to perform condition bit calculations based on different computation types, and the processor architecture corresponding to the source code being different from the processor architecture corresponding to the target code; during the execution of the target code, in response to the preset instruction sequence being executed in the target code, determining a target storage address based on the target computation type of a second target instruction, wherein the second target instruction is used to request the generation of a condition bit; obtaining a target preset instruction associated with the target computation type from the preset instruction sequence based on the target storage address; and executing the target preset instruction to obtain the target condition bit requested by the first target instruction.

[0007] According to another aspect of the embodiments of this application, an instruction translation method is also provided, comprising: in the process of translating source code into target code, in response to the instruction to be translated in the source code being a first target instruction, obtaining a preset instruction sequence, wherein the first target instruction is used to request the use of a condition bit, the preset instruction sequence is used to perform condition bit calculations based on multiple calculation types, and the processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code; translating the instruction to be translated to obtain the translated instruction, and inserting the preset instruction sequence before the translated instruction; wherein the target code is executed by a second processor using the instruction execution method of the above embodiments.

[0008] According to another aspect of the embodiments of this application, an instruction execution apparatus is provided, comprising: a code acquisition module, configured to acquire target code, wherein the target code is obtained by inserting a preset instruction sequence before a first target instruction during the translation of source code, the first target instruction being used to request the use of a condition bit, the preset instruction sequence containing at least a plurality of preset instructions, different preset instructions being used to perform condition bit calculations based on different computation types, and the processor architecture corresponding to the source code being different from the processor architecture corresponding to the target code; a determination module, configured to, during the execution of the target code, determine a target storage address based on the target computation type of a second target instruction in response to the fact that the instruction to be executed in the target code is a preset instruction sequence, wherein the second target instruction is used to request the generation of a condition bit; an instruction acquisition module, configured to acquire a target preset instruction associated with the target computation type from the preset instruction sequence based on the target storage address; and a running module, configured to run the target preset instruction to obtain the target condition bit requested by the first target instruction.

[0009] According to another aspect of the embodiments of this application, an instruction translation apparatus is also provided, comprising: an acquisition module, configured to, during the process of translating source code into target code, acquire a preset instruction sequence in response to the instruction to be translated in the source code being a first target instruction, wherein the first target instruction is used to request the use of a condition bit, the preset instruction sequence is used to perform condition bit calculations based on multiple calculation types, and the processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code; and a translation module, configured to translate the instruction to be translated to obtain the translated instruction, and insert the preset instruction sequence before the translated instruction; wherein the target code is executed by a second processor using the instruction execution method of the above embodiments.

[0010] According to another aspect of the embodiments of this application, a computing device is also provided, including: a memory storing an executable program; and a processor for running the program, wherein the program executes the methods in various embodiments of this application when it runs.

[0011] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein the methods of various embodiments of this application are implemented when the executable program is executed by a processor.

[0012] According to another aspect of the embodiments of this application, a computer program product is also provided, including computer instructions that, when executed by a processor, implement the methods in various embodiments of this application.

[0013] According to another aspect of the embodiments of this application, a computer program product is also provided, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods in various embodiments of this application.

[0014] According to another aspect of the embodiments of this application, a computer program is also provided, which, when executed by a processor, implements the methods of the various embodiments of this application.

[0015] In this embodiment, during the execution of the target code, in response to the pre-defined instruction sequence in the target code being executed, a target storage address is determined based on the target computation type of the second target instruction; based on the target storage address, a target pre-defined instruction associated with the target computation type is obtained from the pre-defined instruction sequence; and the target pre-defined instruction is executed to obtain the target condition bit requested by the first target instruction. It is noteworthy that during the code translation stage, a pre-defined instruction sequence containing multiple pre-defined instructions is inserted before the first target instruction requesting the use of the condition bit. Different pre-defined instructions are used for pre-defined instructions that perform condition bit calculations based on different computation types. This allows the target storage address to be found based on the target computation type during target code execution, and the condition bit to be calculated delayed based on the obtained target pre-defined instructions, without needing to call functions. This avoids inefficient operations such as function calls, improves code execution efficiency, and solves the technical problem of low execution efficiency of translated code due to simulated condition bit calculations during code translation.

[0016] It is worth noting that the general description above and the detailed description that follow are merely for illustrative purposes and do not constitute a limitation on this application. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 This is a hardware architecture block diagram of a RISC-V system used to implement instruction execution methods;

[0019] Figure 2 Is it using the above? Figure 1 The diagram shows a System-on-Chip (SOC) based on the RISC-V architecture.

[0020] Figure 3 This is a flowchart of an instruction execution method according to an embodiment of this application;

[0021] Figure 4 This is a flowchart of an instruction translation method according to an embodiment of this application;

[0022] Figure 5 This is a flowchart illustrating an optional method of using a jump table for jumps according to an embodiment of this application;

[0023] Figure 6 This is a schematic diagram of an instruction execution device according to an embodiment of this application;

[0024] Figure 7 This is a schematic diagram of an instruction translation device according to an embodiment of this application;

[0025] Figure 8 This is a structural block diagram of a computing device according to an embodiment of this application. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows:

[0029] Condition bits: Condition bits are a set of flags in some CPU architectures used to indicate the result status of the most recently executed instruction, thereby allowing subsequent instructions to perform conditional branching or other operations based on these statuses.

[0030] Delayed computation: a method of simulating condition bit computation. Its main idea is to record the calculation method of condition bit computation and the values ​​involved in the calculation. Unlike direct computation, it only performs calculations when the condition bits are needed, thus avoiding unnecessary condition bit computations.

[0031] Inlining: Embedding a block of code or a sequence of assembly code directly into the location where it is called, instead of executing it through a function call. This technique can reduce the overhead of function calls and improve program execution efficiency, but it can increase the size of the code.

[0032] NZCV: The collective name for the four condition bits in the ARM architecture. N stands for Negative Flag, indicating whether the result is negative; Z stands for Zero Flag, indicating whether the result is zero; C stands for Carry Flag, indicating carry in unsigned arithmetic; and V stands for Overflow Flag, indicating overflow in signed arithmetic.

[0033] The host function is a function written on the local architecture during binary translation, which is different from the code obtained by translating the instruction set of the target architecture.

[0034] According to an embodiment of this application, an instruction execution method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0035] The method embodiment provided in Embodiment 1 of this application can be executed in a mobile terminal, computer terminal, or similar computing device. The computing device can employ a multi-core processor architecture, which may be RISC (Reduced Instruction Set Computing), ARM (Advanced RISC Machine), x86, etc., but is not limited to these. The processor can integrate multiple processing cores, each with its own independent L1 cache, sharing a larger L2 cache, and a unified LLC (Last Level Cache). The multi-level cache adopts a set-associative architecture, where both the L2 cache and LLC are highly configurable to adapt to different types of applications and workloads.

[0036] For example, taking the RISC-V architecture as an example, Figure 1 This is a hardware architecture block diagram of a RISC-V system used to implement instruction execution methods. (Example:) Figure 1As shown, the RISC-V system can be divided into the following layers from bottom to top: Reduced Instruction Set Architecture 101 (including the basic instruction set 101-1 and extended instruction set 101-2), hardware layer 102 (including processor 102-1, peripheral hardware circuits 102-2, etc.), interface layer 103, operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), middleware and library layer 105 (including system library 105-1, API 105-2 and middleware services 105-3), and application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system also includes a toolchain 107 that runs from the underlying hardware to the application layer. This toolchain may include compilers and assemblers 107-1, linkers 107-2, debuggers 107-3, simulators and emulators 107-4, integrated development environments 107-5, hardware description language tools 107-6, performance analysis tools 107-7, and version control systems 107-8, etc.

[0037] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the basic instruction set and the extended instruction set. The basic instruction set represents the basic integer instruction set, such as RV32I and RV64I, while the extended instruction set can be floating-point, atomic operations, compressed instructions, etc.

[0038] Interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution units, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0039] The operating system layer 104 sits above the hardware, providing a hardware abstraction layer and management mechanisms, enabling applications to interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, and more.

[0040] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while middleware can provide complex services such as network communication and graphical user interfaces.

[0041] The application layer 106 utilizes the functions and services provided by the lower layer to implement specific application logic. These applications can be command-line tools, graphical interface applications, server-side services, etc.

[0042] Toolchain 107 is a key component connecting the underlying hardware to the upper-level software. The various tools in toolchain 107 play a role at different levels to support the entire process from hardware design to software development, ensuring the coherence and effectiveness of the entire system design.

[0043] It should be noted that the layered design of the RISC-V architecture allows for decoupling between different layers, enabling each layer to be developed and optimized independently.

[0044] In one alternative embodiment, Figure 2 Is it using the above? Figure 1 The diagram shows a System-on-Chip (SOC) based on the RISC-V architecture. Figure 2 As shown, the SOC contains at least one RISC-V core 202 (only one is shown in the figure). The RISC-V core 202 is connected to peripheral devices via bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0045] Under the aforementioned operating environment, this application provides the following: Figure 3 The instruction execution method shown. This method can... Figure 3 This is a flowchart of an instruction execution method according to an embodiment of this application. Figure 3 As shown:

[0046] Step S302: Obtain target code. The target code is obtained by inserting a preset instruction sequence before the first target instruction during the translation of the source code. The first target instruction is used to request the use of condition bits. The preset instruction sequence contains at least a number of preset instructions. Different preset instructions are used to perform condition bit calculations based on different calculation types. The processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code.

[0047] The source code in the above steps can be binary code that runs on a specific CPU architecture, such as ARM or x86, but is not limited to these. The target code in the above steps can be binary code that runs on another CPU architecture, such as RISC-V (Reduced Instruction Set Computing-Fifth version), but is not limited to these. Because the two CPU architectures are different, cross-architecture code compatibility can be achieved by translating the source code. For example, a translator can be used to translate the source code into target code; the source code can be used as the input to the translator, and the output of the translator can be used as the target code.

[0048] The first target instruction in the above steps is the instruction that needs to update the condition bits after execution. The purpose of the instruction execution method in this application is to ensure the correct calculation of the condition bits and to achieve delayed calculation of the condition bits without calling a function.

[0049] The preset instruction sequence in the above steps is a set of instructions used to calculate condition bits corresponding to various calculation types. An instruction sequence can be pre-constructed and stored in the memory space corresponding to the target memory address. After the instructions to be translated are translated, the preset instruction sequence is embedded into the translated code to avoid the overhead of function calls.

[0050] The condition bits in the above steps are a set of flags used to indicate the result status of the most recently executed instruction. Condition bits may include, but are not limited to, Negative Flag, Zero Flag, Carry Flag, and Overflow Flag.

[0051] In one alternative embodiment, to achieve delayed computation of the condition bit, and considering the limited types of computations typically involved in condition bit computation, multiple preset instructions can be pre-constructed. Different preset instructions can be used to perform condition bit computations based on different computation types. Due to the randomness of computations in the source code, it cannot be certain which instruction generated the condition bit during translation. Therefore, during the translation of the source code into target code, a preset instruction sequence containing multiple preset instructions can be inserted into the target code.

[0052] After binary translation to obtain the target code, the target code can be stored in a pre-defined storage space. When the processor needs to execute the target code, it can directly read it from this storage space. Alternatively, when the processor needs to execute the target code, it can receive target code sent by other devices.

[0053] Step S304: During the execution of the target code, in response to the pre-defined instruction sequence in the target code, the target storage address is determined based on the target calculation type of the second target instruction, wherein the second target instruction is used to request the generation of condition bits.

[0054] The instructions to be executed in the above steps are the instructions in the target code that are waiting to be executed by the processor, and may include, but are not limited to, arithmetic instructions, logical instructions, conditional branch instructions, etc.

[0055] The target calculation type in the above steps refers to the type of operation involved when the second target instruction is executed. For example, the target calculation type can be addition, subtraction, bitwise operations, etc. The calculation logic of the condition bits differs depending on the target calculation type.

[0056] The target storage address in the above steps is a pre-defined address used to store preset instructions related to different computation types. When the instruction to be executed is a preset instruction sequence, the target storage address can be found according to the target computation type of the second target instruction to obtain the target preset instruction corresponding to the target computation type.

[0057] In one optional embodiment, a pre-constructed instruction sequence containing a jump table can be built in advance. The jump table is a data structure used to store the mapping relationship between computation types and storage addresses. During the execution of the target code, when the instruction to be executed is identified as a pre-constructed instruction sequence, a second target instruction can be parsed to obtain its computation type, which is then used as the target computation type. Alternatively, the pre-stored computation type of the second target instruction can be read and used as the target computation type. Then, based on the target computation type, the storage address corresponding to the target computation type is determined from the jump table, and this storage address is used as the target storage address.

[0058] In another optional embodiment, a pre-constructed jump table can be used to store the calculation type and its corresponding offset address. During the execution of the target code, when it is identified that the instruction to be executed is a preset instruction sequence, the second target instruction can be parsed, and its calculation type can be used as the target calculation type; alternatively, the pre-stored calculation type of the second target instruction can be read and used as the target calculation type. Based on the target calculation type, the offset address corresponding to the target calculation type is determined from the jump table, and then the target storage address is determined according to the base address of the jump table and the offset address corresponding to the target calculation type.

[0059] In another alternative embodiment, a mapping table, such as a hash table, can be created. The key is set to the target computation type, and the value is set to the starting address of the target preset instruction, i.e., the target storage address. During the execution of the target code, when it is identified that the instruction to be executed is a preset instruction sequence, the second target instruction can be parsed, and its computation type can be used as the target computation type. Alternatively, the computation type of the pre-stored second target instruction can be read and used as the target computation type. Then, the target computation type of the instruction to be executed is extracted as the key, and the mapping table is queried using the key to obtain the target storage address.

[0060] Step S306: Based on the target storage address, obtain the target preset instruction that is related to the target computing type from the preset instruction sequence.

[0061] In one optional embodiment, a jump method can be used to determine the assembly instruction corresponding to the target computing type from the preset instruction sequence, and the assembly instruction can be compiled to obtain the target preset instruction that is associated with the target computing type.

[0062] In another alternative embodiment, a jump method can be used to directly obtain the target preset instruction that is related to the target calculation type from the preset instruction sequence.

[0063] Step S308: Execute the target preset instruction to obtain the target condition bit requested by the first target instruction.

[0064] In one optional embodiment, a target preset instruction can be executed to calculate the condition bits according to the calculation logic described in the target preset instruction, thereby obtaining the target condition bit, that is, the state of the condition bit. Specifically, the state of the condition bit may include the state of the negative number flag bit, the zero flag bit, the carry flag bit, and the overflow flag bit.

[0065] In this embodiment, during the execution of the target code, in response to the pre-defined instruction sequence in the target code being executed, a target storage address is determined based on the target computation type of the second target instruction; based on the target storage address, a target pre-defined instruction associated with the target computation type is obtained from the pre-defined instruction sequence; and the target pre-defined instruction is executed to obtain the target condition bit requested by the first target instruction. It is noteworthy that during the code translation stage, a pre-defined instruction sequence containing multiple pre-defined instructions is inserted before the first target instruction requesting the use of the condition bit. Different pre-defined instructions are used for pre-defined instructions that perform condition bit calculations based on different computation types. This allows the target storage address to be found based on the target computation type during target code execution, and the condition bit to be calculated delayed based on the obtained target pre-defined instructions, without needing to call functions. This avoids inefficient operations such as function calls, improves code execution efficiency, and solves the technical problem of low execution efficiency of translated code due to simulated condition bit calculations during code translation.

[0066] In one embodiment of this application, determining the target storage address based on the target computation type of the second target instruction includes: obtaining the base address of a jump table contained in a preset instruction sequence, wherein the jump table stores a mapping relationship between different computation types and different offset addresses, and the offset address is used to characterize the offset between the storage address storing the corresponding target preset instruction and the base address; obtaining the target offset address corresponding to the target computation type from the jump table; and adding the base address and the target offset address to obtain the target storage address.

[0067] The jump table in the above steps is a data structure used to determine the target storage address of the preset instruction corresponding to the target computation type based on the target computation type of the second target instruction. By querying the jump table, the target preset instruction required by the target computation type can be quickly located without complex conditional branch judgments, thereby improving code execution efficiency.

[0068] The base address of the jump table in the above steps is the starting position of the jump table in memory, and it is the common reference point for the entries in the jump table.

[0069] The offset address in the above steps is used to point to the relative position of the target preset instruction. The offset is relative to the base address of the jump table and is used to calculate the target memory address of the target preset instruction.

[0070] The target offset address in the above steps is the offset address corresponding to the target calculation type in the jump table, which points to the target preset instruction corresponding to the target calculation type.

[0071] In an optional embodiment, after constructing the jump table, lookup is performed using relative addresses instead of absolute addresses. Therefore, the jump table can be stored anywhere. In this application, the jump table can be inserted into a preset instruction sequence, thereby achieving inlining of the preset instruction sequence and inserting it into the target code. When it is identified that the instruction to be executed is a preset instruction sequence and the target calculation type of the second target instruction is determined, the target calculation type can be used as an index to query the jump table and determine the target offset address corresponding to the target calculation type from multiple offset addresses in the jump table. Adding the base address of the jump table to the target offset address yields the absolute address where the target preset instruction is stored, i.e., the target storage address.

[0072] Using a jump table that stores offset addresses to determine the storage location of the target preset instruction and obtain the target preset instruction avoids the extra overhead of absolute address jumps and function calls, further optimizing the execution efficiency of the code.

[0073] In one embodiment of this application, obtaining the target offset address corresponding to the target calculation type from the jump table includes: determining the table entry offset address based on the identification information corresponding to the target calculation type, wherein the table entry offset address is used to characterize the offset between the target table entry storing the target offset address in the jump table and the base address; adding the base address and the table entry offset address to obtain the target table entry address, wherein the target table entry address is used to characterize the address of the target table entry in the jump table; and reading the target offset address from the jump table based on the target table entry address.

[0074] The identification information in the above steps is a unique identifier associated with the calculation type. It can be the table entry number corresponding to the calculation type or an index, used to locate the table entry corresponding to the target calculation type in the jump table.

[0075] The offset address of the entry in the above steps is the offset of the target entry in the jump table relative to the base address of the jump table. Each entry in the jump table stores the offset address corresponding to a calculation type, while the target entry stores the target offset address corresponding to the target calculation type. The entry offset address is added to the base address of the jump table to obtain the target entry address corresponding to the target entry.

[0076] The target entry address in the above steps is the absolute address of the target entry in the jump table. Based on the target entry address, the target entry can be found in the jump table, and the target offset address corresponding to the target calculation type can be obtained from the target entry.

[0077] In one optional embodiment, predefined encoding rules can be used to determine the identification information corresponding to the target calculation type. For example, the predefined encoding rules may include: setting the identification information to 0 when the target calculation type is addition, setting the identification information to 1 when the target calculation type is subtraction, and so on.

[0078] Then, based on the predefined mapping relationship between the identification information and the table entry offset address, the table entry offset address corresponding to the target table entry is determined according to the identification information corresponding to the target calculation type. For example, assuming that each table entry in the jump table occupies a fixed number of bytes, the identification information can be regarded as the index of the table entry in the jump table, and the table entry offset address is obtained by multiplying the index by the table entry size.

[0079] Add the base address of the jump table to the offset address of the entry to obtain the target entry address. The target entry address directly points to the entry in the jump table that stores the target offset address. Then, by accessing the target entry at the target entry address, the target offset address can be read.

[0080] By identifying the relative position of the target entry in the jump table using the identification information, it is ensured that the target preset instruction corresponding to the target calculation type can be accurately obtained, reducing the probability of error location and thus improving the accuracy of code execution.

[0081] In one embodiment of this application, the method further includes: constructing assembly code containing assembly instructions of multiple calculation types; and constructing a jump table based on the storage addresses of different assembly instructions in the assembly code.

[0082] The assembly instructions described above are used to directly control computer hardware. They consist of an opcode and operands. The opcode instructs the processor to perform a specific operation, while the operands provide the parameters for that operation. Assembly instructions can include, but are not limited to, data movement instructions, arithmetic operation instructions, logical operation instructions, and control flow instructions.

[0083] The assembly code in the above steps is program code composed of a series of assembly instructions.

[0084] The storage addresses of the different assembly instructions in the above steps are the addresses where the assembly instructions are loaded into memory after the assembly code is compiled and linked. In memory, each assembly instruction has a unique storage address, which is the offset of the assembly instruction relative to the starting point of the assembler. Assembly instructions of different calculation types occupy different addresses in memory.

[0085] In one alternative embodiment, assembly code containing assembly instructions for multiple computation types is written using assembly language. Then, an assembler is used to compile the written assembly code into machine code. During the compilation process, the layout of the assembly code is parsed, the memory allocation of the assembly instructions for multiple computation types is determined, and the starting position of the assembly instructions for multiple computation types, i.e., the storage address of different assembly instructions in the assembly code, is recorded.

[0086] Next, a jump table is created, selecting a fixed memory location as the base address of the jump table. Simultaneously, the difference between the storage address of the assembly instructions of different calculation types in the assembly code and the base address of the jump table is calculated to obtain the offset address. The mapping relationship between different calculation types and different offset addresses is stored in the jump table, thus completing the construction of the jump table.

[0087] Assembly code containing assembly instructions for various calculation types is pre-built, and a jump table is constructed based on the position of the assembly instructions in the assembly code. This allows the target preset instruction to be retrieved through the jump table, improving the efficiency of instruction retrieval and the smoothness of program execution.

[0088] In one embodiment of this application, obtaining a target preset instruction that is associated with a target computing type from a preset instruction sequence based on a target storage address includes: obtaining a target assembly instruction that is associated with a target computing type from a preset instruction sequence based on a target storage address.

[0089] In one optional embodiment, after determining the target memory address, the translator can read target assembly instructions related to the target computation type from the assembly code already loaded into memory, based on the target memory address. Specifically, the translator can first obtain the length of the target assembly instructions, then start reading the target assembly instructions from the target memory address, and complete the reading based on the length of the target assembly instructions to obtain the complete target assembly instructions.

[0090] Then, an inline compiler or assembler can be used to compile the target assembly instructions, converting them into binary machine code to obtain the target preset instructions.

[0091] By compiling the target assembly instructions, target preset instructions closely related to the target calculation type are generated, ensuring the accuracy and applicability of the target preset instructions, improving the accuracy and execution efficiency of condition bit calculation, and thus optimizing the quality of the translated code.

[0092] In one embodiment of this application, compiling target assembly instructions to obtain target preset instructions includes: compiling the target assembly instructions to obtain compilation instructions; disassembling the compilation instructions to obtain disassembly instructions; and determining the compilation instructions as target preset instructions when the disassembly instructions are the same as the target assembly instructions.

[0093] The compilation instructions in the above steps are binary instructions generated when assemblies are converted into machine code in binary format. These compilation instructions can be executed directly by the processor.

[0094] The disassembly instructions in the above steps are instructions obtained by disassembling the compilation instructions. Disassembly is the reverse operation of the compilation process, that is, the process of converting machine code back into assembly code.

[0095] In one alternative embodiment, an assembler is used to parse the target assembly instructions, understand their semantics and operations, and convert them into equivalent machine code instructions based on the instruction set specification of the second format code, thereby obtaining the compiled instructions.

[0096] Then, a disassembler is used to parse the compilation instructions, find the instruction name corresponding to the opcode, convert the operand format, and convert the compilation instructions back to their representation in assembly language to obtain the disassembled instructions.

[0097] If the disassembly instructions are the same as the target assembly instructions, it can be determined that there are no errors in the compilation process, and the compilation instructions can correctly implement the condition bit calculation logic required by the target calculation type. In this case, the compilation instructions can be identified as the target preset instructions.

[0098] By compiling and disassembling the target assembly instructions for verification, the matching between the obtained target preset instructions and the target calculation type is ensured, avoiding unnecessary code bloat and thus improving execution efficiency.

[0099] In one embodiment of this application, running a target preset instruction to obtain a target condition bit requested by a first target instruction includes: obtaining an operand corresponding to a second target instruction; running the target preset instruction; and generating the target condition bit based on the operand.

[0100] The operands in the above steps are numerical values ​​or variables involved in the calculation. Operands may include, but are not limited to, register values, memory addresses, and immediate values. In an optional embodiment, the operands and the target calculation type may be stored in the same register.

[0101] In one optional embodiment, during the translation of source code into target code, a translator can be used to translate the second target instruction to obtain the translated instruction. Simultaneously, the operands corresponding to the second target instruction are parsed to determine the register values, memory addresses, etc., involved in the calculation, i.e., the operands are determined. Then, the determined operands and the target calculation type of the second target instruction are saved to a set of predefined target registers so that the information in the target registers can be quickly accessed for condition bit calculations.

[0102] By obtaining the target calculation type and operands, the necessary information is provided for subsequent condition bit calculations, ensuring the accuracy of the condition bit calculations and the coherence of the program logic.

[0103] In one embodiment of this application, a first processor for executing source code has hardware condition bits, while a second processor for executing object code does not have hardware condition bits.

[0104] The hardware condition bits mentioned above are a set of flag bits in the processor status register, used to perform condition bit calculations in hardware. The design of the hardware condition bits allows the processor to execute conditional branches or perform conditional operations based on the state of the condition bits, without requiring additional software implementation for condition bit calculations.

[0105] In one optional embodiment, when a first processor for executing source code has hardware condition bits, but a second processor for executing target code does not, directly executing the target code translated from the source code on the second processor will cause instructions such as branch conditions and loop control that depend on hardware condition bits to malfunction. Therefore, it is necessary to perform the instruction translation method described in the following embodiment, inserting a preset instruction sequence for performing condition bit calculations based on different calculation types before the instruction requesting the use of condition bits, to ensure that the second processor, which does not have hardware condition bits, can correctly execute the target code translated from the source code.

[0106] In cases where the second processor does not support hardware condition bits, condition bit calculations are simulated using software methods, which solves the problem caused by architecture incompatibility and expands the portability of the code.

[0107] In one embodiment of this application, the second processor employs a reduced instruction set architecture.

[0108] The Reduced Instruction Set Computing (RISC) architecture mentioned in the above steps is a processor architecture that uses a simple and small instruction set to improve processor performance, simplify hardware design, and increase code execution efficiency. In RISC architecture, instructions typically have a fixed length. Because the processor does not need additional logic to parse instructions of different lengths, instruction storage and decoding can be simplified.

[0109] By executing the above instruction execution method, efficient and accurate condition bit simulation can be achieved even on a reduced instruction set architecture (RISC) lacking hardware condition bit support, thereby improving the program's running efficiency on RISC architecture.

[0110] This application also provides a method for translating instructions. Figure 4 This is a flowchart of an instruction translation method according to an embodiment of this application. Figure 4 As shown:

[0111] In step S402, during the process of translating the source code into target code, in response to the instruction to be translated in the source code being a first target instruction, a preset instruction sequence is obtained. The first target instruction is used to request the use of condition bits, and the preset instruction sequence is used to perform condition bit calculations based on multiple calculation types. The processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code.

[0112] The instructions to be translated in the above steps are the instructions in the source code that are waiting to be translated by the translator, which may include, but are not limited to, arithmetic instructions, logical instructions, conditional branch instructions, etc.

[0113] In one alternative embodiment, to achieve delayed computation of the condition bit, and considering the limited types of computations typically involved in condition bit computation, multiple preset instructions can be pre-constructed. Different preset instructions can be used to perform condition bit computations based on different computation types. Due to the randomness of computations in the source code, it cannot be certain which instruction generated the condition bit during translation. Therefore, during the translation of the source code into target code, a preset instruction sequence containing multiple preset instructions can be inserted into the target code.

[0114] Furthermore, since the preset instruction sequence contains multiple preset instructions, but the target code only needs one preset instruction corresponding to a specific calculation type during execution, the preset instruction sequence can also include a jump table. The jump table stores the mapping relationship between calculation types and memory addresses, or between calculation types and offset addresses, with different memory addresses corresponding to different preset instructions. Alternatively, a mapping table, such as a hash table, can be created, where the keys represent calculation types and the values ​​represent memory addresses, with different memory addresses corresponding to different preset instructions. Therefore, using a jump table or mapping table, it is possible to query a specific preset instruction based on its address.

[0115] Step S404: Translate the instruction to be translated to obtain the translated instruction, and insert the preset instruction sequence before the translated instruction.

[0116] The target code is executed by the second processor using the instruction execution method described in the above embodiments.

[0117] The translated instructions in the above steps are the instructions obtained after binary translation of the instructions to be translated, and the format of the instructions is the same as that of the target code.

[0118] In one optional embodiment, a translator translates the instructions to be translated in the source code into translated instructions in the target code. Furthermore, the translator inserts a preset instruction sequence before the translated instructions to ensure that the preset instruction sequence is executed first to calculate condition bits before executing the translated instructions. After calculating the condition bits, the translated instructions can directly use the calculated condition bits, avoiding the overhead of function calls and thus improving code execution efficiency.

[0119] In one embodiment of this application, the method further includes: in response to the instruction to be translated being a second target instruction, translating the instruction to be translated to obtain the translated instruction, and determining the operands corresponding to the instruction to be translated, wherein the second target instruction is used to request the generation of condition bits; storing the operands and the target calculation type of the instruction to be translated into a target register, wherein a preset instruction sequence is used to perform condition bit calculation based on the target calculation type and the operands.

[0120] The operands in the above steps are numerical values ​​or variables that participate in the calculation. Operands can include, but are not limited to, register values, memory addresses, immediate values, etc.

[0121] The target register in the above steps is a register used to store the operands of the second target instruction and the target calculation type.

[0122] In one optional embodiment, when the instruction to be translated is a second target instruction, a translator can translate the instruction to obtain the translated instruction. Simultaneously, the operands of the instruction to be translated are parsed to determine the register values, memory addresses, etc., involved in the calculation, i.e., the operands are determined. Then, the determined operands and the target calculation type of the second target instruction are saved to a set of predefined target registers. This allows the translator to quickly access the information in the target registers and perform condition bit calculations when branching or other conditional operations need to be performed based on condition bits.

[0123] Storing the calculation type and operand value in the destination register provides the necessary information for subsequent condition bit calculations, ensuring the accuracy of condition bit calculations and the coherence of program logic.

[0124] The following description uses a preferred embodiment as an example. Figure 5 This is a flowchart illustrating an optional method of using a jump table for jumps according to an embodiment of this application, such as... Figure 5 As shown, the process of using a jump table for jumps is as follows:

[0125] Step S502: Obtain the table entry offset address based on the table entry number.

[0126] The entry number is equivalent to the identification information mentioned above. In determining the target preset instruction used for condition bit calculation, the target calculation type corresponding to the second target instruction can be determined first, then the entry number in the jump table corresponding to the target calculation type can be determined, and finally, the entry offset address corresponding to the entry number can be determined.

[0127] Step S504: Obtain the base address of the jump table.

[0128] The jump table base address can be added to the table entry offset address to obtain the address of the target table entry, which is also known as the target table entry address.

[0129] Step S506: Obtain the address of the target table entry.

[0130] Add the jump table base address and the table entry offset address to obtain the target table entry address.

[0131] Step S508: Obtain the content of the target table entry, i.e., the jump offset.

[0132] Access the target entry address to retrieve the target entry content, which is also known as the jump offset. The jump offset is the target offset address mentioned above, which is the offset address of the instruction sequence used for condition bit calculation relative to the jump table.

[0133] Step S510: Obtain the target address for the jump.

[0134] Adding the jump table base address and the jump offset yields the target address for the jump. This target address is also the target memory address mentioned above, which is the absolute address of the instruction sequence used for condition bit calculations.

[0135] Step S512, jump.

[0136] Jump to the target address to obtain the target preset instruction for condition bit calculation.

[0137] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0138] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0139] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, they can also be implemented by hardware. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a processor to execute the methods described in the various embodiments of this application.

[0140] According to embodiments of this application, an instruction execution apparatus for implementing the above-described instruction execution method is also provided, such as... Figure 6 As shown, the device 600 includes: a code acquisition module 602, a determination module 604, an instruction acquisition module 606, and an execution module 608.

[0141] The code acquisition module 602 is used to acquire target code, which is obtained by inserting a preset instruction sequence before the first target instruction during the translation of the source code. The first target instruction is used to request the use of condition bits. The preset instruction sequence contains at least a number of preset instructions, and different preset instructions are used to perform condition bit calculations based on different calculation types. The processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code. The determination module 604 is used to determine the target storage address during the execution of the target code, in response to the fact that the instruction to be executed in the target code is a preset instruction sequence, based on the target calculation type of the second target instruction. The second target instruction is used to request the generation of condition bits. The instruction acquisition module 606 is used to acquire target preset instructions that are associated with the target calculation type from the preset instruction sequence based on the target storage address. The execution module 608 is used to execute the target preset instructions to obtain the target condition bits requested by the first target instruction.

[0142] It should be noted that the code acquisition module 602, determination module 604, instruction acquisition module 606, and execution module 608 correspond to steps S302 to S308 in the above embodiments. The four modules and their corresponding steps implement the same instances and application scenarios, but are not limited to the content disclosed in the above embodiments. It should also be noted that the above modules or units can be hardware or software components stored in memory and processed by one or more processors. These modules can also run as part of a device in the RISC-V system provided in the above embodiments.

[0143] In one embodiment of this application, the determining module is further configured to: obtain the base address of the jump table contained in the preset instruction sequence, wherein the jump table stores the mapping relationship between different calculation types and different offset addresses, and the offset address is used to characterize the offset between the storage address storing the corresponding target preset instruction and the base address; obtain the target offset address corresponding to the target calculation type from the jump table; and add the base address and the target offset address to obtain the target storage address.

[0144] In one embodiment of this application, the determining module is further configured to: determine the table entry offset address based on the identification information corresponding to the target calculation type, wherein the table entry offset address is used to characterize the offset between the target table entry storing the target offset address in the jump table and the base address; add the base address and the table entry offset address to obtain the target table entry address, wherein the target table entry address is used to characterize the address of the target table entry in the jump table; and read the target offset address from the jump table based on the target table entry address.

[0145] In one embodiment of this application, the apparatus further includes a code building module and a table building module.

[0146] The code building module is used to build assembly code containing assembly instructions of multiple calculation types; the table building module is used to build jump tables based on the storage addresses of different assembly instructions in the assembly code.

[0147] In one embodiment of this application, the instruction acquisition module is further configured to: acquire target assembly instructions that are associated with the target computation type from a preset instruction sequence based on the target storage address.

[0148] In one embodiment of this application, the instruction acquisition module is further configured to: compile the target assembly instructions to obtain compilation instructions; disassemble the compilation instructions to obtain disassembly instructions; and determine the compilation instructions as target preset instructions if the disassembly instructions are the same as the target assembly instructions.

[0149] In one embodiment of this application, the running module is further configured to: obtain the operands corresponding to the second target instruction; run the target preset instruction; and generate the target condition bit based on the operands.

[0150] According to an embodiment of this application, an instruction translation apparatus for implementing the above-described instruction translation method is also provided, such as... Figure 7 As shown, the device 700 includes an acquisition module 702 and a translation module 704.

[0151] The acquisition module 702 is used to acquire a preset instruction sequence in response to the instruction to be translated in the source code being a first target instruction during the process of translating the source code into target code. The first target instruction is used to request the use of condition bits, and the preset instruction sequence is used to perform condition bit calculations based on multiple calculation types. The processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code. The translation module 704 is used to translate the instruction to be translated to obtain the translated instruction and insert the preset instruction sequence before the translated instruction. The target code is executed by the second processor using the instruction execution method of the above embodiment.

[0152] It should be noted that the acquisition module 702 and translation module 704 mentioned above correspond to steps S402 to S404 in the above embodiments. The two modules and their corresponding steps implement the same instances and application scenarios, but are not limited to the content disclosed in the above embodiments. It should be noted that the above modules or units can be hardware or software components stored in memory and processed by one or more processors. The above modules can also be part of a device and run in the RISC-V system provided in the above embodiments.

[0153] In one embodiment of this application, the device further includes a determination module and a storage module.

[0154] The determination module is used to translate the instruction to be translated in response to the instruction being a second target instruction, to obtain the translated instruction, and to determine the operands corresponding to the instruction to be translated, wherein the second target instruction is used to request the generation of condition bits; the storage module is used to store the operands and the target calculation type of the instruction to be translated into the target register, wherein a preset instruction sequence is used to perform condition bit calculation based on the target calculation type and the operands.

[0155] It should be noted that the preferred embodiments involved in the above embodiments of this application are the same as the solutions, application scenarios and implementation processes provided in the above embodiments, but are not limited to the solutions provided in the above embodiments.

[0156] Embodiments of this application may provide a computing device. Figure 8 This is a structural block diagram of a computing device according to an embodiment of this application. Figure 8 As shown, the computing device A may include one or more (only one is shown in the figure) processors 802, memory 804 and peripheral interfaces 806, wherein the processors 802, memory 804 and peripheral interfaces 806 are interconnected via a bus 808.

[0157] The memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the methods and apparatus in the embodiments of this application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby implementing the methods in the above embodiments. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to terminal A via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0158] The processor can invoke information and application programs stored in the memory through a transmission device to execute the methods in the various embodiments of this application.

[0159] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0160] Embodiments of this application also provide a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store program code executed by the method provided in the above embodiments.

[0161] Optionally, in this embodiment, the storage medium may be located in any one of the computing devices in the computing device group.

[0162] Optionally, in this embodiment, the computer-readable storage medium includes a stored executable program, wherein the methods of various embodiments of the present application are implemented when the executable program is executed by a processor.

[0163] Embodiments of this application also provide a computer program product. Optionally, in this embodiment, the computer program product may include a computer program that, when executed by a processor, implements the methods provided in the embodiments described above.

[0164] Embodiments of this application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which can be used to store a computer program that, when executed by a processor, implements the method provided in the above embodiments.

[0165] Embodiments of this application also provide a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, it implements the method provided in the above embodiments.

[0166] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0167] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0168] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0169] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0170] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0171] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for executing instructions, characterized in that, include: The target code is obtained by inserting a preset instruction sequence before the first target instruction during the translation of the source code. The first target instruction is used to request the use of a condition bit. The preset instruction sequence contains at least a plurality of preset instructions. Different preset instructions are used to perform condition bit calculations based on different calculation types. The processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code. During the execution of the target code, in response to the pre-defined instruction sequence in the target code, the target storage address is determined based on the target computation type of the second target instruction, wherein the second target instruction is used to request the generation of condition bits; Based on the target storage address, obtain the target preset instruction that is related to the target computing type from the preset instruction sequence; Run the target preset instruction to obtain the target condition bit requested by the first target instruction.

2. The method according to claim 1, characterized in that, Determining the target storage address based on the target computation type of the second target instruction includes: Obtain the base address of the jump table contained in the preset instruction sequence, wherein the jump table stores the mapping relationship between different calculation types and different offset addresses, and the offset address is used to characterize the offset between the storage address storing the corresponding target preset instruction and the base address; Obtain the target offset address corresponding to the target calculation type from the jump table; The base address and the target offset address are added together to obtain the target storage address.

3. The method according to claim 2, characterized in that, The step of obtaining the target offset address corresponding to the target calculation type from the jump table includes: Based on the identification information corresponding to the target calculation type, the table entry offset address is determined, wherein the table entry offset address is used to characterize the offset between the target table entry storing the target offset address and the base address in the jump table; The base address and the table entry offset address are added together to obtain the target table entry address, wherein the target table entry address is used to characterize the address of the target table entry in the jump table; Based on the target entry address, the target offset address is read from the jump table.

4. The method according to claim 2 or 3, characterized in that, The method further includes: Construct assembly code containing assembly instructions for multiple computation types; The jump table is constructed based on the storage addresses of different assembly instructions in the assembly code.

5. The method according to any one of claims 1 to 3, characterized in that, The step of obtaining a target preset instruction that is associated with the target computing type from the preset instruction sequence based on the target storage address includes: Based on the target storage address, obtain the target assembly instructions that are related to the target computing type from the preset instruction sequence; The target assembly instructions are compiled to obtain the target preset instructions.

6. The method according to claim 5, characterized in that, The process of compiling the target assembly instructions to obtain the target preset instructions includes: The target assembly instructions are compiled to obtain compiled instructions; The compilation instructions are disassembled to obtain disassembled instructions; If the disassembly instruction is the same as the target assembly instruction, the compilation instruction is determined to be the target preset instruction.

7. The method according to any one of claims 1 to 3, characterized in that, The step of running the target preset instruction to obtain the target condition bit requested by the first target instruction includes: Obtain the operands corresponding to the second target instruction; Run the target preset instruction and generate the target condition bit based on the operand.

8. The method according to any one of claims 1 to 3, characterized in that, The first processor for executing the source code has hardware condition bits, while the second processor for executing the target code does not have hardware condition bits.

9. The method according to claim 8, characterized in that, The second processor uses a reduced instruction set architecture.

10. A method for translating instructions, characterized in that, include: During the process of translating source code into target code, in response to the instruction to be translated in the source code being a first target instruction, a preset instruction sequence is obtained, wherein the first target instruction is used to request the use of condition bits, the preset instruction sequence is used to perform condition bit calculations based on multiple calculation types, and the processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code. The instruction to be translated is translated to obtain a translated instruction, and the preset instruction sequence is inserted before the translated instruction. The target code is executed by a second processor using the method described in any one of claims 1 to 9.

11. The method according to claim 10, characterized in that, The method further includes: In response to the instruction to be translated being a second target instruction, the instruction to be translated is translated to obtain a translated instruction, and the operands corresponding to the instruction to be translated are determined, wherein the second target instruction is used to request the generation of condition bits; The operands and the target computation type of the instruction to be translated are stored in the target register, wherein the preset instruction sequence is used to perform condition bit calculations based on the operands.

12. An instruction execution device, characterized in that, include: The code acquisition module is used to acquire target code, wherein the target code is obtained by inserting a preset instruction sequence before the first target instruction during the translation of the source code. The first target instruction is used to request the use of condition bits. The preset instruction sequence contains at least a plurality of preset instructions. Different preset instructions are used to perform condition bit calculations based on different calculation types. The processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code. The determination module is used to determine the target storage address based on the target calculation type of the second target instruction in response to the fact that the instruction to be executed in the target code is a preset instruction sequence during the execution of the target code, wherein the second target instruction is used to request the generation of condition bits; The instruction acquisition module is used to acquire a target preset instruction that is associated with the target computing type from a preset instruction sequence based on the target storage address; The execution module is used to execute the target preset instruction to obtain the target condition bit requested by the first target instruction.

13. An instruction translation device, characterized in that, include: The acquisition module is used to acquire a preset instruction sequence in response to the first target instruction being the instruction to be translated in the source code during the process of translating the source code into target code. The first target instruction is used to request the use of a condition bit, and the preset instruction sequence is used to perform condition bit calculations based on multiple calculation types. The processor architecture corresponding to the source code is different from the processor architecture corresponding to the target code. The translation module is used to translate the instruction to be translated, obtain the translated instruction, and insert the preset instruction sequence before the translated instruction; The target code is executed by a second processor using the method described in any one of claims 1 to 9.

14. A computing device, characterized in that, include: Memory, which stores executable programs; A processor for running the program, wherein the program, when running, performs the method according to any one of claims 1 to 11.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored executable program, wherein the executable program, when executed by a processor, implements the method according to any one of claims 1 to 11.

16. A computer program product, characterized in that, Includes computer instructions that, when executed by a processor, implement the method according to any one of claims 1 to 11.

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