A floating point accumulation method and floating point accumulator
Patent Information
- Application Number
- CN202611131224.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-28
- Publication Date
- 2026-10-27
AI Technical Summary
但这种方案会导致加法器资源成倍增加，增加芯片面积和功耗开销
[0028]本申请实施例提供的一种浮点累加方法和浮点累加器，浮点累加方法包括：获取输入数据序列；根据待累加数据项在输入数据序列中的位置索引，将待累加数据项划分为偶数位数据或奇数位数据；将偶数位数据写入当前组奇偶寄存器的偶数寄存器，并将奇数位数据写入当前组奇偶寄存器的奇数寄存器；在输入数据序列中的所有待累加数据项均已写入对应寄存器的情况下，将当前组奇偶寄存器中的偶数寄存器与奇数寄存器的值合并，得到累加结果，其中，前一轮次的合并操作与当前轮次中的首个待累加数据项的写入操作在同一时钟周期内并行执行。应用本申请技术方案，通过奇偶分离累加和双缓冲交替机制，将浮点加法器的流水线延迟隐藏在奇偶交替过程中，同时利用时序重叠使合并操作与数据写入并行，从而在单输出通道批次场景下实现满带宽的累加吞吐量，无需增加额外的浮点加法器。
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Figure CN122985244A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, specifically to a floating-point accumulation method and a floating-point accumulator. Background Technology
[0002] In deep learning accelerators, the accumulator of convolution operations is responsible for cyclically accumulating the output of the multiplication array along the height, width, and input channel directions of the convolution kernel to obtain the pixel value of each pixel in the output feature map.
[0003] Floating-point adders typically employ a multi-stage pipelined design to achieve high operating frequencies. A typical floating-point adder requires exponent alignment and mantissa shifting before performing signed addition of the mantissa, thus requiring a delay of several clock cycles from the adder input to the result being written to the register.
[0004] In existing floating-point accumulator designs, when multiple output channel batches exist, the pipeline delay of the floating-point adder can be hidden by utilizing the rotation between different output channel batches. Specifically, a special first-in-first-out queue is added after the accumulator. Because multiple output channel batches take turns using the adder, the pipeline delay of the adder is naturally hidden, and the input bandwidth is fully utilized.
[0005] However, the aforementioned round-robin mechanism fails when only one output channel batch needs to be accumulated. In this case, after each accumulation operation, several clock cycles must be waited for the result to be obtained and used for the next accumulation, while the next valid data arrives after even fewer clock cycles. This forces the accumulator to frequently insert wait cycles, resulting in wasted input bandwidth and a significant decrease in accumulation throughput.
[0006] Another existing approach is to configure multiple adders for each accumulation channel, avoiding pipeline conflicts through spatial parallelism. However, this approach leads to a significant increase in adder resources, increasing chip area and power consumption. For accumulators with high parallelism, increasing the number of adders means a significant increase in hardware cost. Summary of the Invention
[0007] This application provides a floating-point accumulation method and a floating-point accumulator to eliminate the waiting period caused by pipeline delay and achieve full-bandwidth cyclic accumulation throughput in a single-output channel batch floating-point accumulation scenario without increasing the number of floating-point adders.
[0008] The first aspect of this application provides a floating-point accumulation method, including: Obtain the input data sequence, which belongs to the same output channel batch and includes multiple data items to be accumulated; Based on the position index of the data item to be accumulated in the input data sequence, the data item to be accumulated is divided into even-numbered data or odd-numbered data; Even-numbered data bits are written to the even-numbered register of the current group's parity register, and odd-numbered data bits are written to the odd-numbered register of the current group's parity register. The parity register includes a first group of parity registers and a second group of parity registers. In each round of accumulation, one group of parity registers is selected as the current group. The accumulation in adjacent rounds is performed alternately on the first group of parity registers and the second group of parity registers, and the adjacent rounds overlap by a preset number of clock cycles in timing. When all data items to be accumulated in the input data sequence have been written to their corresponding registers, the values of the even registers and odd registers in the current group are merged to obtain the accumulation result. The merging operation in the previous round and the writing operation of the first data item to be accumulated in the current round are executed in parallel within the same clock cycle.
[0009] In this way, by using parity-even separation accumulation and double buffering alternation mechanism, the pipeline delay of the floating-point adder is hidden in the parity-even alternation process. At the same time, timing overlap is used to make the merging operation and data writing parallel, thereby achieving full bandwidth accumulation throughput in single-output channel batch scenarios without the need to add an additional floating-point adder.
[0010] In one implementation, writing even-numbered data bits to the even-numbered register of the current group's parity register and writing odd-numbered data bits to the odd-numbered register of the current group's parity register includes: For the first data item to be accumulated in each round of accumulation, the first data item to be accumulated is stored in the even register of the current group parity register without passing through the floating-point adder; For the second data item to be accumulated in each round of accumulation, the second data item to be accumulated is stored in the odd register of the current group parity register without passing through the floating-point adder; For the Nth data item to be accumulated, the even-numbered data is added to the even-numbered register using a floating-point adder and then updated to the even-numbered register. The odd-numbered data is added to the odd-numbered register using a floating-point adder and then updated to the odd-numbered register. N is a positive integer greater than 2.
[0011] In this way, by using the first-shot direct storage strategy, the first two data items to be accumulated in each round are bypassed and directly stored into the register, thereby freeing up the adder resources for two clock cycles, so that the adder can perform the merge operation of the previous round at the beginning of the current round.
[0012] In one implementation, the step of executing the merge operation of the previous round and the write operation of the first data item in the current round in parallel within the same clock cycle further includes: When the first data item to be accumulated in the current round is written to the even register of the current group's parity register, the floating-point adder is in an idle state and is used to perform the merge operation of the previous round.
[0013] In this way, by utilizing the adder idle window created by the first direct storage, the merge operation of the previous round can be seamlessly inserted, achieving zero additional delay in the parity register merge operation of the previous round, and further ensuring the continuity of the accumulator data pipeline.
[0014] In one implementation, adjacent rounds overlap by a preset number of clock cycles in timing, specifically: adjacent rounds overlap by two clock cycles in timing. In the first overlapping period, the first data item to be accumulated in the current round is written to the even register of the current group of parity registers, and the merge result of the previous round is written to the odd register of the previous group of parity registers. In the second overlapping period, the second data item to be accumulated in the current round is written to the odd register of the current group's parity register, and the values of the even register and odd register of the previous group's parity register are merged, with the merged result written to the odd register of the previous group's parity register.
[0015] In this way, by precisely overlapping two clock cycles, the writing of the merge result from the previous round and the writing of the first two data items to be accumulated in the current round are completed within the same time period, which ensures the continuity of the data flow and avoids the waste of additional register resources.
[0016] In one implementation, the floating-point accumulation method also includes: After the last data item to be accumulated in the last input data sequence is written to the corresponding register, the floating-point adder is idle during the first clock cycle, waiting for the last data item to be accumulated to complete the register update; during the second clock cycle, the merge operation of the current round is performed, adding the values of the even register and the odd register of the current group of odd and even registers to obtain the final accumulation result.
[0017] In this way, by providing an efficient termination mechanism, the total drain delay is only 2 to 3 clock cycles, ensuring that the cumulative result of the last round can be output correctly, while avoiding the long drain cycle in traditional solutions, thus further improving the overall efficiency.
[0018] In one implementation, the first and second parity registers physically consist of only three registers. The first set of parity registers includes both even and odd registers, while the second set of parity registers contains only even registers. The odd registers in the second set of parity registers are multiplexed with either the odd or even registers in the first set of parity registers.
[0019] In this way, timing analysis reduces the number of parity registers from 4 to 3, saving register area and reducing hardware costs.
[0020] In one implementation, after the step of obtaining the input data sequence, the method further includes: When the number of output channel batches is greater than or equal to 2, a multi-output channel batch rotation mode is adopted. When the number of output channel batches is equal to 1, the working mode of alternating execution of the first set of parity registers and the second set of parity registers is adopted.
[0021] This approach ensures compatibility with existing multi-output channel batch rotation solutions, allowing for automatic switching based on actual workload without requiring hardware architecture modifications, thus improving the solution's versatility and practicality.
[0022] In one implementation, the floating-point adder employs a two-stage pipeline design. The first-stage pipeline performs exponent alignment and mantissa shift, while the second-stage pipeline performs mantissa addition and writes the result to the destination register.
[0023] In this way, by designing the floating-point adder as a two-stage pipelined structure, the combinational logic path is rationally decomposed. The first-stage pipeline is dedicated to handling exponent alignment and mantissa shift operations, while the second-stage pipeline is dedicated to mantissa addition and result writing operations. This decomposition shortens the critical path length of each pipeline stage, enabling the floating-point adder to operate stably at higher clock frequencies. Simultaneously, register isolation between the two pipeline stages avoids timing violations caused by excessive cascading of combinational logic, ensuring the reliability and stability of the floating-point adder under high-speed operating conditions. Furthermore, the clear pipeline hierarchy provides clear boundaries for the overall timing design and scheduling of the accumulator, facilitating timing coordination between the accumulator and other modules.
[0024] In one implementation, for an input data sequence of length n, the steady-state scheduling period for each round of accumulation is n clock cycles, the throughput is 1.0 data items per clock cycle, and the utilization rate of the floating-point adder is (n-1) / n, where n is a positive integer greater than or equal to 2.
[0025] In this way, full bandwidth throughput can be achieved for any accumulation dimension n≥2, and the adder utilization increases as n increases.
[0026] This application also provides a floating-point accumulator, including: An input buffer unit is used to receive the input data sequence to be accumulated; A floating-point adder is used to perform floating-point addition operations; The first set of parity registers and the second set of parity registers, each set of parity registers contains even registers and odd registers; The control logic unit is used to control the input buffer unit, the floating-point adder, and the first and second sets of parity registers to execute the above floating-point accumulation method.
[0027] In this way, by setting up an independent input buffer unit, the input data sequence is temporarily stored and isolated from backpressure, avoiding the direct impact of front-end data fluctuations on back-end accumulation operations. The floating-point adder performs floating-point addition operations, ensuring the accuracy and speed of the accumulation process. By configuring a first set of parity registers and a second set of parity registers, each containing both even and odd registers, a clear hardware storage foundation is provided for subsequent parity-separated accumulation and double-buffered alternating execution, allowing intermediate results during the accumulation process to be stored in an orderly and independent manner. The control logic unit coordinates the timing and data paths of the input buffer unit, the floating-point adder, and the two sets of parity registers, enabling collaborative operation between modules. The overall floating-point accumulator has a modular structure with clear boundaries between functional units, facilitating integration, verification, and reuse in deep learning accelerators or other digital signal processing chips. It also has good scalability, adapting to application requirements with different parallelism and data widths.
[0028] This application provides a floating-point accumulation method and a floating-point accumulator. The floating-point accumulation method includes: acquiring an input data sequence; dividing the data to be accumulated into even-numbered data or odd-numbered data based on the position index of the data item to be accumulated in the input data sequence; writing the even-numbered data into the even register of the current group of parity registers, and writing the odd-numbered data into the odd register of the current group of parity registers; when all data items to be accumulated in the input data sequence have been written to their corresponding registers, merging the values of the even register and the odd register in the current group of parity registers to obtain the accumulation result. The merging operation of the previous round and the writing operation of the first data item to be accumulated in the current round are executed in parallel within the same clock cycle. By applying the technical solution of this application, through parity-even separation accumulation and a double-buffered alternation mechanism, the pipeline delay of the floating-point adder is hidden in the parity-even alternation process. Simultaneously, timing overlap allows the merging operation and data writing to be performed in parallel, thereby achieving full-bandwidth accumulation throughput in a single-output-channel batch scenario without the need for an additional floating-point adder. Attached Figure Description
[0029] To more clearly illustrate the implementation methods in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0030] Figure 1 A flowchart illustrating a floating-point accumulation method provided in this application embodiment. Figure 1 .
[0031] Figure 2 The timing relationship of the accumulation of two adjacent rounds is provided for the embodiments of this application.
[0032] Figure 3 A flowchart illustrating a floating-point accumulation method provided in this application embodiment. Figure 2 .
[0033] Figure 4 This is a schematic diagram of a floating-point accumulator provided in an embodiment of this application. Detailed Implementation
[0034] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of this application.
[0035] It should be noted that many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of this application is not limited to the specific embodiments disclosed below.
[0036] In this application, the use of terms such as "first," "second," etc., is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.
[0037] The various embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of protection of this application.
[0038] This application provides a floating-point accumulation method and a floating-point accumulator to achieve full-bandwidth floating-point accumulation without adding an adder in a single-output channel batch scenario.
[0039] The first aspect of this application provides a floating-point accumulation method applied to the accumulator in a deep learning accelerator. It includes an input buffer stage, a floating-point adder, a first set of parity registers, a second set of parity registers, and a control logic unit. Figure 1 As shown, the floating-point accumulation method includes steps S110 to S140.
[0040] Step S110: Obtain the input data sequence. The input data sequence belongs to the same output channel batch and includes multiple data items to be accumulated.
[0041] First, the accumulator acquires the input data sequence, which belongs to the same output channel batch (OCB) and contains multiple data items to be accumulated.
[0042] For example, when the number of output channel batches OCB_NUM=1, the accumulator receives the partial sum (Psum) from the multiplication array. The partial sum is arranged along the kernel height (KH), kernel width (KW), and input channel batch (ICB) directions to form an input data sequence with an accumulation dimension of length .
[0043] Step S120: Based on the position index of the data item to be accumulated in the input data sequence, divide the data item to be accumulated into even-numbered data or odd-numbered data.
[0044] Next, based on the position index of each data item to be accumulated in the input data sequence, the data items to be accumulated are distinguished into even-numbered data or odd-numbered data.
[0045] For example, the position index starts counting from 0. The data items to be accumulated with position indices of 0, 2, 4, ..., 2m are even-numbered data, and the data items to be accumulated with indices of 1, 3, 5, ..., (2m+1) are odd-numbered data, where m is an integer greater than or equal to 0.
[0046] For example, for the input data sequence {D0, D1, D2, D3}, D0 and D2 are even-numbered data, and D1 and D3 are odd-numbered data.
[0047] Step S130: Write the even-numbered data into the even register of the current group parity register, and write the odd-numbered data into the odd register of the current group parity register.
[0048] Then, the even-numbered data bits are written to the even register of the current group's parity register, and the odd-numbered data bits are written to the odd register of the current group's parity register.
[0049] The parity register includes a first set of parity registers and a second set of parity registers. In each round of accumulation, one set of parity registers is selected as the current set of parity registers. The accumulation in adjacent rounds is performed alternately on the two sets of parity registers, and the adjacent rounds overlap by a preset number of clock cycles in timing.
[0050] For example, such as Figure 2 The diagram illustrates the timing relationship between two consecutive rounds of accumulation. The first round uses the first set of parity registers (ping group registers), and the second round uses the second set of parity registers (pong group registers). The third round then uses the first set of parity registers again, the fourth round uses the second set, and so on, alternating between the two sets. For example, the number of overlapping clock cycles is 2 clock cycles (beat).
[0051] Step S140: If all data items to be accumulated in the input data sequence have been written to the corresponding registers, merge the values of the even registers and odd registers in the current group's parity registers to obtain the accumulation result.
[0052] Finally, assuming all data items to be accumulated in the input data sequence have been written to their corresponding registers, such as Figure 2 As shown, the values of the even registers and odd registers in the current group's parity registers are merged to obtain the cumulative result for this round.
[0053] In this process, the merging operation of the parity register in the previous round and the writing operation of the first data item to be accumulated in the current round are executed in parallel within the same clock cycle.
[0054] For example, when the first data item to be accumulated (D0) in the current round is written to the even register, the floating-point adder is idle and can perform the merge operation of the previous round, thus achieving a bubble-free pipeline.
[0055] In this way, by using parity-even separation accumulation and double buffering alternation mechanism, the pipeline delay of the floating-point adder is hidden in the parity-even alternation process. At the same time, timing overlap is used to make the merging operation and data writing parallel, thereby achieving full bandwidth accumulation throughput in single-output channel batch scenarios without the need to add an additional floating-point adder.
[0056] In some embodiments, in the steps of writing even-numbered bits of data to the even-numbered register of the current group parity register and writing odd-numbered bits of data to the odd-numbered register of the current group parity register, as follows: Figure 3 As shown, the floating-point accumulation method also includes steps S310 to S330.
[0057] Step S310: For the first data item to be accumulated in each round of accumulation, the first data item to be accumulated is stored in the even register of the current group parity register without passing through the floating-point adder.
[0058] For the first data item to be accumulated in each round of accumulation (i.e., the data with position index 0), the first data item to be accumulated is directly stored into the even register in the current group's parity register without going through the floating-point adder.
[0059] For example, D0 is written to the even register of the first set of parity registers after a one-clock-cycle delay, without going through the adder. This frees up adder resources, allowing the adder to be used to perform the merge operation of the previous round of accumulation.
[0060] Step S320: For the second data item to be accumulated in each round of accumulation, the second data item to be accumulated is stored in the odd register of the current group parity register without passing through the floating-point adder.
[0061] For the second data item to be accumulated in each round of accumulation (i.e., the data with position index 1), the second data item to be accumulated is directly stored into the odd register of the current parity register without going through the floating-point adder. For example, D1 is written to the odd register of the first parity register after a one-clock-cycle delay, also without going through the adder.
[0062] Step S330: For the Nth data item to be accumulated, the even-numbered data is accumulated with the value of the even register through a floating-point adder and then updated to the even register. The odd-numbered data is accumulated with the value of the odd register through a floating-point adder and then updated to the odd register. N is a positive integer greater than 2.
[0063] For the third and subsequent data items to be accumulated (i.e., data with a position index ≥ 2), the even-numbered data is added to the even-numbered register using a floating-point adder and then updated to the even-numbered register. The odd-numbered data is added to the odd-numbered register using a floating-point adder and then updated to the odd-numbered register.
[0064] For example, D2 (even bit) is added to the value in the even register of the first set of parity registers (which has already stored D0) by an adder, and the result is written back to the even register.
[0065] For example, D3 (odd bit) is added to the value in the odd register of the first set of parity registers (which has already stored D1) using an adder, and the result is written back to the odd register. Subsequent data are processed in the same way.
[0066] In this way, by using the first-shot direct storage strategy, the first two data items to be accumulated in each round are bypassed and directly stored into the register, thereby freeing up the adder resources for two clock cycles, so that the adder can perform the merge operation of the previous round at the beginning of the current round.
[0067] In some embodiments, when the first data item to be accumulated in the current round is written to the even register of the current group parity register, the floating-point adder is in an idle state and is used to perform the merge operation of the previous round.
[0068] For example, suppose the current round is round M, using the first set of parity registers. In the first clock cycle (Beat0) of round M, D0 is written to the even register of the first set of parity registers. At this time, the floating-point adder does not receive a new accumulation request (because D0 does not pass through the adder), so the adder is idle. At the same time, the merge operation of the previous round (round M-1) needs to be performed at this time, so the adder adds the values of the even register and the odd register of the first set of parity registers to obtain the accumulation result of round N-1.
[0069] In this way, by utilizing the adder idle window created by the first direct storage, the merge operation of the previous round can be seamlessly inserted, achieving zero additional delay in the parity register merge operation of the previous round, and further ensuring the continuity of the accumulator data pipeline.
[0070] In some embodiments, adjacent rounds overlap by a preset number of clock cycles in timing, specifically: adjacent rounds overlap by two clock cycles in timing.
[0071] In the first overlapping period, the first data item to be accumulated in the current round is written to the even register of the current group of parity registers, while the merge result of the previous round is written to the odd register of the previous group of parity registers.
[0072] In the second overlapping cycle, the second data item to be accumulated in the current round is written to the odd register of the current group of parity registers. At the same time, the values of the even register and the odd register of the previous group of parity registers are merged. The merge result of the previous round is written to the odd register of the previous group of parity registers and synchronously written to the output buffer.
[0073] Taking a three-round accumulation (rounds D, E, and F) as an example, starting from the fourth clock cycle (Beat3), the last data (D3) of round D is fed into the adder, while the first data (E0) of round E is written to the even register of the second set of parity registers, achieving overlap of two clock cycles. In the fifth clock cycle (Beat4), the merged result of round D is written to the output buffer, and at the same time, the second data (E1) of round E is written to the odd register of the second set of parity registers.
[0074] In this way, by precisely overlapping two clock cycles, the writing of the merge result from the previous round and the writing of the first two data items to be accumulated in the current round are completed within the same time period, which ensures the continuity of the data flow and avoids the waste of additional register resources.
[0075] In some embodiments, the finalization phase begins after the last data item to be accumulated in the last input data sequence is written to its corresponding register. During the first clock cycle, the floating-point adder is idle, waiting for the last data item to be accumulated in the final round to complete its register update. For example, when all data items to be accumulated in the final round have been fed into the adder and calculation has begun, but the accumulated result of the last data item has not yet been written back to the register, the adder is temporarily idle for one clock cycle. During the second clock cycle, the merge operation of the final round of accumulation is performed, adding the values of the even-numbered registers and odd-numbered registers of the current group to obtain the final accumulated result, which is then written to the output buffer.
[0076] For example, suppose the last round is round E, using the first set of parity registers. After the last data in round E (e.g., D3) updates the odd register of the first set of parity registers through the adder, the adder idles in the next clock cycle (Beat_end-1), waiting for the odd register of the first set of parity registers to stabilize. In the next clock cycle (Beat_end), a merge operation is performed, adding the even register of the first set of parity registers to the odd register of the first set of parity registers to obtain the final result.
[0077] In this way, by providing an efficient termination mechanism, the total drain delay is only 2 to 3 clock cycles, ensuring that the cumulative result of the last round can be output correctly, while avoiding the long drain cycle in traditional solutions, thus further improving the overall efficiency.
[0078] In some embodiments, the first and second parity registers physically consist of only three registers. Specifically, the first parity register includes an even register and an odd register, the second parity register includes only an even register, and the odd registers of the second parity register are multiplexed with either the odd or even registers of the first parity register.
[0079] Analysis of the timing of the double-buffered parity registers shows that in the two clock cycles of the parity register and the second set of parity registers overlapping, the first overlapping cycle only requires the even and odd registers of the first set of parity registers to maintain their state (2 registers), while the second overlapping cycle requires the even register of the first set of parity registers, the odd register of the first set of parity registers, and the even register of the second set of parity registers to maintain their state simultaneously (3 registers).
[0080] Therefore, the four registers that are logically required can be physically optimized into three registers. The second set of parity registers does not need to exist independently, and the function of the second set of parity registers can be multiplexed by the even or odd registers of the first set of parity registers at a specific time.
[0081] In this way, timing analysis reduces the number of parity registers from 4 to 3, saving register area and reducing hardware costs.
[0082] In some embodiments, after the step of acquiring the input data sequence, the working mode is automatically selected based on the number of output channel batches.
[0083] Specifically, when the number of output channel batches is greater than or equal to 2, a multi-output channel batch rotation mode is adopted, that is, the pipeline delay of the floating-point adder is hidden by rotating between multiple output channel batches. In this case, there is no need to enable the double-buffered parity register mechanism.
[0084] When the number of output channel batches is equal to 1, the double-buffered parity register working mode is adopted, in which the first parity register and the second parity register are executed alternately.
[0085] For example, when the accumulator is detected, a traditional bypass FIFO queue round-robin scheme is used. When the accumulator is detected, it automatically switches to double-buffered parity register mode.
[0086] This approach ensures compatibility with existing multi-output channel batch rotation solutions, allowing for automatic switching based on actual workload without requiring hardware architecture modifications, thus improving the solution's versatility and practicality.
[0087] In some embodiments, the floating-point adder involved in this application employs a two-stage pipeline design. The first-stage pipeline performs exponent alignment and mantissa shift operations, outputting the aligned mantissa and exponent difference. The second-stage pipeline performs signed addition of the mantissa and writes the result to the destination register. The entire addition operation, from input to result writing to the register, requires two clock cycles.
[0088] For example, when the value of D2 and the even register of the first set of parity registers are fed into the adder, the first clock cycle completes the exponent comparison and alignment shift, and the second clock cycle completes the mantissa addition and writes it back to the even register of the first set of parity registers.
[0089] In this way, by designing the floating-point adder as a two-stage pipelined structure, the combinational logic path is rationally decomposed. The first-stage pipeline is dedicated to handling exponent alignment and mantissa shift operations, while the second-stage pipeline is dedicated to mantissa addition and result writing operations. This decomposition shortens the critical path length of each pipeline stage, enabling the floating-point adder to operate stably at higher clock frequencies. Simultaneously, register isolation between the two pipeline stages avoids timing violations caused by excessive cascading of combinational logic, ensuring the reliability and stability of the floating-point adder under high-speed operating conditions. Furthermore, the clear pipeline hierarchy provides clear boundaries for the overall timing design and scheduling of the accumulator, facilitating timing coordination between the accumulator and other modules.
[0090] In some embodiments, for an input data sequence of length n, the steady-state scheduling period for each round of accumulation is n clock cycles, the throughput is 1.0 data item per clock cycle, and the utilization rate of the floating-point adder is (n-1) / n, where n is a positive integer greater than or equal to 2.
[0091] Taking n=4 as an example, each round requires 4 clock cycles to complete the accumulation of 4 data points, processing an average of 1 data point per cycle. The adder uses 3 clock cycles per round (merge operation + two accumulation operations), with a utilization rate of 75%. As n increases, the utilization rate gradually increases and approaches 100%.
[0092] In this way, full bandwidth throughput can be achieved for any accumulation dimension n≥2, and the adder utilization increases as n increases.
[0093] This application also provides a floating-point accumulator for performing the above-described floating-point accumulation method. For example... Figure 4 As shown, the floating-point accumulator includes: an input buffer unit, a floating-point adder, a first set of parity registers, a second set of parity registers, and a control logic unit.
[0094] The input buffer unit is used to receive the input data sequence to be accumulated. The input buffer unit contains a data input first-in-first-out queue with a depth of 2, which is used to isolate the timing of the reverse voltage signal.
[0095] The floating-point adder is used to perform floating-point addition operations. The floating-point adder adopts a two-stage pipelined design. The first stage performs exponent alignment and mantissa shift, and the second stage performs mantissa addition and writes it to the destination register.
[0096] The first and second parity register sets contain both even and odd registers. In physical implementation, both parity register sets contain only three registers, with the odd registers in the second set being multiplexed with either the odd or even registers in the first set.
[0097] The control logic unit controls the input buffer unit, floating-point adder, and the first and second sets of parity registers to execute the above floating-point accumulation method. The control logic unit automatically selects the operating mode based on the number of output channel batches and generates corresponding control signals, including data strobe, register write enable, adder operation enable, and merge operation trigger.
[0098] In addition, the accumulator may also include a double-buffered FIFO (First In First Out) unit and an output stage, which are used to buffer the final accumulation result and to complete bandwidth conversion and number system conversion, respectively.
[0099] In this way, by setting up an independent input buffer unit, the input data sequence is temporarily stored and isolated from backpressure, avoiding the direct impact of front-end data fluctuations on back-end accumulation operations. The floating-point adder performs floating-point addition operations, ensuring the accuracy and speed of the accumulation process. By configuring a first set of parity registers and a second set of parity registers, each containing both even and odd registers, a clear hardware storage foundation is provided for subsequent parity-separated accumulation and double-buffered alternating execution, allowing intermediate results during the accumulation process to be stored in an orderly and independent manner. The control logic unit coordinates the timing and data paths of the input buffer unit, the floating-point adder, and the two sets of parity registers, enabling collaborative operation between modules. The overall floating-point accumulator has a modular structure with clear boundaries between functional units, facilitating integration, verification, and reuse in deep learning accelerators or other digital signal processing chips. It also has good scalability, adapting to application requirements with different parallelism and data widths.
Claims
1. A floating-point accumulation method, characterized in that, include: Obtain an input data sequence, wherein the input data sequence belongs to the same output channel batch and includes multiple data items to be accumulated; Based on the position index of the data item to be accumulated in the input data sequence, the data item to be accumulated is divided into even-numbered data or odd-numbered data. The even-numbered data is written to the even-numbered register of the current group of parity registers, and the odd-numbered data is written to the odd-numbered register of the current group of parity registers. The parity registers include a first group of parity registers and a second group of parity registers. In each round of accumulation, one group of parity registers is selected as the current group. The accumulation in adjacent rounds is performed alternately on the first group of parity registers and the second group of parity registers, and the adjacent rounds overlap by a preset number of clock cycles in timing. When all data items to be accumulated in the input data sequence have been written to the corresponding registers, the values of the even registers and odd registers in the current group are merged to obtain the accumulation result. The merging operation of the previous round and the writing operation of the first data item to be accumulated in the current round are executed in parallel within the same clock cycle.
2. The floating-point accumulation method according to claim 1, characterized in that, The step of writing the even-numbered data into the even-numbered register of the current group parity register and writing the odd-numbered data into the odd-numbered register of the current group parity register includes: For the first data item to be accumulated in each round of accumulation, the first data item to be accumulated is stored in the even register of the current group parity register without passing through the floating-point adder; For the second data item to be accumulated in each round of accumulation, the second data item to be accumulated is stored in the odd register of the current group parity register without passing through the floating-point adder; For the Nth data item to be accumulated, the even-numbered data is accumulated with the value of the even-numbered register through the floating-point adder and then updated to the even-numbered register. The odd-numbered data is accumulated with the value of the odd-numbered register through the floating-point adder and then updated to the odd-numbered register. N is a positive integer greater than 2.
3. The floating-point accumulation method according to claim 2, characterized in that, The step of executing the merge operation of the previous round and the write operation of the first data item in the current round in parallel within the same clock cycle also includes: When the first data item to be accumulated in the current round is written to the even register of the current group's parity register, the floating-point adder is in an idle state and is used to perform the merge operation of the previous round.
4. The floating-point accumulation method according to claim 1, characterized in that, The adjacent rounds overlap by a preset number of clock cycles in time sequence, specifically: adjacent rounds overlap by two clock cycles in time sequence; In the first overlapping period, the first data item to be accumulated in the current round is written to the even register of the current group of parity registers, and the merge result of the previous round is written to the odd register of the previous group of parity registers. In the second overlapping period, the second data item to be accumulated in the current round is written to the odd register of the current group's parity register, and the values of the even register and odd register of the previous group's parity register are merged, with the merged result written to the odd register of the previous group's parity register.
5. The floating-point accumulation method according to claim 1, characterized in that, Also includes: After the last data item to be accumulated in the last input data sequence is written to the corresponding register, the floating-point adder is idle during the first clock cycle, waiting for the last data item to be accumulated to complete the register update; during the second clock cycle, the merge operation of the current round is performed, adding the values of the even register and the odd register of the current group of odd and even registers to obtain the final accumulation result.
6. The floating-point accumulation method according to claim 1, characterized in that, The first and second parity registers physically consist of only three registers. The first set of parity registers includes both even and odd registers, while the second set of parity registers contains only even registers. The odd registers in the second set of parity registers are multiplexed with either the odd or even registers in the first set of parity registers.
7. The floating-point accumulation method according to claim 1, characterized in that, After the step of obtaining the input data sequence, the following steps are also included: When the number of output channel batches is greater than or equal to 2, a multi-output channel batch rotation mode is adopted. When the number of output channel batches is equal to 1, the working mode of alternating execution of the first set of parity registers and the second set of parity registers is adopted.
8. The floating-point accumulation method according to claim 2, characterized in that, The floating-point adder employs a two-stage pipeline design. The first-stage pipeline performs exponent alignment and mantissa shift, while the second-stage pipeline performs mantissa addition and writes the result to the target register.
9. The floating-point accumulation method according to claim 1, characterized in that, For an input data sequence of length n, the steady-state scheduling period for each round of accumulation is n clock cycles, the throughput is 1.0 data item per clock cycle, and the utilization rate of the floating-point adder is (n-1) / n, where n is a positive integer greater than or equal to 2.
10. A floating-point accumulator, characterized in that, include: An input buffer unit is used to receive the input data sequence to be accumulated; A floating-point adder is used to perform floating-point addition operations; The first set of parity registers and the second set of parity registers, each set of parity registers contains even registers and odd registers; A control logic unit is used to control the input buffer unit, the floating-point adder, and the first set of parity registers and the second set of parity registers to perform the floating-point accumulation method as described in any one of claims 1 to 9.