A memory access instruction optimization method

Abstract

The application relates to the technical field of integrated circuits, in particular to a memory access instruction optimization method, which comprises the following steps: traversing instruction sets, constructing tree structures corresponding to the instruction sets, comparing the tree structures of the instruction sets, determining whether the base addresses of different instruction sets are uniform, when the base addresses of different instruction sets are uniform, merging and optimizing the different instruction sets, obtaining an instruction optimization result, reducing the number of address calculation-related instructions, reducing the calculation amount of a chip, and improving the calculation efficiency of the chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method for optimizing memory access instructions. Background Technology

[0002] In a chip, memory access is a crucial step in the data interaction between the processing unit and memory, and it has a vital impact on the performance of the entire system.

[0003] Memory access instructions generally include instruction type, data, base address, and offset. In existing technologies, the compiler needs to calculate the base address and offset. The base address is a virtual register, while the offset is an immediate constant, thereby determining the address in memory. Memory is accessed based on the address, and the virtual register corresponding to the data is used to store the data involved in the memory access.

[0004] However, existing methods require recalculating the base address for each memory access instruction, resulting in a large number of redundant calculation instructions. In addition, since the base address is not uniform, it also reduces the possibility of merging memory access instructions, which leads to a large amount of computation on the chip and reduces the chip's computing efficiency.

[0005] Therefore, optimizing memory access instructions to improve the chip's computational efficiency has become an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0007] A memory access instruction optimization method, the memory access instruction optimization method comprising:

[0008] S101, obtain M instruction sets, wherein the m-th instruction set includes K(m) basic instructions, the K(m)-th basic instruction is a memory access instruction, m is an integer in the range [1, M], the basic instruction includes instruction type, virtual register and several operands, and M is a positive integer.

[0009] S102, for any instruction set, construct a root node based on the instruction type and virtual registers included in the memory access instructions in the instruction set, and use the root node as the parent node.

[0010] S103, generate each child node corresponding to the parent node according to the operands included in the basic instruction corresponding to the parent node.

[0011] S104, all child nodes that meet the first preset condition are taken as parent nodes, and the process returns to step S103 until there are no more child nodes that meet the first preset condition, thus obtaining the tree structure corresponding to the instruction set.

[0012] S105, compare the tree structures of any two instruction sets. If the comparison result meets the second preset condition, optimize the current two instruction sets to obtain the instruction optimization result.

[0013] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the memory access instruction optimization method provided by the present invention achieves considerable technical progress and practicality, and has broad industrial application value. It has at least the following advantages:

[0014] This invention provides a memory access instruction optimization method, comprising: S101, obtaining M instruction sets, wherein the m-th instruction set includes K(m) basic instructions, the K(m)-th basic instruction is a memory access instruction, m is an integer in the range [1, M], the basic instruction includes an instruction type, a virtual register and several operands, and M is a positive integer; S102, for any instruction set, constructing a root node according to the instruction type and virtual register included in the memory access instruction in the instruction set, and using the root node as a parent node; S103, generating each child node corresponding to the parent node according to each operand included in the basic instruction corresponding to the parent node; S104, taking all child nodes that satisfy a first preset condition as parent nodes, returning to step S103, until there are no child nodes that satisfy the first preset condition, and obtaining the tree structure corresponding to the instruction set; S105, comparing the tree structures of any two instruction sets, and if the comparison result satisfies a second preset condition, optimizing the current two instruction sets to obtain the instruction optimization result.

[0015] It can be seen that by traversing the instruction set, a tree structure corresponding to the instruction set is constructed. By comparing the tree structures of the instruction sets, it can be determined whether the base addresses of different instruction sets are consistent. When the base addresses of different instruction sets are consistent, the different instruction sets can be merged and optimized to obtain the instruction optimization result, thereby reducing the number of instructions related to address calculation, reducing the computational load of the chip, and improving the computational efficiency of the chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart illustrating a memory access instruction optimization method provided in an embodiment of the present invention;

[0018] Figure 2This is a schematic diagram of the first tree structure corresponding to the first example instruction set in a memory access instruction optimization method provided in an embodiment of the present invention;

[0019] Figure 3 This is a schematic diagram of the second tree structure corresponding to the second example instruction set in a memory access instruction optimization method provided in an embodiment of the present invention.

[0020] Figure 4 This is a schematic diagram illustrating the instruction optimization of the first example instruction set and the second example instruction set in a memory access instruction optimization method provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] This embodiment provides a memory access instruction optimization method, see [link to relevant documentation] Figure 1 The present invention provides a flowchart illustrating a memory access instruction optimization method, the memory access instruction optimization method comprising:

[0023] S101, obtain M instruction sets, wherein the m-th instruction set includes K(m) basic instructions, the K(m)-th basic instruction is a memory access instruction, m is an integer in the range [1, M], the basic instruction includes instruction type, virtual register and several operands, and M is a positive integer;

[0024] S102, For any instruction set, construct a root node based on the instruction type and virtual registers included in the memory access instructions in the instruction set, and use the root node as the parent node;

[0025] S103, Generate each child node corresponding to the parent node according to each operand included in the basic instruction corresponding to the parent node;

[0026] S104, take all child nodes that meet the first preset condition as parent nodes, return to step S103, until there are no child nodes that meet the first preset condition, and obtain the tree structure corresponding to the instruction set.

[0027] S105, compare the tree structures of any two instruction sets. If the comparison result meets the second preset condition, optimize the current two instruction sets to obtain the instruction optimization result.

[0028] In this context, an instruction set can refer to a set of instructions related to a memory access instruction. In this embodiment, the instructions contained in the instruction set are used as basic instructions. Different instruction sets may contain different numbers of basic instructions. However, the last basic instruction contained in different instruction sets is a memory access instruction. That is, for the m-th instruction set, the first basic instruction to the K(m)-1-th basic instruction are all instructions used for base address calculation, and the K(m)-th basic instruction is a memory access instruction.

[0029] Basic instructions include an instruction type, virtual registers, and several operands. For non-memory-access basic instructions, the instruction type can be addition, multiplication, multiply-add, or subtraction. For memory-access instructions, the instruction type can refer to the memory access bit width. For non-memory-access basic instructions, the virtual register can be used to store the result of the calculation of each operand. For memory-access instructions, the virtual register can be used to store memory-access-related data. Non-memory-access basic instructions can include several operands; for example, addition instructions include two operands, which are added together. For memory-access instructions, two operands can be included, representing the base address and offset, respectively.

[0030] Specifically, for any instruction set, a root node is constructed based on the instruction types and virtual registers included in the memory access instructions in the instruction set. Virtual registers can be represented by register numbers. Based on the operands included in the basic instruction corresponding to the parent node, each child node corresponding to the parent node is generated. For example, if the root node includes two operands, then when the root node is the parent node, two child nodes are generated.

[0031] When there are no child nodes that meet the first preset condition, that is, when there are no child nodes that can be parent nodes, the generation of child nodes stops, and the tree structure corresponding to the instruction set is obtained.

[0032] In one specific implementation, the operands include immediate values ​​and virtual registers;

[0033] Step S103 includes the following steps:

[0034] S1031, for any operand contained in the parent node, if the operand is an immediate value, generate the child node corresponding to the parent node according to the immediate value;

[0035] S1032, if the operand is a virtual register and the virtual register does not have a corresponding basic instruction, generate the child node corresponding to the parent node based on the virtual register;

[0036] S1033, if the operand is a virtual register and the virtual register has a corresponding basic instruction, generate the child node corresponding to the parent node according to the instruction type contained in the virtual register and its corresponding basic instruction.

[0037] The operands can be immediate values ​​or virtual registers.

[0038] Specifically, the content of the generated child node is determined based on the operands contained in the parent node. If the operand is an immediate value, the generated child node contains only that immediate value. If the operand is a virtual register and there is no corresponding basic instruction for that virtual register, the generated child node contains only the register number corresponding to that virtual register. If the operand is a virtual register and there is a corresponding basic instruction for that virtual register, the generated child node contains the register number corresponding to that virtual register and the instruction type corresponding to the basic instruction.

[0039] In one specific implementation, the step of determining whether a child node satisfies the first preset condition includes:

[0040] For any child node, if the operand corresponding to the child node is an immediate value, then it is determined that the child node does not meet the first preset condition.

[0041] If the operand corresponding to the child node is a virtual register and the virtual register exists in at least two instruction sets, then the child node is determined not to meet the first preset condition.

[0042] Otherwise, determine that the child node satisfies the first preset condition.

[0043] In this case, if the operand corresponding to the child node is a virtual register and the virtual register exists in at least two instruction sets, it indicates that the virtual register is a public variable and will no longer be traversed based on the child node.

[0044] In one embodiment, if the operand corresponding to the child node is a virtual register and the virtual register belongs to an instruction outside the basic block, then the child node is determined not to meet the first preset condition.

[0045] In one specific implementation, step S104 further includes the following steps:

[0046] The parent node whose child nodes do not meet the first preset condition is designated as the termination instruction node.

[0047] If none of the child nodes of a parent node meet the first preset condition, then the parent node is regarded as a termination instruction node. The tree structure corresponding to an instruction set may include multiple termination instruction nodes.

[0048] In one specific implementation, the tree structure includes a number of nodes, each node corresponding to a root node or a child node;

[0049] The comparison of the tree structures of any two instruction sets includes:

[0050] S1051, the tree structures of the two instruction sets are respectively used as the first tree structure and the second tree structure;

[0051] S1052, compare the topology of the first tree structure and the second tree structure to obtain the first comparison result;

[0052] S1053, if the first comparison result is a match, then determine several node pairs based on the first tree structure and the second tree structure, and check each node pair;

[0053] S1054: When two nodes in any node pair are not child nodes of the termination instruction node, and both nodes in the node pair correspond to virtual registers, if each of the two virtual registers corresponds to a basic instruction, then the second comparison result corresponding to the node pair is determined to be consistent; otherwise, the two virtual registers are compared to obtain the second comparison result corresponding to the node pair.

[0054] S1055, when two nodes in any node pair are child nodes of the termination instruction node, and both nodes in the node pair correspond to virtual registers, the two virtual registers are compared to obtain the second comparison result corresponding to the node pair.

[0055] S1056, when two nodes in any node pair are immediate values, backtrack any node in the node pair to the root node in the tree structure to obtain the backtracking path corresponding to the node, and the backtracking path contains several backtracking nodes.

[0056] S1057, if any backtracking node in the backtracking path is related to the multiplication operation bit of a node whose instruction type satisfies the third preset condition, and the multiplication operation bit of the node whose instruction type satisfies the third preset condition is also related to a virtual register, then the two immediate values ​​are compared to obtain the second comparison result corresponding to the node pair; otherwise, it is determined that the second comparison result corresponding to the node pair is consistent.

[0057] The comparison of the topology of the first tree structure and the second tree structure can refer to the comparison of the topological relationship and instruction type of the first tree structure and the second tree structure. That is, each node in the first tree structure should have a unique corresponding node in the second tree structure. If a node in the first tree structure has an instruction type, then the corresponding node in the second tree structure should also have an instruction type. The instruction types of the two nodes should also be the same. Thus, the first comparison result can be considered as a match.

[0058] Specifically, when neither of the two nodes in any node pair is a child node of the terminating instruction node, and both nodes in the node pair correspond to virtual registers, if each of the two virtual registers corresponds to a basic instruction, it means that both nodes in the node pair have child nodes. No comparison is needed, and the second comparison result corresponding to the node pair is directly determined to be consistent. However, if neither of the two virtual registers has a corresponding basic instruction, it means that neither of the two nodes in the node pair has a child node. A comparison of the virtual registers is required, and the second comparison result corresponding to the node pair is determined based on the comparison result of the virtual registers. It should be noted that the first comparison result has already determined whether the node pair has a corresponding basic instruction, and the types of the basic instructions are the same. Therefore, there are only the above two cases.

[0059] For example, taking the first example instruction set {[MUL%7,%4,0x02], [MUL%10,%8,%7], [ADD%11,%9,0x02], [IMA%12,%11,0x02%10], [LDG%13,%12,0x00]} and the second example instruction set {[MUL%3,%4,0x02], [MUL%6,%8,%3], [ADD%14,%9,0x04], [IMA%15,%14,0x02%6], [LDG%16,%15,0x00]} as examples, see [link to example]. Figure 2 This is a schematic diagram of the first tree structure corresponding to the first example instruction set in a memory access instruction optimization method provided in an embodiment of the present invention. See also... Figure 3This is a schematic diagram of the second tree structure corresponding to the second example instruction set in a memory access instruction optimization method provided in an embodiment of the present invention. Here, MUL can refer to a multiplication instruction, ADD can refer to an addition instruction, IMA can refer to a multiply-add instruction, LDG can refer to a memory access instruction, and %a can refer to the virtual register number corresponding to virtual register a. As an example, for virtual register %11 in [IMA%12,%11,0x02%10], the parent node is IMA%12, which is not a terminating instruction node. It corresponds to virtual register %14 in [IMA%15,%14,0x02%6], whose parent node is IMA%15, which is not a terminating instruction. Since %11 corresponds to the basic instruction [ADD%11,%2,0x02] and %14 corresponds to the basic instruction [ADD%14,%9,0x04], both nodes in the node pair have child nodes. Therefore, there is no need for comparison, and the second comparison result of the node pair is directly determined to be consistent. However, for register %8 in [MUL%10,%8,%7], the parent node is MUL%10, which is not a termination instruction node. It corresponds to virtual register %8 in [MUL%6,%8,%3], whose parent node is MUL%6, which is not a termination instruction node. However, neither of them has a corresponding basic instruction. Therefore, the second comparison result of the node pair is determined to be consistent only when the two are the same.

[0060] When two nodes in any node pair are child nodes of the termination instruction node, and the operands of both nodes in the node pair are virtual registers, the two virtual registers are compared to obtain the second comparison result corresponding to the node pair. Continuing with the example above, for virtual register %9 in [ADD%11,%9,0x02], the parent node is ADD%11, which is the termination instruction node. It corresponds to virtual register %9 in [ADD%14,%9,0x04], where the parent node is ADD%14, which is also the termination instruction node. Therefore, the second comparison result corresponding to the node pair is determined to be consistent only when the two are the same.

[0061] When two nodes in any node pair are immediate values, backtrack any node in the node pair to the root node in its tree structure to obtain the backtracking path corresponding to that node. The backtracking path contains several backtracking nodes. Following the example above, for the immediate value 0x02 in [MUL%7,%4,0x02], its backtracking path is MUL%7, MUL%10, IMA%12, LDG%13.

[0062] If any backtracking node in the backtracking path is related to the multiplication operation bit of a node whose instruction type satisfies the third preset condition, and the multiplication operation bit of the node whose instruction type satisfies the third preset condition is also related to a virtual register, then the two immediate values ​​are compared to obtain the second comparison result corresponding to the node pair; otherwise, it is determined that the second comparison result corresponding to the node pair is consistent.

[0063] The third preset condition can refer to the instruction type being a multiplication operation type or a multiply-addition operation type. For nodes with a multiplication operation type instruction, both operation bits of the node are multiplication operation bits. For nodes with a multiply-addition operation type instruction, the first and second operation bits of the node are usually multiplication operation bits. Continuing with the example above, for the immediate value 0x02 in [MUL%7,%4,0x02], its backtracking path is MUL%7, MUL%10, IMA%12, LDG%13. The other multiplication operation of MUL%7 is located in the virtual register. Therefore, it is necessary to compare the immediate value 0x02 in [MUL%7,%4,0x02] with the immediate value 0x02 in its corresponding [MUL%3,%4,0x02]. Only when the two are the same can it be determined that the second comparison result of the node pair is consistent.

[0064] For the immediate number 0x02 in [ADD%11,%9,0x02], its backtracking path is ADD%11, IMA%12, LDG%13. IMA%12 meets the third preset condition, but the other multiplication operation bit of IMA%12 is an immediate number. Therefore, the immediate number 0x02 in [ADD%11,%9,0x02] and its corresponding immediate number 0x04 in [ADD%14,%9,0x04] do not need to be compared. It can be directly determined that the second comparison result of the node pair is consistent.

[0065] In one specific implementation, if the comparison result meets the second preset condition, then the current two instruction sets are optimized to obtain an instruction optimization result, including:

[0066] If the second comparison results of each node pair are consistent, it is determined that the comparison results meet the second preset condition. Address offset calculation and base address calculation are performed based on the current two instruction sets. Based on the address offset calculation results and base address calculation results, the instruction optimization result is determined.

[0067] Only after the first comparison result is consistent can the comparison continue to obtain the second comparison result of each node pair. When the second comparison results of each node pair are consistent, the comparison result is determined to meet the second preset condition.

[0068] Optimization of the two current instruction sets can include calculating the address offset and the base address based on the two current instruction sets.

[0069] This embodiment only uses the comparison of two instruction sets as an example. In one implementation, the implementer can compare multiple instruction sets. If the comparison results between multiple instruction sets all meet the second preset condition, then the multiple instruction sets are optimized simultaneously to obtain the instruction optimization result.

[0070] In one specific implementation, the feature is that the address offset calculation based on the current two instruction sets includes:

[0071] S1061, For any instruction set, determine the nodes in the tree structure of the instruction set whose instruction types satisfy the fourth preset condition as temporary nodes;

[0072] S1062, If the addition operation bit of the temporary node is an immediate value, backtrack the temporary node to the root node in the tree structure to obtain the backtracking path corresponding to the temporary node.

[0073] S1063, use the temporary node as the current backtracking node, and use the immediate value of the addition operation bit of the temporary node as the offset reference value;

[0074] S1064, if the instruction type corresponding to the previous backtracking node of the current backtracking node in the backtracking path satisfies the third preset condition, and the current backtracking node is related to the multiplication operation bit of the previous backtracking node, and the multiplication operation bit of the previous backtracking node is also related to the immediate value, then the offset intermediate value is calculated based on the immediate value related to the multiplication operation bit of the previous backtracking node and the offset reference value.

[0075] S1065, if the previous backtracking node of the current backtracking node in the backtracking path satisfies the fourth preset condition, and the addition operation bit of the current backtracking node is related to the previous backtracking node, and the addition operation bit of the previous backtracking node is unrelated to the immediate value, then the offset reference value is used as the offset intermediate value.

[0076] S1066, if the previous backtracking node of the current backtracking node in the backtracking path satisfies the fourth preset condition, and the current backtracking node is related to the addition operation bit of the previous backtracking node, and the addition operation bit of the previous backtracking node is related to the immediate value, then the offset intermediate value is calculated based on the immediate value related to the addition operation bit of the previous backtracking node and the offset reference value.

[0077] S1067, otherwise, switch the temporary node and return to step S1062;

[0078] S1068: Using the previous backtracking node as the current backtracking node and the offset median value as the offset reference value, return to execute S1064 until the current backtracking node corresponds to a memory access instruction, and determine the offset reference value as the address offset calculation result.

[0079] The fourth preset condition can refer to the instruction type being a multiplication-addition operation type, an addition operation type, or a subtraction operation type. When the temporary node is a multiplication-addition operation type, its addition operation bit is usually the third operation bit. When the temporary node is an addition operation type or a subtraction operation type, its addition operation bit is the first operation bit and the second operation bit.

[0080] Specifically, if the instruction type corresponding to the previous backtracking node in the backtracking path satisfies the third preset condition, and the current backtracking node is related to the multiplication operation bit of the previous backtracking node, and the multiplication operation bit of the previous backtracking node is also related to the immediate value, then the product of the immediate value related to the multiplication operation bit of the previous backtracking node and the offset reference value is used as the offset intermediate value.

[0081] If the previous backtracking node of the current backtracking node in the backtracking path satisfies the fourth preset condition, and the current backtracking node is related to the addition operation bit of the previous backtracking node, and the addition operation bit of the previous backtracking node is related to the immediate value, then the sum of the immediate value related to the addition operation bit of the previous backtracking node and the offset reference value is used as the offset intermediate value.

[0082] Following the example above, in [ADD%11,%9,0x02], the addition operation bit of the ADD%11 node includes the immediate value 0x02. The ADD%11 node can be used as a temporary node. The ADD%11 node is used as the current backtracking node, and its backtracking path is IMA%12 and LDG%13. The previous backtracking node of the current backtracking node is the IMA%12 node. The IMA%12 node satisfies the third preset condition, and the current backtracking node is related to the multiplication operation bit of the IMA%12 node. The multiplication operation bit of the IMA%12 node is also related to the immediate value 0x02. Then, the offset intermediate value 0x04 is calculated based on the immediate value 0x02 related to the multiplication operation bit of the previous backtracking node and the offset reference value 0x02.

[0083] In one specific implementation, the base address is calculated based on the current two instruction sets, including:

[0084] For any set of instructions, the nodes in the tree structure of the instruction set whose instruction types satisfy the third preset condition are taken as intermediate nodes;

[0085] Traverse each intermediate node. If the intermediate node is of the first instruction type or the second instruction type, and the addition operation bit of the intermediate node is related to the virtual register and the immediate value, then delete the node corresponding to the immediate value and assign the virtual register to the intermediate node.

[0086] If the intermediate node is of the third instruction type and the addition operation bit of the intermediate node is related to the immediate value, then the node corresponding to the immediate value is deleted and the instruction type of the intermediate node is changed to the fourth instruction type.

[0087] Obtain the optimized tree structure corresponding to the instruction set;

[0088] The base address calculation result is determined based on the optimization tree structure corresponding to the two instruction sets.

[0089] The first instruction type is an addition operation type, the second instruction type is a subtraction operation type, the third instruction type is a multiplication-addition operation type, and the fourth instruction type is a multiplication operation type.

[0090] Specifically, for example, for the instruction [ADD%11,%9,0x02] which is an addition operation type, there are nodes ADD%11, %9, and 0x02. The 0x02 node corresponding to the immediate value is deleted, and the virtual register %9 node is assigned to the ADD%11 node. That is, [ADD%11,%9,0x02] only corresponds to the %9 node.

[0091] By optimizing the tree structure, a unified base address can be determined.

[0092] In one specific implementation, determining the instruction optimization result based on the address offset calculation result and the base address calculation result includes:

[0093] Based on the address offset calculation results and the base address calculation results, the target instruction set is reconstructed, and the target instruction set is used as the instruction optimization result.

[0094] Specifically, based on the base address calculation result, a unified base address and base address calculation instructions can be determined. Based on the unified base address and the address offset calculation results corresponding to different instruction sets, the memory access instructions corresponding to different instruction sets are updated. A target instruction set is formed based on several base address calculation instructions and each updated memory access instruction.

[0095] Specifically, for any memory access instruction corresponding to any instruction set, a unified base address is used as the base address of the updated memory access instruction. The address offset calculation result corresponding to the instruction set is added to the offset of the memory access instruction corresponding to the instruction set, and the sum is used as the offset of the updated memory access instruction.

[0096] See Figure 4 This is a schematic diagram of instruction optimization for a first example instruction set and a second example instruction set in a memory access instruction optimization method provided in an embodiment of the present invention, wherein the instruction optimization diagram includes the optimized instruction set.

[0097] Compared to the unoptimized instruction sets, the target instruction set effectively reduces the number of instructions used for address calculations, thereby reducing the computational load on the chip and improving its computational efficiency.

[0098] In one specific implementation, the memory access instruction optimization method further includes:

[0099] S106, if the Q memory access instructions in the instruction optimization result satisfy the fifth preset condition, then the memory access instructions in the instruction optimization result are converted into the target memory access instruction and Q copy instructions, where Q is an integer greater than one.

[0100] The fifth preset condition can refer to the fact that the difference between adjacent offsets in the offsets of the Q memory access instructions is the same as the bit width of the memory access instruction. For example, if the bit width of the memory access instruction is 32 bits, corresponding to 4 bytes, and the difference between adjacent offsets in the offsets of the Q memory access instructions is 4 bytes, such as 0x04, 0x08, etc., then the Q memory access instructions in the instruction optimization result can be converted into a single target memory access instruction. The bit width of the target memory access instruction is Q×32 bits, the base address of the target access instruction is the same as the base address of the Q memory access instructions, the offset of the target access instruction is the same as the minimum offset of the Q memory access instructions, the target access instruction corresponds to the target register, the virtual register in the Q copy instructions can correspond to the virtual register of the Q memory access instructions, and the access address of the qth copy instruction can be the qth sub-segment of the target register, where q is an integer in the range [1, Q] and the bit width of the sub-segment is 32 bits.

[0101] Taking the two memory access instructions [LDG%13,%12,0x04] and [LDG%16,%12,0x08] in the instruction optimization result as examples that satisfy the fifth preset condition, the target memory access instruction can be [LDG%17,%12,0x04]. Correspondingly, the copy instructions can be [COPY%13,%17.sub_bit0] and [COPY%16,%17.sub_bit1]. Here, %17.sub_bit0 can represent fetching the first sub-segment of the target register %17, and %17.sub_bit1 can represent fetching the second sub-segment of the target register %17.

[0102] This embodiment merges shorter memory access instructions that meet the conditions into longer memory access instructions, thereby effectively reducing the number of memory access instructions. Since the execution time of memory access instructions is usually much longer than that of copy instructions, this effectively reduces the execution time of memory access instructions and thus improves the efficiency of memory access instruction execution.

[0103] In this embodiment, the tree structure corresponding to the instruction set is constructed by traversing the instruction set. The tree structures of the instruction sets are compared to determine whether the base addresses of different instruction sets are consistent. When the base addresses of different instruction sets are consistent, the different instruction sets can be merged and optimized to obtain the instruction optimization result, thereby reducing the number of instructions related to address calculation, reducing the computational load of the chip, and improving the computational efficiency of the chip.

[0104] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. A method for optimizing memory access instructions, characterized in that, The memory access instruction optimization method includes: S101, obtain M instruction sets, wherein the m-th instruction set includes K(m) basic instructions, the K(m)-th basic instruction is a memory access instruction, m is an integer in the range [1, M], the basic instruction includes instruction type, virtual register and several operands, and M is a positive integer; S102, For any instruction set, construct a root node based on the instruction type and virtual registers included in the memory access instructions in the instruction set, and use the root node as the parent node; S103, Generate each child node corresponding to the parent node according to each operand included in the basic instruction corresponding to the parent node; S104, take all child nodes that meet the first preset condition as parent nodes, return to step S103, until there are no child nodes that meet the first preset condition, and obtain the tree structure corresponding to the instruction set. S105, compare the tree structures of any two instruction sets. If the comparison result meets the second preset condition, optimize the current two instruction sets to obtain the instruction optimization result.

2. The memory access instruction optimization method according to claim 1, characterized in that, The operands include immediate values ​​and virtual registers; Step S103 includes the following steps: S1031, for any operand contained in the parent node, if the operand is an immediate value, generate the child node corresponding to the parent node according to the immediate value; S1032, if the operand is a virtual register and the virtual register does not have a corresponding basic instruction, generate the child node corresponding to the parent node based on the virtual register; S1033, if the operand is a virtual register and the virtual register has a corresponding basic instruction, generate the child node corresponding to the parent node according to the instruction type contained in the virtual register and its corresponding basic instruction.

3. The memory access instruction optimization method according to claim 2, characterized in that, The steps to determine whether a child node satisfies the first preset condition include: For any child node, if the operand corresponding to the child node is an immediate value, then it is determined that the child node does not meet the first preset condition. If the operand corresponding to the child node is a virtual register and the virtual register exists in at least two instruction sets, then the child node is determined not to meet the first preset condition. Otherwise, determine that the child node satisfies the first preset condition.

4. The memory access instruction optimization method according to claim 3, characterized in that, Step S104 also includes the following steps: The parent node whose child nodes do not meet the first preset condition is designated as the termination instruction node.

5. The memory access instruction optimization method according to claim 4, characterized in that, The tree structure contains several nodes, each node corresponding to either a root node or a child node; The comparison of the tree structures of any two instruction sets includes: S1051, the tree structures of the two instruction sets are respectively used as the first tree structure and the second tree structure; S1052, compare the topology of the first tree structure and the second tree structure to obtain the first comparison result; S1053, if the first comparison result is a match, then determine several node pairs based on the first tree structure and the second tree structure, and check each node pair; S1054: When two nodes in any node pair are not child nodes of the termination instruction node, and both nodes in the node pair correspond to virtual registers, if each of the two virtual registers corresponds to a basic instruction, then the second comparison result corresponding to the node pair is determined to be consistent; otherwise, the two virtual registers are compared to obtain the second comparison result corresponding to the node pair. S1055, when two nodes in any node pair are child nodes of the termination instruction node, and both nodes in the node pair correspond to virtual registers, the two virtual registers are compared to obtain the second comparison result corresponding to the node pair. S1056, when two nodes in any node pair are immediate values, backtrack any node in the node pair to the root node in the tree structure to obtain the backtracking path corresponding to the node, and the backtracking path contains several backtracking nodes. S1057, if any backtracking node in the backtracking path is related to the multiplication operation bit of a node whose instruction type satisfies the third preset condition, and the multiplication operation bit of the node whose instruction type satisfies the third preset condition is also related to a virtual register, then the two immediate values ​​are compared to obtain the second comparison result corresponding to the node pair; otherwise, it is determined that the second comparison result corresponding to the node pair is consistent.

6. The memory access instruction optimization method according to claim 5, characterized in that, If the comparison result meets the second preset condition, then the current two instruction sets are optimized to obtain the instruction optimization result, including: If the second comparison results of each node pair are consistent, it is determined that the comparison results meet the second preset condition. Address offset calculation and base address calculation are performed based on the current two instruction sets. Based on the address offset calculation results and base address calculation results, the instruction optimization result is determined.

7. The memory access instruction optimization method according to claim 6, characterized in that, Calculate the address offset based on the current two instruction sets, including: S1061, For any instruction set, determine the nodes in the tree structure of the instruction set whose instruction types satisfy the fourth preset condition as temporary nodes; S1062, If the addition operation bit of the temporary node is an immediate value, backtrack the temporary node to the root node in the tree structure to obtain the backtracking path corresponding to the temporary node. S1063, use the temporary node as the current backtracking node, and use the immediate value of the addition operation bit of the temporary node as the offset reference value; S1064, if the instruction type corresponding to the previous backtracking node of the current backtracking node in the backtracking path satisfies the third preset condition, and the current backtracking node is related to the multiplication operation bit of the previous backtracking node, and the multiplication operation bit of the previous backtracking node is also related to the immediate value, then the offset intermediate value is calculated based on the immediate value related to the multiplication operation bit of the previous backtracking node and the offset reference value. S1065, if the previous backtracking node of the current backtracking node in the backtracking path satisfies the fourth preset condition and the addition operation bit of the current backtracking node is related to the previous backtracking node, then the offset reference value is used as the offset intermediate value. S1066, if the previous backtracking node of the current backtracking node in the backtracking path satisfies the fourth preset condition, and the current backtracking node is related to the addition operation bit of the previous backtracking node, and the addition operation bit of the previous backtracking node is related to the immediate value, then the offset intermediate value is calculated based on the immediate value related to the addition operation bit of the previous backtracking node and the offset reference value. S1067, otherwise, switch the temporary node and return to step S1062; S1068: Using the previous backtracking node as the current backtracking node and the offset median value as the offset reference value, return to execute S1064 until the current backtracking node corresponds to a memory access instruction, and determine the offset reference value as the address offset calculation result.

8. The memory access instruction optimization method according to claim 7, characterized in that, The base address is calculated based on the current two instruction sets, including: For any set of instructions, the nodes in the tree structure of the instruction set whose instruction types satisfy the third preset condition are taken as intermediate nodes; Traverse each intermediate node. If the intermediate node is of the first instruction type or the second instruction type, and the addition operation bit of the intermediate node is related to the virtual register and the immediate value, then delete the node corresponding to the immediate value and assign the virtual register to the intermediate node. If the intermediate node is of the third instruction type and the addition operation bit of the intermediate node is related to the immediate value, then the node corresponding to the immediate value is deleted and the instruction type of the intermediate node is changed to the fourth instruction type. Obtain the optimized tree structure corresponding to the instruction set; The base address calculation result is determined based on the optimization tree structure corresponding to the two instruction sets.

9. The memory access instruction optimization method according to claim 8, characterized in that, The step of determining the instruction optimization result based on the address offset calculation result and the base address calculation result includes: Based on the address offset calculation results and the base address calculation results, the target instruction set is reconstructed, and the target instruction set is used as the instruction optimization result.

10. The memory access instruction optimization method according to claim 8, characterized in that, The memory access instruction optimization method further includes: S106, if the Q memory access instructions in the instruction optimization result satisfy the fifth preset condition, then the memory access instructions in the instruction optimization result are converted into the target memory access instruction and Q copy instructions, where Q is an integer greater than one.

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