Method, system, medium, terminal and program product for jump instruction splitting and launching

Abstract

The application provides a method, system, medium, terminal and program product for splitting and transmitting jump instructions. The method comprises the following steps: obtaining an instruction to be executed and a corresponding data space, dividing the data space into a plurality of logical blocks, splitting each logical block into a plurality of sub-blocks with the same number, and generating micro-operations for each sub-block; for a current sub-block sequence number, sequentially selecting the micro-operations of the corresponding sub-block across a plurality of logical blocks to transmit, switching the sub-block sequence number after completing a round of logical block traversal, and until all micro-operation transmissions are completed. The logical block index and the sub-block index can also be determined based on a natural transmission count through a preset mapping function. The application can reduce the probability of head and tail address conflict of adjacent micro-operations, reduce storage arbitration, scheduling and write-back conflict, and improve the stability of the pipeline without changing the storage layout and transmission throughput.

Description

Technical Field

[0001] This application relates to the field of instruction splitting and transmission technology, and in particular to a skip instruction splitting and transmission method, system, medium, terminal and program product. Background Technology

[0002] In AI accelerators, operators such as GridSample, interpolation, and feature map processing often consist of logical data blocks in W and K dimensions, such as W32K4. Hardware controllers typically break down an instruction into multiple Units of Operation (UOPs), which are then pipelined and executed by the memory access module, computation module, and write-back module.

[0003] When a logical block is split into multiple smaller sub-blocks, the intuitive way to issue UOPs is to issue them sequentially within the block. For example, issue W32_0_sub0 first, then W32_0_sub1, then W32_1_sub0 and W32_1_sub1. This sequential issuance within the block is simple to control, but in scenarios where data space exhibits locality, the access addresses of adjacent UOPs are often contiguous or very close, making them prone to falling into the same bank group, the same cache line, the same storage conflict detection window, the same write-back merge window, or adjacent half-segments.

[0004] The aforementioned head-to-tail address conflicts between adjacent UOPs can increase L1 read-write arbitration conflicts, bank conflict detection conflicts, non-linear read scheduling conflicts, write-back queue conflicts, or merge / schedule logic conflicts, causing backpressure, bubbles, or additional wait times in the pipeline. Especially when UOPs are continuously issued 1 / cycle, the address correlation between adjacent UOPs directly affects the parallelism of memory access and pipeline stability.

[0005] Therefore, it is necessary to provide a skip-style instruction splitting and issuing method, system, medium, terminal and program product, which aims to solve the problem of increased memory access conflicts caused by the sequential issuance of micro-operations after instruction splitting. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method, system, medium, terminal and program product for skip instruction splitting and sending, so as to solve the above problems.

[0007] To achieve the above and other related objectives, a first aspect of this application provides a skip-style instruction splitting and issuing method, comprising: acquiring an instruction to be executed and its corresponding data space; dividing the data space into multiple logical blocks; splitting each logical block into multiple sub-blocks of the same number; generating corresponding micro-operations for each sub-block; wherein corresponding sub-blocks in different logical blocks have the same sub-block number; issuing each micro-operation according to a preset issuing order; wherein the preset issuing order includes: for the current sub-block number, sequentially selecting the micro-operation corresponding to the sub-block with the current sub-block number from each logical block according to the arrangement order of the multiple logical blocks; after completing the traversal of the multiple logical blocks, determining the next sub-block number to be traversed as the new current sub-block number according to the preset sub-block traversal order, and re-selecting the corresponding micro-operations sequentially according to the arrangement order of the multiple logical blocks, until the issuing of all micro-operations corresponding to the sub-blocks in each logical block is completed.

[0008] In some embodiments of the first aspect of this application, the specific process of transmitting each of the micro-operations in a preset transmission order includes: obtaining a natural transmission count, wherein the natural transmission count is accumulated one by one as the micro-operations are transmitted; and calculating the logic block and sub-block corresponding to the micro-operation to be transmitted using a preset mapping function based on the natural transmission count.

[0009] In some embodiments of the first aspect of this application, the preset mapping function specifically includes: performing a modulo operation based on the natural emission count and the total number of the plurality of logic blocks to obtain the logic block corresponding to the current micro-operation to be emitted; performing an integer division operation based on the natural emission count and the total number of the plurality of logic blocks to obtain the current logic block traversal round, and determining the current sub-block index according to the current logic block traversal round and the preset sub-block traversal order; when the preset sub-block traversal order is in ascending order of sub-block number, determining the current logic block traversal round as the current sub-block index.

[0010] In some embodiments of the first aspect of this application, the number of sub-blocks of each logic block is determined according to the data type of the instruction to be executed. Specifically: when the data type is a first data type, the number of sub-blocks is two; when the data type is a second data type, the number of sub-blocks is four; the bit width of the first data type is smaller than the bit width of the second data type.

[0011] In some embodiments of the first aspect of this application, the logic block is a W32K4 logic block.

[0012] In some embodiments of the first aspect of this application, the preset sub-block traversal order is either in ascending order of sub-block number or in a sub-block priority order determined according to the storage address distribution corresponding to each sub-block.

[0013] To achieve the above and other related objectives, a second aspect of this application provides a skip-type instruction splitting and issuing system, comprising: an instruction splitting module, configured to acquire an instruction to be executed and its corresponding data space, divide the data space into multiple logical blocks, and split each logical block into multiple sub-blocks of the same number, generating corresponding micro-operations for each sub-block; wherein corresponding sub-blocks in different logical blocks have the same sub-block sequence number; and an issuing control module, configured to issue each micro-operation according to a preset issuing order; wherein the preset issuing order includes: for the current sub-block sequence number, selecting the micro-operation corresponding to the sub-block with the current sub-block sequence number from each logical block in the order of arrangement of the multiple logical blocks; after completing the traversal of the multiple logical blocks, determining the next sub-block sequence number as the new current sub-block sequence number, and re-selecting the corresponding micro-operation in the order of arrangement of the multiple logical blocks, until the issuing of all micro-operations corresponding to the sub-blocks in each logical block is completed.

[0014] To achieve the above and other related objectives, a third aspect of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the skip instruction splitting and issuing method.

[0015] To achieve the above and other related objectives, a fourth aspect of this application provides a computer program product comprising computer program code, which, when executed on a computer, enables the computer to implement the jump instruction splitting and issuing method.

[0016] To achieve the above and other related objectives, a fifth aspect of this application provides an electronic terminal, including a memory, a processor, and a computer program stored in the memory; the processor executes the computer program to implement the skip instruction splitting and sending method.

[0017] As described above, this application has the following beneficial effects:

[0018] This application divides the data space corresponding to the instruction to be executed into multiple logical blocks, and further divides each logical block into multiple sub-blocks of equal number. During the micro-operation issuance process, the current sub-block number remains unchanged, and the micro-operation of the corresponding sub-block is selected sequentially across multiple logical blocks. After completing one round of logical block traversal, the sub-block number is switched. This changes the behavior of adjacent micro-operations from accessing adjacent sub-blocks within the same logical block to accessing corresponding sub-blocks in different logical blocks. This increases the address span between adjacent micro-operations, reduces the probability that the tail address of the previous micro-operation and the head address of the next micro-operation fall into the same storage conflict detection window, the same bank group, or the same write-back merging window, and reduces storage access arbitration conflicts, bank conflicts, scheduling conflicts, and write-back conflicts. It also reduces the possibility of pipeline blockage and cavitation.

[0019] Meanwhile, this application can determine the current logical block index and the current sub-block index through natural emission counting and preset mapping functions, without the need to set complex independent emission states for different data types. It can achieve skip-emission while maintaining continuous emission throughput of micro-operations. In addition, this application does not require changing the original data storage layout, nor does it require adding storage ports, expanding buffer queues, or reducing the micro-operation emission frequency. This helps to reduce hardware area overhead and control complexity, and improve the parallelism of storage access and the stability of hardware pipeline operation. Attached Figure Description

[0020] Figure 1 The diagram shown is a flowchart illustrating a skip-command splitting and issuing method according to an embodiment of this application.

[0021] Figure 2 The diagram shown is a structural schematic of a skip-command splitting and launching system according to an embodiment of this application.

[0022] Figure 3 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this application. Detailed Implementation

[0023] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0024] In the embodiments of this application, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" do not necessarily imply that they are different.

[0025] It should be noted that, in the embodiments of this application, the words "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0026] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0027] The technical solutions of this application can be applied to various communication systems, such as: Long Term Evolution (LTE) systems, LTE Frequency Division Duplex (FDD) systems, future 5th Generation (5G) communication systems, new radio access technology (NR), LTE Time Division Duplex (TDD), Worldwide Interoperability for Microwave Access (WiMAX), Universal Mobile Telecommunication System (UMTS), and vehicle-to-XV2X. V2X can include vehicle to network (V2N), vehicle to vehicle (V2V), vehicle to infrastructure (V2I), vehicle to pedestrian (V2P), Long Term Evolution-Vehicle (LTE-V), vehicle-to-everything (V2X), machine-type communication (MTC), Internet of Things (IoT), Long Term Evolution-Machine (LTE-M), and machine to machine (M2M).

[0028] To facilitate understanding of the embodiments of this application, firstly, in conjunction with Figure 1 Detailed explanation. Figure 1 A flowchart illustrating a skip-command splitting and issuing method according to an embodiment of the present invention is shown. The skip-command splitting and issuing method in this embodiment mainly includes the following steps:

[0029] Step S11: Obtain the instruction to be executed and the corresponding data space, divide the data space into multiple logical blocks, and split each logical block into multiple sub-blocks of the same number, and generate corresponding micro-operations for each sub-block; wherein, the corresponding sub-blocks in different logical blocks have the same sub-block number.

[0030] Specifically, the controller receives the instruction to be executed and parses it to obtain instruction parameters such as data type, data space size, source address, destination address, step size, and execution granularity. Based on the data space size and execution granularity, the controller determines the data space covered by the instruction and divides it into multiple sequentially arranged logical blocks according to a preset logical block specification. Each logical block can be assigned a corresponding logical block index according to its position in the data space; for example, the logical block indices can be set sequentially from 0 to M-1, where M is the total number of logical blocks.

[0031] In one embodiment of this application, the number of sub-blocks of each logic block is determined according to the data type of the instruction to be executed. Specifically: when the data type is a first data type, the number of sub-blocks is two; when the data type is a second data type, the number of sub-blocks is four; the bit width of the first data type is smaller than the bit width of the second data type.

[0032] In one embodiment of this application, the logical block is a data block defined by both the W and K dimensions. For example, the logical block can be a W32K4 logical block, meaning that each logical block includes 32 data positions in the W dimension and 4 data positions in the K dimension. It should be noted that W32K4 is only an exemplary logical block specification. In other embodiments, other combinations of W and K dimensions can be used to form the logical block according to the operator type corresponding to the instruction to be executed, the width of the computation array, or the storage access granularity.

[0033] After the logical block partitioning is completed, the number of sub-blocks corresponding to each logical block is determined according to the data type of the instruction to be executed. Specifically, when the data type is a first data type, each logical block is split into two sub-blocks; when the data type is a second data type, each logical block is split into four sub-blocks. The bit width of the first data type is smaller than the bit width of the second data type. For example, the first data type can be an int8 data type, and the second data type can be an int16 data type. When the data type of the instruction to be executed is an int8 data type, each W32K4 logical block is split into two sub-blocks; when the data type of the instruction to be executed is an int16 data type, each W32K4 logical block is split into four sub-blocks.

[0034] Furthermore, sub-block numbers are assigned to the multiple sub-blocks within each logic block. For the case of splitting into two sub-blocks, the sub-block numbers can be sub0 and sub1, respectively; for the case of splitting into four sub-blocks, the sub-block numbers can be sub0, sub1, sub2, and sub3, respectively. Since the logic blocks corresponding to the same instruction to be executed use the same splitting method, sub-blocks in the same relative position within different logic blocks have the same sub-block number. For example, sub0 in the 0th logic block corresponds to sub0 in the 1st logic block, and sub1 in the 0th logic block corresponds to sub1 in the 1st logic block.

[0035] Furthermore, a corresponding micro-operation is generated for each sub-block. Each micro-operation is associated with at least a corresponding logical block index and sub-block number, and the data access range and execution parameters corresponding to the micro-operation can be determined based on the source address, destination address, and step size information in the instruction to be executed. Thus, each micro-operation can be uniquely identified by a combination of the logical block index and the sub-block number.

[0036] For example, when the data space comprises four W32K4 logic blocks, and each W32K4 logic block is split into two sub-blocks, the generated micro-operations include:

[0037] W32_0_sub0, W32_0_sub1;

[0038] W32_1_sub0, W32_1_sub1;

[0039] W32_2_sub0, W32_2_sub1;

[0040] W32_3_sub0, W32_3_sub1.

[0041] When each W32K4 logic block is split into four sub-blocks, four micro-operations with sub-block numbers sub0, sub1, sub2 and sub3 are generated for each logic block.

[0042] Step S12: Execute each micro-operation according to a preset execution order; wherein the preset execution order includes: for the current sub-block number, select the micro-operation corresponding to the sub-block with the current sub-block number from each of the multiple logic blocks in the order of arrangement; after completing the traversal of the multiple logic blocks, determine the next sub-block number to be traversed as the new current sub-block number according to the preset sub-block traversal order, and select the corresponding micro-operation again in the order of arrangement of the multiple logic blocks until the execution of the micro-operations corresponding to all sub-blocks in each of the logic blocks is completed.

[0043] Specifically, for multiple sub-blocks within multiple logic blocks, instead of continuously issuing all micro-operations corresponding to the sub-blocks within the same logic block, the micro-operations corresponding to the sub-blocks with the current sub-block number are selected sequentially from different logic blocks according to the order of the multiple logic blocks, while keeping the current sub-block number unchanged. Thus, during the same round of logic block traversal, adjacent micro-operations belong to different logic blocks. After completing one round of logic block traversal corresponding to the current sub-block number, the next sub-block number to be traversed is determined as the new current sub-block number, and the next round of logic block traversal begins again from the first logic block.

[0044] Compared to the method of continuously issuing micro-operations corresponding to adjacent sub-blocks within a single logic block, this issuance order allows adjacent micro-operations to proceed across different logic blocks, thereby breaking up the address access relationships between adjacent micro-operations.

[0045] In one embodiment of this application, the specific process of transmitting each micro-operation according to a preset transmission order includes: obtaining a natural transmission count, wherein the natural transmission count is accumulated one by one as micro-operations are transmitted; and calculating the logic block and sub-block corresponding to the micro-operation to be transmitted using a preset mapping function based on the natural transmission count.

[0046] In one embodiment of this application, the preset mapping function specifically includes: performing a modulo operation based on the natural emission count and the total number of the plurality of logic blocks to obtain the logic block corresponding to the current micro-operation to be emitted; performing an integer division operation based on the natural emission count and the total number of the plurality of logic blocks to obtain the current logic block traversal round, and determining the current sub-block index according to the current logic block traversal round and the preset sub-block traversal order; when the preset sub-block traversal order is in ascending order of sub-block sequence number, determining the current logic block traversal round as the current sub-block index.

[0047] Specifically, let the natural emission count be n and the total number of the multiple logic blocks be M. Then, perform a modulo operation between the natural emission count n and the total number of logic blocks M, and determine the current logic block index using the modulo result.

[0048] Simultaneously, the natural emission count value n is divided by the total number of logic blocks M, and the result of the division is determined as the current logic block traversal round.

[0049] When the preset sub-block traversal order is in ascending order of sub-block numbers, the current logical block traversal round is directly determined as the current sub-block index. Therefore, when the natural emission count n varies within the range of 0 to M-1, the current sub-block index remains 0, and the current logical block index changes sequentially from 0 to M-1; when the natural emission count n increases to M, the current logical block index becomes 0 again, and the current sub-block index switches to 1, thus starting the traversal of the logical block corresponding to the next sub-block number.

[0050] In one specific embodiment, when a row of data includes four W32K4 logic blocks, and each W32K4 logic block is split into two sub-blocks, the total number of logic blocks M is 4, the total number of sub-blocks S is 2, and the natural emission count value n is 0 to 7. According to the aforementioned preset mapping function, the obtained logic block index and sub-block index are as follows:

[0051] When n = 0, 1, 2, 3, the current sub-block index is 0, and the current logical block index is 0, 1, 2, 3 respectively;

[0052] When n = 4, 5, 6, 7, the current sub-block index is 1, and the current logical block index is 0, 1, 2, 3 respectively.

[0053] Therefore, the corresponding micro-operation launch sequence is:

[0054] W32_0_sub0, W32_1_sub0, W32_2_sub0, W32_3_sub0, W32_0_sub1, W32_1_sub1, W32_2_sub1, W32_3_sub1.

[0055] When each W32K4 logic block is divided into four sub-blocks, the natural emission count n ranges from 0 to 15. Every four consecutive natural emission counts correspond to one round of logic block traversal. During each round of logic block traversal, the current sub-block index remains unchanged, while the current logic block index changes sequentially from 0 to 3. The corresponding micro-operation emission sequence is as follows:

[0056] W32_0_sub0, W32_1_sub0, W32_2_sub0, W32_3_sub0,

[0057] W32_0_sub1, W32_1_sub1, W32_2_sub1, W32_3_sub1,

[0058] W32_0_sub2, W32_1_sub2, W32_2_sub2, W32_3_sub2,

[0059] W32_0_sub3, W32_1_sub3, W32_2_sub3, W32_3_sub3.

[0060] In one embodiment of this application, the preset sub-block traversal order is either in ascending order of sub-block number or in a sub-block priority order determined according to the storage address distribution corresponding to each sub-block.

[0061] When the preset sub-block traversal order is in ascending order of sub-block numbers, i.e., sub-block numbers sub0, sub1, ..., subS-1 are sequentially determined as the current sub-block number, the natural emission count value divided by the total number of logic blocks can be directly used as the current sub-block index.

[0062] In another embodiment of this application, the preset sub-block traversal order is a sub-block priority order predetermined based on the distribution of storage addresses corresponding to each sub-block. Specifically, based on the distribution of storage units, bank groups, address regions, or conflict detection windows corresponding to different sub-blocks, a corresponding traversal priority can be configured for each sub-block number, forming a sub-block traversal order table. After obtaining the current logical block traversal round, the sub-block traversal order table is queried using the current logical block traversal round, and the queried sub-block number is determined as the current sub-block index. For example, for four sub-blocks, the preset sub-block traversal order can be sub0, sub2, sub1, and sub3, then the current sub-block numbers corresponding to the logical block traversals from round 0 to round 3 are sub0, sub2, sub1, and sub3, respectively.

[0063] Figure 2 This is a structural block diagram of the skip-command splitting and issuing system 200 provided in an embodiment of this application. For example... Figure 2 As shown, the device includes an instruction splitting module 201 and a launch control module 202.

[0064] The instruction splitting module 201 is used to obtain the instruction to be executed and the corresponding data space, divide the data space into multiple logical blocks, and split each logical block into multiple sub-blocks of the same number, and generate corresponding micro-operations for each sub-block; wherein, corresponding sub-blocks in different logical blocks have the same sub-block number.

[0065] The launch control module 202 is used to launch each of the micro-operations according to a preset launch sequence; wherein the preset launch sequence includes: for the current sub-block number, selecting the micro-operation corresponding to the sub-block with the current sub-block number from each of the multiple logic blocks in the order of arrangement; after completing the traversal of the multiple logic blocks, determining the next sub-block number as the new current sub-block number, and selecting the corresponding micro-operation again in the order of arrangement of the multiple logic blocks, until the launch of the micro-operations corresponding to all sub-blocks in each of the multiple logic blocks is completed.

[0066] It should be understood that the specific process of each module performing the above-mentioned steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0067] It should also be understood that the module division in the embodiments of this application is illustrative and only represents a logical functional division; in actual implementation, there may be other division methods. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0068] Figure 3 This is a schematic block diagram of the electronic terminal provided in an embodiment of this application. Figure 3 As shown, the electronic terminal 300 includes at least one processor 301, a memory 302, at least one network interface 303, and a user interface 305. The various components in the electronic terminal 300 are coupled together via a bus system 304. It is understood that the bus system 304 is used to implement communication between these components. In addition to a data bus, the bus system 304 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in… Figure 3 The general will label all buses as bus systems.

[0069] The user interface 305 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0070] It is understood that memory 302 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0071] In this embodiment of the invention, the memory 302 is used to store various types of data to support the operation of the electronic terminal 300. Examples of this data include: any executable program for operation on the electronic terminal 300, such as the operating system 3021 and application programs 3022; the operating system 3021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 3022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The method for implementing the jump instruction splitting and issuing provided in this embodiment of the invention can be included in the application program 3022.

[0072] The methods disclosed in the above embodiments of the present invention can be applied to processor 301, or implemented by processor 301. Processor 301 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 301 or by instructions in the form of software. The processor 301 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 301 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. General-purpose processor 301 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0073] In an exemplary embodiment, the electronic terminal 300 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to execute the aforementioned method.

[0074] According to the method provided in the embodiments of this application, this application also provides a computer program product, which includes: computer program code, which, when run on a computer, causes the computer to execute the skip instruction splitting and issuing method of any of the above embodiments.

[0075] According to the method provided in the embodiments of this application, this application also provides a computer-readable storage medium storing program code, which, when run on a computer, causes the computer to execute the skip instruction splitting and issuing method of any of the above embodiments.

[0076] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0077] Those skilled in the art will recognize that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0078] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0079] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0080] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0081] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0082] In the above embodiments, the functions of each functional unit can be implemented entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., high-density digital video discs (DVDs)), or semiconductor media (e.g., solid-state disks (SSDs)).

[0083] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0084] In summary, this application provides a skip-style instruction splitting and issuing method, system, medium, terminal, and program product. The method obtains the instruction to be executed and its corresponding data space, divides the data space into multiple logical blocks, and further divides each logical block into an equal number of sub-blocks, generating micro-operations for each sub-block. For the current sub-block index, the method sequentially selects the corresponding sub-block's micro-operation across multiple logical blocks for issuing. After completing one round of logical block traversal, the sub-block index is switched until all micro-operations have been issued. The logical block index and sub-block index can also be determined based on a preset mapping function using natural issuance counts. This invention can reduce the probability of head-to-tail address conflicts between adjacent micro-operations, reduce storage arbitration, scheduling, and write-back conflicts, and improve pipeline stability without changing the storage layout and issuance throughput. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0085] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A method for splitting and issuing skip-type commands, characterized in that, include: Obtain the instruction to be executed and its corresponding data space, divide the data space into multiple logical blocks, and further divide each logical block into multiple sub-blocks of the same number, generating corresponding micro-operations for each sub-block; wherein, corresponding sub-blocks in different logical blocks have the same sub-block number; Each micro-operation is launched according to a preset launch order; wherein the preset launch order includes: for the current sub-block number, selecting the micro-operation corresponding to the sub-block with the current sub-block number from each of the multiple logic blocks in the order of arrangement; after completing the traversal of the multiple logic blocks, determining the next sub-block number to be traversed as the new current sub-block number according to the preset sub-block traversal order, and selecting the corresponding micro-operation again in the order of arrangement of the multiple logic blocks in the order of arrangement, until the launch of all micro-operations corresponding to the sub-blocks in each of the multiple logic blocks is completed.

2. The skip-command splitting and issuing method according to claim 1, characterized in that, The specific process of transmitting each micro-operation according to a preset transmission sequence includes: Obtain the natural emission count, which is accumulated one by one with each emission of the micro-operation; Based on natural emission counting, a preset mapping function is used to calculate the logic block and sub-block corresponding to the micro-operation to be emitted.

3. The skip-command splitting and issuing method according to claim 2, characterized in that, The preset mapping function specifically includes: The logic block corresponding to the current micro-operation to be emitted is obtained by performing a modulo operation based on the natural emission count and the total number of the plurality of logic blocks; The current logic block traversal round is obtained by dividing the natural emission count by the total number of the multiple logic blocks, and the current sub-block index is determined according to the current logic block traversal round and the preset sub-block traversal order. When the preset sub-block traversal order is in ascending order of sub-block number, the current logic block traversal round is determined as the current sub-block index.

4. The skip-command splitting and issuing method according to claim 1, characterized in that, The number of sub-blocks in each logical block is determined according to the data type of the instruction to be executed, specifically: When the data type is the first data type, the number of sub-blocks is two; When the data type is the second data type, the number of sub-blocks is four; The bit width of the first data type is smaller than the bit width of the second data type.

5. The skip-command splitting and issuing method according to claim 1, characterized in that, The logic block is a W32K4 logic block.

6. The skip-command splitting and issuing method according to claim 1, characterized in that, The preset sub-block traversal order is either in ascending order of sub-block number or in a sub-block priority order determined according to the distribution of storage addresses corresponding to each sub-block.

7. A skip-command splitting and issuing system, characterized in that, include: The instruction splitting module is used to obtain the instruction to be executed and its corresponding data space, divide the data space into multiple logical blocks, and split each logical block into multiple sub-blocks of the same number, and generate corresponding micro-operations for each sub-block; wherein, corresponding sub-blocks in different logical blocks have the same sub-block number; The launch control module is used to launch each of the micro-operations according to a preset launch sequence. The preset launch sequence includes: for the current sub-block number, selecting the micro-operation corresponding to the sub-block with the current sub-block number from each of the multiple logic blocks in the order of arrangement; after completing the traversal of the multiple logic blocks, determining the next sub-block number as the new current sub-block number, and selecting the corresponding micro-operation again in the order of arrangement of the multiple logic blocks, until the launch of the micro-operations corresponding to all sub-blocks in each of the multiple logic blocks is completed.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the skip instruction splitting and issuing method as described in any one of claims 1 to 6.

9. A computer program product, characterized in that, The computer program product includes computer program code, which, when run on a computer, causes the computer to implement the skip instruction splitting and issuing method as described in any one of claims 1 to 6.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the skip instruction splitting and issuing method as described in any one of claims 1 to 6.

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