A restart control system for a mass storage embedded real-time operating system
Patent Information
- Application Number
- CN202611343517.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-01
- Publication Date
- 2026-10-27
AI Technical Summary
[0018]本申请的目的是针对大容量存储器设备在操作系统重启前后由于SPI NOR FLASH上字节地址模式与CPU字节地址模式不一致造成的操作系统加载失败的问题，提供一种大容量存储器下嵌入式实时操作系统的重启控制系统，设计以SPI为接口的容量超过16MB的SPI NOR FLASH作为程序载体的嵌入式实时操作系统重启方法，使嵌入式实时操作系统重启时，在模块不掉电情况下能够重新从SPI接口的大容量的SPI NOR FLASH上正确读取程序，进行重启
[0043]提供一种大容量存储器下嵌入式实时操作系统的重启控制系统：
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Figure CN122985258A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of embedded real-time operating system design technology, specifically relating to a restart control system for an embedded real-time operating system under a large-capacity memory. Background Technology
[0002] SPI NOR FLASH is a type of flash memory with a serial external interface. It communicates with the host controller via the SPI bus and offers advantages such as small package size, low power consumption, and fast response. Because SPI NOR FLASH uses a serial interface for data transmission, it has the advantage of fewer pins compared to parallel interfaces. It is widely used in embedded real-time operating systems where CPU controller pin resources are limited, such as VxWorks or Tianmai systems. VxWorks and Tianmai systems, as operating systems specifically designed and developed for embedded real-time systems, offer scalability, customizability, and high reliability, and are widely used in embedded fields such as aerospace and automotive.
[0003] SPI NOR FLASH supports two address modes: three-byte address mode and four-byte address mode. The addressable range of the three-byte address mode is 0~16MB, and the addressable range of the four-byte address mode is 0~4GB.
[0004] In embedded real-time operating systems, SPI NOR FLASH is widely used for operating system booting and loading. During startup, the CPU (such as Phytium 2000 / D2000) uses its SPI controller as the SPI master and the SPI NOR FLASH as the SPI slave. The CPU accesses the SPI NOR FLASH through the SPI interface to obtain the program stored there, and then loads and executes the system program. To correctly access the large storage area exceeding 16MB on the SPI NOR FLASH, the operating system needs to change the byte address mode of the SPI NOR FLASH from three-byte to four-byte address mode.
[0005] During operating system debugging, operating system restarts commonly occur in the following two situations:
[0006] User-initiated reset, such as using the reboot command to reset the operating system;
[0007] The operating system was abnormally reset due to anomalies such as program out of bounds.
[0008] When the operating system restarts, the board power supply is usually kept on, and only the CPU is reset. At this time, the CPU executes the loading program from the chip firmware area and reads the program from the SPI NOR FLASH memory area. The chip firmware area loads the program using a three-byte address mode from the SPI NOR FLASH. However, since the SPI NOR FLASH on the board was set to a four-byte address mode by the operating system before the restart, and the operating system does not power down the SPI NOR FLASH during the restart, the SPI NOR FLASH remains in four-byte address mode. This results in an inconsistency between the address modes of the SPI master and SPI slave devices on the SPI bus, causing the failure to read the program from the SPI NOR FLASH and thus causing the embedded real-time operating system to fail to restart.
[0009] Currently, the common approach to resolving operating system reboot failures caused by byte address mode inconsistencies between the SPI master and SPI slave devices is to power cycle the operating system board or manually reset the SPI NORFLASH. However, this approach has the following drawbacks:
[0010] This requires all devices on the operating system board to be powered on and off again, which will affect the normal operation of other devices.
[0011] Frequent power-on and power-off cycles during the debugging process generate frequent current pulse impacts on the equipment, which can easily cause equipment damage and increase the equipment failure rate.
[0012] When the operating system and the debugging equipment are located in different places, frequent power-on and power-off processes will reduce debugging efficiency and are not conducive to equipment debugging.
[0013] Only a few manufacturers' SPI NOR FLASH models support resetting the SPI NOR FLASH via external pins, which greatly limits its use and requires additional hardware resources such as control pins.
[0014] Additionally, in some designs for SPI NOR FLASH, without changing the byte address mode, extended address instructions are used to access memory areas exceeding 16MB. This method has the following drawbacks:
[0015] The extended address instructions of different SPI NOR FLASH manufacturers are not the same, and different drivers need to be written according to the product manuals of different manufacturers, resulting in poor driver portability.
[0016] SPI NOR FLASH with a capacity of less than 16MB only supports SPI standard commands. Drivers that support both SPI extended address commands and SPI standard commands need to be written, which makes driver development difficult.
[0017] In view of the aforementioned technical deficiencies, this application is hereby filed. Summary of the Invention
[0018] The purpose of this application is to address the problem of operating system loading failure caused by the inconsistency between the byte address mode on the SPI NOR FLASH and the CPU byte address mode before and after the operating system restart in large-capacity memory devices. It provides a restart control system for an embedded real-time operating system under large-capacity memory, and designs a restart method for an embedded real-time operating system using an SPI NOR FLASH with a capacity exceeding 16MB as the program carrier, which enables the embedded real-time operating system to correctly read the program from the large-capacity SPI NOR FLASH with the SPI interface and restart without power loss.
[0019] The technical solution of this application is:
[0020] A restart control system for an embedded real-time operating system with a large-capacity memory includes: a CPU, a memory, a reset controller, and a control circuit;
[0021] The memory is used to store system programs;
[0022] The CPU is connected to the memory. During initialization, the firmware program reads from the memory to complete the reading and loading process of the embedded real-time operating system. The default SPI byte address mode in the firmware program is three-byte address mode.
[0023] After the operating system starts normally, the CPU calls the restart registration function to register the user callback function to the restart program. After registration, it reads the reset mode of the reset controller. If the reset mode is 0 or 2, it sets the reset mode to 1.
[0024] When the operating system restarts, the CPU calls the user callback function. The user callback function sends a reset enable command to the memory and a device reset command to the memory. After the memory reset is complete:
[0025] Read the EXADDR bit in the non-volatile register. If it is 0, set the reset mode value to 2. If the EXADDR bit is non-zero, send an exit four-byte address instruction to the memory to change the byte address mode to three-byte address mode.
[0026] Read the EXADDR bit in the non-volatile register again. If it is 0, set the reset mode value to 2. If it is not 0, set the reset mode value to 1.
[0027] The reset controller samples the reset request signal and reads the reset mode value. When the reset mode is 1, it sends a high pulse to the control circuit. The pulse width meets the memory power-down timing requirements. It then waits for a certain period of time, which meets the memory power-up timing requirements, and generates a pulse signal that meets the CPU reset timing requirements. This pulse signal is then sent to the CPU. When the reset mode is 0 or 2, there is no need to send a high pulse signal or wait for a certain period of time.
[0028] The control circuit is mainly controlled by a reset controller to control the voltage output. This voltage serves as the power supply voltage for the memory and is used to provide a controlled chip level for the memory. It includes a first resistor R1, a second resistor R2, a third resistor R3, and a transistor Vec.
[0029] The first resistor R1 is connected to the base of the transistor Vec, the second resistor R2 is connected to the first resistor R1, and the third resistor R3 is connected to the collector of the transistor Vec.
[0030] The emitter of transistor Vec is connected to power supply Vcc, which is connected to the second resistor R2. The input level Vin is connected between the first resistor R1 and the second resistor R2. The input level Vin is connected to the reset controller. The third resistor R3 is grounded, and the output level Vout is connected between the third resistor R3 and transistor Vec. The output level Vout is connected to the input pin of the memory.
[0031] The voltage of the power supply Vcc is the sum of the voltage required by the memory and the voltage difference of the transistor Vec. The first resistor R1 and the second resistor R2 have the same resistance value.
[0032] When the input level Vin is low, the output level Vout is equal to the difference between the power supply Vcc and the transistor Vec, and the memory is powered normally; when the input level Vin is open, the output level Vout is 0V, and the memory is powered down.
[0033] According to at least one embodiment of this application, in the above-described restart control system of the embedded real-time operating system under the large-capacity memory, the CPU communicates with the reset controller, and the communication interface is a PCIe interface, a UART interface, or an SRIO interface.
[0034] The CPU is a PowerPC processor or Phytium processor with an SPI controller, a reset request pin, and a reset pin.
[0035] According to at least one embodiment of this application, in the above-described restart control system for an embedded real-time operating system with a large-capacity memory, the memory is an SPI NOR FLASH with an SPI interface, which serves as a storage medium for the embedded real-time system program and other programs, and is controlled and read by the SPI master device as an SPI slave device.
[0036] According to at least one embodiment of this application, in the above-described restart control system of an embedded real-time operating system under a large-capacity memory, the reset controller receives the reset mode from the CPU through a PCIe interface, a Uart interface, or an SRIO interface.
[0037] The reset controller is an FPGA processor, CPLD processor, or MCU processor.
[0038] According to at least one embodiment of this application, in the above-described restart control system for an embedded real-time operating system under a large-capacity memory, the operating system restart includes user-initiated reset or abnormal operating system reset restart.
[0039] According to at least one embodiment of this application, in the above-described restart control system of an embedded real-time operating system under a large-capacity memory, the reset controller samples reset request signals, including CPU reset requests and external reset request signals.
[0040] According to at least one embodiment of this application, in the above-described restart control system of an embedded real-time operating system under a large-capacity memory, the reset controller sends a high pulse to the control circuit through an OD pin.
[0041] According to at least one embodiment of this application, in the above-described restart control system of the embedded real-time operating system under the large-capacity memory, the resistance values of the first resistor R1 and the second resistor R2 are 5-30K, and the resistance value of the third resistor R3 is not less than 10K.
[0042] This application has at least the following beneficial technical effects:
[0043] A reboot control system for an embedded real-time operating system with large-capacity memory is provided:
[0044] This enables the embedded real-time operating system to correctly read and write large-capacity SPI NOR FLASH and load the system in the event of a reboot.
[0045] Compared to using extended address instructions to access large-capacity SPI NOR FLASH, standard SPI instructions can be used, avoiding the poor driver portability caused by writing different drivers using extended address instructions from different manufacturers and chips. This reduces driver development difficulty and improves code reusability.
[0046] It can reload the operating system for a single CPU without restarting the entire system, improving the security and reliability of the operating system;
[0047] In debugging scenarios, there is no need to restart the entire operating system, which improves debugging efficiency;
[0048] It supports CPU restart without power-down in various scenarios, such as user command reset or external pin reset of the board;
[0049] Not using SPI NOR FLASH with an external reset pin saves hardware costs and reduces operating system design complexity. Furthermore, not using an SPI NOR FLASH driver that supports extended address instructions reduces software design costs. Attached Figure Description
[0050] Figure 1 This is a schematic diagram of the restart control system of the embedded real-time operating system under a large-capacity memory provided in the embodiments of this application;
[0051] Figure 2 This is a flowchart of the restart callback function registration process provided in an embodiment of this application;
[0052] Figure 3 This is a flowchart of the user restart callback function provided in an embodiment of this application;
[0053] Figure 4 This is a flowchart of the reset controller provided in the embodiments of this application;
[0054] Figure 5 This is a schematic diagram of the control circuit provided in the embodiments of this application.
[0055] To better illustrate this embodiment, some content in the accompanying drawings may be omitted, enlarged, or reduced. They are for illustrative purposes only and should not be construed as limiting the scope of this application. Detailed Implementation
[0056] To make the technical solution and advantages of this application clearer, the technical solution of this application will be described in a clearer and more complete manner below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of this application, and are only used to explain this application, not to limit this application. It should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, and other related parts can be referred to the general design.
[0057] Furthermore, unless otherwise defined, the technical or scientific terms used in this application description shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The word "comprising" as used in this application description indicates that the concept preceding the word encompasses the concepts listed following the word and their equivalents, without excluding other related concepts.
[0058] Furthermore, the terms indicating location used in the description of this application are only used to indicate relative directions or positional relationships. When the absolute position of the described object changes, its relative positional relationship may also change accordingly. It should also be noted that, unless otherwise explicitly specified and limited, terms such as "installation" and "connection" used in the description of this application should be interpreted broadly. For example, a connection can be a fixed connection or a detachable connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand its specific meaning in this application according to the specific circumstances.
[0059] A reboot control system for an embedded real-time operating system with a large-capacity memory, such as Figure 1 As shown, it includes a CPU, memory, reset controller, and control circuitry.
[0060] The CPU is used to read programs from memory, load the embedded real-time operating system, execute reboot instructions, execute reboot user callback functions, switch between different byte address modes in memory, and communicate with the reset controller. It can set the reset mode, and the communication interface can be a common PCIe interface, UART interface, or SRIO interface. The CPU can be a PowerPC processor or Phytium processor with an SPI controller, a reset request pin, and a reset pin.
[0061] The memory is used to store system programs and other programs. It can be an SPI NOR FLASH with an SPI interface. It serves as a storage medium for embedded real-time system programs and other programs, and is controlled and read by the SPI master device as an SPI slave device.
[0062] The CPU connects to the memory via the SPI interface. During initialization, the CPU uses the default firmware settings to read from the memory, completing the reading and loading process of the embedded real-time operating system. The default SPI byte address mode in the firmware is three-byte address mode.
[0063] The reset controller monitors the CPU's reset request information. Upon receiving a reset request, it sends a reset signal that meets the reset timing requirements to the CPU. It receives the reset mode from the CPU via a PCIe interface, UART interface, or SRIO interface and performs different operations according to the reset mode. The reset controller can be an FPGA processor, CPLD processor, or MCU processor.
[0064] The control circuit is mainly controlled by a reset controller to control the voltage output, which serves as the power supply voltage for the memory.
[0065] After the operating system boots normally, the CPU calls the restart registration function to register the user callback function with the restart program. After registration, it reads the reset mode of the reset controller. If the reset mode is 0 or 2, it sets the reset mode to 1. Figure 2 As shown.
[0066] When the CPU performs a user-initiated reset or an abnormal operating system reset and restart, it calls a user callback function. The user callback function sends a reset enable command to the memory, followed by a device reset command to the memory. After the memory reset is complete:
[0067] Read the EXADDR bit in the non-volatile register. If it is 0, it indicates that the memory is in three-byte address mode after reset. Set the reset mode value to 2. If the EXADDR bit is not 0, it indicates that the memory is in four-byte address mode after reset. You need to send an exit four-byte address instruction to the memory to change the byte address mode to three-byte address mode.
[0068] Read the EXADDR bit in the non-volatile register again. If it is 0, set the reset mode value to 2. If it is not 0, it indicates that the memory address mode configuration has failed, and set the reset mode value to 1. The execution process is as follows: Figure 3 As shown.
[0069] The reset controller samples reset request signals, including CPU reset requests and external reset request signals, and reads the reset mode value. When the reset mode value is 0, it indicates that the board is undergoing a power-on reset. When the reset mode is 2, it indicates that the CPU is requesting a reset and the memory has been restored to the three-byte address mode, so there is no need to power down the memory. When the reset mode is 1, it indicates that the reset is generated by an external reset button or that the CPU is requesting a reset due to an abnormal memory address mode. In this case, the reset controller sends a high pulse to the control circuit through an OD (open drain) pin (the default state is low). The pulse width meets the memory power-down timing requirements. Then, it waits for a period of time, which needs to meet the memory power-on timing requirements. The reset controller generates a specific pulse signal that meets the CPU reset timing and sends the pulse to the CPU's reset pin.
[0070] The reset controller does not need to send a high pulse signal and wait for a delay when the reset mode is 0 or 2; it only sends a high pulse signal and waits for a delay when the reset mode is 1. Figure 4 As shown.
[0071] The control circuit functions to provide a controlled chip level for the memory under the pin control of the reset controller, including a first resistor R1, a second resistor R2, a third resistor R3, and a transistor Vec.
[0072] The first resistor R1 is connected to the base of the transistor Vec, the second resistor R2 is connected to the first resistor R1, and the third resistor R3 is connected to the collector of the transistor Vec.
[0073] The emitter of transistor Vec is connected to power supply Vcc, which is connected to the second resistor R2. The input level Vin is connected between the first resistor R1 and the second resistor R2. The input level Vin is connected to the OD pin of the reset controller. The third resistor R3 is grounded, and the output level Vout is connected between the third resistor R3 and transistor Vec. The output level Vout is connected to the input pin of the memory.
[0074] The power supply Vcc amplitude is the sum of the voltage required by the memory and the voltage difference of the transistor Vec. The first resistor R1 and the second resistor R2 have the same resistance value, ranging from 5 to 30K. The third resistor R3 is a protection resistor with a resistance value of not less than 10K.
[0075] When the input level Vin is low, the output level Vout is equal to the difference between the power supply Vcc and the transistor Vec, and the memory is powered normally; when the input level Vin is open (logic level 1), the output level Vout is 0V, and the memory is powered down.
[0076] The above-described embodiments disclose a restart control system for an embedded real-time operating system with a large-capacity memory. This system addresses the issue of operating system restart failures due to user-initiated restarts during debugging or abnormal interruptions caused by operating system malfunctions during debugging. For large-capacity SPI NOR FLASH memory, accessing storage exceeding 16MB requires address mode modification, leading to inconsistencies between the SPI master and slave byte address modes during restart. The system enables correct read / write access to the large-capacity SPI NOR FLASH memory during embedded real-time operating system restarts. This allows for restarting the embedded real-time operating system without power-on / off, without using the external SPI NOR FLASH reset pin, and without using extended address instructions, thus improving operating system reliability, debugging convenience, driver portability, and compatibility.
[0077] The reboot control system for the embedded real-time operating system under a large-capacity memory disclosed in the above embodiments adopts the following core technologies:
[0078] Byte address mode change technology: Upon completion of reboot, the byte address mode on the SPI NOR FLASH is changed, enabling switching between three-byte address mode and four-byte address mode on the SPI NOR FLASH;
[0079] Restart callback function registration technology: This technology registers user callback functions after the operating system starts up and executes these user callback functions upon restart.
[0080] Reset signal capture and transmission technology: Captures the CPU reset request signal during restart and generates and transmits a reset signal that meets the reset timing requirements;
[0081] Voltage control circuit technology: enables controlled management of the power supply voltage of the memory.
[0082] The reboot control system for an embedded real-time operating system under a large-capacity memory disclosed in the above embodiments has the following advantages:
[0083] Breaking the capacity limitation: It breaks through the capacity limitation of less than 16MB for SPI NOR FLASH read and write range when the embedded real-time operating system restarts, and realizes correct reading and writing of large-capacity SPI NOR FLASH and loading of the operating system when the embedded real-time operating system restarts;
[0084] Strong driver versatility: Compared with using extended address instructions to access large-capacity SPI NOR FLASH, this application uses standard SPI instructions to complete the access, which can avoid the problem of poor driver portability caused by using extended address instructions from different manufacturers and different chips to write different drivers;
[0085] Strong applicability to various scenarios: It can meet the reset requirements of various scenarios such as external manual reset, CPU instruction reset, and abnormal state reset.
[0086] Low development complexity: Standard SPI instructions can be used to complete read and write operations on SPI NOR FLASH from different manufacturers and with different capacities, reducing the difficulty of driver development and improving code reusability;
[0087] Low hardware cost: By not using SPI NOR FLASH with external reset function, hardware costs are saved, and the complexity of operating system design is also reduced;
[0088] High debugging efficiency: In debugging scenarios, the reset of other devices is avoided, which can reduce current surges and improve debugging efficiency;
[0089] High reliability: Enables the operating system to correctly execute restart operations in abnormal situations, thus improving the reliability of the operating system;
[0090] With broad application prospects, it is suitable for embedded fields such as aerospace, automotive electronics, and industrial control, and has great application value.
[0091] The technical solution of this application has been described in conjunction with the preferred embodiments shown in the accompanying drawings. Those skilled in the art should understand that the protection scope of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the protection scope of this application.
Claims
1. A restart control system for an embedded real-time operating system under a large-capacity memory, characterized in that, include: CPU, memory, reset controller, and control circuitry; The memory is used to store system programs; The CPU is connected to the memory. During initialization, the firmware program reads from the memory to complete the reading and loading process of the embedded real-time operating system. The default SPI byte address mode in the firmware program is three-byte address mode. After the operating system starts normally, the CPU calls the restart registration function to register the user callback function to the restart program. After registration, it reads the reset mode of the reset controller. If the reset mode is 0 or 2, it sets the reset mode to 1. When the operating system restarts, the CPU calls the user callback function. The user callback function sends a reset enable command to the memory and a device reset command to the memory. After the memory reset is complete: Read the EXADDR bit in the non-volatile register. If it is 0, set the reset mode value to 2. If the EXADDR bit is non-zero, send an exit four-byte address instruction to the memory to change the byte address mode to three-byte address mode. Read the EXADDR bit in the non-volatile register again. If it is 0, set the reset mode value to 2. If it is not 0, set the reset mode value to 1. The reset controller samples the reset request signal and reads the reset mode value. When the reset mode is 1, it sends a high pulse to the control circuit. The pulse width meets the memory power-down timing requirements. It then waits for a certain period of time, which meets the memory power-up timing requirements, and generates a pulse signal that meets the CPU reset timing requirements. This pulse signal is then sent to the CPU. When the reset mode is 0 or 2, there is no need to send a high pulse signal or wait for a certain period of time. The control circuit is mainly controlled by a reset controller to control the voltage output. This voltage serves as the power supply voltage for the memory and is used to provide a controlled chip level for the memory. It includes a first resistor R1, a second resistor R2, a third resistor R3, and a transistor Vec. The first resistor R1 is connected to the base of the transistor Vec, the second resistor R2 is connected to the first resistor R1, and the third resistor R3 is connected to the collector of the transistor Vec. The emitter of transistor Vec is connected to power supply Vcc, which is connected to the second resistor R2. The input level Vin is connected between the first resistor R1 and the second resistor R2. The input level Vin is connected to the reset controller. The third resistor R3 is grounded, and the output level Vout is connected between the third resistor R3 and transistor Vec. The output level Vout is connected to the input pin of the memory. The voltage of the power supply Vcc is the sum of the voltage required by the memory and the voltage difference of the transistor Vec. The first resistor R1 and the second resistor R2 have the same resistance value. When the input level Vin is low, the output level Vout is equal to the difference between the power supply Vcc and the transistor Vec, indicating that the memory is powered normally. When the input level Vin is in an open circuit state, the output level Vout is 0V, and the memory is powered off.
2. The restart control system for an embedded real-time operating system under a large-capacity memory according to claim 1, characterized in that, The CPU communicates with the reset controller via a PCIe interface, a UART interface, or an SRIO interface. The CPU is a PowerPC processor or Phytium processor with an SPI controller, a reset request pin, and a reset pin.
3. The restart control system for an embedded real-time operating system under a large-capacity memory according to claim 2, characterized in that, The memory is an SPI NOR FLASH with an SPI interface, which serves as a storage medium for embedded real-time system programs and other programs, and is controlled and read by the SPI master device as an SPI slave device.
4. The restart control system for an embedded real-time operating system under a large-capacity memory according to claim 3, characterized in that, The reset controller receives the reset mode from the CPU via a PCIe interface, UART interface, or SRIO interface; The reset controller is an FPGA processor, CPLD processor, or MCU processor.
5. The restart control system for an embedded real-time operating system under a large-capacity memory according to claim 4, characterized in that, Operating system restarts include user-initiated resets and restarts due to abnormal operating system resets.
6. The restart control system for an embedded real-time operating system under a large-capacity memory according to claim 5, characterized in that, The reset controller samples reset request signals, including CPU reset requests and external reset request signals.
7. The restart control system for an embedded real-time operating system under a large-capacity memory according to claim 6, characterized in that, The reset controller sends a high pulse to the control circuit via an OD pin.
8. The restart control system for an embedded real-time operating system under a large-capacity memory according to claim 7, characterized in that, The resistance values of the first resistor R1 and the second resistor R2 are 5-30K, and the resistance value of the third resistor R3 is not less than 10K.