Memory controller and credit management method
Patent Information
- Application Number
- CN202611221210.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-12
- Publication Date
- 2026-10-27
Smart Images
Figure CN122985349A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuits, and more particularly to a memory controller and a credit management method. Background Technology
[0002] A System-on-Chip (SoC) integrates a DDR (Double Data Rate) controller and a Network-on-Chip (NoC) system. Since their clocks are asynchronous, when the upstream NoC interconnect sends a request or writes data to the controller, the DDR controller performs credit management. Credit management allocates credit limits based on the remaining cache capacity, constraining the total number of packets sent upstream and preventing cross-clock cache overflow. Traditional cross-clock credit management architectures use a single-level cross-clock storage master queue. After the DDR controller initializes, it issues an equal number of credits to upstream devices based on the total depth of the master queue. Each time an upstream device sends a data packet to the master queue, it consumes one credit. Downstream devices read data from the master queue and then send a new credit to upstream devices, thus completing the flow control in a cycle. Based on this credit management mechanism, ordered transmission of data packets across clock domains can be achieved, preventing cache overflow and packet loss. However, when the upstream packet sending rate is higher than the downstream read rate, the DDR controller's main queue will quickly fill up. At this time, all upstream credits have been consumed, and the transmission will be interrupted immediately. Furthermore, when the downstream reads data to make room, the read pointer still needs to be synchronized to the write clock domain through two levels of registers. Credits cannot be resent during the synchronization delay, resulting in transmission gaps in the link and causing bandwidth fluctuations. Summary of the Invention
[0003] The purpose of this application is to provide a memory controller and credit management method that can eliminate transmission interruptions and bandwidth fluctuations caused by cross-clock synchronization delays, thereby improving data transmission efficiency.
[0004] To achieve the above objectives, embodiments of this application provide a memory controller for communicating with an upstream data transmitter. The memory controller includes a high-speed interconnect interface module and a write module connected in communication. The high-speed interconnect interface module is used to receive data packets sent by the upstream data sender; wherein, the upstream data sender consumes one credit for each data packet sent, and the credit is the authorized quota for sending data packets by the upstream data sender; when there is available credit, the upstream data sender is allowed to send data packets and consumes the corresponding credit; when the available credit is 0, the upstream data sender is restricted from sending data packets. The write module includes a main queue and a temporary queue. The main queue is used to cache the data packets. The temporary queue is used to temporarily cache the data packets when the main queue is full, and to write the temporarily cached data packets into the main queue when there is space in the main queue. The write module determines whether to return credit to the upstream data sender based on the writing method of the data packets, so that the upstream data sender can update the available credit balance for sending the remaining data packets.
[0005] In this embodiment, traffic control between the memory controller and the upstream data sender is based on credit quotas. Credits are used as the upstream packet sending authorization quota to constrain the upstream packet sending behavior. The upstream can only send packets when there are available credits. When the credits are exhausted, packet sending automatically stops, thus preventing the upstream from sending packets without limit, which could cause buffer overflow, data loss, or link blockage on the receiving side. At the same time, the write module sets up a two-level buffer of main queue and temporary queue. When the main queue is full, packets are temporarily stored in the temporary queue. After the main queue releases empty slots, the packets stored in the temporary queue are prioritized to fill the empty slots. The mechanism of differentiating credit return based on different packet writing methods can quickly clear the backlog of packets in the temporary queue, thereby timely restoring the upstream packet sending credits. It can also avoid the transmission gap caused by the inability to resend credits in time due to cross-clock domain pointer synchronization delay. It can eliminate the transmission interruption and bandwidth fluctuation caused by cross-clock synchronization delay and improve data transmission efficiency.
[0006] In one possible implementation, the write module determines whether to return credit to the upstream data sender based on the writing method of the data packet, including one of the following methods: When the write module directly writes the data packet sent by the upstream data sender into the main queue, it returns a credit to the upstream data sender. When the writing module directly writes the data packet sent by the upstream data sender into the temporary queue, it stops returning credits. When the write module writes the data packet in the temporary queue to the main queue, it returns a credit to the upstream data sender.
[0007] In this embodiment, a differentiated credit return mechanism is set for different data packet writing scenarios. This mechanism can dynamically adjust the upstream packet sending permissions based on the actual storage occupancy status of the receiving side, thereby achieving closed-loop flow control, effectively suppressing instantaneous packet sending impacts, and preventing queue overflow blocking.
[0008] In one possible implementation, when the temporary queue has data packets and the main queue has empty slots, the write module writes all the newly sent data packets from the upstream data sender into the temporary queue before all the data packets temporarily cached in the temporary queue are written into the main queue.
[0009] In this embodiment, by prioritizing the emptying of the temporary queue, when there are cached data packets in the temporary queue, even if there are empty slots in the main queue, the existing data packets are transferred first. Before the temporary queue is completely empty, new packets from upstream are intercepted and directly written into the main queue, which can quickly release the storage space of the temporary queue, trigger credit resending actions in a timely manner, and effectively improve the transmission gap caused by cross-clock domain pointer synchronization delay.
[0010] In one possible implementation, the write module sends an initial credit to the upstream data sender based on the queue depth of the temporary queue; wherein the initial credit is used to specify the maximum value of the authorized quota.
[0011] In this embodiment, the initial credit limit is configured based on the depth of the temporary queue, thereby limiting the maximum packet sending authorization quota of the upstream data sender. This ensures that the maximum packet sending volume of the upstream and the buffer carrying capacity of the receiver are matched, constraining the total number of upstream packets from the source and further improving the stability of data transmission.
[0012] In one possible implementation, when the write module writes data packets from the temporary queue to the main queue, it selects the data packet with the longest temporary buffer duration and writes it to the main queue according to the order in which the data packets are written to the temporary queue.
[0013] In this embodiment, the temporary queue prioritizes the transfer of data packets with the longest buffer time according to the order in which the data packets are stored, following the first-in-first-out transmission rule. This ensures the consistency of data packet transmission sequence, avoids data verification anomalies or data packet retransmission caused by out-of-order transmission, and reduces additional system processing overhead.
[0014] In one possible implementation, the memory controller further includes a read module, which is communicatively connected to the write module, and the read module is used to read data packets from the main queue.
[0015] In this embodiment, the read module reads and outputs data packets from the main queue. The read-write separation architecture ensures that the write module focuses on data packet caching and scheduling and credit management, while the read module completes the data reading operation, thereby improving the parallel processing efficiency of data reading and writing.
[0016] In one possible implementation, the memory controller is configured with a write pointer and a read pointer; wherein, The write pointer is set in the write module, and the write module updates the pointer position of the write pointer every time it writes a data packet to the main queue. The read pointer is set in the read module, and the read module updates the pointer position every time it completes a data packet reading operation.
[0017] In this embodiment, by configuring independent pointers in the write module and the read module respectively, and updating the pointer positions in real time along with the data packet writing and reading actions, the storage occupancy status of the main queue can be marked in real time, providing a basis for determining whether the queue is full in the future.
[0018] In one possible implementation, the write module receives the read pointer sent by the read module and performs a slapping process on the read pointer based on two-level registers to obtain a synchronous read pointer; when the write module detects that the bits of the synchronous read pointer and the write pointer meet a preset matching condition, it determines that the main queue is full.
[0019] In this embodiment, the read pointer transmitted across clock domains is synchronized by using two-level registers, which can effectively eliminate the fluctuations caused by asynchronous pointer transmission across domains, output a stable and reliable synchronous read pointer, avoid misjudgment of queue status due to pointer transmission abnormalities, and ensure the stable operation of credit management logic.
[0020] In one possible implementation, the matching condition is that the highest bit of the synchronous read pointer and the write pointer are different, while the remaining bits are the same.
[0021] In this embodiment of the application, the matching conditions can accurately distinguish between the full and empty states of the main queue, thereby achieving high-precision queue fullness determination.
[0022] To achieve the above objectives, this application provides a credit management method applied to a memory controller. The memory controller includes a high-speed interconnect interface module and a write module connected via communication. The write module includes a main queue and a temporary queue. The main queue is used to cache data packets, and the temporary queue is used to temporarily cache the data packets when the main queue is full, and to write the temporarily cached data packets into the main queue when there is space in the main queue. The method includes: The high-speed interconnect interface module receives data packets sent by the upstream data sender; wherein, the upstream data sender consumes one credit for each data packet sent, and the credit is the authorized quota for sending data packets by the upstream data sender; when there is available credit, the upstream data sender is allowed to send data packets and consumes the corresponding credit; when the available credit is 0, the upstream data sender is restricted from sending data packets. The write module determines whether to return credit to the upstream data sender based on the writing method of the data packet, so that the upstream data sender can update the available credit balance for sending the remaining data packets.
[0023] In this embodiment, traffic control between the memory controller and the upstream data sender is based on credit quotas. Credits are used as the upstream packet sending authorization quota to constrain the upstream packet sending behavior. The upstream can only send packets when there are available credits. When the credits are exhausted, packet sending automatically stops, thus preventing the upstream from sending packets without limit, which could cause buffer overflow, data loss, or link blockage on the receiving side. At the same time, the write module sets up a two-level buffer of main queue and temporary queue. When the main queue is full, packets are temporarily stored in the temporary queue. After the main queue releases empty slots, the packets stored in the temporary queue are prioritized to fill the empty slots. The mechanism of differentiating credit return based on different packet writing methods can quickly clear the backlog of packets in the temporary queue, thereby timely restoring the upstream packet sending credits. It can also avoid the transmission gap caused by the inability to resend credits in time due to cross-clock domain pointer synchronization delay. It can eliminate the transmission interruption and bandwidth fluctuation caused by cross-clock synchronization delay and improve data transmission efficiency. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of pointer interaction in a cross-clock domain transmission architecture provided by existing technology; Figure 2 This is a structural block diagram of a memory controller provided in an embodiment of this application; Figure 3 This is a schematic diagram of the credit update logic provided in the embodiments of this application; Figure 4 This is a schematic diagram of pointer interaction between the write clock field and the read clock field in an on-chip system provided in an embodiment of this application; Figure 5 This is a flowchart of a credit management method provided in an embodiment of this application. Detailed Implementation
[0025] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0026] In current system-on-chip (SoC) designs, the clock frequency of the DDR controller and the clock frequency of the on-chip interconnect network (ITN) are often designed asynchronously. Information exchange between the two ends is completed through a cross-clock domain transmission architecture. Due to varying timing requirements in chip development, the clock frequency of the DDR controller often does not need to be consistent with the clock frequency of the IPN; that is, they reside in different clock domains. Therefore, according to the IPN transmission protocol, when the upstream IPN sends a request or writes data to the DDR controller, the DDR controller must perform credit management. This means the DDR controller must reserve sufficient space for each sent credit to ensure that there is available receive buffer for each packet sent from the upstream.
[0027] See Figure 1 , Figure 1 This is a schematic diagram of pointer interaction in a cross-clock domain transmission architecture provided by existing technology. The cross-clock domain transmission architecture includes a write module and a read module belonging to two asynchronous clock domains, such as... Figure 1 The right side of the image represents the write module, which operates in the write clock domain corresponding to the DDR controller. Figure 1 The left side of the diagram represents the read module, operating in the read clock domain corresponding to the on-chip interconnect network. The write module integrates a high-speed interconnect interface module and a credit calculation logic module. The high-speed interconnect interface module handles basic transmission and reception tasks such as upstream and downstream interface handshakes and data packet protocol parsing. The credit calculation logic module collects the write pointer generated by the local write clock domain and the read pointer after synchronization processing from the read clock domain. It uses these two sets of pointer values to determine the remaining available cache space within the storage queue in real time, thereby calculating the credit limit that can be released to the upstream on-chip interconnect network. Because the read pointer is generated in the asynchronous read clock domain, directly transmitting the signal to the write clock domain would cause metastability. Therefore, after the read pointer signal enters the write clock domain, it needs to undergo two consecutive stages of synchronization processing through a timing register. Only after the signal stabilizes can it be sent to the credit calculation logic for queue space determination. It should be noted that the read clock domain includes read action control logic and other supporting circuits. The attached diagram only shows the functional logic directly related to the credit calculation process; other unrelated circuits are not shown.
[0028] The complete data interaction process of the existing cross-clock domain transmission architecture specifically includes the following steps: 1. The DDR controller reset is complete, and initialization is finished.
[0029] 2. The DDR controller completes link-layer handshake interaction with the upstream on-chip interconnect network's request channel and write data channel to establish a complete data transmission link; 3. The write module has built-in credit calculation logic, storage queue and high-speed interconnection interface module. The credit calculation logic reads the maximum storage depth of the storage queue, uses the maximum storage depth as the initial credit, and issues the initial credit to the upstream on-chip interconnection network through the high-speed interconnection interface module. Each credit corresponds to a data packet buffer space in the storage queue. 4. The upstream on-chip interconnect network sends data packets to the DDR controller. Each successful transmission of a data packet consumes one credit. After the data packet is received by the high-speed interconnect interface module of the write module, it is temporarily stored in the storage queue. 5. After the downstream of the DDR controller is ready, the read module performs a data packet read operation, reads the data packet from the storage queue of the write module, and sends the data packet to the downstream. After a single read operation is completed, the read module synchronously updates the read pointer in Gray code format. 6. The read module transmits the updated read pointer across the clock domain to the write module. After being synchronized by the two-level registers of the write module, it reaches a stable state. The credit calculation logic inside the write module reads the synchronized read pointer and compares it with the local write pointer. After comparison, it can identify the new cache space released by the storage queue due to the reading of the data packet, and then send a credit to the upstream through the high-speed interconnect interface module. 7. Repeat the above data packet sending, data packet reading, and credit re-issuance process to continuously complete on-chip data interaction.
[0030] As the above process shows, when a large number of unread data packets accumulate inside the storage queue, the queue has no free storage space, the credit calculation logic cannot release new credits upstream, and the upstream on-chip interconnect will directly stop sending data packets due to credit exhaustion, causing data congestion in the link. Even if the downstream completes the reading of data packets and releases the buffer space, the updated read pointer still needs to go through two write clock cycles of synchronization delay. During the synchronization window, the credit calculation logic cannot recognize the changes in queue space and cannot resend credits in time, resulting in continuous gaps in data transmission and degrading the cross-clock domain transmission bandwidth performance. If the hardware overhead is reduced by decreasing the storage queue depth, the probability of data packet accumulation and congestion will also increase, and bandwidth fluctuations and transmission interruption problems will become more prominent. If the storage queue depth is increased to alleviate the congestion problem, the number of cross-clock signal lines corresponding to the queue will increase linearly, increasing the difficulty of physical routing at the back end of the chip, and in extreme cases, it will also limit the system's maximum operating clock frequency. At the same time, a large-capacity storage queue is entirely built by register arrays, which will simultaneously increase the overall chip area of the DDR controller, making it difficult to balance transmission performance and hardware cost.
[0031] To address the transmission interruption and bandwidth fluctuation issues caused by cross-clock synchronization delays in existing technologies, this application provides a memory controller for communicating with the upstream data transmitter. Specifically, the memory controller can be a DDR controller, and the upstream data transmitter can be an on-chip interconnect network. This application adds an independent temporary queue to the traditional main queue, constructing a two-layer buffer scheduling and differentiated credit management architecture. When the main queue is full, it does not directly block the transmission of upstream data packets; instead, newly sent data packets from the upstream are temporarily buffered in the temporary queue, preventing momentary link interruptions. After the memory controller completes data packet reading and updates the Gray code read pointer, since the read pointer still needs two clock cycles of synchronization to be stably transmitted to the write clock domain, this application continuously buffers upstream-sent data packets during this synchronization gap using the temporary queue, preventing transmission link interruptions. This application fills the delay gap in the two-level synchronization of pointers by using a temporary queue, so that the entire data link always maintains effective data transmission. It eliminates the transmission interruption and bandwidth fluctuation problems caused by the inability to reissue credits in a timely manner in the traditional architecture. It does not require increasing the depth of the main queue, and improves the bandwidth stability and overall throughput performance of asynchronous transmission across clock domains without increasing the routing pressure, chip area and power consumption.
[0032] See Figure 2 , Figure 2 This is a structural block diagram of a memory controller provided in an embodiment of this application. The memory controller includes a high-speed interconnect interface module 10, a write module 20, and a read module 30, which are connected by communication. The high-speed interconnection interface module 10 is used to receive data packets sent by the upstream data sender. Each data packet sent by the upstream data sender consumes one credit, and the credit is the authorized quota for sending data packets by the upstream data sender. When there is available credit, the upstream data sender is allowed to send data packets and consumes credit accordingly. When the available credit is 0, the upstream data sender is restricted from sending data packets.
[0033] The write module 20 includes a main queue 21 and a temporary queue 22. The main queue 21 is used to buffer data packets, and the temporary queue 22 is used to temporarily buffer data packets when the main queue is full, and to write the temporarily buffered data packets into the main queue 21 when there is space in the main queue 21. The write module 20 determines whether to return credit to the upstream data sender based on the writing method of the data packets, so that the upstream data sender can update the available credit balance for sending the remaining data packets.
[0034] Read module 30 is used to read data packets from main queue 21.
[0035] For example, the high-speed interconnect interface module 10 serves as a high-speed interaction port between the memory controller and the upstream data sender. It is primarily responsible for receiving cross-clock domain data packets, parsing protocols, and performing link handshakes. It also works with a credit mechanism to manage upstream packet sending permissions. This application uses credit as the data packet sending authorization quota for the upstream data sender. Each successful data packet transmission by the upstream data sender consumes one credit. Available credit balance refers to the number of credits currently remaining that the upstream data sender can use to send data packets, representing the number of data packets the upstream can still send. When available credit balance exists, the upstream data sender can continuously send data packets and consume the corresponding credit balance in real time. When the credit balance is exhausted, the upstream data sender's packet sending behavior is restricted, thereby preventing uncontrolled packet sending by the upstream from causing buffer overflow at the receiving end and achieving basic closed-loop traffic control. The write module 20 is the functional module for implementing differentiated credit management and two-level queue scheduling in this application. It has a built-in two-level cache structure of main queue 21 and temporary queue 22. The main queue 21 is a regular data cache queue used to cache data packets sent by the upstream data sender and complete cross-clock domain data relay. The temporary queue 22 is an expansion buffer queue specifically used to temporarily cache newly sent data packets from the upstream data sender when the main queue 21 is full, avoiding direct link interruption and blockage. At the same time, the write module 20 can execute differentiated credit return strategies according to different data packet writing scenarios and dynamically update the available packet sending credit balance upstream. The read module 30 is communicatively connected to the write module 20 and is mainly responsible for orderly reading the cached data packets from the main queue 21 and outputting the data downstream.
[0036] In this embodiment, the memory controller and the upstream data sender implement traffic control based on credit quotas. Credits are used as the upstream packet sending authorization quota to constrain the upstream packet sending behavior. The upstream can only send packets when there are available credits. When the credits are exhausted, packet sending automatically stops, thus avoiding the problem of buffer overflow, data loss, or link blockage caused by the upstream sending packets without restriction. At the same time, the write module 20 sets up a two-level buffer of main queue 21 and temporary queue 22. When the main queue 21 is full, the packets are temporarily stored in the temporary queue 22. After the main queue 21 releases empty space, the existing packets in the temporary queue 22 are prioritized to fill the empty space. The mechanism of differentiating credit return based on different packet writing methods can quickly empty the backlog of packets in the temporary queue 22, thereby timely restoring the upstream packet sending credit reserve. It can also avoid the transmission gap caused by the inability to resend credits in time due to cross-clock domain pointer synchronization delay. It can eliminate the transmission interruption and bandwidth fluctuation caused by cross-clock synchronization delay and improve data transmission efficiency.
[0037] Furthermore, the write module 20 sends the initial credit to the upstream data sender based on the queue depth of the temporary queue 22; wherein the initial credit is used to specify the maximum value of the authorized quota.
[0038] For example, the queue depth of the temporary queue 22 refers to the maximum number of data packets that the temporary queue 22 can buffer, representing the maximum storage capacity of the temporary queue 22. For instance, if the queue depth of the temporary queue 22 is configured to 4, it means that the temporary queue 22 can temporarily buffer a maximum of 4 data packets. After the main queue 21 is full, the temporary queue 22 is needed to receive burst data packets from upstream to fill the transmission gap caused by the two-beat synchronization delay of the read pointer. If the initial credit is greater than the queue depth of the temporary queue 22, excessive upstream packet sending will exceed the carrying capacity of the temporary queue 22, still causing packet blocking. If the initial credit is too small, the buffering advantage of the temporary queue 22 cannot be fully utilized, and the link bandwidth cannot be fully utilized. Therefore, this application configures the initial credit based on the queue depth of the temporary queue 22 to match the maximum number of data packets that can be sent upstream with the buffer capacity of the temporary queue.
[0039] It should be noted that the queue depth n of the temporary queue 22 must satisfy: n≥3. When the temporary queue depth n is configured to 4, once the main queue is full, the upstream can continuously send a maximum of 4 data packets to fill the temporary queue. After the read module completes the reading of the data packets and updates the read pointer, the read pointer needs to go through two clock cycles of synchronization to be stably transmitted to the write clock domain. During the synchronization gap of these two write clock cycles, the temporary queue can continuously carry the existing data packets, and there are always pending packets on the link, so there will be no transmission interruption. If the temporary queue depth is 2, it matches the 2-clock cycle duration required for pointer synchronization. At this time, the effective buffer window is: n-2=0. There is no extra buffer capacity to carry the data packets continuously sent by the upstream during the synchronization delay stage. During the gap of the two-level clock cycle synchronization, the temporary queue will quickly fill up, the upstream credit will be exhausted and stop sending packets, the link will be interrupted, and the defects of bandwidth fluctuation and transmission performance degradation in the existing technology will be reproduced. Therefore, this application matches the initial credit limit with the temporary queue depth n. Based on the effective buffer window of n-2 clock cycles, it can cover the pipeline pause delay caused by the two-level synchronization of the read pointer. It can continuously maintain data transmission without increasing the main queue depth and eliminate the problem of bandwidth gaps across clock domains.
[0040] In this embodiment of the application, the initial credit limit is configured based on the queue depth of the temporary queue 22, thereby limiting the maximum packet sending authorization quota of the upstream data sender, matching the maximum packet sending volume of the upstream with the buffer carrying capacity of the receiver, constraining the total number of upstream packets from the source, and further improving the stability of data transmission.
[0041] Furthermore, the write module 20 determines whether to return credit to the upstream data sender based on the data packet writing method, including one of the following methods: 1) When the write module 20 writes the data packet sent by the upstream data sender directly into the main queue 21, it returns a credit to the upstream data sender.
[0042] For example, when there is free storage space in the main queue 21, data packets sent from the upstream can be directly written into the main queue 21 for caching, and the overall capacity of the queue is not saturated. Therefore, after the data packet is directly written into the main queue 21, the write module 20 immediately returns a credit to the upstream data sender, enabling the upstream to restore the packet sending quota in a timely manner and continuously send new data packets, ensuring that the link maintains maximum transmission efficiency when the queue is idle.
[0043] 2) When the write module 20 directly writes the data packet sent by the upstream data sender into the temporary queue 22, it stops returning credits.
[0044] For example, the scenario of writing data packets into the temporary queue 22 corresponds to the condition that the main queue 21 has no free space to receive new data packets. In this case, the temporary queue 22 is used as a temporary buffer. If credit is returned upstream in this scenario, the upstream will continuously consume credit to send new data packets. The continuous influx of data packets will quickly fill the entire buffer capacity of the temporary queue 22, causing the data packets in the temporary queue to overflow and eventually leading to link blockage. Therefore, this application suspends credit return during the stage of storing data packets in the temporary queue 22, actively limiting the continuous packet sending by the upstream, suppressing the instantaneous traffic surge from the source, and avoiding data packet overflow and link blockage during the cross-clock synchronization delay.
[0045] 3) When the write module 20 writes the data packet in the temporary queue 22 into the main queue 21, it returns a credit to the upstream data sender.
[0046] For example, when an empty space is detected in the main queue 21, the write module 20 will write the cached data packets in the temporary queue 22 into the main queue 21. This action means that the memory controller has released the effective storage space and the overall cache capacity of the system has been restored. Therefore, after the temporary data packets are written into the main queue 21, the write module 20 will return a credit to the upstream, allowing the upstream to regain the right to send packets.
[0047] Further, see Figure 3 , Figure 3 This is a schematic diagram of the credit update logic provided in the embodiments of this application, combined with Figure 3 This paper details the complete scheduling process for differentiated credit return and dynamic changes in upstream credit limits in this application. In this embodiment, the temporary queue depth is 4, so the system issues an initial authorized quota of up to 4 to the upstream. The total capacity of the main queue is 8. Differentiated control of credit reissue is implemented under three working conditions: direct writing to the main queue, data packets being stored in the temporary queue, and temporary data packets being migrated back to the main queue. The complete operating logic at each time point is as follows: At time t0: The memory controller reset is completed, initialization is finished, and the link layer handshake interaction is completed with the request channel and write data channel of the upstream data sender to establish a complete data transmission link. The main queue has buffered data packets A1~A7, with 1 empty slot remaining. The temporary queue has no data packets. At this time, the write module issues initial credit 4 to the upstream data sender, indicating that the upstream can send a maximum of 4 data packets. At time t1: The upstream sends data packet A8. At this time, there is an empty space in the main queue, and the data packet is directly written to the main queue. The upstream consumes 1 credit, and the remaining credit is updated to 3. Because the data packet is written directly to the main queue, the temporary queue is not occupied by 1 storage position. The write module sends 1 credit to the upstream, and the available credit of the upstream is restored to 4. After completion, the main queue is full, there is no empty space, and the temporary queue is still empty. At time t2: The main queue is full. The upstream sends two data packets, B1 and B2, which cannot be written to the main queue and are all stored in the temporary queue. The temporary queue occupies 2 buffer slots. The upstream consumes 2 credits in succession, and the remaining credits are updated to 2. In this scenario, the data packets are only stored in the temporary queue, which occupies 2 storage slots. Therefore, no credits are sent to the upstream, and the upstream credits remain at 2. At time t3: The read module reads data packet A1 from the main queue, freeing up one space in the main queue. However, at this time, the read pointer has not yet completed the two-level sync synchronization, the write clock domain has not recognized the empty space in the main queue, and the data packets in the temporary queue are not transferred to the main queue. There is no effective storage space to be released, so no credits are reissued, and the available credits upstream remain at 2. At time t4: The read pointer completes two-step synchronization, the write clock domain identifies an idle position in the main queue, and the data packet B1 in the temporary queue is transferred and written to the main queue. The temporary queue releases one buffer slot, indicating that the memory controller has released effective storage space to receive new packets from upstream. The write module sends one credit to upstream, and the available credit upstream is updated from 2 to 3. After the transfer is completed, only B2 remains in the temporary queue. At time t5: The upstream sends data packet B3. Although there are empty slots in the main queue, there are still data packets in the temporary queue that have not been cleared. According to the scheduling rule of clearing the temporary queue first, the new data packet B3 is stored in the temporary queue, which occupies 2 buffer slots. The upstream consumes 1 credit, and the remaining credit is updated to 2. The storage of the data packet in the temporary queue does not trigger credit reissue. At time t6: The upstream continues to send two data packets, B4 and B5. There are 2 empty slots in the temporary queue that can be received. The data packets are stored in the temporary queue until the temporary queue is completely full. The upstream consumes 2 credits in succession, and the available credits are cleared to 0. At this time, the upstream has no credits left and stops sending new data packets. Packet sending can only resume after the data packets in the temporary queue are gradually migrated back to the main queue and the system reissues credits.
[0048] Depend on Figure 3As shown in the timing diagram, this application uses a temporary queue to handle data packets during the full load phase of the main queue. It does not directly block upstream packet transmission. Credits are only reissued when data packets are directly written to the main queue or when data packets from the temporary queue are migrated back to the main queue. Reissue is paused when data packets are simply stored in the temporary queue. This matches the actual release status of hardware storage resources and continuously buffers packets during the delay gap of pointer synchronization, avoiding data transmission gaps in the link and smoothing bandwidth fluctuations across clock domains. At the same time, the initial credit limit is matched with the depth of the temporary queue, which can constrain the maximum burst packet volume upstream and prevent the temporary queue from overflowing and blocking.
[0049] In this embodiment, a differentiated credit return mechanism is set for different data packet writing scenarios. This mechanism can dynamically adjust the upstream packet sending permissions based on the actual storage occupancy status of the receiving side, thereby achieving closed-loop flow control, effectively suppressing instantaneous packet sending impacts, and preventing queue overflow blocking.
[0050] Furthermore, when the temporary queue has data packets and the main queue has empty slots, the write module writes all newly sent data packets from the upstream data sender into the temporary queue before all the data packets temporarily cached in the temporary queue are written into the main queue.
[0051] For example, this rule serves as the scheduling priority constraint for the dual-layer caching architecture of this application, prioritizing the emptying of existing data packets in the temporary queue, and ensuring that newly sent data packets from upstream do not preempt empty slots in the main queue. Figure 3 At time t3, the main queue becomes available due to reading A1, while the temporary queue still has untransferred data packet B2. If a new data packet B3 is sent from upstream at this time, even if there is an empty slot in the main queue, the write module will not write B3 directly to the main queue, but will instead send it to the temporary queue. If the upstream is allowed to directly occupy the empty slot in the main queue, the existing data packets in the temporary queue will continue to accumulate, causing data packets sent by the upstream a long time ago to remain cached in the temporary queue, which the read module cannot read. This results in a continuously increasing cache duration for early-sent data packets, increasing data transmission latency and causing out-of-order packets. Therefore, this rule ensures that the existing data packets in the temporary queue always have the highest scheduling priority for the empty slot in the main queue, continuously clearing the temporary buffer, and, together with the differentiated credit return mechanism, stabilizing the continuous data transmission of the entire link.
[0052] In this embodiment, by prioritizing the emptying of the temporary queue, when there are cached data packets in the temporary queue, even if there are empty slots in the main queue, the existing data packets are transferred first. Before the temporary queue is completely empty, new packets from upstream are intercepted and directly written into the main queue, which can quickly release the storage space of the temporary queue, trigger credit resending actions in a timely manner, and effectively improve the transmission gap caused by cross-clock domain pointer synchronization delay.
[0053] Furthermore, when the write module writes data packets from the temporary queue to the main queue, it selects the data packet with the longest temporary buffer time and writes it to the main queue according to the order in which the data packets were written to the temporary queue.
[0054] For example, this mechanism corresponds to the First In First Out (FIFO) scheduling rule. The order in which data packets enter the temporary queue is the order of their buffering duration. The data packet that enters the temporary queue first has the longest buffering duration and will be preferentially transferred to the main queue. Figure 3 At time t2, B1 and B2 are stored in the temporary queue in sequence. B1 is written first and has a longer cache duration. When the main queue becomes empty at time t4, the write module prioritizes transferring B1, which has the longest cache duration, to the main queue. The temporary queue only retains B2, which was stored later.
[0055] In this embodiment, the temporary queue prioritizes the transfer of data packets with the longest buffer time according to the order in which the data packets are stored, following the first-in-first-out transmission rule. This ensures the consistency of data packet transmission sequence, avoids data verification anomalies or data packet retransmission caused by out-of-order transmission, and reduces additional system processing overhead.
[0056] Furthermore, the memory controller is configured with a write pointer and a read pointer; the write pointer is set in the write module, and the write module updates the pointer position every time it writes a data packet to the main queue; the read pointer is set in the read module, and the read module updates the pointer position every time it completes a data packet reading operation.
[0057] For example, see Figure 4 , Figure 4 This is a schematic diagram illustrating the pointer interaction between the write clock domain and the read clock domain in the on-chip system provided in this application embodiment. The hardware architecture of this application is also divided into independent write clock domains and read clock domains. The write pointer and read pointer reside within their respective clock domains and are updated in real-time with each read / write operation. Cross-domain synchronization is achieved through two levels of timing registers, providing the credit calculation logic with information to determine queue occupancy status. The write pointer is generated in the main queue within the write clock domain. Whenever the high-speed interconnect interface module sends a data packet, the write module writes the data packet to the main queue, and the main queue synchronously updates the write pointer position. The write pointer is directly sent to the credit calculation logic as a local queue write boundary identifier within the write clock domain. The read pointer is generated by the read action control logic within the read clock domain. Whenever the read module completes a data packet read operation, the read action control logic updates the Gray code-encoded read pointer, marking the current read boundary of the main queue.
[0058] In this embodiment, by configuring independent pointers in the write module and the read module respectively, and updating the pointer positions in real time along with the data packet writing and reading actions, the storage occupancy status of the main queue can be marked in real time, providing a basis for determining whether the queue is full in the future.
[0059] Furthermore, the write module receives the read pointer sent by the read module and performs a slapping process on the read pointer based on the two-level registers to obtain a synchronous read pointer; when the write module detects that the bits of the synchronous read pointer and the write pointer meet the preset matching conditions, it determines that the main queue is full.
[0060] For example, if the read pointer is generated in the asynchronous read clock domain and directly sent to the credit calculation logic in the write clock domain, metastability will occur, causing errors in queue status judgment. Therefore, this application adopts a two-level register continuous staking synchronization scheme. After the read pointer is output from the read clock domain, it passes through two levels of staking registers sequentially, and after waiting for two write clock cycles, a stable, glitch-free synchronous read pointer is output, eliminating the metastability problem of cross-clock domain signals and ensuring the reliability of the pointer value. Similarly, the write pointer also needs to pass through two levels of registers for continuous staking, and after stabilizing for two read clock cycles, it is sent to the read clock domain. This avoids metastability during cross-domain transmission of the write pointer, ensuring that the read clock domain can accurately identify the range of data packets stored in the main queue, and realizing reliable interaction of queue status information between the read and write clock domains.
[0061] In this embodiment, the read pointer transmitted across clock domains is synchronized by using two-level registers, which can effectively eliminate the fluctuations caused by asynchronous pointer transmission across domains, output a stable and reliable synchronous read pointer, avoid misjudgment of queue status due to pointer transmission abnormalities, and ensure the stable operation of credit management logic.
[0062] Furthermore, the matching condition is: the highest bit of the synchronous read pointer and the write pointer are different, while the remaining bits are the same.
[0063] For example, this application uses Gray code pointer determination logic to distinguish the queue loop state by the highest bit, thereby distinguishing between a full and empty queue state. For instance, assuming the main queue pointer has a bit width of 3 bits, with the highest bit being the 2nd bit and the lowest bits being the 1st and 0th bits, if the synchronous read pointer value is 011 and the write pointer value is 111, their highest bits are 0 and 1 respectively, and the remaining low bits are completely identical, then the matching condition is met, and the main queue is determined to be full. If both the synchronous read pointer and the write pointer are 011, and the highest and lowest bits are all the same, then the queue is determined to be empty. The reason for setting this matching condition is that when the circular FIFO read and write pointers loop, simply having the same pointer cannot distinguish whether all data has been read or all data has been written. When the highest bit is reversed and the remaining low bits are all equal, it indicates that the write pointer has completed a full loop of the cache and caught up with the read pointer. At this point, all positions in the cache are full of data, with no empty spaces, meaning that all storage units in the main queue are occupied. Once the main queue is determined to be full, new data packets from upstream are transferred to the temporary queue for buffering. When the read pointer is updated and the bit matching relationship is broken, it means that there is an empty slot in the main queue. The memory controller can then schedule the data packets in the temporary queue to be migrated back to the main queue and reissue credits.
[0064] In this embodiment, the matching condition can accurately distinguish between the full and empty states of the main queue, achieving high-precision queue fullness determination. Furthermore, this determination method requires only simple bit comparison operations, has extremely low hardware combinational logic latency, does not require additional complex counting circuits, and can quickly identify whether the main queue storage space is exhausted.
[0065] Compared to existing technologies, the memory controller in this application, by adding a temporary queue to form a two-layer cache scheduling architecture, can alleviate the transmission bandwidth reduction problem caused by short-term pauses in the cross-clock pipeline. When the main queue storage space is full, the system can provide a buffer window of up to n-2 write clock cycles (n is the depth of the temporary queue, and 2 represents the fixed 2 write clock cycle delay occupied during two-level synchronization) to wait for the downstream to complete the data packet reading operation, covering the transmission delay gap caused by the two-level synchronization of the read pointer, and maintaining message transmission and no interruption gaps throughout the link. At the same time, this application does not need to increase the depth of the main asynchronous queue to deal with traffic congestion and synchronization delay problems, reduces the number of cross-clock signal lines, reduces the design difficulty of physical wiring at the back end of the chip, and can also control the size of the register array, effectively reducing the controller chip area and operating power consumption, balancing transmission performance and hardware implementation cost.
[0066] See Figure 5 , Figure 5This is a flowchart of a credit management method provided in an embodiment of this application. The method is applied to a memory controller, which includes a high-speed interconnect interface module and a write module connected by communication. The write module includes a main queue and a temporary queue. The main queue is used to cache data packets, and the temporary queue is used to temporarily cache data packets when the main queue is full, and to write the temporarily cached data packets into the main queue when there is space in the main queue. The method includes: S1. Receive data packets sent by the upstream data sender through the high-speed interconnection interface module; wherein, the upstream data sender consumes one credit for each data packet sent, and the credit is the authorized quota for sending data packets by the upstream data sender; when there is available credit, the upstream data sender is allowed to send data packets and consumes credit accordingly; when the available credit is 0, the upstream data sender is restricted from sending data packets. S2. The write module determines whether to return credit to the upstream data sender based on the data packet writing method, so that the upstream data sender can update the available credit balance for sending the remaining data packets.
[0067] Furthermore, the memory controller also includes a read module, which is communicatively connected to the write module. After performing step S2, the method further includes: reading data packets from the main queue via the read module.
[0068] It is worth noting that the working process of the credit management method described in this application embodiment can refer to the working process of the memory controller described in the above embodiment, and will not be repeated here.
[0069] In this embodiment, traffic control between the memory controller and the upstream data sender is based on credit quotas. Credits are used as the upstream packet sending authorization quota to constrain the upstream packet sending behavior. The upstream can only send packets when there are available credits. When the credits are exhausted, packet sending automatically stops, thus preventing the upstream from sending packets without limit, which could cause buffer overflow, data loss, or link blockage on the receiving side. At the same time, the write module sets up a two-level buffer of main queue and temporary queue. When the main queue is full, packets are temporarily stored in the temporary queue. After the main queue releases empty slots, the packets stored in the temporary queue are prioritized to fill the empty slots. The mechanism of differentiating credit return based on different packet writing methods can quickly clear the backlog of packets in the temporary queue, thereby timely restoring the upstream packet sending credits. It can also avoid the transmission gap caused by the inability to resend credits in time due to cross-clock domain pointer synchronization delay. It can eliminate the transmission interruption and bandwidth fluctuation caused by cross-clock synchronization delay and improve data transmission efficiency.
[0070] The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications are also considered to be within the scope of protection of this application.
Claims
1. A memory controller, characterized in that, The memory controller is used for communication with the upstream data sender, and includes an interconnect high-speed interface module and a write module for communication connection; wherein... The high-speed interconnect interface module is used to receive data packets sent by the upstream data sender; wherein, the upstream data sender consumes one credit for each data packet sent, and the credit is the authorized quota for sending data packets by the upstream data sender; when there is available credit, the upstream data sender is allowed to send data packets and consumes the corresponding credit; when the available credit is 0, the upstream data sender is restricted from sending data packets. The write module includes a main queue and a temporary queue. The main queue is used to cache the data packets. The temporary queue is used to temporarily cache the data packets when the main queue is full, and to write the temporarily cached data packets into the main queue when there is space in the main queue. The write module determines whether to return credit to the upstream data sender based on the writing method of the data packets, so that the upstream data sender can update the available credit balance for sending the remaining data packets.
2. The memory controller as described in claim 1, characterized in that, The write module determines whether to return credit to the upstream data sender based on the writing method of the data packet, including one of the following methods: When the write module directly writes the data packet sent by the upstream data sender into the main queue, it returns a credit to the upstream data sender. When the writing module directly writes the data packet sent by the upstream data sender into the temporary queue, it stops returning credits. When the write module writes the data packet in the temporary queue to the main queue, it returns a credit to the upstream data sender.
3. The memory controller as described in claim 1, characterized in that, When the temporary queue has data packets and the main queue has empty slots, the write module writes all newly sent data packets from the upstream data sender into the temporary queue before all data packets temporarily cached in the temporary queue are written into the main queue.
4. The memory controller as described in claim 1, characterized in that, The write module sends initial credits to the upstream data sender based on the queue depth of the temporary queue; wherein the initial credits are used to specify the maximum value of the authorized quota.
5. The memory controller as described in claim 1, characterized in that, When the write module writes data packets from the temporary queue to the main queue, it selects the data packet with the longest temporary buffer duration and writes it to the main queue according to the order in which the data packets are written to the temporary queue.
6. The memory controller as described in claim 1, characterized in that, The memory controller also includes a read module, which is communicatively connected to the write module. The read module is used to read data packets from the main queue.
7. The memory controller as described in claim 6, characterized in that, The memory controller is configured with write pointers and read pointers; wherein... The write pointer is set in the write module, and the write module updates the pointer position of the write pointer every time it writes a data packet to the main queue. The read pointer is set in the read module, and the read module updates the pointer position every time it completes a data packet reading operation.
8. The memory controller as described in claim 7, characterized in that, The write module receives the read pointer sent by the read module and performs a slapping process on the read pointer based on two-level registers to obtain a synchronous read pointer; when the write module detects that the bits of the synchronous read pointer and the write pointer meet the preset matching conditions, it determines that the storage of the main queue is full.
9. The memory controller as described in claim 8, characterized in that, The matching condition is that the highest bit of the synchronous read pointer and the write pointer are different, while the remaining bits are the same.
10. A credit management method, characterized in that, The method is applied to a memory controller, which includes a high-speed interconnect interface module and a write module for communication connection. The write module includes a main queue and a temporary queue. The main queue is used to cache data packets, and the temporary queue is used to temporarily cache the data packets when the main queue is full, and to write the temporarily cached data packets into the main queue when there is space in the main queue. The method includes: The high-speed interconnect interface module receives data packets sent by the upstream data sender; wherein, the upstream data sender consumes one credit for each data packet sent, and the credit is the authorized quota for sending data packets by the upstream data sender; when there is available credit, the upstream data sender is allowed to send data packets and consumes the corresponding credit; when the available credit is 0, the upstream data sender is restricted from sending data packets. The write module determines whether to return credit to the upstream data sender based on the writing method of the data packet, so that the upstream data sender can update the available credit balance for sending the remaining data packets.