A cache maintenance system and method for a DSP chip sharing memory

Abstract

The application belongs to the technical field of cache maintenance, and particularly relates to a cache maintenance system and method for shared storage of a DSP chip. The application configures a protocol state identifier in a directory entry, dynamically switches a stable maintenance state, a dynamic adjustment state and an access freezing state according to an access type, a cache state and a data version state corresponding to a target cache line, so that a cache maintenance process can select different maintenance strategies according to actual access conditions of the target cache line, improve the adaptability of a cache consistency maintenance process, reduce the number of processing cores that do not need to participate in cache maintenance, concentrate cache invalidation control, version checking and cache update operations on related processing cores, improve cache maintenance resource utilization, dynamically adjust a cache processing core set and a target maintenance core set, so that a cache maintenance range is determined according to actual access conditions of the target cache line, and communication pressure caused by cache consistency maintenance in a multi-core expansion process is reduced.

Description

Technical Field

[0001] This invention belongs to the field of cache maintenance technology, specifically relating to a cache maintenance system and method for shared memory of DSP chips. Background Technology

[0002] With the development of high-performance digital signal processing technology, multi-core DSP (Digital Signal Processor) chips are increasingly being applied in fields such as radar signal processing, communication baseband processing, industrial control, intelligent sensing, and real-time computing. To meet the demands of large-scale parallel data processing under complex tasks, existing multi-core DSP architectures typically employ a collaborative approach with multiple processing cores, using a shared memory area for data exchange between different cores. Simultaneously, to improve data access efficiency, multi-core DSP chips are usually configured with on-chip cache structures, enabling each processing core to cache frequently accessed data, thereby reducing the number of accesses to the shared memory area and increasing data processing throughput. During the operation of a multi-core DSP, both the processing cores and DMA (Direct Memory Access) units may access data in the shared memory area. The processing cores obtain local data copies through caching mechanisms, while DMA units are typically used for high-speed data transfer operations. Therefore, maintaining the consistency of cached data in the shared memory area becomes a crucial factor affecting the reliability and real-time performance of the multi-core DSP system.

[0003] In existing technologies, multi-core DSP shared memory cache maintenance typically adopts a fixed cache consistency strategy, which cannot dynamically adjust the cache maintenance scope according to changes in cache line access, data version changes, and processing core access. It also lacks an effective state control mechanism during DMA access, which can easily cause cache directory updates and data access conflicts, resulting in reduced cache maintenance efficiency and insufficient data consistency reliability. Summary of the Invention

[0004] The purpose of this invention is to provide a cache maintenance system and method for shared memory of DSP chips, which can improve data consistency and cache maintenance efficiency of shared memory of multi-core DSPs and reduce invalid communication overhead by dynamically adjusting the cache maintenance scope and combining it with access state control.

[0005] The specific technical solution adopted by this invention is as follows: A cache maintenance method for shared memory of a DSP chip includes: In a multi-core DSP architecture, it receives access requests to the shared memory area, determines the target cache line based on the access address in the access request, and generates a cache line index corresponding to the target cache line. Based on the cache line index query, the corresponding directory entry is retrieved, the cache line status identifier, data version identifier and the processing core set corresponding to the target cache line are obtained from the directory entry, and the corresponding protocol status identifier is configured according to the directory entry. The protocol status identifier includes stable maintenance status, dynamic adjustment status and access freeze status. Based on the access type, cache line status identifier, and data version identifier corresponding to the access request, the protocol status identifier is processed for state transition, so that the target cache line switches between stable maintenance state, dynamic adjustment state, and access freeze state. When the protocol status flag indicates that the target cache line is in a dynamic adjustment state, a cache processing core set is generated based on the processing core set, historical access sequence, and data version flag corresponding to the target cache line, and a cache replica propagation set is established based on the cache processing core set; Based on the cache replica propagation set and the access type corresponding to the access request, determine the cache replica maintenance object, and adjust the processing core range corresponding to the cache replica maintenance object according to the protocol status identifier to generate the target maintenance core set; Based on the target maintenance kernel set and the access type corresponding to the access request, perform cache copy maintenance operation on the target cache line; After completing the cache copy maintenance operation, the cache processing core set is dynamically updated based on the execution result and protocol status identifier of the cache copy maintenance operation, and the data version identifier and protocol status identifier in the directory entries are adjusted synchronously.

[0006] In a preferred embodiment, in a multi-core DSP architecture, an access request to a shared memory region is received, and a target cache line is determined based on the access address in the access request. A cache line index corresponding to the target cache line is then generated, including: In a multi-core DSP architecture, it receives access requests to the shared memory region and obtains the access address information corresponding to the access request. The data access location corresponding to the access request is determined based on the access address information, and the target cache line corresponding to the access request is located based on the data access location; Obtain the cache line address information corresponding to the target cache line, and determine the cache line identifier corresponding to the target cache line based on the cache line address information; Generate the corresponding cache line index based on the cache line identifier.

[0007] In a preferred embodiment, the corresponding directory entry is queried based on the cache line index to obtain the cache line status identifier, data version identifier, and processing core set corresponding to the target cache line from the directory entry. The corresponding protocol status identifier is configured according to the directory entry, wherein the protocol status identifier includes stable maintenance status, dynamic adjustment status, and access freeze status, including: Based on the cache line index query, the directory entry corresponding to the target cache line is retrieved to obtain the cache line status identifier, data version identifier and processing core set corresponding to the target cache line recorded in the directory entry; Based on the processing core set, cache line status identifier, and data version identifier corresponding to the target cache line, configure the corresponding protocol status identifier for the target cache line and associate the protocol status identifier with the directory entry; Set the protocol status identifier as the status identifier of the target cache line cache maintenance process. The protocol status identifier includes stable maintenance status, dynamic adjustment status, and access freeze status.

[0008] In a preferred embodiment, based on the access type corresponding to the access request, the cache line status identifier, and the data version identifier, a state transition process is performed on the protocol status identifier to switch the target cache line between a stable maintenance state, a dynamic adjustment state, and an access-frozen state, including: Retrieve the access request corresponding to the target cache line, and obtain the access type in the access request; Get the cache line status identifier and data version identifier from the directory entry corresponding to the target cache line, and get the current identifier status corresponding to the cache line status identifier and the current identifier status corresponding to the data version identifier; Based on the access type, the current identifier status corresponding to the cache line status identifier, and the current identifier status corresponding to the data version identifier, determine the protocol status switching conditions corresponding to the target cache line; According to the protocol state switching conditions, the protocol state identifier is processed for state transition, and the cache maintenance state corresponding to the protocol state identifier is adjusted so that the target cache line switches between stable maintenance state, dynamic adjustment state and access freeze state.

[0009] In a preferred embodiment, when the protocol status flag indicates that the target cache line is in a dynamic adjustment state, a cache processing core set is generated based on the processing core set corresponding to the target cache line, the historical access sequence, and the data version flag. A cache replica propagation set is then established based on the cache processing core set, including: When the protocol status flag indicates that the target cache line is in a dynamic adjustment state, read the directory entry corresponding to the target cache line and obtain the processing core set corresponding to the target cache line recorded in the directory entry. Obtain the historical access sequence corresponding to the target cache line and read the data version identifier from the directory entry; Generate a cache processing core set based on the processing core set corresponding to the target cache line, the historical access sequence, and the data version identifier; The processing cores that participate in the maintenance of cache replicas of the target cache line are determined based on the cache processing core set, and a cache replica propagation set is formed based on the processing cores that participate in the maintenance of cache replicas.

[0010] In a preferred embodiment, a cache processing core set is generated based on the processing core set corresponding to the target cache line, the historical access sequence, and the data version identifier, including: Obtain the access request records corresponding to the target cache line in the historical access sequence, and determine the access count and access order of the target cache line corresponding to each processing core based on the access request records; Based on the number of accesses and the access order for each processing core, determine the access characteristics of the processing cores corresponding to the target cache line, and combine the processing core set and data version identifier corresponding to the target cache line to determine the processing core set adjustment conditions; Based on the processing core set adjustment conditions, the processing cores in the processing core set corresponding to the target cache line are filtered to determine the filtered processing core set, which includes retained processing cores, added processing cores, and removed processing cores. The processing core set corresponding to the target cache line is updated based on the filtered processing core set to generate a cache processing core set.

[0011] In a preferred embodiment, the cache replica maintenance object is determined based on the cache replica propagation set and the access type corresponding to the access request. The processing core range corresponding to the cache replica maintenance object is then adjusted according to the protocol status identifier to generate a target maintenance core set, including: Based on the cache replica propagation set and the access type corresponding to the access request, determine the cache replica processing method for the access request; Based on the cache replica propagation set and cache replica processing method, determine the cache replica to be maintained corresponding to the target cache line, and obtain the processing core set corresponding to the cache replica to be maintained; The current cache maintenance status is determined based on the protocol status identifier, and the range of the processing core set corresponding to the cache copy to be maintained is adjusted based on the current cache maintenance status to select the processing cores to participate in the cache copy maintenance. The target maintenance kernel set is generated based on the filtered processing kernels.

[0012] In a preferred embodiment, based on the target maintenance kernel set and the access type corresponding to the access request, a cache copy maintenance operation is performed on the target cache line, including: Determine the cache copy maintenance method corresponding to the target cache line based on the access type; Read the data version identifier and protocol status identifier corresponding to the target cache line based on the cache copy maintenance method; When the access type is a write request, the data version corresponding to the target cache line is updated according to the data version identifier, an updated data version identifier is generated, and the corresponding cache copy is determined according to the target maintenance kernel set, and a status update operation is performed on the cache copy. When the access type is a read request, the data version identifier corresponding to the local cache copy is checked against the data version identifier corresponding to the target cache line. If the check result does not match, the data corresponding to the target cache line is retrieved from the shared storage area to update the local cache copy. When the access type is a DMA access request, the protocol status flag is switched to the access freeze state according to the data access process corresponding to the DMA access request, and the update operations of directory entries and cache processing cores are restricted based on the access freeze state.

[0013] In a preferred embodiment, after completing the cache copy maintenance operation, the cache processing core set is dynamically updated based on the execution result and protocol status identifier of the cache copy maintenance operation, and the data version identifier and protocol status identifier in the directory entries are adjusted synchronously, including: After completing the cache copy maintenance operation, obtain the execution result corresponding to the cache copy maintenance operation, and read the protocol status flag corresponding to the target cache line; The update conditions for the cache processing core set are determined based on the execution results and protocol status identifiers. The processing cores in the cache processing core set are then updated based on the update conditions to generate the updated cache processing core set. Update the processing core set corresponding to the target cache line recorded in the directory entry according to the updated cache processing core set, so that the processing core set in the directory entry corresponds to the current cache copy state; Based on the execution results and protocol status identifiers, the data version identifiers and protocol status identifiers in the directory entries are updated synchronously.

[0014] The present invention also provides a cache maintenance system for shared memory of a DSP chip, and a cache maintenance method for the shared memory of the aforementioned DSP chip, comprising: The cache line generation module is used in a multi-core DSP architecture to receive access requests to the shared memory area, determine the target cache line based on the access address in the access request, and generate a cache line index corresponding to the target cache line. The entry configuration module queries the corresponding directory entry based on the cache line index, obtains the cache line status identifier, data version identifier and the processing core set corresponding to the target cache line in the directory entry, and configures the corresponding protocol status identifier according to the directory entry. The protocol status identifier includes stable maintenance status, dynamic adjustment status and access freeze status. The state transition module is used to perform state transition processing on the protocol state identifier according to the access type, cache line status identifier and data version identifier corresponding to the access request, so that the target cache line can switch between stable maintenance state, dynamic adjustment state and access frozen state. The cache replica module is used to generate a cache processing core set based on the processing core set, historical access sequence, and data version identifier corresponding to the target cache line when the protocol status identifier indicates that the target cache line is in a dynamic adjustment state, and to establish a cache replica propagation set based on the cache processing core set. The target maintenance module is used to determine the cache replica maintenance object based on the cache replica propagation set and the access type corresponding to the access request, and to adjust the processing core range corresponding to the cache replica maintenance object according to the protocol status identifier, thereby generating the target maintenance core set. The cache maintenance module performs cache copy maintenance operations on the target cache line based on the target maintenance kernel set and the access type corresponding to the access request; The dynamic update module is used to dynamically update the cache processing core set after the cache copy maintenance operation is completed, based on the execution result of the cache copy maintenance operation and the protocol status identifier, and synchronously adjust the data version identifier and protocol status identifier in the directory entries.

[0015] The technical effects achieved by this invention are as follows: This invention configures protocol status identifiers in directory entries and dynamically switches between stable maintenance, dynamic adjustment, and access freeze states based on the access type, cache status, and data version status corresponding to the target cache line. This allows the cache maintenance process to select different maintenance strategies based on the actual access situation of the target cache line, improving the adaptability of the cache consistency maintenance process. It can also reduce the number of processing cores that do not need to participate in cache maintenance, allowing cache invalidation control, version verification, and cache update operations to be concentrated on relevant processing cores, thereby improving the utilization rate of cache maintenance resources. By dynamically adjusting the cache processing core set and the target maintenance core set, the scope of cache maintenance no longer expands linearly with the number of processing cores, but is determined based on the actual access situation of the target cache line. This reduces the communication pressure brought by cache consistency maintenance during multi-core expansion and improves the scalability of multi-core DSP architecture. This invention, by setting an access freeze state, switches the protocol status flag to the access freeze state when a DMA access request is detected, and restricts the updates of directory entries and cache processing core sets. This keeps the cache maintenance state stable during DMA access, reducing data consistency anomalies caused by cache state changes during DMA transmission. Based on the maintenance execution results and protocol status flag feedback, the cache processing core set, data version flag, and protocol status flag are adjusted, ensuring that directory entries continuously reflect the current cache state of the target cache line. This achieves dynamic synchronization between cache directory information and the actual cache copy state, improving cache maintenance accuracy. The target maintenance core set is dynamically generated based on the target cache line access characteristics, and cache maintenance operations are performed only on the relevant processing cores, avoiding the problem of sending maintenance messages to all processing cores in traditional broadcast consistency protocols. Therefore, it can reduce invalid communication in the on-chip network, improve resource utilization efficiency during DSP chip shared memory access, and reduce power consumption during cache maintenance. Attached Figure Description

[0016] Figure 1 This is a flowchart of the method provided by the present invention; Figure 2 This is a system module diagram provided by the present invention. Detailed Implementation

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0018] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0019] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in a preferred embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that mutually excludes other embodiments.

[0020] Furthermore, the present invention will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present invention in detail, the schematic diagrams are merely examples for ease of explanation and should not limit the scope of protection of the present invention.

[0021] Please see the appendix Figure 1 As shown, a cache maintenance method for shared memory of a DSP chip is provided, including: S1. In a multi-core DSP architecture, receive access requests to the shared memory area, determine the target cache line based on the access address in the access request, and generate a cache line index corresponding to the target cache line. S2. Query the corresponding directory entry based on the cache line index, obtain the cache line status identifier, data version identifier and the processing core set corresponding to the target cache line in the directory entry, and configure the corresponding protocol status identifier according to the directory entry. The protocol status identifier includes stable maintenance status, dynamic adjustment status and access freeze status. S3. Based on the access type, cache line status identifier and data version identifier corresponding to the access request, perform state transition processing on the protocol status identifier to switch the target cache line between stable maintenance state, dynamic adjustment state and access freeze state. S4. When the protocol status flag indicates that the target cache line is in a dynamic adjustment state, generate a cache processing core set according to the processing core set, historical access sequence and data version flag corresponding to the target cache line, and establish a cache replica propagation set according to the cache processing core set. S5. Based on the cache replica propagation set and the access type corresponding to the access request, determine the cache replica maintenance object, and adjust the processing core range corresponding to the cache replica maintenance object according to the protocol status identifier to generate the target maintenance core set. S6. Based on the target maintenance kernel set and the access type corresponding to the access request, perform cache copy maintenance operation on the target cache line; S7. After completing the cache copy maintenance operation, dynamically update the cache processing core set according to the execution result of the cache copy maintenance operation and the protocol status identifier, and synchronously adjust the data version identifier and protocol status identifier in the directory entries.

[0022] As described in steps S1 to S7 above, during the operation of the multi-core DSP architecture, the processing core or DMA unit initiates an access request to the shared memory area according to the task execution requirements. After receiving the access request, the access address in the access request is parsed, the corresponding data storage location is determined based on the access address, and the target cache line corresponding to the data is further located. Since the data in the shared memory area is cached at the cache line granularity, a cache line index is generated based on the address information corresponding to the target cache line. Using the cache line index as the basis for directory lookup, the directory entry corresponding to the target cache line can be quickly located, thereby avoiding direct traversal of all cache state information and improving the efficiency of state lookup during cache maintenance. Accessing the target cache line based on the generated cache line index... The system retrieves the corresponding directory entries and obtains the cache line status identifier, data version identifier, and processing core set of the target cache line recorded in the directory entries. The cache line status identifier describes the current cache status of the target cache line, such as whether a valid cache copy exists and whether the cache copy is maintainable. The data version identifier describes the current data version information of the target cache line, enabling different processing cores to determine whether the cached data is synchronized based on the version information. The processing core set records the range of processing cores for the current target cache line, i.e., which processing cores contain a cache copy corresponding to the target cache line. Based on the current cache status, data version status, and processing core set status of the target cache line, the system configures the corresponding protocol status identifier for the target cache line. Protocol status identifiers describe the current maintenance stage of the cache maintenance process, including stable maintenance, dynamic adjustment, and access freeze. Stable maintenance indicates that the target cache line access status is relatively stable, and routine cache maintenance is performed according to the current processing core set. Dynamic adjustment indicates that the target cache line access pattern has changed, requiring readjustment of the cache processing core range. Access freeze indicates that a DMA access process is currently underway, requiring temporary restriction of directory entries and processing core set changes to avoid cache state conflicts during DMA transfer. Based on the access type, cache line status identifier, and data version identifier corresponding to the current access request, the protocol status identifier is used for state transition judgment. When data access corresponding to the access request is detected... When behavior changes, such as increased access frequency, changes in cache replica distribution, data version updates, or the presence of DMA access requests, the protocol status flag is adjusted to switch the target cache line between a stable maintenance state, a dynamic adjustment state, and an access freeze state. The protocol status flag controls the cache maintenance behavior at different stages, allowing the cache maintenance process to no longer rely on a fixed consistency processing flow but instead select the appropriate maintenance strategy based on the actual access state of the target cache line. When the protocol status flag indicates that the target cache line has entered the dynamic adjustment state, the processing core set, historical access sequence, and data version flag corresponding to the target cache line are further read. The historical access sequence records the access request information of the target cache line during continuous access.This includes tracking access to the target cache line by different processing cores. Data version identifiers reflect changes in the target cache line data. Access characteristics of different processing cores to the target cache line are determined based on historical access sequences, such as access concentration and changes. Adjustment conditions for the processing core set are determined by combining the current processing core set and data version identifiers. Based on these conditions, dynamic filtering is performed on the processing core set corresponding to the target cache line, generating an updated cache processing core set. The processing cores participating in cache replica maintenance are then determined based on the updated cache processing core set, forming a cache replica propagation set. Finally, the cache replica maintenance objects are determined based on the access type corresponding to the current access request. For example, for a write access request, the range of cache replicas requiring invalidation needs to be determined. For read access requests, the range of data replicas requiring version verification needs to be determined. For DMA access requests, the range of directory maintenance to be frozen needs to be determined. The processing core range corresponding to the cache replica maintenance object is adjusted based on the current protocol status identifier. In dynamic adjustment mode, the updated processing core range is used; in stable maintenance mode, the current maintenance range is maintained; and in access freeze mode, changes to the processing core set are restricted. Finally, a target maintenance core set is generated. Based on the generated target maintenance core set and the access request type, the corresponding cache replica maintenance operation is performed on the target cache line. When the access request is a write request, the data version of the target cache line is updated according to the current data version identifier, and a status update is performed on the cache replicas corresponding to the target maintenance core set to ensure that... It handles the invalidation or pending update of old cache copies in the core, ensuring that the written data version is correctly propagated. When the access request is a read request, it verifies the data version identifier of the local cache copy with the data version identifier in the directory entry. If they do not match, it retrieves the target cache line data from the shared storage area and updates the local cache copy to keep the read data up-to-date. When the access request is a DMA access request, it switches the protocol status to the access freeze state and restricts update operations on directory entries and the cache processing core set, keeping the cache maintenance state stable during DMA data transfer. After completing the cache copy maintenance operation, it obtains the execution result corresponding to the cache copy maintenance operation and combines it with the current protocol status. Feedback adjustments are made to the cache processing core set. If the cache replica distribution changes, the cache processing core set is adjusted based on the execution results to ensure that the processing core set in the directory entry reflects the current actual cache replica status. Data version identifiers in the directory entry are synchronously updated based on data version changes generated during cache maintenance, and protocol status identifiers are adjusted based on the current access status, causing the target cache line to re-enter the corresponding maintenance state. This forms a closed-loop maintenance process of access request acquisition, status judgment, dynamic adjustment, cache maintenance, and status feedback. Protocol status identifiers are configured in the directory entry, and the stable maintenance state, dynamic adjustment state, and access freeze state are dynamically switched based on the access type, cache status, and data version status corresponding to the target cache line.This system enables the cache maintenance process to select different maintenance strategies based on the actual access situation of the target cache line, improving the adaptability of the cache consistency maintenance process. It reduces the number of processing cores that do not need to participate in cache maintenance, allowing cache invalidation control, version verification, and cache update operations to be concentrated on relevant processing cores, thus improving cache maintenance resource utilization. By dynamically adjusting the cache processing core set and the target maintenance core set, the scope of cache maintenance no longer expands linearly with the number of processing cores, but is determined based on the actual access situation of the target cache line. This reduces the communication pressure brought by cache consistency maintenance during multi-core expansion, improving the scalability of multi-core DSP architectures. By setting an access freeze state, when a DMA access request is detected, the protocol status flag is switched to the access freeze state, and updates to directory entries and the cache processing core set are restricted, enabling DM... During access, the cache maintenance state remains stable, reducing data consistency anomalies caused by cache state changes during DMA transfer. The cache processing core set, data version identifier, and protocol status identifier are adjusted based on maintenance execution results and protocol status feedback, ensuring that directory entries continuously reflect the current cache state of the target cache line. This achieves dynamic synchronization between cache directory information and the actual cache copy state, improving cache maintenance accuracy. A target maintenance core set is dynamically generated based on the target cache line access characteristics, performing cache maintenance operations only on relevant processing cores. This avoids the problem of sending maintenance messages to all processing cores in traditional broadcast consistency protocols, thus reducing invalid communication in the on-chip network, improving resource utilization efficiency during DSP chip shared memory access, and reducing power consumption during cache maintenance.

[0023] In a preferred embodiment, in a multi-core DSP architecture, an access request to a shared memory region is received, and a target cache line is determined based on the access address in the access request. A cache line index corresponding to the target cache line is generated, including: S101. In a multi-core DSP architecture, receive access requests initiated to the shared memory area and obtain the access address information corresponding to the access request; S102. Determine the data access location corresponding to the access request based on the access address information, and locate the target cache line corresponding to the access request based on the data access location; S103. Obtain the cache line address information corresponding to the target cache line, and determine the cache line identifier corresponding to the target cache line based on the cache line address information; S104. Generate the corresponding cache line index based on the cache line identifier.

[0024] As described in steps S101 to S104 above, a multi-core DSP architecture refers to a hardware architecture that integrates multiple digital signal processing cores with independent computing capabilities within the same DSP chip, and realizes data interaction between the multiple processing cores through on-chip interconnection, cache control modules, and shared memory control modules. Taking an 8-core DSP chip as an example, this DSP chip includes eight processing cores: Core0, Core1, Core2, Core3, Core4, Core5, Core6, and Core7. Each processing core has an independent instruction execution unit, register resources, and a level 1 cache space. Each processing core is connected to a shared cache area and a shared memory area through an on-chip bus. Core0 can be used to perform data acquisition and processing. In a DSP chip, Core1 can be used to perform signal filtering tasks, while Core2 can be used to perform feature calculation tasks. Different processing cores access common data in the shared memory area according to their own task requirements. A processing core is a basic arithmetic unit in the DSP chip that performs computational tasks. For example, when Core0 executes program instructions, it generates a read request based on the data access requirements in the current instruction. When Core1 needs to modify shared data, it generates a write access request based on the write instruction. The access requests generated by the processing cores usually include access source information, access type information, and access address information. The access source information is used to indicate the number of the processing core that generated the access behavior, such as Core0. The access type information is used to indicate the current access operation, such as a read operation or a write operation.Access address information indicates the storage location of target data in the shared memory space. A DMA unit refers to a data transfer module within the DSP chip used for automatic data transfer. It can complete data transfer without continuous processing core involvement based on pre-configured data source address, target address, and data length. For example, in image processing applications, image data generated by an external acquisition device is first stored in external memory. The DMA unit then transfers the image data to the shared memory area according to configuration parameters, enabling multiple processing cores to simultaneously read and process the image data in parallel. When the DMA unit performs data transfer, for example, when it needs to write data from external memory address 0x90000000 to shared memory address 0x80010000, the DMA controller generates a corresponding data access request. This request includes a DMA access identifier, write type, and target access address. The shared memory area refers to the data storage space in a multi-core DSP architecture that can be accessed by multiple processing cores or DMA units. Examples include shared SRAM and shared L2 cache within the DSP chip. The shared memory region is mapped to an external memory region. Taking shared SRAM as an example, the address range of the shared memory region is set to 0x80000000~0x803FFFFF. Data in this region can be accessed by Core0~Core7 and DMA units simultaneously. When the processing core or DMA unit needs to access data in the shared memory region, it sends an access request to the shared memory control module through the on-chip interconnect bus. The shared memory control module listens for request signals on the processing core interface and DMA interface in real time. After detecting the access request, it parses the data field of the access request and extracts the access address field from the access request. For example, when Core0 performs a data read operation, it generates an access request. This access request includes the request source as Core0, the access type as a read request, and the access address as 0x80001280. After receiving the request, the shared memory control module reads 0x80001280 from the request field as the access address information corresponding to the current access request, realizing the unified reception of processing core access requests and DMA access requests, and obtaining the access address information corresponding to the access request.After obtaining the access address information corresponding to the access request, the specific access location of the target data in the shared memory area is determined based on this access address information. Furthermore, the corresponding target cache line is located according to the cache line partitioning rules. Since cache management in DSP chips is not based on a single byte, but rather on cache lines as the basic unit for data loading, updating, and consistency maintenance, it is necessary to convert the access address generated by the processing core or DMA unit into the corresponding cache line location and determine whether the access address belongs to the shared memory area. For example, if the shared memory area is set to 0x80000000... When an access address of 0x80001280 is received, it is compared with the start address (0x80000000) and end address (0x803FFFFFF) of the shared memory region. Since 0x80001280 falls within this range, it is determined that the data corresponding to this access address is located within the shared memory region. The data access position is calculated based on the access address, i.e., the offset position of the target data relative to the start address of the shared memory region is determined. For example, if the start address of the shared memory region is 0x80000000 and the current access address is 0x80001280... If the address is 0x1280, then the offset of the access address relative to the starting address of the shared memory region is 0x1280. This determines that the target data is located 0x1280 bytes after the start of the shared memory region. Since data is managed at the cache line granularity, the target cache line is determined based on the preset cache line size. For example, if the DSP chip cache line size is set to 64 bytes, meaning every consecutive 64 bytes of data is managed as a single cache line, then for the access address 0x80001280, the cache line range for that address is determined to be 0x80001280~0x800012BF. This determines the data block corresponding to the range as the target cache line. If another processing core accesses the address 0x80001290, since this address is also within the range of 0x80001280 to 0x800012BF, it is determined that the two access requests correspond to the same target cache line. Therefore, it is not necessary to create separate cache maintenance objects. The access addresses from different processing cores or DMA units are mapped to the corresponding cache lines, so that the cache consistency maintenance process can be executed around the target cache line. This avoids repeated processing for a single data address and improves the data management efficiency of the shared memory cache maintenance process.After determining the target cache line, the cache line address information corresponding to the target cache line is obtained, and a cache line identifier that can uniquely identify the target cache line is generated based on this address information. This identifier is then used to record the status information corresponding to the target cache line through directory entries. Since cache lines are divided using a fixed length, the target cache line address information typically includes the cache line start address, cache line end address, and cache line length information. Address alignment is performed on the access address based on the access address and the cache line size to obtain the start address corresponding to the target cache line. For example, if the current access address is 0x80001290 and the preset cache line size is 64 bytes, since the cache line start address must be divided according to the 64-byte boundary, 0x80001290 is adjusted downwards to the nearest 64-byte boundary, resulting in the target cache line start address 0x80001280. Simultaneously, based on the cache line length of 64 bytes, the target cache line end address is determined to be 0x800012BF. This yields the complete cache line address information. Based on the target cache... The line address information determines the cache line identifier, which uniquely identifies a cache line in the shared storage area. It is numbered based on the starting address of the shared storage area and the cache line length. For example, if the starting address of the shared storage area is 0x80000000, the starting address of the target cache line is 0x80001280, and the cache line size is 64 bytes, then the address offset of the target cache line relative to the starting address of the shared storage area is 0x1280. This offset range corresponds to 74 cache lines, so the target cache line identifier is determined to be Cache_Line_ID = 74. By generating cache line identifiers, unified management can be achieved for data accesses from different addresses that belong to the same cache line. It also provides a unique index for directory entry queries. For example, when Core0 accesses 0x80001280 and Core1 accesses 0x80001290, although the two access addresses are different, their corresponding cache line identifiers are both 74. Therefore, it can be determined that the two access requests are acting on the same cache maintenance object.After obtaining the cache line identifier corresponding to the target cache line, a cache line index is generated according to the preset directory mapping rules to establish the correspondence between the target cache line and the directory entries. Since a multi-core DSP chip may contain a large number of cache lines, and the directory storage space used to store cache status information usually has a fixed capacity, an unlimited number of directory entries cannot be directly created for each cache line. Instead, the cache line index is used to map a large number of cache lines to a limited number of directory entries. The number of directory entries corresponding to the directory storage area is obtained. For example, the directory storage area is set to include 1024 directory entries, each used to store the status identifier, data version identifier, and cache processing core set information of the corresponding cache line. A cache line index is generated based on the target cache line identifier and the number of directory entries. For example, when the target cache line identifier is 74... Since the number of directory entries (1024) is greater than the cache line identifier (74), 74 is directly used as the cache line index, i.e., Cache_Index = 74 is generated. The 74th directory entry is accessed based on this cache line index. When the target cache line identifier is greater than the number of directory entries, for example, if the target cache line identifier is 2100, a corresponding cache line index is generated according to a preset mapping rule. For example, using a modulo mapping method, 2100 is mapped to the number of directory entries (1024), resulting in a remainder of 52. Therefore, cache line index 52 is generated, and the corresponding directory entry is accessed through this index. By generating cache line indexes, a fast mapping from the access request address and target cache line to the directory entry is achieved. It also enables the rapid retrieval of cache status information, data version information, and processing kernel information corresponding to the target cache line based on the cache line index.

[0025] In a preferred implementation, the corresponding directory entry is queried based on the cache line index to obtain the cache line status identifier, data version identifier, and processing core set corresponding to the target cache line from the directory entry. The corresponding protocol status identifier is configured according to the directory entry, wherein the protocol status identifier includes stable maintenance status, dynamic adjustment status, and access freeze status, including: S201. Based on the cache line index, query the directory entry corresponding to the target cache line, and obtain the cache line status identifier, data version identifier, and processing core set corresponding to the target cache line recorded in the directory entry; S202. Based on the processing core set, cache line status identifier and data version identifier corresponding to the target cache line, configure the corresponding protocol status identifier for the target cache line, and associate the protocol status identifier with the directory entry. S203. Set the protocol status identifier to the status identifier of the target cache line cache maintenance process, wherein the protocol status identifier includes stable maintenance status, dynamic adjustment status and access freeze status.

[0026] As described in steps S201 to S203 above, after generating the target cache line index, the directory storage area is accessed based on the cache line index to query the directory entry corresponding to the target cache line. The directory storage area is a dedicated storage area for storing cache line maintenance information. It can be set in the cache control module inside the DSP chip. For example, in an 8-core DSP architecture, an independent directory storage area is set up. The directory storage area includes 1024 directory entries. Each directory entry is used to record maintenance information corresponding to one or more target cache lines. The maintenance information includes a cache line status identifier, a data version identifier, and the processing core set of the target cache line. The cache line status identifier is used to indicate the current status of the target cache line. Data status, such as whether the target cache line is in exclusive, shared, or invalid state; data version identifier, used to indicate the current data version information of the target cache line, used to determine whether the data between different cache replicas is consistent; processing core set, used to record the processing core set in the current DSP architecture that caches a replica of the target cache line. For example, if the target cache line index is 74 obtained according to the aforementioned steps, cache line index 74 is used as the directory access address to access the directory entry numbered 74 in the directory storage area. During the query process, the cache line index signal is received, and then the cache line index is converted into a directory entry access address according to the directory entry address mapping rule. For example, the starting address of the directory storage area is set to... 0xA0000000, each directory entry occupies 32 bytes of storage space. Therefore, the storage location corresponding to directory entry number 74 is the 74th directory entry after the starting address of the directory region. That is, the corresponding address location is determined based on the number of 74 directory entries and the storage space size of a single directory entry. Then, the data content stored at that location is read to obtain the directory entry corresponding to the target cache line. After reading the directory entry, the fields in the directory entry are parsed. For example, the stored content of a directory entry includes a cache line status identifier field that is "shared state," a data version identifier field that is version number 15, and a processing core set field record that is Core0, Core2, or Core5. Here, "shared state" indicates that when... The data of the previous target cache line has been cached by multiple processing cores. Version number 15 indicates that the data version of the current target cache line is the version after the 15th update. Core0, Core2, and Core5 indicate that there are data copies of the target cache line inside the three processing cores Core0, Core2, and Core5. After reading the fields, the cache line status identifier, data version identifier, and processing core set are cached into the internal control registers respectively. This serves as the data basis for protocol status judgment and cache copy maintenance scope determination. It enables the cache maintenance module to quickly locate the corresponding directory entry based on the target cache line index and accurately obtain the current cache status, data version, and cache processing scope of the target cache line.After obtaining the processing core set, cache line status identifier, and data version identifier corresponding to the target cache line, and determining the current maintenance stage of the target cache line, a corresponding protocol status identifier is configured for the target cache line. The protocol status identifier indicates the maintenance state adopted by the target cache line during the current cache maintenance process. It does not simply represent the cache data state, but rather is used to control the status control information of cache replica adjustment, access processing, and directory update processes. During configuration, the number of processing core sets, cache line status identifier, and data version identifier changes corresponding to the target cache line are read, and the protocol status identifier is determined according to preset status judgment rules. For example, the protocol status is set to include stable maintenance state, dynamic adjustment state, and access freeze state. When the number of processing cores corresponding to the target cache line is small and the cache line status is stable, the protocol status flag is configured to stable maintenance state. When an increase in the number of accesses to the processing cores corresponding to the target cache line is detected, the access frequency changes significantly, or the data version continuously changes, the protocol status flag is configured to dynamic adjustment state. When a DMA unit is detected accessing the target cache line and changes to the directory information need to be avoided, the protocol status flag is configured to access frozen state. For example, if the directory entry records that the target cache line processing cores are Core0 and Core2, the cache line status flag is in shared state, and the data version flag remains version 15 for multiple consecutive access cycles, it indicates that the access status of the target cache line is stable, and therefore the protocol status flag is configured to... If the system is set to a stable maintenance state, and it detects that Core3 and Core4 frequently access the target cache line in historical access records, and the data version changes continuously from 15 to 16, 17, and 18, it indicates that the current cache access range has changed. The protocol status flag is then switched to a dynamic adjustment state. If the DMA unit performs data transfer operations on the target cache line, for example, if the DMA needs to read data from this cache line for external data transfer, the protocol status flag is configured to an access-frozen state to prevent changes in the processing core set and version information in the directory entry during DMA transfer. After determining the protocol status flag, it needs to be associated with the corresponding directory entry by adding a protocol status field to the directory entry, or by setting the protocol status flag to a dynamic adjustment state. The status identifier is stored in the status register bound to the directory entry. For example, the original directory entry includes a cache line status field, a data version field, and a processing core set field. After adding a protocol status field, the structure of the directory entry becomes a cache line status identifier field, a data version identifier field, a processing core set field, and a protocol status identifier field. The protocol status field records the current status, such as dynamically adjusting the status. When the directory entry is queried again through the cache line index, the protocol status information corresponding to the target cache line can be obtained at the same time. The protocol status identifier is associated with the directory entry, so that the data status information and maintenance control status information of the target cache line form a corresponding relationship. This allows the cache maintenance process to be dynamically controlled according to the actual access situation of the target cache line.After configuring the protocol status identifier, it is written to the status control field of the directory entry corresponding to the target cache line. This allows the protocol status identifier to be updated throughout the entire cache maintenance cycle of the target cache line. For example, when the protocol status field in the directory entry corresponding to the target cache line is set to stable maintenance, it indicates that the access behavior and cache replica distribution of the current target cache line are within a stable range. At this time, access requests are handled according to the normal directory maintenance method, and the cache processing core set is not actively adjusted. When the access of multiple processing cores corresponding to the target cache line changes frequently, the protocol status field is changed to dynamic adjustment, indicating that the current target cache line needs to readjust the cache replica maintenance range based on historical access data. For example, initially, the target cache line is only cached by Core0 and Core2, and the processing core set in the directory entry is recorded as Core0 and Core2. After multiple access cycles, it is found that Core5 and Core6 continuously access the target cache line, so the protocol status identifier is switched to dynamic adjustment, and the cache processing core set is re-determined based on the access history. When there is a DMA access request for the target cache line, the protocol status identifier is switched to access freeze state. The protocol status indicates that dynamic modification of the target cache line directory information is paused during DMA access. For example, during DMA data transfer, modification of the processing core set and data version identifier is prohibited to avoid conflicts between the processing core cache copy status and DMA access data. For instance, when the DMA unit is reading data corresponding to the target cache line, and Core1 simultaneously attempts to write to the same target cache line, the DMA access status is detected, the protocol status identifier is set to the access freeze state, and the processing core set and data version identifier in the current directory entry remain unchanged. Normal maintenance procedures are resumed after the DMA access is completed. By setting the protocol status identifier to the status identifier of the target cache line cache maintenance process, the target cache line has three different maintenance modes: stable maintenance state, dynamic adjustment state, and access freeze state. The stable maintenance state is used to handle regular access scenarios, the dynamic adjustment state is used to handle scenarios where the cache access range changes, and the access freeze state is used to handle special access scenarios such as DMA. This allows the cache maintenance process to select the corresponding processing method based on the actual access status of the target cache line, providing a status basis for adjusting the cache copy propagation range and maintaining cache consistency.

[0027] In a preferred embodiment, based on the access type corresponding to the access request, the cache line status identifier, and the data version identifier, a state transition process is performed on the protocol status identifier to switch the target cache line between a stable maintenance state, a dynamic adjustment state, and an access freeze state, including: S301. Obtain the access request corresponding to the target cache line, and obtain the access type in the access request; S302. Obtain the cache line status identifier and data version identifier in the directory entry corresponding to the target cache line, and obtain the current identifier status corresponding to the cache line status identifier and the current identifier status corresponding to the data version identifier. S303. Determine the protocol state switching conditions corresponding to the target cache line based on the access type, the current identifier state corresponding to the cache line status identifier, and the current identifier state corresponding to the data version identifier. S304. Perform state transition processing on the protocol state identifier according to the protocol state switching conditions, and adjust the cache maintenance state corresponding to the protocol state identifier so that the target cache line switches between stable maintenance state, dynamic adjustment state and access freeze state.

[0028] As described in steps S301 to S304 above, when the processing core or DMA unit initiates an access request to the shared memory region, the access request is transmitted to the cache maintenance control module via the on-chip interconnect bus. The cache maintenance control module is an extended functional module based on the cache control module. Located between the on-chip interconnect bus and the shared memory region, the cache maintenance control module performs cache line-oriented consistency maintenance control between the processing core cache layer and the shared memory region. It receives access requests from the processing core and DMA unit for the shared memory region and performs directory lookup, cache state maintenance, cache replica consistency control, and protocol state switching operations based on the cache line information corresponding to the access request. The cache maintenance control module listens to the processing core access interface. The system retrieves access requests generated within the current period via the DMA access interface. Each access request includes a request source field, an access address field, an access type field, and an access control field. The request source field indicates which access subject generated the current access request, such as Core0, Core1, or the DMA unit. The access address field indicates the location of the data being accessed. The access type field indicates the specific type of the current access behavior, such as a read request, write request, or DMA access request. Based on the cache line index, the system determines the target cache line to be processed and reads access requests matching the address of that target cache line from the access request cache queue. For example, the current target cache line corresponds to a cache address range of 0x800012. From 80 to 0x800012BF, the cache maintenance control module monitors the access request queue in real time. When it detects a request sent by Core2 with an access address of 0x80001290, since this access address is within the target cache line range, it determines that the access request corresponds to the target cache line. The cache maintenance control module reads the access type field in the access request. For example, if the access request field content is "Source: Core2; Access Type: Write Request; Access Address: 0x80001290", it extracts the access type information and determines that the current access type is a write request. If the access request field content is "Source: DMA; Access Type: DMA Read Request; Access Address: 0x80001290", it will not retrieve the request. If the current access type is determined to be a DMA access request, the cache maintenance control module can accurately obtain the corresponding access behavior for the target cache line and identify the current access type. This allows the protocol state transition process to select different state switching strategies based on different access scenarios. For example, normal processing core read / write access may trigger a switch between a stable maintenance state and a dynamic adjustment state, while DMA access may trigger an access freeze state. After determining the access type corresponding to the target cache line, the cache maintenance control module reads the cache line status identifier and data version identifier from the directory entry corresponding to the target cache line to obtain the current data maintenance status and version changes of the target cache line. The directory entry is the cache maintenance information storage unit corresponding to the target cache line.It locates cache lines using cache line indexes. Each directory entry stores the status information of the corresponding cache line. It accesses the directory storage area based on the cache line index corresponding to the target cache line. For example, if the current cache line index is 74, it accesses the 74th directory entry in the directory storage area and reads the cache line status field and data version field from that directory entry. For instance, the 74th directory entry stores the following: cache line status identifier = shared state, data version identifier = version number 15, processing core set {Core0, Core2, Core5}. After reading this directory entry, it extracts the cache line status identifier field to obtain the current cache line status as shared state, and simultaneously reads the data version identifier field to obtain the current data version as 15. Further... The parsing process determines the current status of the corresponding identifier. For cache line status identifiers, the current status indicates the current cache state of the target cache line. For example, a shared state means multiple processing cores may simultaneously hold a copy of the cache line; an exclusive state means only one processing core has a valid copy; and an invalid state means the current cache copy is unavailable. For data version identifiers, the current status indicates the current data version number of the target cache line. For example, version number 15 means the target cache line data has undergone 15 valid updates. When an access request occurs, by comparing the current data version identifier with the version identifier in the local cache copy, it can be determined whether the cache copy is the latest version. For example, the data version identifier in the directory entry is 15, while the version identifier in the Core 3 local cache copy is 15. If the cache replica record version identifier is 14, it indicates that the cached data in Core 3 is lagging behind the target cache line data in the shared storage area, requiring cache update processing. The system can obtain the current cache state and data version state of the target cache line. Based on the access type information, cache line status identifier, and data version identifier, it comprehensively determines whether the target cache line needs to undergo a protocol state transition and identifies the corresponding protocol state transition conditions. These conditions describe the triggering conditions for the target cache line to switch from its current maintenance state to another maintenance state under different access scenarios. They are determined jointly based on the access subject's behavior, cache state changes, and data version changes. When the access type is a normal read or write request, further consideration is given. The cache line status flag determines whether the current cache state is stable. When the access type is a DMA access request, the priority is to determine whether to enter an access freeze state. For example, the following status judgment process can be set: If the target cache line's current cache line status flag is in a shared state, the data version flag remains unchanged for multiple consecutive access cycles, and all access requests come from a fixed processing core, then the target cache line meets the stable maintenance conditions and is maintained or switched to a stable maintenance state. If the target cache line's current processing core set changes, for example, if the original processing core set was Core0 and Core2, and Core5 and Core6 accesses are added during consecutive access cycles, and the data version flag changes from 15 to 16 and 17, then it indicates that the target cache line's access range has changed.If the access request type is a DMA access request (e.g., the DMA unit is performing a target cache line data transfer task), then the normal cache access rules are no longer applied; instead, the access freeze state switching conditions are directly determined to be met. For example, if the current protocol state is stable maintenance, the target cache line directory entry record cache line state is shared, and the data version is 15, and Core1 generates a write request, since the current access subject is the processing core and the data version has only changed once, it is determined that this access will not cause a significant change in the cache maintenance scope, so the stable maintenance state continues. However, if it is detected that four different processing cores access the target cache line within five consecutive access cycles, and the data version... If the changes occur more than three times consecutively, the current access behavior is determined to have deviated from a stable state, meeting the conditions for dynamic state adjustment. By comprehensively judging based on access type, cache state, and version state, protocol state transitions are no longer triggered by a single factor but are dynamically determined based on the actual access behavior of the target cache line, improving the accuracy of protocol state transitions. After determining the protocol state transition conditions, an update operation is performed on the protocol state identifier in the directory entry based on the currently met conditions, thereby adjusting the current cache maintenance state of the target cache line. The protocol state identifier, as a state control field in the cache maintenance process of the target cache line, is stored in the corresponding directory entry of the target cache line and is used to indicate which dimension the current target cache line adopts. The cache maintenance strategy involves the cache state control module reading the current protocol state identifier and modifying the corresponding state field according to the state transition rules when the protocol state transition conditions are met. For example, if the current protocol state identifier is "stable maintenance," and an increase in the number of accesses to the processing core corresponding to the target cache line, an expansion of the historical access range, or continuous changes in data versions are detected, the protocol state field in the directory entry is changed from "stable maintenance" to "dynamic adjustment." After the state modification is completed, the cache maintenance process enters the dynamic adjustment process, redetermining the cache processing core set based on the new access situation. When the target cache line is in the dynamic adjustment state, if the access requests return to stability—for example, if the access processing core set remains unchanged for multiple consecutive access cycles and the data version change frequency decreases—the cache... The cache maintenance control module re-checks the stable maintenance conditions and restores the protocol status field from the dynamically adjusted state to the stable maintenance state. When the DMA unit accesses the target cache line, for example, when the DMA needs to continuously read data from the target cache line for data transfer, to avoid inconsistencies in cache copy information caused by changes in directory entries during the DMA access process, the cache maintenance control module modifies the protocol status field to the access frozen state. In this state, updates to the processing core set and data version identifier are suspended. After the DMA transfer is completed, the cache maintenance control module unfreezes the conditions and resets the protocol status according to the current access situation. For example, if there are no new changes in processing core access after the DMA access ends, the cache status is restored from the access frozen state to the stable maintenance state.If a large number of processing core access changes are detected during DMA access, the cache line transitions from an access-frozen state to a dynamic adjustment state. This allows the target cache line to dynamically switch between stable maintenance, dynamic adjustment, and access-frozen states based on different access scenarios, achieving stateful management of the cache maintenance process.

[0029] In a preferred embodiment, when the protocol status identifier indicates that the target cache line is in a dynamic adjustment state, a cache processing core set is generated based on the processing core set corresponding to the target cache line, the historical access sequence, and the data version identifier. A cache replica propagation set is then established based on the cache processing core set, including: S401. When the protocol status flag indicates that the target cache line is in a dynamic adjustment state, read the directory entry corresponding to the target cache line and obtain the processing core set corresponding to the target cache line recorded in the directory entry. S402. Obtain the historical access sequence corresponding to the target cache line and read the data version identifier in the directory entry; S403. Generate a cache processing core set based on the processing core set corresponding to the target cache line, the historical access sequence, and the data version identifier; S404. Determine the processing cores that participate in the maintenance of cache replicas of the target cache line based on the cache processing core set, and form a cache replica propagation set based on the processing cores that participate in the maintenance of cache replicas.

[0030] As described in steps S401 to S404 above, when the cache maintenance control module detects that the protocol status identifier corresponding to the target cache line is in a dynamic adjustment state, it indicates that the access range, cache replica distribution, or data update status of the current target cache line has changed. Therefore, it is necessary to redetermine the range of processing cores participating in subsequent cache maintenance. This requires reading the directory entry corresponding to the target cache line and obtaining the current processing core set recorded in the directory entry. The target cache line has already generated a corresponding cache line index based on the access address. The target directory entry in the directory storage area is located based on this cache line index. For example, if the cache line index corresponding to the current target cache line is 74, and the directory storage area includes 1024 directory entries, then the directory entry is accessed based on index number 74. The 74th directory entry in the storage area sends its cache line index to the directory access control unit. The directory access control unit converts the cache line index into a directory entry storage address based on a preset directory mapping relationship. For example, if the starting address of the directory storage area is 0xA0000000 and each directory entry occupies 32 bytes of storage space, then the storage address of the 74th directory entry is the offset position of 74 entries after the directory starting address. That is, the corresponding storage location is determined by the directory number and the storage space size of a single directory entry. Subsequently, the complete directory entry data is read from this storage location. The read directory entry includes a cache line status identifier field, a data version identifier field, a processing core set field, and a protocol status identifier field. The processing core set field... This section records the processing core information of the currently cached target cache line copy. For example, after reading the 74th directory entry, the cache line status is identified as shared, the data version as version number 15, the protocol status as dynamically adjusted, and the processing core set field is recorded as Core0, Core2, and Core5. The directory entry is parsed to extract the data content of the processing core set field, obtaining the processing core set of the current cached target cache line, i.e., Core0, Core2, and Core5. This processing core set is stored in the internal adjustment register as initial reference data for adjusting the processing core range. For example, in an 8-core DSP architecture, the processing core number range is Core0 to Core7. The directory entries only record Core0, Core2, and Core5, indicating that only three processing cores currently contain a copy of the target cache line. After the target cache line enters a dynamic adjustment state, the processing core set recorded in the current directory is retrieved. This allows cache range adjustments to be based on the existing cache copy distribution, rather than rescanning all processing cores, improving the targeting of the cache maintenance process. After obtaining the current processing core set of the target cache line, the historical access sequence corresponding to the target cache line is obtained, and the data version identifier in the directory entries is read to analyze the access changes and current data update status of the target cache line over a period of time. The historical access sequence records the access behavior information generated by the target cache line within a continuous access cycle.It can be stored in the access record cache area inside the cache maintenance and control module. The historical access record area is queried based on the target cache line identifier. This historical access record area is indexed and stored according to the cache line identifier. Each record unit corresponds to an access record of a target cache line. For example, if the target cache line identifier is Cache_Line_ID = 74, then the cache maintenance and control module accesses record unit numbered 74 in the historical access record area and reads the access records for the most recent multiple access cycles of that cache line. The historical access sequence includes information such as access time, access source processing core, access type, and number of accesses. For example, the historical access record stores the information for the most recent 5 accesses: 1st access: Core0, read request; 2nd access: Core0, read request; 3rd access: Core0, read request; 4th access: Core0, read request; 5th access: Core0, read request; 6th access: Core0, read request; 7th access: Core0, read request; 8th access: Core0, read request; 9th access: Core0, read request; 10th access: Core0, read request; 1st ... The first access: Core2, read request; the third access: Core5, write request; the fourth access: Core5, read request; the fifth access: Core6, read request. Based on the access records, the target cache line was recently accessed mainly by Core0, Core2, Core5, and Core6, with Core5 being accessed more frequently. Core6 is a newly added access processing core. The data version identifier in the directory entry corresponding to the target cache line is read again. Based on the directory entry address, the data version field in the directory entry is accessed, and the current data version information is extracted. For example, if the data version field in the 74th directory entry records version number 15, then the target cache line data version in the current shared storage area is determined. The original value is 15. If the data version changes from 12 to 13, 14, or 15 during historical access, it indicates that the target cache line has undergone multiple data updates recently. If the data version remains at 15 for a long period, it indicates that the target cache line data is in a stable state. By simultaneously acquiring the historical access sequence and the current data version identifier, we can obtain the historical access situation and current data change status of the target cache line, providing data basis for determining which processing cores should continue to retain cache copies and which processing cores need to be added or removed. Statistical processing of the historical access sequence determines the access characteristics of different processing cores to the target cache line. Access characteristics include the number of times the processing core accesses, the most recent access time, and the distribution of access types. For example, based on the historical access sequence, the package... This includes Core0 (accessed 1 time), Core2 (accessed 1 time), Core5 (accessed 2 times), and Core6 (accessed 1 time). Simultaneously, by combining the processing core set {Core0, Core2, Core5} in the current directory entry, the access activity of the existing processing cores is determined, and newly added access processing cores are identified. For example, Core5 performed 2 accesses in the most recent access cycle, including one write request, indicating that Core5 has a high access demand for the target cache line, so it is retained. Although Core0 and Core2 have fewer accesses, they already cache a copy of the target cache line, so they are temporarily retained. Although Core6 is not currently recorded in the directory entry processing core set, it continuously accesses the target cache line.Therefore, as a new processing core added to the candidate set, the processing core adjustment needs are determined based on changes in the data version identifier. For example, if the current data version identifier changes from 12 to 15, it indicates that the target cache line has been updated multiple times. In this case, processing cores that frequently access the cache line should be prioritized to reduce the cache synchronization range. A set of filtered processing cores is generated according to preset filtering rules. For example, if the access count threshold is set to 2 times, a processing core is added to the cache processing core set when its recent access count reaches 2 times or more. If a processing core has not accessed the target cache line for 5 consecutive access cycles, it is removed from the cache processing core set. According to these rules, Core5 has 2 access counts, meeting the retention conditions. Although Core6 is not currently in the original processing core set, it has access counts of 2 times. If an object is accessed once consecutively, it is added according to the dynamic adjustment rules. Core0 and Core2 are retained because they already have cache copies and there are no conflicting accesses. A new cache processing core set {Core0, Core2, Core5, Core6} is ultimately generated. The cache processing core set no longer uses the initial directory record but dynamically changes according to the actual access behavior of the target cache line, ensuring that the cache maintenance scope matches the current data access characteristics. The cache processing core set represents the range of processing cores currently considered necessary to participate in the cache maintenance of the target cache line. The cache copy propagation set represents the processing core set that needs to receive control information when performing cache update, invalidation notification, or state adjustment operations. The generated cache processing core set is then read. For example, the cache processing core set {Core0, Core2, Core5, Core6} determines the specific range of processing cores involved in maintenance based on the current access request type. For instance, when the current access request is a write request, invalidation control information needs to be sent to processing cores that may hold old cache copies; therefore, all processing cores in the cache processing core set are included in the maintenance. When the current access request is a read request, the range of processing cores that need version verification is primarily determined. For example, if the current target cache behavior is a write access scenario, the read cache processing core set {Core0, Core2, Core5, Core6} is used, and then a cache copy propagation set {Core0, Core2, Core5, Core6} is established. The propagation scope can be further adjusted based on the protocol status flag. For example, when the protocol status flag is still in a dynamic adjustment state, to avoid sending maintenance information to all processing cores at once, the scope can be filtered based on the source of the current access request. If the current write request comes from Core 5, then Core 0, Core 2, and Core 6 (excluding Core 5) will be prioritized as cache replica propagation targets for old replica invalidation processing. If the current DMA access targets a cache line, no actual propagation operation will be performed temporarily, and the current cache replica propagation set state will be maintained until the DMA access freeze state is lifted before maintenance is performed. Therefore, the cache replica propagation set is actually a maintenance scope jointly determined by the cache processing core set, access type, and protocol status.By forming a cache replica propagation set, the cache maintenance control module can clearly identify which processing cores need to participate in cache replica synchronization, invalidation, or update operations. This avoids the traditional broadcast method of sending maintenance information to all processing cores, improving the targeting and resource utilization efficiency of the cache maintenance process in multi-core DSP architectures.

[0031] In a preferred embodiment, a cache processing core set is generated based on the processing core set corresponding to the target cache line, the historical access sequence, and the data version identifier, including: S40301. Obtain the access request record corresponding to the target cache line in the historical access sequence, and determine the access count and access order of the target cache line corresponding to each processing core based on the access request record; S40302. Based on the number of accesses and the access order corresponding to each processing core, determine the access characteristics of the processing core corresponding to the target cache line, and combine the processing core set and data version identifier corresponding to the target cache line to determine the processing core set adjustment conditions. S40303. Based on the processing core set adjustment conditions, perform filtering processing on the processing cores in the processing core set corresponding to the target cache line to determine the filtering processing core set, wherein the filtering processing core set includes retained processing cores, added processing cores, and removed processing cores. S40304. Update the processing core set corresponding to the target cache line according to the filtered processing core set to generate a cache processing core set.

[0032] As described in steps S40301 to S40304 above, after the protocol status identifier corresponding to the target cache line enters the dynamic adjustment state, the cache maintenance control module needs to re-evaluate the scope of processing cores currently involved in cache maintenance based on the access behavior of the target cache line over a period of time. Therefore, it first extracts the access request record corresponding to the target cache line from the historical access sequence. In a multi-core DSP architecture, when the cache maintenance control module processes each request from a processing core or DMA unit to access the shared storage area, it synchronously records the cache line identifier, access source, access type, and access time corresponding to the access request, and stores them in association with the target cache line to form a historical access sequence. When it is necessary to perform dynamic adjustment on the target cache line... When the target cache line is selected, the historical access record storage area is accessed based on the cache line identifier corresponding to the target cache line. Access request records with cache line identifiers matching the target cache line are then selected from all historical access records. For example, if the current target cache line is cache line identifier 74, the historical access record storage area stores the following access records: Record 1 is cache line 74, access source Core0, access type read request; Record 2 is cache line 52, access source Core3, access type write request; Record 3 is cache line 74, access source Core2, access type read request; Record 4 is cache line 74, access source Core5, access type write request; Record 5 is cache line 74, access source Core5, access type read request; Record 6 is... The cache line is set to 74, the access source is Core6, and the access type is a read request. The cache line identifier field in the history is read, and records with a cache line identifier equal to 74 are filtered out, resulting in records 1, 3, 4, 5, and 6. These are used as the access request records corresponding to the target cache line. The source processing cores of these filtered access request records are categorized and statistically analyzed. The corresponding processing core is determined based on the access source field in each access record, and the number of times each processing core appears is accumulated. For example, in the access records, Core0 appears once, Core2 appears once, Core5 appears twice, and Core6 appears once. Therefore, the access count for the target cache line corresponding to Core0 is determined to be 1, and the access count for Core2 is determined to be 1. Core 5 was accessed twice, and Core 6 was accessed once. Furthermore, the access records were sorted according to the access time field to determine the order in which different processing cores accessed the target cache line. For example, after sorting by access time from earliest to latest, Core 0 accessed the target cache line first, followed by Core 2, then Core 5 accessed it twice consecutively, and finally Core 6 accessed it. This formed the processing core access order corresponding to the target cache line, allowing us to obtain the historical access distribution of the target cache line, clarifying which processing cores frequently accessed the target cache line and which were occasional accesses, thus providing a true basis for adjusting the processing core set.To avoid fixed maintenance based solely on the current cache replica distribution, this approach analyzes the access behavior of different processing cores to the target cache line based on the access frequency and order of each processing core. This generates processing core access characteristics that reflect the activity level of the processing cores. Furthermore, by combining this with changes in the processing core set corresponding to the current target cache line and the data version identifier, it determines whether the current processing core set needs adjustment. The processing core access characteristics describe the access association between each processing core and the target cache line, primarily obtained from historical access records. These characteristics include processing core access frequency characteristics, consecutive access characteristics, and data update association characteristics. The processing core access frequency characteristics are determined based on the number of times a processing core appears within a preset historical access range, such as in cache maintenance control. The module reads the last 5 access records of the target cache line. Core5 appears twice, while Core0, Core2, and Core6 each appear once. This indicates that Core5 has a higher access frequency than the other processing cores. Continuous access is determined by whether the same processing core appears consecutively in adjacent access records. For example, if Core5 continuously executes write and read requests, it indicates a continuous access relationship between Core5 and the target cache line. Data update association is determined by changes in the data version identifier during the access process. For example, if the target cache line data version changes from 12 to 13, then from 13 to 14, and finally to 15, and all corresponding changes are initiated by Core5, it indicates that Core5 participates in the target cache line data maintenance process. Based on access characteristics, further adjustments are made in conjunction with the processing core set in the current directory entry. For example, if the current target cache line corresponds to the processing core set {Core0, Core2, Core5}, and the current data version identifier is 15, historical access results show that Core5 has the highest access frequency and has caused data version changes. Although Core6 does not belong to the current processing core set, it has recently been accessed. Therefore, it is determined that Core5 needs to be retained, Core6 meets the conditions for addition, and Core0 and Core2 need to be further judged based on access information. Pre-set processing core set adjustment conditions, including retention conditions, addition conditions, and removal conditions. Among them, the retention condition is used to determine whether a processing core that already exists in the processing core set should continue to be used. Processing cores are included in cache maintenance if they are accessed more than once recently or if they participate in data version changes. Retention is granted if a core is not currently in the core set. Addition criteria determine whether a core should be added to cache maintenance if it accesses the target cache line at least once in its last five accesses. Removal criteria determine whether a core should be removed from cache maintenance if it hasn't accessed the target cache line for five consecutive access cycles. The core set adjustment criteria are determined by historical access behavior, current cache distribution, and data version changes, ensuring that changes to the core set match the actual access patterns of the target cache line. The core set corresponding to the current target cache line is read from the directory entry.For example, if the current processing core set is recorded as {Core0, Core2, Core5}, this processing core set represents the processing cores that currently cache a copy of the target cache line or participate in the maintenance of the target cache line. The access characteristics corresponding to each processing core in the current processing core set are obtained one by one and matched with the processing core set adjustment conditions. For example, if Core5 appears twice in the historical access sequence, including one write request, and causes a change in the target cache line data version, it meets the retention condition and is assigned to the retained processing core set. Although Core0 has fewer accesses, it still holds a cache copy, so it continues to be retained according to the cache copy continuity rule and is assigned to the retained processing core set. If Core2... If no new access records have been found in recent access cycles, it is determined whether the core meets the removal criteria. If it does, it is assigned to the removal processing core set. The process continues to iterate through processing cores that appeared in the historical access sequence but were not recorded in the current processing core set. For example, although Core6 does not exist in the current processing core set {Core0, Core2, Core5}, there is a record of Core6 accessing the target cache line in the historical access sequence, and the access time is relatively recent. Therefore, Core6 meets the addition criteria and is assigned to the addition processing core set. After filtering, for example, the following filtered processing core sets are obtained: the retained processing core set is {Core0, Core5}, the addition processing core set is {Core6}, and the removal processing core set is... {Core2}, where reserved processing cores represent processing cores that continue to maintain the cache replica relationship of the target cache line, newly added processing cores represent processing cores that need to be added to the cache replica maintenance scope, and removed processing cores represent processing cores that need to be removed from the current cache maintenance scope. By dividing the processing core adjustment process into three categories of processing objects, the cache processing core set adjustment process has a clear update direction, avoiding a large number of invalid cache migration operations caused by replacing the entire processing core set. The processing core set corresponding to the current target cache line is obtained. For example, if the directory entry records the current processing core set as {Core0, Core2, Core5}, the corresponding update operations are performed according to the reserved, newly added, and removed processing cores in the filtered processing core set. For reserved processing cores... The processing cores in the core set maintain their original state; for example, Core0 and Core5 are retained and therefore not deleted. For cores newly added to the core set, they are added to the original core set; for example, Core6 is added to the original core set, making Core6 eligible for target cache line cache maintenance. For cores removed from the core set, they are deleted from the original core set; for example, Core2 is removed from the core set. After the update, the original core set {Core0, Core2, Core5} is transformed into a new cache processing core set {Core0, Core5, Core6}. The generated cache processing core set is written to the processing core set field of the corresponding directory entry in the target cache line.Simultaneously update the internal records of the cache maintenance control module to ensure that the range of processing cores in the directory entries is consistent with the current cache replica distribution. The cache processing core set can be adjusted as the access behavior of the target cache line changes. When a new processing core continuously accesses the target cache line, it can be added to the maintenance range in a timely manner, and when an existing processing core no longer accesses the target cache line for a long time, it can be removed from the maintenance range, thus forming a cache maintenance range that matches the actual access pattern.

[0033] In a preferred embodiment, based on the cache replica propagation set and the access type corresponding to the access request, the cache replica maintenance object is determined, and the processing core range corresponding to the cache replica maintenance object is adjusted according to the protocol status identifier to generate a target maintenance core set, including: S501. Determine the cache copy processing method corresponding to the access request based on the cache copy propagation set and the access type corresponding to the access request; S502. Based on the cache replica propagation set and cache replica processing method, determine the cache replica to be maintained corresponding to the target cache line, and obtain the processing core set corresponding to the cache replica to be maintained; S503. Determine the current cache maintenance status based on the protocol status identifier, and adjust the range of the processing core set corresponding to the cache copy to be maintained based on the current cache maintenance status, and select the processing cores to participate in the cache copy maintenance. S504. Generate the target maintenance kernel set based on the filtered processing kernels.

[0034] As described in steps S501 to S504 above, after obtaining the cache replica propagation set corresponding to the target cache line, the cache maintenance control module needs to determine the specific processing method for the cache replicas based on the access type of the current access request. This clarifies which cache replicas need to be maintained subsequently. The cache replica propagation set represents the set of processing cores currently participating in the maintenance of the target cache line's cache replicas. It is dynamically generated based on the target cache line's historical access history, data version changes, and processing core access characteristics. For example, if the cache replica propagation set corresponding to the current target cache line is {Core0, Core5, Core6}, it means that the three processing cores Core0, Core5, and Core6 may currently cache the target cache line. The cache maintenance control module retrieves the access type field from the current access request. This access type field is generated by the request initiator and transmitted along with the access request. For example, when processing core Core1 in a multi-core DSP architecture sends a write request to the shared memory area, the access request carries a write request identifier. When processing core Core3 reads the target data from the shared memory area, the access request carries a read request identifier. When the DMA unit performs peripheral data transfer, the access request carries a DMA access request identifier. The cache copy processing method is determined based on the access type and the distribution of the cache copy propagation centralized processing cores. For example, when the access type is a write request, because the write... The operation will change the data content corresponding to the target cache line. To ensure the validity of the cache replicas in other processing cores, a replica invalidation maintenance method is required. This involves sending replica invalidation control information to other processing cores in the cache replica propagation set, invalidating the old version of the cache replica. For example, if the current cache replica propagation set is {Core0, Core5, Core6}, and Core1 needs to write data to the target cache line, the cache maintenance control module determines that Core0, Core5, and Core6 need to perform cache replica status updates. When the access type is a read request, since the read operation does not change the data content in the shared storage area, a replica version verification maintenance method is used. This involves comparing the data version identifier of the local cache replica with... The target cache line data version identifier in the directory entry is used to determine whether the cache copy needs to be updated. For example, if the data version identifier in the directory entry is 15, but the data version identifier recorded in the Core2 local cache copy is 14, then the Core2 cache copy version is considered too old, and the target cache line data needs to be reloaded. When the access type is a DMA access request, since the DMA unit may directly access the shared storage area and bypass some processing core cache access processes, an access freeze maintenance method is adopted. That is, changes to the directory entry and cache processing core set are temporarily restricted to avoid changes in the cache copy status during DMA transfer. By dynamically determining the cache copy processing method based on the access type, different types of access requests can be matched with corresponding cache maintenance strategies.To avoid invalid cache synchronization caused by using a uniform maintenance method for all accesses and improve the efficiency of shared storage access in multi-core DSP architectures, the cache replica propagation set is filtered according to the cache replica handling method to determine the cache replicas to be maintained corresponding to the target cache line. Furthermore, the set of processing cores holding these cache replicas is obtained. The cache replica propagation set only represents the range of all processing cores currently participating in the maintenance of the target cache line, but the maintenance objects differ for different access types. Therefore, it is necessary to further determine the actual maintenance scope based on the cache replica handling method. For example, the cache replica propagation set corresponding to the current target cache line is {Core0, Core5, Core6}, where Core0 and Core5 store... The target cache line cache copy is recorded on Core6, which only records the access relationship of the target cache line but does not currently save a valid cache copy. When the access request is a write request, the cache maintenance control module reads the cache copy status record area according to the copy invalidation maintenance method to obtain the cache copy status information corresponding to each processing core in the cache copy propagation set. For example, if Core0 and Core5 are both valid cache copies, and Core6 is idle, then the cache copies corresponding to Core0 and Core5 are determined as cache copies to be maintained, while Core6 is not directly maintained. When the access request is a read request, the local cache copy corresponding to the processing core that initiated the read request is determined according to the copy version verification maintenance method. The main maintenance object is the cache copy, and the corresponding processing core set is obtained from the directory entries for version comparison. For example, when Core2 requests to read the target cache line, the local cache copy information of Core2 is obtained, and the data version identifiers of existing cache copies of Core0 and Core5 are read to determine whether the latest version of the data exists. When the access request is a DMA access request, the processing core set corresponding to all cache copies involving the target cache line access is obtained according to the access freeze maintenance method. For example, {Core0, Core5, Core6} is obtained as the range of processing cores to be monitored during the freeze period. The cache maintenance control module reads the processing core set field in the directory entries and filters the cache copies according to their status identifiers. The processing cores should be selected. For example, if the target cache line processing core set for a directory entry record is {Core0, Core2, Core5}, where Core0 and Core5 correspond to valid cache replica states and Core2 corresponds to an invalid state, then the processing cores {Core0, Core5} corresponding to the valid cache replicas are obtained as the cache replica processing core set to be maintained. This allows for precise determination of the cache replicas that need maintenance based on the actual access type, reducing the participation of irrelevant processing cores in cache maintenance operations and lowering cache consistency control overhead. The cache maintenance control module further combines the protocol status identifier corresponding to the target cache line to dynamically adjust the processing core set corresponding to the cache replicas to be maintained, ensuring that the final range of processing cores participating in cache maintenance matches the current cache maintenance state.The protocol status identifier indicates the current cache maintenance status of the target cache line, including stable maintenance, dynamic adjustment, and access freeze. The protocol status identifier field associated with the target cache line is read from the directory entry, and the current cache maintenance status is determined based on the field content. For example, when the protocol status identifier is stable, it indicates that the target cache line's access pattern is stable and the current processing core set has changed little. In this case, there is no need to expand the maintenance scope; therefore, the processing core set corresponding to the cache copy to be maintained is retained. For example, if the processing core set of the cache copy to be maintained is {Core0, Core5}, then Core0 and Core5 are directly retained as participating processing cores in the maintenance. When the protocol status identifier is dynamic adjustment, it indicates that the target cache line is in a stable maintenance state. When access conflicts increase or the distribution of processing core accesses changes, the maintenance scope needs to be adjusted based on the current access situation. In this case, the cache maintenance control module reads the cache processing core set and expands or shrinks the processing core set corresponding to the cache copy to be maintained. For example, the original processing core set to be maintained was {Core0, Core5}, but during dynamic adjustment, it is found that Core6 accessed the target cache line three times consecutively, and all data version changes were triggered by Core6. Therefore, Core6 is added to the maintenance scope, forming {Core0, Core5, Core6}. If Core0 does not access the target cache line for several consecutive access cycles, Core0 is removed from the maintenance scope. When the protocol status is marked as "access frozen," it indicates that the current cache is frozen. During DMA access, it is necessary to ensure the stability of directory entries and cache copy states. Therefore, changes in the range of processing cores are restricted, and only the processing cores corresponding to the currently valid cache copies are retained. For example, if the set of processing cores to be maintained is {Core0, Core5, Core6}, only the processing cores with existing valid copies {Core0, Core5} are allowed to participate in maintenance during DMA access. The cache maintenance control module performs status checks on each processing core in the set of processing cores to be maintained according to the processing rules corresponding to the protocol status identifier. This includes determining whether the processing core has a valid cache copy, whether it is in an active access state, and whether it meets the current maintenance status requirements. This allows the cache maintenance scope to be adjusted according to changes in the access status of the target cache line, while ensuring... To ensure cache consistency while reducing unnecessary cache maintenance communication, the cache maintenance control module obtains a filtered list of processing cores. This list contains processing cores that meet the current protocol state requirements and need to participate in the maintenance of the target cache line. For example, in a dynamically adjusted state, the filtered processing cores obtained through access behavior analysis include Core0, Core5, and Core6. Core0 and Core5 are processing cores held by existing cache copies, while Core6 is a newly added access processing core. The cache maintenance control module then organizes the processing cores according to cache maintenance priority, generating a target maintenance core set {Core0, Core5, Core6}. Each processing core in the target maintenance core set corresponds to a maintenance object identifier.For example, Core0 corresponds to the first cache copy, Core5 corresponds to the second cache copy, and Core6 corresponds to the newly added maintenance object. The cache maintenance control module associates the generated target maintenance core set with the current target cache line, enabling it to directly determine the processing core that needs to send control information when performing cache copy maintenance operations. For instance, when the access request is a write request, cache copy status update control information is sent to Core0, Core5, and Core6 based on the target maintenance core set; when the access request is a read request, the corresponding data version identifier is obtained from the target maintenance core set for verification. By generating the target maintenance core set, the cache maintenance process is transformed from a fixed processing core broadcast method to a method that dynamically determines the maintenance object based on access behavior and protocol status. This reduces invalid communication during multi-core DSP shared memory access, improves cache maintenance efficiency, and enhances the adaptive capability of cache consistency control.

[0035] In a preferred embodiment, based on the target maintenance kernel set and the access type corresponding to the access request, a cache copy maintenance operation is performed on the target cache line, including: S601. Determine the cache copy maintenance method corresponding to the target cache line based on the access type; S602. Read the data version identifier and protocol status identifier corresponding to the target cache line based on the cache copy maintenance method; When the access type is a write request, the data version corresponding to the target cache line is updated according to the data version identifier, an updated data version identifier is generated, and the corresponding cache copy is determined according to the target maintenance kernel set, and a status update operation is performed on the cache copy. When the access type is a read request, the data version identifier corresponding to the local cache copy is checked against the data version identifier corresponding to the target cache line. If the check result does not match, the data corresponding to the target cache line is retrieved from the shared storage area to update the local cache copy. When the access type is a DMA access request, the protocol status flag is switched to the access freeze state according to the data access process corresponding to the DMA access request, and the update operations of directory entries and cache processing cores are restricted based on the access freeze state.

[0036] As described in steps S601 to S602 above, after obtaining the target maintenance core set, it is necessary to determine the cache copy maintenance method corresponding to the target cache line based on the access type corresponding to the current access request, thereby determining the data consistency maintenance process to be executed for the cache copy. The access request is initiated by the processing core or DMA unit in the multi-core DSP architecture, and carries an access type identifier during the access request generation stage. This access type identifier is used to indicate whether the current access behavior is a data read, data write, or DMA data transfer operation. The access type field in the access request is read, and the preset cache copy maintenance rules are matched according to the access type field. For example, in a multi-core DSP chip, processing core Core1 needs to modify address 0x8 in the shared memory area. When the data corresponding to 0001000 is accessed, an access request containing a write request identifier is generated. The access type field in the access request is read, and if the current access type is determined to be a write request, the cache replica invalidation maintenance method is selected. If the processing core Core2 only needs to read the data at this address, the access request carries a read request identifier, and the cache maintenance control module determines to use the cache replica version verification maintenance method. If the external acquisition device continuously writes sampling data to the shared storage area through the DMA unit, the access request carries a DMA access request identifier, and the cache maintenance control module determines to use the cache access freeze maintenance method. Among these, the cache replica invalidation maintenance method is mainly used to handle data changes caused by write operations by making the old version in other processing cores invalidate the data. This cache copy expires to prevent multiple processing cores from continuing to use expired data. The cache copy version verification maintenance method is mainly used for handling read operations. It determines the validity of local cache data by comparing the data version identifier of the local cache copy with that of the directory entry record. The cache access freeze maintenance method is mainly used for handling DMA access processes. It avoids inconsistencies between the cache state and directory records during direct DMA access to the shared storage area by temporarily restricting changes to directory entries and adjusting the processing core set. For example, if the current target cache line is cache line number 100, and the corresponding target maintenance core set is {Core0, Core3, Core5}, when Core2 sends a write request, it determines whether Core0, Core3, and Core5 need to be affected based on the write request type. Core 3 and Core 5 perform cache replica invalidation maintenance. When Core 2 sends a read request, it determines that version verification maintenance is required. By dynamically matching the cache replica maintenance method according to the access type, different types of data access adopt corresponding consistency maintenance processes, avoiding increased cache communication volume caused by all access requests using the same maintenance strategy, and improving the efficiency of multi-core DSP shared memory access. In the multi-core DSP cache maintenance architecture, each target cache line corresponds to a directory entry. This directory entry records the current cache maintenance status of the target cache line, including the cache line status identifier, data version identifier, the processing core set corresponding to the target cache line, and the protocol status identifier. The corresponding directory entry is located based on the target cache line index.Then, the data version identifier field and protocol status identifier field are read from the directory entry. For example, if the target cache line is cache line number 100, the corresponding directory entry is found through the cache line index. The data version identifier recorded in the directory entry is 20, indicating that the data version of the current target cache line has been effectively updated 20 times. The protocol status identifier is recorded as dynamically adjusted, indicating that the current target cache line is adjusting the cache maintenance scope according to access behavior. After reading these two fields, the data version identifier is used as the basis for judging the newness of the cached copy data, and the protocol status identifier is used as the basis for determining the current cache maintenance strategy. For example, when performing write request maintenance, if the read data version identifier is 20, then after performing the write operation, the version will be updated to 21. When performing read request maintenance, the version identifier in the local cache copy is compared with the version identifier 20 in the directory entry. When performing a DMA access request, the protocol status identifier is read to determine whether the directory entry update is allowed. By simultaneously reading the data version identifier and the protocol status identifier, the cache copy maintenance process is controlled not only based on the access type but also dynamically based on the current maintenance status of the target cache line and data changes, improving the accuracy of cache consistency control. When the cache maintenance control module determines that the current access request is a write request, since the write operation will change the data content in the target cache line, the data version identifier of the target cache line needs to be updated first to indicate that the cache line has generated a new data state. Then, according to the target cache line... The cache maintenance control module identifies the cache replicas that require state updates and performs consistency maintenance operations on the corresponding cache replicas. For example, if the current data version identifier of the target cache line is 20, it means that the current shared storage area and cache replicas both correspond to version 20 data. When processing core Core2 writes new data to the target cache line, the cache maintenance control module detects that the write request was successfully executed. It then performs an increment update operation on the current data version identifier, adding a version number to the original identifier, updating 20 to 21, generating the updated data version identifier 21, and writing this identifier to the directory entry. The module then reads the target maintenance core set, for example, {Core0, Core3, Core5}, and queries each processing core. The cache copy status information corresponding to each core determines which processing cores currently store the target cache line copy. For example, if the cache status of Core0 is valid, the cache status of Core3 is valid, and the cache status of Core5 is invalid, then the cache copies corresponding to Core0 and Core3 are determined to be the cache copies that need to undergo status updates. The cache maintenance control module sends cache status update control information to Core0 and Core3, changing the status of the corresponding cache copies from valid to invalid, or marking them as waiting for reloading, so that they no longer use version 20 data. When Core0 or Core3 reads the target cache line again later, it retrieves the latest data according to the updated data version identifier 21.To ensure data version consistency across multiple processing cores and prevent write operations from causing different cores to continue accessing older versions of data, thus improving shared storage cache consistency, when an access request is a read request, the cache maintenance control module needs to determine whether the target cache line copy in the current processing core's local cache is the latest version. Therefore, version verification is performed by comparing the data version identifier corresponding to the local cache copy with the data version identifier recorded in the directory entry. When a processing core executes a read request, it accesses its own cache area to obtain the version identifier corresponding to its local cache copy. For example, if the Core4 processing core stores the target cache line copy in its local cache and records the data version identifier as 19, the cache maintenance control module queries the directory entry corresponding to the target cache line to obtain the shared version. The current data version identifier recorded in the storage area is 21. The cache maintenance control module compares the two version identifiers. Since the local cache version 19 is less than the target cache line version 21, it determines that the local cache copy has expired, and the version verification result indicates a mismatch. At this time, the cache maintenance control module sends a data read request to the shared storage area to retrieve the latest data based on the target cache line address. For example, if the data content corresponding to the target cache line number 100 in the shared storage area is the latest sampled data Data21, the cache maintenance control module reads this data, transfers it to the corresponding cache area of ​​Core4, replaces the original version 19 data, and simultaneously updates the data version identifier of the local cache copy to 21, ensuring that the local cache copy matches the directory entry. To maintain consistency, if the version verification results are consistent (e.g., both the local cache version identifier and the directory entry version identifier are 21), it indicates that the local cache copy is already up-to-date and data reloading is unnecessary. The version verification mechanism only updates data when the cache copy versions are inconsistent, reducing shared memory access frequency and improving DSP chip efficiency. When the access request is a DMA access request, since DMA units typically directly access the shared memory area to perform continuous data transfer, their access process may bypass the processing core cache access path. Therefore, it is necessary to freeze the cache maintenance state to prevent changes in directory entries and processing cores during DMA transfers. Information about the data access process corresponding to the DMA access request, including DMA transfer details, is also required. The starting address, target address range, transfer direction, and transfer status are generated by the DMA controller when initiating a data transfer task. For example, when an external ADC acquisition module needs to write 1024 bytes of sampled data to the shared memory area via DMA, the DMA controller generates a DMA access request, which includes the source address (ADC buffer address 0x40000000), the target address (shared memory area address 0x80001000), the transfer length (1024 bytes), and the write direction identifier. After reading the DMA access information, it determines whether the current target buffer line is within the DMA access range. If the target buffer line belongs to the DMA transfer area, the protocol status identifier in the directory entry is switched from the current state to the access frozen state. For example...If the target cache line is currently in a stable maintenance state, and the cache maintenance control module detects that DMA is modifying the shared storage data corresponding to that cache line, it will change the protocol status to an access-frozen state. In the access-frozen state, the cache maintenance control module suspends processing core set update operations in the directory entries, i.e., prohibits adding, removing, or adjusting the range of processing cores. It also suspends data version identifier changes to avoid inconsistencies between the processing core cache state and the shared storage data state during DMA transfer. For example, even if a processing core accesses the target cache line during DMA transfer, it will not immediately trigger a processing core set adjustment; instead, it will wait for the DMA transfer to complete before processing. After the DMA transfer ends, the cache maintenance control module will lift the access-frozen state based on the DMA completion status and re-execute the cache consistency maintenance process. By introducing the access-frozen state, frequent changes in cache maintenance logic during high-speed DMA data transfer can be avoided, improving the coordination between DMA access and multi-core cache maintenance, and ensuring the reliability of shared storage data.

[0037] In a preferred embodiment, after completing the cache copy maintenance operation, the cache processing core set is dynamically updated based on the execution result and protocol status identifier of the cache copy maintenance operation, and the data version identifier and protocol status identifier in the directory entries are adjusted synchronously, including: S701. After completing the cache copy maintenance operation, obtain the execution result corresponding to the cache copy maintenance operation and read the protocol status flag corresponding to the target cache line. S702. Determine the update conditions of the cache processing core set based on the execution results and protocol status identifiers, and update the processing cores in the cache processing core set based on the update conditions to generate the updated cache processing core set. S703. Update the processing core set corresponding to the target cache line recorded in the directory entry according to the updated cache processing core set, so that the processing core set in the directory entry corresponds to the current cache copy status. S704. Based on the execution results and protocol status identifiers, synchronize and update the data version identifiers and protocol status identifiers in the directory entries.

[0038] As described in steps S701 to S704 above, after completing the cache copy maintenance operation corresponding to the target cache line, the cache maintenance control module needs to obtain the execution result of this cache copy maintenance operation to determine whether the cache copy has completed the state change according to the preset maintenance method. It also needs to determine the update method for the subsequent processing core set, data version identifier, and protocol status identifier based on the current protocol status of the target cache line. The cache copy maintenance operation includes cache copy invalidation operations corresponding to write requests, cache copy update operations corresponding to read requests, and access freeze operations corresponding to DMA access requests. Different maintenance operations correspond to different execution result acquisition methods. When the access request is a write request, the cache maintenance control module sends the cache copy status to the processing core in the target maintenance core set. After updating the status control information, the system receives status feedback information from each processing core. This feedback includes whether the cache replica has been successfully invalidated, whether the cache status has been switched, and whether the control information has been received correctly. For example, if the target maintenance core set is {Core0, Core3, Core5}, and Core2 is currently performing a write operation on the target cache line, the cache maintenance control module sends cache replica invalidation instructions to Core0, Core3, and Core5. If Core0 returns invalidation complete, Core3 returns invalidation complete, and Core5 returns no valid replica and no processing is needed, then the write maintenance operation is considered successful based on the feedback information from each processing core. When the access request is a read request, the execution result is obtained based on the local cache replica update result. As a result, for example, the cache update completion flag and the updated data version flag returned by the processing core are read. If the data version flag of the local cache copy has been updated from 19 to 21, then the read maintenance operation is determined to be complete. When the access request is a DMA access request, the execution result is obtained according to the transfer completion status fed back by the DMA controller. For example, if the DMA controller returns a transfer completion flag, it indicates that the data transfer process corresponding to the target cache line has ended. The cache maintenance control module reads the protocol status flag in the directory entry corresponding to the target cache line, locates the directory entry address according to the target cache line index, and reads the protocol status field in the directory entry. For example, if the target cache line is cache line number 100, the corresponding directory entry address is Index100. The control module accesses the directory entry corresponding to Index100 and reads the protocol status identifier field. A current record value of "dynamic adjustment" indicates that the target cache line is currently in the processing core-wide adjustment phase. A "stable maintenance" status indicates that the target cache line's access behavior is stable and no large-scale adjustment is needed. An "access frozen" status indicates that a DMA access process is currently underway, requiring restrictions on directory entry changes. By obtaining the maintenance execution result and the current protocol status identifier, the cache processing core set adjustment process can make dynamic decisions based on the actual maintenance completion status and the current maintenance phase of the target cache line. This avoids premature updates to directory information before cache state synchronization is complete.The process determines whether the processing core set corresponding to the current target cache line needs adjustment. Based on the update conditions, it then performs retention, addition, or removal operations on the processing cores in the cache processing core set, thereby generating an updated cache processing core set that matches the current cache replica state. The cache processing core set represents the set of processing cores currently participating in the target cache line cache maintenance. It is recorded in a directory entry to indicate which processing cores have a cache replica of the target cache line or participate in the target cache line consistency maintenance. After the cache replica maintenance operation is completed, the result determines whether the current processing core set needs adjustment. For example, in a write request scenario, if all processing cores in the target maintenance core set successfully complete cache replica invalidation, it indicates that the original cache replica relationship has changed. It is necessary to re-determine which processing cores will continue to participate in subsequent maintenance. In read request scenarios, if a newly added processing core successfully loads the latest version of the target cache line data, then that processing core needs to be added to the cache processing core set. In DMA access scenarios, since directory entries are in an access-frozen state, adjusting the cache processing core set is temporarily not allowed. The cache maintenance control module determines the specific update conditions based on the protocol status flag. For example, when the protocol status flag is "stable maintenance," the update condition is set to only make minor adjustments based on the actual existence of cache copies, that is, only remove processing cores that no longer have valid cache copies. When the protocol status flag is "dynamic adjustment," the update condition is set to readjust the range of processing cores based on the latest access situation, such as adding frequently accessed directories. The processing cores that handle cache lines are deleted. When the protocol status is "access frozen," the update condition is set to prohibit modification of the processing core set, keeping the current set unchanged. For example, if the current cache processing core set is {Core0, Core3, Core5}, after a write maintenance operation, the cache copies of Core3 and Core5 successfully expire. Core6 rereads the target cache line and establishes a valid cache copy during maintenance. Simultaneously, the protocol status is set to "dynamic adjustment." Based on the update condition, Core0 remains under maintenance. Core3 and Core5 need to be removed because their cache copies have expired and there have been no recent access records. Core6 needs to be removed because it has established a valid cache copy and exists... Since new access behavior is required, the original processing core set {Core0, Core3, Core5} is adjusted to include the retained processing core Core0 and the newly added processing core Core6, resulting in an updated cache processing core set {Core0, Core6}. The update conditions are determined jointly based on execution results and protocol state, ensuring that changes to the processing core set are consistent with actual cache copy changes. This avoids mismatches between the processing core range recorded in the directory entries and the actual cache state, improving the accuracy of cache consistency maintenance. The directory entries serve as state recording units during shared storage cache maintenance, storing a field representing the processing core set corresponding to the target cache line. This field indicates which processing cores are currently participating in the target cache line's cache maintenance. For example…The initial processing core set of the directory entry corresponding to the target cache line is {Core0, Core3, Core5}, indicating that Core0, Core3, and Core5 all have cache maintenance associations with this cache line. After the cache copy maintenance operation is completed, a new cache processing core set {Core0, Core6} is generated based on the execution result. The original processing core set field in the directory entry needs to be replaced and updated. The directory entry corresponding to the target cache line is located, and then the original processing core set field is read. Processing core identifiers that no longer meet the maintenance conditions are deleted, such as Core3 and Core5. Subsequently, newly added processing core identifiers that meet the maintenance conditions are written to the directory entry, such as adding Core6. Finally, the processing core sets in the directory entries are updated to {Core0, Core6}. Simultaneously, the cache maintenance and control module performs consistency checks on the updated processing core sets in the directory entries. For example, it checks whether each processing core in the directory entry has a corresponding cache replica status record. If Core6 has completed cache loading and has a valid cache replica, the processing core set update is considered valid. If a processing core does not have a valid cache replica, the filtering process is re-executed to ensure that the directory entries always reflect the actual cache distribution of the current target cache line. The data version identifier is used to indicate the update status of the target cache line's data content. This identifier is incremented whenever a valid data modification occurs in the target cache line, distinguishing between different versions of the data replica. Protocol status identifiers indicate whether the target cache line is currently in a stable maintenance state, a dynamic adjustment state, or an access-frozen state. The decision to update the data version identifier is based on the cache copy maintenance execution result. For example, when a write request is executed, if the write operation completes successfully, it indicates that the target cache line data content has changed. In this case, the current data version identifier in the directory entry is read; for example, if the current version identifier is 21, it is updated to 22 and written back to the directory entry. If a read request is executed and only the cache copy is loaded, the data version identifier remains unchanged because the data in the shared storage area has not changed. When a DMA access request is executed, if the DMA only completes a read operation, the data version identifier is not changed; if the DMA completes a read operation, the data version identifier is not changed. If a write operation is initiated, the data version identifier is updated based on the DMA write completion status. The protocol status is adjusted based on the protocol status identifier and the current maintenance results. For example, if the target cache line was originally in a dynamically adjusted state, and the processing core set is reconfigured and access conflicts decrease, the protocol status identifier is switched from dynamically adjusted to stable maintenance. If the DMA access ends, the access freeze state is restored to stable maintenance. If persistent access conflicts still exist, the dynamically adjusted state is maintained. For example, if the target cache line's current data version identifier is 21 and the protocol status identifier is dynamically adjusted, after completing the write request maintenance, the data version is updated to 22, and a decrease in current access conflicts is detected, the protocol status identifier is adjusted to stable maintenance.The updated data version identifier 22 and stable maintenance status are written to the directory entry. By synchronously updating the data version identifier and protocol status identifier, the directory entry can simultaneously reflect changes in the target cache line data and cache maintenance status, avoiding asynchrony between data version, processing core range, and protocol status, and improving the reliability and stability of the multi-core DSP shared memory cache maintenance process.

[0039] Please see the appendix Figure 2 As shown, the present invention also provides a cache maintenance system for shared memory of a DSP chip, used for the aforementioned cache maintenance method for shared memory of a DSP chip, comprising: The cache line generation module is used in a multi-core DSP architecture to receive access requests to the shared memory area, determine the target cache line based on the access address in the access request, and generate a cache line index corresponding to the target cache line. The entry configuration module queries the corresponding directory entry based on the cache line index, obtains the cache line status identifier, data version identifier and the processing core set corresponding to the target cache line in the directory entry, and configures the corresponding protocol status identifier according to the directory entry. The protocol status identifier includes stable maintenance status, dynamic adjustment status and access freeze status. The state transition module is used to perform state transition processing on the protocol state identifier according to the access type, cache line status identifier and data version identifier corresponding to the access request, so that the target cache line can switch between stable maintenance state, dynamic adjustment state and access frozen state. The cache replica module is used to generate a cache processing core set based on the processing core set, historical access sequence, and data version identifier corresponding to the target cache line when the protocol status identifier indicates that the target cache line is in a dynamic adjustment state, and to establish a cache replica propagation set based on the cache processing core set. The target maintenance module is used to determine the cache replica maintenance object based on the cache replica propagation set and the access type corresponding to the access request, and to adjust the processing core range corresponding to the cache replica maintenance object according to the protocol status identifier, thereby generating the target maintenance core set. The cache maintenance module performs cache copy maintenance operations on the target cache line based on the target maintenance kernel set and the access type corresponding to the access request; The dynamic update module is used to dynamically update the cache processing core set after the cache copy maintenance operation is completed, based on the execution result of the cache copy maintenance operation and the protocol status identifier, and synchronously adjust the data version identifier and protocol status identifier in the directory entries.

[0040] As described above, the cache line generation module receives access requests from processing cores and DMA units in a multi-core DSP architecture. It then determines the target cache line based on the access address corresponding to the access request. When a processing core within the DSP chip needs to access data in the shared memory area, or when a DMA unit needs to perform a data transfer operation, a corresponding access request is generated. This request carries the access address information of the target data. The cache line generation module parses this access address, mapping it to the corresponding cache line address range to determine the target cache line corresponding to the access request. Furthermore, it generates a cache line index based on the address information of the target cache line. This cache line index uniquely identifies the target cache line in directory management. The query location within the region allows for quick location of the directory entry corresponding to the target cache line. For example, in a multi-core DSP chip, if processing core Core0 needs to read data from the shared memory region address 0x80001000, the cache line generation module determines its corresponding cache line number as 128 based on this address and generates a corresponding cache line index 128. This index allows access to cache maintenance information, enabling unified mapping of access requests from different processing cores and DMA units to the corresponding cache lines, improving access location efficiency during cache maintenance. The entry configuration module queries the corresponding directory entry based on the cache line index generated by the cache line generation module and obtains the cache status information corresponding to the target cache line. The directory entry is used to record the total cache line information. The shared storage area contains maintenance status information for each cache line, including cache line status identifier, data version identifier, and the processing core set corresponding to the target cache line. The cache line status identifier indicates the current cache status of the target cache line, such as valid, invalid, or updating. The data version identifier indicates the current data version of the target cache line, used to determine data consistency between cache copies from different processing cores. The processing core set records the processing core sets that currently have a cache copy of the target cache line or participate in the maintenance of that cache line. The entry configuration module accesses the directory storage area based on the cache line index, reads the information from the corresponding directory entry, and further configures the protocol status identifier based on the current cache status of the target cache line. Protocol status identifiers describe the current cache maintenance stage of the target cache line, including stable maintenance, dynamic adjustment, and access freeze states. For example, when the target cache line has stable access over a long period and there are no frequent cache copy changes, the protocol status identifier is set to stable maintenance. When multiple processing cores are detected frequently accessing the same cache line, leading to an increase in cache copy changes, the protocol status identifier is set to dynamic adjustment. When the DMA unit is performing continuous data transfer operations on the target cache line, to avoid changes in directory information affecting DMA consistency, the protocol status identifier is set to access freeze. By introducing protocol status identifiers, different cache maintenance strategies can be selected based on the current access environment of the target cache line.The state transition module dynamically transitions the protocol status identifier of the target cache line based on the access request type, cache line status identifier, and data version identifier. The module continuously acquires the current access request type (e.g., processing read requests, write requests, or DMA access requests) and, combined with cache line status changes and data version changes in the directory entries, determines whether the current cache maintenance state needs adjustment. When the target cache line is accessed infrequently and data version changes are minimal, a stable maintenance state is maintained. However, when multiple processing cores continuously access the same cache line, causing frequent changes in the number of cache replicas or an increase in the number of data version updates, a state transition is triggered, putting the target cache line into a dynamic adjustment state for readjustment. Within the entire cache maintenance scope, when a DMA unit is detected occupying a shared memory area for data transfer, the protocol state is switched to an access-frozen state, temporarily prohibiting changes to directory entries and processing core sets. For example, if the target cache line is currently in a stable maintenance state, and frequent write accesses are detected from Core1, Core2, and Core3 within 20 consecutive access cycles, with data version identifiers continuously increasing, the state transition module determines that access conflicts are increasing and switches the target cache line from a stable maintenance state to a dynamic adjustment state. Through this dynamic state transition mechanism, the cache maintenance strategy can be changed according to the actual access environment, improving the adaptability of cache consistency control. The cache replica module is used when the target cache line is in a dynamic adjustment state. A cache processing core set is generated based on the target cache line's corresponding processing core set, historical access sequence, and data version identifier. A cache replica propagation set is then established. The cache replica module reads the current processing core set recorded in the directory entries and simultaneously obtains the target cache line's historical access sequence, such as the number of times different processing cores accessed the cache line, the access time order, and the access type. It also considers changes in the data version identifier to determine if the current cache replica distribution is reasonable. For example, if the original processing core set includes Core0, Core1, and Core2, and the historical access sequence shows that Core0 accessed the target cache line 50 times consecutively, while Core1 and Core2 only accessed it twice, and the data version frequently changed from 10 to 20, then the cache replica distribution is unreasonable. This module determines that Core0 is a high-frequency access processing core and retains it. Core1 and Core2 are deemed to have low maintenance value and are removed. Meanwhile, Core4 is found to be continuously accessing this cache line recently, so it is added to the processing core set, forming a new cache processing core set. Based on the updated cache processing core set, the processing cores participating in cache replica maintenance are determined, forming a cache replica propagation set. By dynamically adjusting the scope of cache processing cores, invalid cache replica maintenance operations can be reduced, lowering cache communication overhead in multi-core DSPs. The target maintenance module is used to determine the actual range of target processing cores that need to perform cache maintenance operations based on the cache replica propagation set and the access request type. Since different access requests correspond to different maintenance needs...Therefore, the target maintenance module first determines the cache replica maintenance method based on the access type. For example, for write access, it needs to notify processing cores that may have old data replicas to perform cache status updates; for read access, it needs to determine whether there are cache replicas with inconsistent versions; for DMA access, it needs to restrict cache status changes. The target maintenance module determines the range of processing cores that may be involved based on the cache replica propagation set, and further filters the maintenance objects based on the current protocol status identifier. For example, in the dynamic adjustment state, processing cores that have been frequently accessed recently can be selected as key maintenance objects; in the stable maintenance state, regular maintenance can be performed according to the current set of processing cores; and in the access frozen state, the adjustment of the range of processing cores is restricted, and only the current maintenance objects remain unchanged. The final result is a target maintenance core set, providing precise control over cache copy maintenance operations. The cache maintenance module, based on the target maintenance core set and the access request type, performs corresponding cache copy maintenance operations on the target cache line. When the access request is a write request, the cache maintenance module performs a version update based on the current data version identifier. For example, if the current data version identifier is 30, it is updated to 31 after the write operation, and a cache copy status update instruction is sent to the processing core in the target maintenance core set to invalidate the old version cache copy. When the access request is a read request, the cache maintenance module compares the data version identifier of the local cache copy with the data version identifier in the directory entry. For example, if the local version is 30 and the directory version is 31, the local cache copy is determined to be expired, and the cache copy is then updated from the local cache entry. The shared storage area re-acquires the target cache line data for updating. When the access request is a DMA access request, the cache maintenance module switches the protocol status flag to the access freeze state, restricting changes to directory entries and processing cores to avoid cache state contention during DMA transfer. By adopting differentiated maintenance strategies for different access types, data consistency during shared storage access is improved. The dynamic update module is used to synchronously update the cache processing core, data version flag, and protocol status flag based on the maintenance execution result and protocol status flag after the cache copy maintenance is completed. The dynamic update module obtains the cache maintenance operation execution result, such as whether the cache copy invalidation was successful, whether the data update was completed, and whether the DMA transfer ended. Then, based on the current protocol state, it is determined whether the processing core set needs adjustment. For example, if a processing core no longer has a valid cache copy, it is removed from the processing core set; if a processing core creates a new valid cache copy, it is added to the processing core set. Simultaneously, the data version identifier is updated based on the write operation results, and the protocol state identifier is adjusted according to changes in the access environment. For example, after DMA access ends, the access freeze state is restored to a stable maintenance state; after dynamic adjustment is completed and access conflicts decrease, the dynamic adjustment state is restored to a stable maintenance state. Through a dynamic update mechanism, the maintenance information in the directory entries is always consistent with the actual cache state. This is achieved through a combination of protocol state control, dynamic adjustment of the processing core set, cache copy range optimization, and the DMA access freeze mechanism.An adaptive cache maintenance scheme suitable for multi-core DSP shared memory architectures was implemented, which reduces cache maintenance overhead while ensuring data consistency, thereby improving the overall operating efficiency and reliability of multi-core DSP systems.

[0041] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained in this invention are implemented according to conventional methods in the art unless otherwise specified or limited.

Claims

1. A cache maintenance method for shared memory of a DSP chip, characterized in that, include: In a multi-core DSP architecture, it receives access requests to the shared memory area, determines the target cache line based on the access address in the access request, and generates a cache line index corresponding to the target cache line. Based on the cache line index query, the corresponding directory entry is retrieved, the cache line status identifier, data version identifier and the processing core set corresponding to the target cache line are obtained from the directory entry, and the corresponding protocol status identifier is configured according to the directory entry. The protocol status identifier includes stable maintenance status, dynamic adjustment status and access freeze status. Based on the access type, cache line status identifier, and data version identifier corresponding to the access request, the protocol status identifier is processed for state transition, so that the target cache line switches between stable maintenance state, dynamic adjustment state, and access freeze state. When the protocol status flag indicates that the target cache line is in a dynamic adjustment state, a cache processing core set is generated based on the processing core set, historical access sequence and data version flag corresponding to the target cache line, and a cache replica propagation set is established based on the cache processing core set; Based on the cache replica propagation set and the access type corresponding to the access request, determine the cache replica maintenance object, and adjust the processing core range corresponding to the cache replica maintenance object according to the protocol status identifier to generate the target maintenance core set; Based on the target maintenance kernel set and the access type corresponding to the access request, perform cache copy maintenance operation on the target cache line; After completing the cache copy maintenance operation, the cache processing core set is dynamically updated based on the execution result and protocol status identifier of the cache copy maintenance operation, and the data version identifier and protocol status identifier in the directory entries are adjusted synchronously.

2. The cache maintenance method for shared memory of a DSP chip according to claim 1, characterized in that, In a multi-core DSP architecture, an access request to a shared memory region is received, the target cache line is determined based on the access address in the access request, and a cache line index corresponding to the target cache line is generated, including: In a multi-core DSP architecture, it receives access requests to the shared memory region and obtains the access address information corresponding to the access request. The data access location corresponding to the access request is determined based on the access address information, and the target cache line corresponding to the access request is located based on the data access location; Obtain the cache line address information corresponding to the target cache line, and determine the cache line identifier corresponding to the target cache line based on the cache line address information; Generate the corresponding cache line index based on the cache line identifier.

3. The cache maintenance method for shared memory of a DSP chip according to claim 1, characterized in that, Based on the cache line index query, the corresponding directory entry is retrieved to obtain the cache line status identifier, data version identifier, and processing core set corresponding to the target cache line. The corresponding protocol status identifier is configured according to the directory entry. The protocol status identifier includes stable maintenance status, dynamic adjustment status, and access freeze status, including: Based on the cache line index query, the directory entry corresponding to the target cache line is retrieved to obtain the cache line status identifier, data version identifier and processing core set corresponding to the target cache line recorded in the directory entry; Based on the processing core set, cache line status identifier, and data version identifier corresponding to the target cache line, configure the corresponding protocol status identifier for the target cache line and associate the protocol status identifier with the directory entry; Set the protocol status identifier as the status identifier of the target cache line cache maintenance process. The protocol status identifier includes stable maintenance status, dynamic adjustment status, and access freeze status.

4. The cache maintenance method for shared memory of a DSP chip according to claim 1, characterized in that, Based on the access type, cache line status identifier, and data version identifier corresponding to the access request, state transition processing is performed on the protocol status identifier to switch the target cache line between stable maintenance state, dynamic adjustment state, and access freeze state, including: Retrieve the access request corresponding to the target cache line, and obtain the access type in the access request; Get the cache line status identifier and data version identifier from the directory entry corresponding to the target cache line, and get the current identifier status corresponding to the cache line status identifier and the current identifier status corresponding to the data version identifier; Based on the access type, the current identifier status corresponding to the cache line status identifier, and the current identifier status corresponding to the data version identifier, determine the protocol status switching conditions corresponding to the target cache line; According to the protocol state switching conditions, the protocol state identifier is processed for state transition, and the cache maintenance state corresponding to the protocol state identifier is adjusted so that the target cache line switches between stable maintenance state, dynamic adjustment state and access freeze state.

5. The cache maintenance method for shared memory of a DSP chip according to claim 1, characterized in that, When the protocol status flag indicates that the target cache line is in a dynamic adjustment state, a cache processing core set is generated based on the processing core set, historical access sequence, and data version flag corresponding to the target cache line. A cache replica propagation set is then established based on this cache processing core set, including: When the protocol status flag indicates that the target cache line is in a dynamic adjustment state, read the directory entry corresponding to the target cache line and obtain the processing core set corresponding to the target cache line recorded in the directory entry. Obtain the historical access sequence corresponding to the target cache line and read the data version identifier from the directory entry; Generate a cache processing core set based on the processing core set corresponding to the target cache line, the historical access sequence, and the data version identifier; The processing cores that participate in the maintenance of cache replicas of the target cache line are determined based on the cache processing core set, and a cache replica propagation set is formed based on the processing cores that participate in the maintenance of cache replicas.

6. The cache maintenance method for shared memory of a DSP chip according to claim 5, characterized in that, Based on the processing core set corresponding to the target cache line, the historical access sequence, and the data version identifier, a cache processing core set is generated, including: Obtain the access request records corresponding to the target cache line in the historical access sequence, and determine the access count and access order of the target cache line corresponding to each processing core based on the access request records; Based on the number of accesses and the access order for each processing core, determine the access characteristics of the processing cores corresponding to the target cache line, and combine the processing core set and data version identifier corresponding to the target cache line to determine the processing core set adjustment conditions; Based on the processing core set adjustment conditions, the processing cores in the processing core set corresponding to the target cache line are filtered to determine the filtered processing core set, which includes retained processing cores, added processing cores, and removed processing cores. The processing core set corresponding to the target cache line is updated based on the filtered processing core set to generate a cache processing core set.

7. The cache maintenance method for shared memory of a DSP chip according to claim 1, characterized in that, Based on the cache replica propagation set and the access type corresponding to the access request, determine the cache replica maintenance object, and adjust the processing core range corresponding to the cache replica maintenance object according to the protocol status identifier to generate the target maintenance core set, including: Based on the cache replica propagation set and the access type corresponding to the access request, determine the cache replica processing method for the access request; Based on the cache replica propagation set and cache replica processing method, determine the cache replica to be maintained corresponding to the target cache line, and obtain the processing core set corresponding to the cache replica to be maintained; The current cache maintenance status is determined based on the protocol status identifier, and the range of the processing core set corresponding to the cache copy to be maintained is adjusted based on the current cache maintenance status to select the processing cores to participate in the cache copy maintenance. The target maintenance kernel set is generated based on the filtered processing kernels.

8. The cache maintenance method for shared memory of a DSP chip according to claim 1, characterized in that, Based on the target maintenance kernel set and the access type corresponding to the access request, perform cache copy maintenance operations on the target cache line, including: Determine the cache copy maintenance method corresponding to the target cache line based on the access type; Read the data version identifier and protocol status identifier corresponding to the target cache line based on the cache copy maintenance method; When the access type is a write request, the data version corresponding to the target cache line is updated according to the data version identifier, an updated data version identifier is generated, and the corresponding cache copy is determined according to the target maintenance kernel set, and a status update operation is performed on the cache copy. When the access type is a read request, the data version identifier corresponding to the local cache copy is checked against the data version identifier corresponding to the target cache line. If the check result does not match, the data corresponding to the target cache line is retrieved from the shared storage area to update the local cache copy. When the access type is a DMA access request, the protocol status flag is switched to the access freeze state according to the data access process corresponding to the DMA access request, and the update operations of directory entries and cache processing cores are restricted based on the access freeze state.

9. The cache maintenance method for shared memory of a DSP chip according to claim 1, characterized in that, After completing the cache replica maintenance operation, based on the execution result and protocol status identifier, the cache processing core set is dynamically updated, and the data version identifier and protocol status identifier in the directory entries are adjusted synchronously, including: After completing the cache copy maintenance operation, obtain the execution result corresponding to the cache copy maintenance operation, and read the protocol status flag corresponding to the target cache line; The update conditions for the cache processing core set are determined based on the execution results and protocol status identifiers. The processing cores in the cache processing core set are then updated based on the update conditions to generate the updated cache processing core set. Update the processing core set corresponding to the target cache line recorded in the directory entry according to the updated cache processing core set, so that the processing core set in the directory entry corresponds to the current cache copy state; Based on the execution results and protocol status identifiers, the data version identifiers and protocol status identifiers in the directory entries are updated synchronously.

10. A cache maintenance system for shared memory of a DSP chip, applied to the cache maintenance method for shared memory of a DSP chip according to any one of claims 1 to 9, characterized in that, include: The cache line generation module is used in a multi-core DSP architecture to receive access requests to the shared memory area, determine the target cache line based on the access address in the access request, and generate a cache line index corresponding to the target cache line. The entry configuration module queries the corresponding directory entry based on the cache line index, obtains the cache line status identifier, data version identifier and the processing core set corresponding to the target cache line in the directory entry, and configures the corresponding protocol status identifier according to the directory entry. The protocol status identifier includes stable maintenance status, dynamic adjustment status and access freeze status. The state transition module is used to perform state transition processing on the protocol state identifier according to the access type, cache line status identifier and data version identifier corresponding to the access request, so that the target cache line can switch between stable maintenance state, dynamic adjustment state and access frozen state. The cache replica module is used to generate a cache processing core set based on the processing core set, historical access sequence, and data version identifier corresponding to the target cache line when the protocol status identifier indicates that the target cache line is in a dynamic adjustment state, and to establish a cache replica propagation set based on the cache processing core set. The target maintenance module is used to determine the cache replica maintenance object based on the cache replica propagation set and the access type corresponding to the access request, and to adjust the processing core range corresponding to the cache replica maintenance object according to the protocol status identifier, thereby generating the target maintenance core set. The cache maintenance module performs cache copy maintenance operations on the target cache line based on the target maintenance kernel set and the access type corresponding to the access request; The dynamic update module is used to dynamically update the cache processing core set after the cache copy maintenance operation is completed, based on the execution result of the cache copy maintenance operation and the protocol status identifier, and synchronously adjust the data version identifier and protocol status identifier in the directory entries.

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