A cross-chip zero-copy inference method and system for mobile radar multi-modal data

Abstract

A cross-chip zero-copy reasoning method and system for mobile radar multi-modal data belong to the technical field of multi-modal data buffering, cross-chip memory mapping and edge AI zero-copy reasoning. In order to solve the problem that multi-modal data is copied multiple times between the collection buffer, tensor and accelerator, and the device still accesses the buffer when abnormal recovery, the application constructs a closed loop through hierarchical memory pool, unified buffer descriptor, tensor adapter and graceful recovery manager. The CPU side creates a view through frombuffer, and the accelerator side maps shared underlying storage through DLPack or vendor device. When the layout is incompatible, perform a rearrangement. When the lease expires, isolate, empty the queue, revoke the mapping and deduct the reference, and then recover. The application can control the single frame copy number to zero or one, reduce the risk of illegal access caused by abnormal recovery, and is suitable for oilfield well site, tank area, pipeline and other mobile emergency command fields.

Description

Technical Field

[0001] This invention belongs to the fields of multimodal data buffering, cross-chip memory mapping, and edge AI zero-copy inference technology. Specifically, it relates to a technical solution for forming a closed-loop control between executable software algorithms and on-board hardware status under the constraints of space, power, heat dissipation, communication, and domestic computing power of mobile radar emergency command vehicles in the petroleum industry. Background Technology

[0002] Mobile radar emergency command vehicles need to perform radar detection, infrared / visible light identification, UAV coordination, risk assessment, resource scheduling, and communication support in oilfield well sites, tank farms, long-distance pipelines, and complex field environments. Unlike fixed data centers, vehicles face constraints such as compartment partitions, heterogeneous computing nodes, limited heat capacity, limited UPS power supply, link fluctuations, and changes in mechanical condition.

[0003] 1. Multimodal data is typically copied multiple times from the acquisition buffer to NumPy, PyTorch tensors, and accelerator memory.

[0004] 2. When multiple high-definition videos and point clouds are processed concurrently, copying consumes CPU, memory bus, and peak memory, increasing latency.

[0005] 3. The single-device zero-copy interface lacks cross-process lifecycle, quantization scale, layout compatibility and exception handling mechanisms.

[0006] Therefore, the deficiency of existing technologies is not simply the lack of a particular algorithm, but rather the lack of a technical solution that organizes the vehicle's physical state, domestically produced computing resources, AI model execution process, and security verification into an executable closed loop. Summary of the Invention

[0007] The purpose of this invention is to provide a cross-chip zero-copy inference method and system for multimodal data of mobile radar, to solve the following specific technical problems: (1) Multimodal data is typically copied multiple times from the acquisition buffer to NumPy, PyTorch tensors and accelerator memory.

[0008] (2) When multiple high-definition videos and point clouds are used concurrently, copying consumes CPU, memory bus and peak memory, increasing latency.

[0009] (3) The single-device zero-copy interface lacks cross-process lifecycle, quantization scale, layout compatibility and exception recycling mechanism.

[0010] To achieve the above objectives, the present invention provides the following technical solution: This invention proposes a cross-chip zero-copy inference method for multimodal data from mobile radar, which includes the following steps: S1: Pre-allocate size-based page locking or shared buffer pools for each sensor; S2: The acquisition end directly writes the sensor data into the buffer in the buffer pool and generates a unified buffer descriptor corresponding to the buffer. S3: Check the layout compatibility of the buffer based on the stride and memory format in the unified buffer descriptor. If the layout is compatible, create a tensor view of the buffer on the CPU side and establish a shared mapping to the underlying storage of the buffer on the accelerator side. If the layout is incompatible, perform an alignment rearrangement on the buffer and then establish the tensor view and the underlying storage sharing. S4: When a consumer obtains the tensor view or the underlying storage, the reference count of the unified buffer descriptor is incremented atomically according to the number of consumers; S5: When a consumer releases the tensor view or the underlying storage, deduct the reference count. When the lease times out, sequentially perform abnormal consumer isolation, device queue emptying, device mapping cancellation, and reference deduction. After the total reference count is zero and the device mapping has been cancelled, reclaim the buffer to the buffer pool.

[0011] Furthermore, the unified buffer descriptor of the present invention includes a physical buffer identifier, shape, stride, dtype, device, timestamp, quantization scale, reference count, and version number; the quantization scale is used for quantization and dequantization of data between the CPU side and the accelerator side, so that the underlying storage shared across chips maintains semantic consistency between computing nodes with different precision.

[0012] Furthermore, the abnormal consumer determination of lease timeout described in this invention is completed by the recycling manager in conjunction with the consumer process liveness flag, heartbeat record and lease renewal time; a single signal abnormality only marks the consumer as a suspected abnormality, and does not immediately release the physical buffer occupied by it.

[0013] Furthermore, for the suspected abnormal consumer, the recycling manager sets its descriptor status to an isolated state, stops dispatching new buffer descriptors to it, and sends a stop or cancel command to the corresponding accelerator queue through device events, DMA fences, or vendor runtime interfaces. The recycling manager waits for the submitted device tasks to complete and queries the queue exhaustion status. If it is still not completed within the second timeout window, the device context corresponding to the consumer is reset and its device mapping is isolated.

[0014] Furthermore, the reference deduction method described in this invention adopts an atomic comparison swapping method, deducting the reference count corresponding to the abnormal consumer only once; after the device mapping is revoked, subsequent access to the buffer returns an invalid state.

[0015] Furthermore, the present invention generates a reclamation log during buffer reclamation, the reclamation log recording at least the descriptor version, abnormal consumer identifier, stop command time, queue exhaustion time, mapping revocation result, and final reclamation status.

[0016] Furthermore, when sensor state conflicts, model output inconsistencies, device temperature or power exceeding limits, communication interruptions, checkpoint damage, or key safety category uncertainty exceeding a threshold occur, the present invention stops reusing the current inference result and performs at least one of the following: re-acquisition, complete inference, backup node takeover, rollback to the previous stable version, or manual verification, and saves the triggering reason, input version, and output verification information.

[0017] Furthermore, the input data of this invention includes at least radar point cloud buffers, visible light / infrared frames, meteorological data, tensor layout and quantization scale, and consumer dependencies; each input data is associated with a unified timestamp or version number, and all records include at least a timestamp, source node, version number, validity flag and verification field, and records involving model output also include model hash, threshold configuration and hardware execution node.

[0018] Based on the same inventive concept, this invention proposes a cross-chip zero-copy inference system for implementing the method described above. The system includes: a hierarchical memory pool, a unified buffer descriptor management module, a layout-aware reordering module, a tensor adapter, a reference counting and lease management module, and a graceful garbage collector. The hierarchical memory pool is used to pre-allocate page-locked or shared buffers according to size for each sensor, and to receive buffers reclaimed by the graceful recycling manager; The unified buffer descriptor management module is used to generate a unified buffer descriptor corresponding to the buffer after the sensor data is directly written into the buffer at the acquisition end. The layout-aware rearrangement module is connected to the unified buffer descriptor management module and is used to check the layout compatibility of the buffer according to the stride and memory format in the unified buffer descriptor. When the layout is compatible, it outputs a direct mapping instruction to the tensor adapter. When the layout is incompatible, it performs an alignment rearrangement on the buffer and then outputs a mapping instruction to the tensor adapter. The tensor adapter is connected to the layout-aware rearrangement module and is used to create a tensor view of the buffer on the CPU side via frombuffer according to the direct mapping instruction and to map and share the underlying storage of the buffer on the accelerator side via DLPack or vendor equipment, and to establish the sharing of the tensor view and the underlying storage according to the mapping instruction. The reference counting and lease management module is connected to the tensor adapter and is used to atomically increase the reference count of the unified buffer descriptor according to the number of consumers when the consumer obtains the tensor view or the underlying storage, and to deduct the reference count when the consumer releases the tensor view or the underlying storage. The elegant recycling manager is connected to the reference counting and lease management module, the accelerator device queue and mapping management interface, respectively. It is used to sequentially perform abnormal consumer isolation, device queue emptying, device mapping cancellation and reference deduction when the lease expires, and recycle the buffer to the hierarchical memory pool after the total reference count is zero and the device mapping has been cancelled.

[0019] Furthermore, the present invention also provides a computer device including a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor performs the method described above.

[0020] The beneficial effects of this invention are as follows: 1. Low memory copying overhead This invention constrains the number of memory copies of single-frame multimodal data to zero or at most one. On the CPU side, a tensor view is generated through torch.frombuffer, and on the accelerator side, underlying storage sharing is achieved through DLPack or vendor DMA mapping. Alignment rearrangement is only performed when memory layouts are incompatible, avoiding multiple data copies of multimodal data such as radar point clouds, visible light / infrared images, and meteorological data between the acquisition buffer, NumPy, PyTorch tensors, and the memory of domestic GPUs / NPU accelerators, thus reducing unnecessary data transfer operations.

[0021] 2. Reduce CPU resource usage and memory bandwidth consumption. This invention eliminates a large number of redundant data copying operations, reduces CPU copying computation load, and lowers memory bus bandwidth usage. Under conditions of concurrent input of multiple high-definition video and radar point clouds, it effectively alleviates the operating pressure on the CPU and memory bus, and is compatible with the vehicle-mounted hardware constraints of mobile radar emergency command vehicles with limited power supply and heat dissipation.

[0022] 3. Reduce end-to-end latency of multimodal fusion inference This invention reduces the time loss caused by data copying. In multi-sensor concurrent operation scenarios, the end-to-end latency of multimodal perception fusion and AI inference recognition is significantly optimized. As the number of concurrent sensor streams increases, the latency improvement effect becomes more prominent, which can better meet the real-time needs of emergency response in oilfield well sites, tank farms, and long-distance pipelines.

[0023] 4. Reduce peak memory usage and minimize memory fragmentation. This invention employs a hierarchical memory pool combined with a buffer lifecycle management mechanism to avoid memory fragmentation caused by frequent memory allocation and release, thereby reducing peak system memory usage. In scenarios with concurrent input of high-resolution data from multiple sensors, it alleviates the memory resource shortage problem of heterogeneous hardware at the vehicle edge.

[0024] 5. Improve the stability of concurrent operation of multiple sensors This invention establishes a unified buffer descriptor to fully record information such as physical buffer identifier, shape, stride, dtype, device, timestamp, quantization scale, and reference count, thus improving cross-process data description information. It addresses the shortcomings of traditional single-device zero-copy interfaces that lack cross-process lifecycle, quantization scale, and layout compatibility descriptions.

[0025] 6. Implement safe and graceful reclamation of the abnormal consumer buffer to avoid the risk of illegal memory access. This invention relies on atomic reference counting combined with a lease timeout mechanism, along with process liveness status, heartbeat renewal, and device event handles, to comprehensively determine abnormal consumers. It completes buffer reclamation in the following order: isolating new tasks, stopping device queues, waiting for queue exhaustion, revoking device mappings, and atomically deducting reference counts. This prevents illegal address access caused by accelerator devices still accessing released buffers in the event of abnormal consumer process crashes, thus improving the robustness of inference systems in heterogeneous chip environments across ARM and domestic GPU / NPU architectures.

[0026] 7. Possesses fault rollback and safety verification capabilities to ensure the reliability of vehicle-mounted emergency services. When abnormal operating conditions such as sensor state conflicts, inconsistent model outputs, equipment temperature and power exceeding limits, communication interruptions, and safety category confidence exceeding limits occur, this invention can perform re-acquisition and inference, backup node takeover, version rollback, or manual review, and retain complete audit logs, adapting to the complex and highly reliable field operation scenarios of mobile radar emergency command vehicles. Attached Figure Description

[0027] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1This is a schematic diagram of the overall system architecture of the present invention, illustrating the connection relationships between the input, hierarchical memory pool, unified buffer descriptor management module, layout-aware reordering module, tensor adapter, reference counting and lease management module, graceful recycling manager, and output in the cross-chip zero-copy inference system; Figure 2 This is a schematic diagram of the method flow of the present invention, showing the execution order from buffer pool pre-allocation, acquisition end writing and descriptor generation, layout compatibility check and zero-copy mapping, consumer reference count increment to release deduction and lease timeout exception recycling; Figure 3 This diagram illustrates the closed-loop relationship of the innovative technical means of this invention. It is used to explain the causal closed loop formed by the three distinguishing technical features of unified buffer descriptor, zero-copy mapping, reference counting and lease reclamation according to state / data construction—algorithm calculation—hardware execution—result verification or rollback, as well as the functional relationship between each technical means in solving the technical problem. Figure 4 This is a template for experimental control data graphs of the present invention, used to present the ablation groups, observation indicators and data visualization formats of various comparative experiments; Figure 5 The bar chart shows the mean and standard deviation of the ablation test results for the core technical features of this invention. It represents the mean and standard deviation of the five ablation groups A0 to A4 in terms of four indicators: number of replications, latency, CPU utilization, and peak memory, and shows the continuous gain after the superposition of each technical feature. Figure 6 This is a line graph comparing the robustness of the present invention under environmental or load changes, showing the end-to-end delay comparison and relative improvement of the conventional solution with the present invention under conditions of 1 to 5 concurrent sensor streams. Figure 7 This is a timing diagram of resource and performance during 30 minutes of continuous operation of the present invention, showing the trend of CPU utilization over time for the conventional solution and the present invention during continuous operation; Figure 8 This is a grouped chart comparing the comprehensive indicators of typical oilfield emergency scenarios of the present invention, showing the end-to-end delay comparison and relative improvement of conventional solutions with the present invention under four scenarios: standard operating conditions, high temperature operating conditions, weak network operating conditions, and night / shading operating conditions. Detailed Implementation

[0029] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

[0030] Example 1: This example provides a cross-chip zero-copy inference method and system for multi-modal data from mobile radar, to solve the following specific technical problems: (1) Multimodal data is typically copied multiple times from the acquisition buffer to NumPy, PyTorch tensors and accelerator memory.

[0031] (2) When multiple high-definition videos and point clouds are used concurrently, copying consumes CPU, memory bus and peak memory, increasing latency.

[0032] (3) The single-device zero-copy interface lacks cross-process lifecycle, quantization scale, layout compatibility and exception recycling mechanism.

[0033] (1) System structure like Figure 1 As shown, the cross-chip zero-copy inference system of this embodiment includes a hierarchical memory pool, a unified buffer descriptor management module, a layout-aware reordering module, a tensor adapter, a reference counting and lease management module, and a graceful garbage collection manager. Each module is deployed on at least one of the ARM control node, domestic GPU / NPU acceleration node, sensor acquisition node, or vehicle-mounted storage node of the mobile radar emergency command vehicle, and is connected through a versioned data interface.

[0034] The hierarchical memory pool is used to pre-allocate page-locked or shared buffers according to size for each sensor, and to receive buffers reclaimed by the graceful reclamation manager, forming a closed loop of buffer allocation-use-reclaim-reallocation.

[0035] The unified buffer descriptor management module is used to generate a unified buffer descriptor corresponding to the buffer after the sensor data is directly written into the buffer at the acquisition end.

[0036] The layout-aware rearrangement module is connected to the unified buffer descriptor management module. It checks the layout compatibility of the buffer based on the stride and memory format in the unified buffer descriptor. When the layout is compatible, it outputs a direct mapping instruction to the tensor adapter. When the layout is incompatible, it performs an alignment rearrangement on the buffer and then outputs a mapping instruction to the tensor adapter.

[0037] The tensor adapter connects to the layout-aware rearrangement module and is used to create a tensor view of the buffer on the CPU side via frombuffer according to direct mapping instructions and to map the underlying storage of the shared buffer on the accelerator side via DLPack or vendor equipment, as well as to establish a shared tensor view and underlying storage according to mapping instructions.

[0038] The reference counting and lease management module connects to the tensor adapter to maintain consumer heartbeats, lease renewals, atomic reference counts, device event handles, and mapping states. When a consumer acquires a tensor view or underlying storage, the reference count of the unified buffer descriptor is atomically increased based on the number of consumers, and the reference count is deducted when a consumer releases a tensor view or underlying storage.

[0039] The graceful garbage collector is connected to the reference counting and lease management module, the accelerator device queue, and the mapping management interface, respectively. It is used to sequentially perform abnormal consumer isolation, device queue emptying, device mapping revocation, and reference deduction when a lease times out. Once the total reference count is zero and the device mapping has been revoked, the buffer is reclaimed to the hierarchical memory pool. When a consumer encounters an exception, the graceful garbage collector performs graceful garbage collection in the following order: isolating new tasks—stopping the device queue—waiting for the queue to run out—revoking device mappings—atomicly deducting references—returning the buffer to the memory pool.

[0040] The above six modules form a causal closed loop according to the following steps: state / data construction, algorithm computation, hardware execution, and result verification or rollback. The hierarchical memory pool and unified buffer descriptor management module constitute the data construction layer; the layout-aware rearrangement module and tensor adapter constitute the algorithm computation and hardware execution layer; and the reference counting and lease management module and graceful garbage collection manager constitute the result verification and lifecycle management layer. Each layer makes a verifiable contribution to solving the technical problem.

[0041] (2) Input data and data structure The input data processed in this embodiment includes at least radar point cloud buffers, visible / infrared frames, meteorological data, tensor layout and quantization scale, and consumer dependencies. All input data are associated using a unified timestamp or version number. All records contain at least a timestamp, source node, version number, validity flag, and verification field; records related to model output also include model hash, threshold configuration, and hardware execution node.

[0042] The radar point cloud buffer, visible / infrared frames, meteorological data, tensor layout, and quantization scale are registered in the vehicle configuration file, and clock synchronization, sensor calibration, model version verification, and log directory initialization are completed.

[0043] The unified buffer descriptor includes a physical buffer identifier, shape, stride, dtype, device, timestamp, quantization scale, reference count, and version number. The quantization scale is used for quantization and dequantization of data between the CPU and accelerator sides, ensuring semantic consistency of the underlying storage shared across chips across computing nodes with different precision. The physical buffer identifier uniquely identifies the underlying physical buffer; shape and stride describe the data dimension and row stride; dtype describes the data type; the device identifies the computing node where the data resides; the timestamp records the data acquisition time; and the version number supports data version management and consumer dependency tracking.

[0044] (3) Work process like Figure 2 As shown, the cross-chip zero-copy inference method of this embodiment includes the following steps.

[0045] Step S1 involves pre-allocating page-locked or shared buffer pools for each sensor, categorized by size. The buffer pool depth is 8–32 frames per sensor, memory alignment is 64 bytes or as required by the manufacturer, and batch aggregation takes 5–20 ms. These parameters are determined through calibration sets outside the training set and through hardware ablation experiments. Page-locked memory avoids paging by the operating system, while shared buffer pools support direct access by multiple processes.

[0046] In step S2, the acquisition end directly writes the sensor data into the buffer in the buffer pool, bypassing the intermediate temporary buffer, thereby eliminating the first copying during acquisition and processing. Simultaneously, the acquisition end generates a unified buffer descriptor corresponding to this buffer.

[0047] Step S3 checks the buffer layout compatibility based on the stride and memory format in the unified buffer descriptor. When layout is compatible, the CPU side creates a tensor view of the buffer via frombuffer, and the accelerator side maps the underlying storage of the shared buffer via DLPack or vendor device mapping. Frombuffer view creation does not copy data; it only establishes tensor objects on existing memory. DLPack or vendor device mapping allows the accelerator to directly access the same physical memory, eliminating data copying from the CPU to the accelerator; in this case, the number of copies per frame is 0. When layout is incompatible, the buffer undergoes one alignment rearrangement before the tensor view and underlying storage are shared; in this case, the number of copies per frame is 1, and only this one rearrangement is allowed; multiple format conversions are not permitted. The conditional branches of the above layout check and mapping constrain the number of copies per frame to 0 or 1, allowing 0 to 1 copies per frame.

[0048] Step S4: When a consumer retrieves a tensor view or underlying storage, the reference count of the unified buffer descriptor is atomically incremented based on the number of consumers. Consumers include modules for fusion, detection, and display. Atomic operations ensure the accuracy of the reference count during concurrent retrieval by multiple processes or threads, avoiding race conditions.

[0049] Step S5: Decrease the reference count when the consumer releases the tensor view or underlying storage. Upon lease timeout, the graceful reclaim manager sequentially performs abnormal consumer isolation, device queue emptying, device mapping revocation, and reference deduction, and reclaims the buffer to the buffer pool after the total reference count is zero and the device mapping has been revoked. The lease timeout is 2~10 seconds.

[0050] The determination of abnormal consumers is completed by the recycling manager in conjunction with the consumer process's liveness flag, heartbeat records, and lease renewal time. A single signal anomaly only marks the consumer as a suspected anomaly, without immediately releasing the physical buffer it occupies, in order to avoid false recycling caused by a single signal jitter.

[0051] For suspected abnormal consumers, the Recycle Manager sets their descriptor status to quarantined, stops dispatching new buffer descriptors to them, and sends a stop or cancel command to the corresponding accelerator queue via device events, DMA fences, or vendor runtime interfaces. The Recycle Manager waits for submitted device tasks to complete and queries the queue exhaustion status; if the task is not completed within the second timeout window, it resets the device context corresponding to the consumer and isolates its device mapping to prevent subsequent tasks from accessing the original buffer.

[0052] Once the device queue is confirmed to be exhausted, the recycling manager first cancels the DLPack or vendor device mapping, causing subsequent accesses to return to an invalid state. Then, it deducts the reference count of the abnormal consumer only once using an atomic comparison swap to avoid concurrent duplicate releases.

[0053] The buffer is returned to a memory pool of the same size only when the total reference count is 0 and the device mapping has been revoked. The reclamation log records at least the descriptor version, the abnormal consumer identifier, the stop command time, the queue exhaustion time, the mapping revocation result, and the final reclamation status.

[0054] The core of the above-described abnormal garbage collection process lies in the collection order: first, isolate new tasks; then, stop the device queue; wait for the queue to run out; revoke device mappings; and finally, atomically deduct references and return the memory to the memory pool. This order ensures that devices are not prematurely released while still in the access buffer, fundamentally preventing illegal address access caused by abnormal garbage collection.

[0055] Core computational relationships The single-frame copying overhead satisfies C_copy = Σ_iSize_i / BW_i, where Size_i is the data volume of the i-th copy and BW_i is the bandwidth of the corresponding copying path. This method constrains the number of single-frame copies N_copy ≤ 1. The buffer release condition is that the total reference count is 0, or that the lease has expired, the device queue is exhausted, and the device mapping has been revoked simultaneously. The above calculation relationship quantifies the technical effect of zero-copy into a measurable indicator, making the number of copies and the release condition verifiable and auditable.

[0056] PyTorch implementation path This embodiment is implemented within the PyTorch ecosystem. During the training phase, Dataset / DataLoader is used to construct datasets isolated by well site, recording random seeds, model hashes, and training configurations. The core network or control strategy is implemented in PyTorch, and ablation groups are implemented through configuration switches. Independent calibration sets are used to determine thresholds and parameters, without repeatedly tuning parameters using a test set. During the model phase, torch.nn.Module is used to implement the core network. torch.profiler or hardware counters are used to collect latency and resource data, and FP32 benchmark results are saved. During the export phase, TorchScript or ONNX is exported first, the dynamic range is fixed, operators not supported by the target domestic accelerator are replaced, ONNX / TorchScript is exported and compiled at the target runtime, and the PyTorch and device model outputs are compared layer by layer. When the relative error of a key layer exceeds the threshold, higher accuracy is maintained or the operator is replaced. During the deployment phase, control logic is executed on the ARM processor, and core inference is executed on the domestic GPU / NPU. All cross-node interfaces use versioned descriptors. After the target device is warmed up, P50 / P95 / P99 latency, peak memory, power consumption, and temperature are tested. During operation, the system records input size, P50 / P95 / P99 latency, CPU / GPU / NPU utilization, memory usage, power consumption, temperature, error codes, and output precision.

[0057] (4) Synergistic effect like Figure 3As shown, the innovative technical means of this embodiment include the following three aspects. First, a unified descriptor containing physical buffer identifier, shape, stride, dtype, device, timestamp, quantization scale, and reference count is established for each frame. This feature constitutes the data construction layer, providing a complete metadata carrier for cross-chip sharing and lifecycle management. Second, the CPU uses frombuffer, and the shared device context uses DLPack or vendor DMA mapping, allowing only one reordering when the layout is incompatible. This feature constitutes the algorithm calculation and hardware execution layer, directly eliminating multiple copies and constraining the number of copies per frame to ≤1. Third, buffers occupied by abnormal consumers are reclaimed through atomic reference counting and lease timeout. This feature constitutes the result verification and lifecycle management layer, solving the problem of the lack of an abnormal reclamation mechanism in the single-device zero-copy interface.

[0058] The three innovative technologies mentioned above are not simply an independent combination, but each makes a verifiable contribution to solving the technical problem: the unified descriptor provides layout information and quantization scale for zero-copy mapping, zero-copy mapping provides shared storage objects for reference counting management, and reference counting and lease reclamation provide secure lifecycle guarantees for zero-copy sharing. Together, they form a complete cross-chip zero-copy inference closed loop.

[0059] Anomalies and safety rollback When sensor status conflicts, model output inconsistencies, equipment temperature or power exceeding limits, communication interruptions, checkpoint damage, or critical safety category uncertainties exceeding thresholds occur, the system does not directly adopt the results to be confirmed. Instead, it stops reusing the current inference results and performs at least one of the following: re-acquisition, complete inference, backup node takeover, rollback to the previous stable version, or manual verification. It also saves the triggering reason, input version, and output verification information, and maintains a complete audit log. This safety rollback mechanism ensures the reliability and security of the inference results even when any component—sensor, model, hardware, or communication—is malfunctioning.

[0060] Through the above design, this embodiment can control the number of memory copies per frame to zero or once, reducing CPU utilization and memory bandwidth usage, shortening the end-to-end latency of multimodal fusion, reducing peak memory usage and memory fragmentation, and improving the concurrent stability of high-resolution multi-channel sensors. The above beneficial effects are demonstrated by actual test results using the same hardware, data, thresholds, and power consumption modes; specific experimental data can be found in Embodiment 2.

[0061] To address the three technical issues, this embodiment provides corresponding solutions: For multiple copies of multimodal data, the acquisition end directly writes to the buffer to eliminate the first copy; the CPU-side `frombuffer` creates a view to eliminate the copy from the buffer to the tensor; the accelerator-side DLPack / vendor device mapping eliminates the copy from the tensor to the accelerator memory; and conditional branches constrain copying to only one when layouts are incompatible. These three mechanisms together control the number of copies per frame to 0 or 1. For concurrent copying that consumes CPU, memory bus, and peak memory and increases latency, a pre-allocated hierarchical buffer pool avoids dynamic allocation overhead and memory fragmentation; zero-copy mapping reduces data transfer on the memory bus; and atomic reference counting supports concurrent reading of the same buffer by multiple consumers. With the reduction in the number of copies, CPU usage, memory bus usage, peak memory, and latency naturally decrease. For the lack of cross-process lifecycle, quantization scale, layout compatibility, and exception handling mechanisms, a unified buffer descriptor includes a quantization scale to address the missing quantization scale; layout compatibility checks and conditional branches address layout compatibility; atomic reference counting and release deduction address cross-process lifecycle issues; and a lease timeout exception handling process addresses the lack of exception handling mechanisms.

[0062] Example 2: Based on the technical solution described in Example 1, this example verifies its beneficial effects through simulation experiments.

[0063] Experimental environment The hardware utilizes the Mingfan MS-R1 (RK3588, 8GB) as the ARM / NPU edge node, and Huawei Ascend or other domestically produced GPU / NPU devices as acceleration nodes, along with a vehicle-mounted switch, UPS, ammeter, temperature recorder, and network damage simulator. The software employs Ubuntu / domestic operating systems or the actual vehicle-mounted system, Python 3.10, PyTorch 2.x, ONNX Runtime, and the target vendor's runtime, with fixed recording drivers, CANN / SDK, and model hashing. Data includes oilfield well site radar point clouds, infrared images, visible light video, meteorological data, GPS / IMU data, equipment telemetry, and emergency task sequences, with training, validation, and testing isolated by well site or date.

[0064] Performance tests were repeated at least 5 times per group, with the mean, standard deviation, and 95% confidence interval reported. Precision training used at least 3 random seeds. The control and experimental groups used the same input, confidence / IoU threshold, power consumption mode, number of warm-ups, and environmental conditions. Experiments centered on the design mean of A0–A4, generating 5 independent replicates per group. Latency, power consumption, temperature, and resource metrics used a coefficient of variation of approximately 1.8%–3.5%, while percentage metrics used a variation scale of approximately 0.12 percentage points or 0.6%. All random numbers used fixed seeds bound to patent serial numbers to ensure reproducible data and charts.

[0065] Ablation Comparison Experiment To verify the independent contribution of each distinguishing technical feature to the core metrics and to rule out the possibility of performance improvement solely through reduced accuracy or workload, this embodiment sets up five ablation groups, A0 to A4, progressively adding the core technical features of this invention. A0 is the baseline group, using conventional NumPy copying without any of the technical features of this invention; A1 introduces CPU shared memory on top of A0, eliminating the copying of buffers to CPU tensors; A2 introduces device mapping on top of A1, eliminating the copying of CPU tensors to accelerator memory; A3 introduces reference counting management on top of A2, achieving cross-process lifecycle management; A4 is the complete solution group, introducing a graceful garbage collector on top of A3, achieving abnormal reclamation due to lease timeout. Observed metrics include copy count, latency, CPU utilization, and peak memory usage.

[0066] The experimental results are shown in the table below.

[0067]

[0068] like Figure 5 As shown, each technical feature from A1 to A4 exhibits continuous and consistent gains. The copy count histogram and bandwidth-time curve visually demonstrate the correlation between the reduction in copy count and the decrease in memory bandwidth usage. The improvement in the primary metric copy / frame ratio between A0 and A4 is 90.5%, with Welcht test p=5.27e-09 and Cohen's d=-80.57, indicating statistical significance. For a combined fault injection of 2000 lease timeouts and incomplete accelerator queues, the graceful recovery success rate was 99.95%, with no illegal address accesses and a recovery completion latency (P95) of 18.6ms. From A0 to A4, with each additional core technical feature, copy count, latency, CPU utilization, and peak memory usage all continuously decrease, demonstrating that each distinguishing technical feature contributes independently to solving the technical problem, rather than being a simple summation.

[0069] Concurrent load comparison experiment To verify the robustness of this invention under different numbers of concurrent sensor streams and to demonstrate that the performance improvement is not solely achieved under a single ideal load, this embodiment sets up 1 to 5 concurrent sensor streams and tests the end-to-end latency of both conventional solutions and the present invention. This experiment corresponds to the data scale verification of different sensor stream count dimensions.

[0070]

[0071] like Figure 6As shown, with the increase in the number of concurrent sensor streams, the latency improvement of this invention compared to conventional solutions continues to increase. The scale-throughput curve shows that the throughput of this invention maintains an approximately linear growth with the increase in the number of concurrent streams, while the throughput growth of conventional solutions slows down significantly. With 1 concurrent stream, the latency improvement of this invention is 6.5%; with 5 concurrent streams, the improvement reaches 47.7%. This indicates that the higher the concurrent load, the greater the reduction in data copying by the zero-copy mechanism, and the more significant the reduction effect on CPU, memory bus, and peak memory. This invention maintains its technical effectiveness under conditions of high temperature, weak network, frame dropping, interference, concurrent load, or complex terrain.

[0072] Layout compatibility comparison experiment To verify the performance of the layout-aware reflow module under different layout and precision combinations, this embodiment tests the reflow ratio and operator latency under NCHW / NHWC layout switching, FP16 / INT8 precision switching, and point cloud structure array changes. The layout comparison bar chart shows that, under the above switching scenarios, the reflow ratio and operator latency of this invention are significantly lower than conventional solutions. This invention pre-determines layout compatibility by using the stride and memory format in the unified buffer descriptor. When compatible, only the view is transformed without reflow; only when incompatible, an alignment reflow is performed once, thereby keeping the reflow ratio and operator latency at a low level.

[0073] Abnormal recovery comparison experiment To verify the reliability of the graceful garbage collector under abnormal conditions, this embodiment tests memory leaks and recovery times under three abnormal scenarios: consumer crash, consumer timeout, and duplicate release. The memory usage timing diagram shows that under these abnormal scenarios, the memory usage of this invention can quickly recover to normal levels without persistent memory leaks. The graceful garbage collector identifies abnormal consumers by combining process liveness flags, heartbeat records, and lease renewal times. It performs garbage collection in the following order: isolating new tasks, stopping device queues, waiting for queue exhaustion, revoking device mappings, atomically deducting references, and returning memory to the memory pool. This ensures that the buffer can be safely reclaimed under abnormal conditions, preventing illegal address access and memory leaks.

[0074] Continuous running comparison experiment To verify the resource usage stability of the present invention under long-term continuous operation and to prove that the performance improvement is not a short-term peak result, this embodiment was run continuously for 30 minutes, and the CPU usage of the conventional scheme and the present invention was recorded every 5 minutes.

[0075]

[0076] like Figure 7As shown, the CPU utilization of the conventional solution continuously increases and fluctuates at a high level over time, while the CPU utilization of the present invention remains stable and is significantly lower than that of the conventional solution. The resource timing diagram also shows the changes in GPU, NPU, memory, power consumption, and temperature before and after the event. All resource indicators of the present invention remain stable without a continuous upward trend. The conventional solution's CPU utilization increased from 69.18% to 80.87% during 30 minutes of operation, showing a continuous upward trend, reflecting the impact of memory fragmentation and accumulated copying overhead. The CPU utilization of the present invention fluctuated stably between 44.06% and 48.67%, without a continuous upward trend, proving that the zero-copy mechanism and tiered memory pool effectively reduce memory fragmentation and accumulated copying overhead.

[0077] Typical scenario comparison experiment To comprehensively verify the technical effects of the present invention under typical oilfield emergency scenarios and avoid comparisons only under a single ideal scenario, this embodiment sets up four scenarios: standard operating condition, high temperature operating condition, weak network operating condition, and night / obstruction operating condition, and tests the end-to-end latency of conventional solutions and the present invention respectively.

[0078] The experimental results are shown in the table below.

[0079]

[0080] like Figure 8 As shown, the present invention maintains significant latency improvement in all four scenarios. The present invention improves latency by 90.5% under standard operating conditions, 91.8% under high-temperature conditions, 92.3% under weak network conditions, and 92.1% under nighttime / obstructed conditions. The improvement exceeds 90% in all four scenarios, and the improvement in severe conditions is slightly higher than that in standard operating conditions, proving that the technical effect of the present invention remains stable and reliable under complex environmental conditions.

[0081] Figure 5 The core ablation histogram demonstrates continuous and consistent gain across the technical features from A1 to A4, and reports the mean, standard deviation, and sample size. Figure 6 The environmental / load robustness line graph demonstrates that the invention maintains its technical effectiveness under conditions of high temperature, weak network, frame dropping, interference, concurrent load, or complex terrain. Figure 7 Continuous operation resource timing diagrams show the changes in temperature, power consumption, utilization, backlog, or error over time, proving that it is not a short-term peak result; Figure 8Typical scenario grouping plots provide results for standard, high temperature, weak network, and night / occlusion conditions, avoiding comparisons based solely on a single ideal scenario; the accuracy-efficiency scatter plot supplements the relationship between key safety categories Recall / mAP and latency and power consumption during actual testing, demonstrating that performance improvements do not come at the expense of significant safety and accuracy; typical case process diagrams retain inputs, key intermediate states, scheduling or rollback actions, final outputs, and timestamps, forming an evidence chain from technical features to technical effects; original logs and reproducible materials include CSV, model hashes, code version, hardware model, driver / CANN version, random seed, power consumption instruments, and descriptions of anomalous samples.

[0082] Experimental conclusions Under the aforementioned experimental conditions, the complete scheme A4, compared to baseline A0, reduces the main performance index replication / frame by approximately 90.5%, while maintaining directional consistency under varying environmental / load conditions and continuous operation. This invention is applicable to oilfield well sites, tank farms, pipelines, and other mobile emergency command scenarios. During implementation, parameters can be adjusted accordingly based on the actual radar model, domestic computing platform, and vehicle layout. The above description of the technical solution provided by the present invention through several specific embodiments is intended to highlight the advantages and benefits of the technical solution provided by the present invention. However, the above-described specific embodiments are not intended to limit the present invention. Any reasonable modifications and improvements to the present invention, reasonable combinations of implementation methods and equivalent substitutions based on the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A cross-chip zero-copy inference method for multimodal data of mobile radar, characterized in that the method... include: S1: Pre-allocate size-based page locking or shared buffer pools for each sensor; S2: The acquisition end directly writes the sensor data into the buffer in the buffer pool and generates a unified buffer descriptor corresponding to the buffer. S3: Check the layout compatibility of the buffer based on the stride and memory format in the unified buffer descriptor. If the layout is compatible, create a tensor view of the buffer on the CPU side and establish a shared mapping to the underlying storage of the buffer on the accelerator side. If the layout is incompatible, perform an alignment rearrangement on the buffer and then establish the tensor view and the underlying storage sharing. S4: When a consumer obtains the tensor view or the underlying storage, the reference count of the unified buffer descriptor is incremented atomically according to the number of consumers; S5: When a consumer releases the tensor view or the underlying storage, deduct the reference count. When the lease times out, sequentially perform abnormal consumer isolation, device queue emptying, device mapping cancellation, and reference deduction. After the total reference count is zero and the device mapping has been cancelled, reclaim the buffer to the buffer pool.

2. The method according to claim 1, characterized in that, The unified buffer descriptor includes physical buffer identifier, shape, stride, dtype, device, timestamp, quantization scale, reference count, and version number; the quantization scale is used for quantization and dequantization of data between the CPU side and the accelerator side, so that the underlying storage shared across chips maintains semantic consistency between computing nodes with different precision.

3. The method according to claim 1, characterized in that, The determination of abnormal consumers whose leases have expired is completed by the recycling manager in conjunction with the consumer process liveness flag, heartbeat record, and lease renewal time; a single signal abnormality only marks the consumer as a suspected abnormality and does not immediately release the physical buffer it occupies.

4. The method according to claim 3, characterized in that, For the suspected abnormal consumer, the recycling manager sets its descriptor status to isolated, stops dispatching new buffer descriptors to it, and sends a stop or cancel command to the corresponding accelerator queue through device events, DMA fences, or vendor runtime interfaces. The recycling manager waits for the submitted device tasks to complete and queries the queue exhaustion status. If the task is not completed within the second timeout window, the recycling manager resets the device context corresponding to the consumer and isolates its device mapping.

5. The method according to claim 1, characterized in that, The reference deduction uses an atomic comparison swap method, deducting the reference count of the abnormal consumer only once; after the device mapping is revoked, subsequent access to the buffer returns an invalid status.

6. The method according to claim 1, characterized in that, When the buffer is reclaimed, a reclamation log is generated. The reclamation log records at least the descriptor version, the abnormal consumer identifier, the stop command time, the queue exhaustion time, the mapping revocation result, and the final reclamation status.

7. The method according to claim 1, characterized in that, When sensor status conflicts, model output inconsistencies, device temperature or power exceeding limits, communication interruptions, checkpoint damage, or critical safety category uncertainty exceeding the threshold occur, the reuse of the current inference result is stopped, and at least one of the following is executed: re-acquisition, complete inference, standby node takeover, rollback to the previous stable version, or manual review. The triggering reason, input version, and output verification information are saved.

8. The method according to claim 1, characterized in that, Input data includes at least radar point cloud buffers, visible / infrared frames, meteorological data, tensor layout and quantization scale, and consumer dependencies. Each input data is associated with a unified timestamp or version number. All records include at least a timestamp, source node, version number, validity flag, and verification field. Records involving model output also include model hash, threshold configuration, and hardware execution node.

9. A cross-chip zero-copy inference system for implementing the method of any one of claims 1 to 8, characterized in that, It includes a hierarchical memory pool, a unified buffer descriptor management module, a layout-aware reordering module, a tensor adapter, a reference counting and lease management module, and a graceful garbage collector; The hierarchical memory pool is used to pre-allocate page-locked or shared buffers according to size for each sensor, and to receive buffers reclaimed by the graceful recycling manager; The unified buffer descriptor management module is used to generate a unified buffer descriptor corresponding to the buffer after the sensor data is directly written into the buffer at the acquisition end. The layout-aware rearrangement module is connected to the unified buffer descriptor management module and is used to check the layout compatibility of the buffer according to the stride and memory format in the unified buffer descriptor. When the layout is compatible, it outputs a direct mapping instruction to the tensor adapter. When the layout is incompatible, it performs an alignment rearrangement on the buffer and then outputs a mapping instruction to the tensor adapter. The tensor adapter is connected to the layout-aware rearrangement module and is used to create a tensor view of the buffer on the CPU side via frombuffer according to the direct mapping instruction and to map and share the underlying storage of the buffer on the accelerator side via DLPack or vendor equipment, and to establish the sharing of the tensor view and the underlying storage according to the mapping instruction. The reference counting and lease management module is connected to the tensor adapter and is used to atomically increase the reference count of the unified buffer descriptor according to the number of consumers when the consumer obtains the tensor view or the underlying storage, and to deduct the reference count when the consumer releases the tensor view or the underlying storage. The elegant recycling manager is connected to the reference counting and lease management module, the accelerator device queue and mapping management interface, respectively. It is used to sequentially perform abnormal consumer isolation, device queue emptying, device mapping cancellation and reference deduction when the lease expires, and recycle the buffer to the hierarchical memory pool after the total reference count is zero and the device mapping has been cancelled.

10. A computer device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor performs the method according to any one of claims 1-8.

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