An AI chip memory verification method, device, equipment and storage medium

Abstract

The application discloses a memory verification method, device and equipment of an AI chip, and a storage medium, and the method is applied to a memory verification platform, and the method comprises the following steps: in response to target verification content filled in a standard template by a verification personnel according to content filling specifications, determining a target memory interface type and verification code to be instantiated according to the target verification content; determining logical content of a reference model corresponding to a bare chip according to the target memory interface type and the verification code to be instantiated; the reference model is used for simulating the behavior of a real RTL of the bare chip; and determining memory data check results or memory performance analysis results corresponding to the bare chip according to the logical content of the reference model and interface monitoring results corresponding to the bare chip of the memory verification platform. The technical scheme of the embodiment of the application can support the verification personnel to verify various different memory types, and quickly output the memory data check results or the memory performance analysis results corresponding to the bare chip.

Description

Technical Field

[0001] This invention relates to the field of speech synthesis technology, and in particular to a memory verification method, apparatus, device, and storage medium for an AI chip. Background Technology

[0002] Currently, in the design of artificial intelligence (AI) chips, different types of memory are switched to adapt to different projects based on power consumption and performance requirements. Examples include third-generation high-bandwidth memory (HBM3), enhanced third-generation high-bandwidth memory (HBM3E), second-generation enhanced high-bandwidth memory (HBM2E), and sixth-generation graphics double data rate memory (GDDR6). In addition, collaborations are made with different memory chip manufacturers based on project architecture decisions. The verifiable models provided by different chip manufacturers for the same type of double data rate (DDR) memory may also be inconsistent, so adaptation and compatibility with existing verification environments are required.

[0003] With the development of AI chips, existing memory verification methods have the following technical shortcomings: For the same type of DDR memory, when there are version updates, specification optimizations, or modifications to some parameters, due to the dispersed code and the inability to unify across multiple projects, verification personnel need to re-adapt to all places on the verification platform that use this code or updated parameters, which is prone to omissions; For switching between different types of DDR memory in different projects, it is necessary to first obtain the verification environment of the previous project, then perform partial adaptation based on it, and develop verification code that can be used for the new DDR memory, which is labor-intensive and inefficient; Depending on the project decision requirements, the third party providing DDR memory may be changed. Therefore, whether for performance evaluation in the early stage or for development needs in the later stage, being able to quickly master the verification models provided by different memory chip manufacturers is also a problem that verification personnel need to face. Summary of the Invention

[0004] This invention provides a method, apparatus, device, and storage medium for verifying the memory of AI chips. It can support verification personnel to verify various memory types and quickly output the memory data verification results or memory performance analysis results corresponding to the bare chip, so that AI chip architects can promptly modify and optimize the chip architecture and save project development time.

[0005] According to one aspect of the present invention, a memory verification method for an AI chip is provided. The method is applied to a memory verification platform, which is connected to a bare chip within the AI ​​chip via a memory interface. The method includes: In response to the target verification content filled in by the verification personnel in the standard template according to the content filling specifications, the target memory interface type and the verification code to be instantiated are determined based on the target verification content. Based on the target memory interface type and the verification code to be instantiated, the logical content of the reference model corresponding to the bare chip is determined; the reference model is used to simulate the behavior of the bare chip's real register transfer level (RTL). Based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip, the memory data verification result or memory performance analysis result corresponding to the bare chip is determined.

[0006] Optionally, after determining the target memory interface type based on the target verification content, the method further includes: The preset interface code corresponding to the target memory interface type is instantiated, and then the memory verification platform is connected to the top layer of the bare chip according to the instantiated interface code.

[0007] Optionally, based on the target verification content, the verification code to be instantiated is determined, including: Based on the target verification content, determine the behavior code of the memory granular model to be instantiated or the behavior code corresponding to the verification intellectual property (IP) interface; The memory particle model and verification IP interface are used to simulate the logical functions of the memory particles.

[0008] Optionally, based on the target memory interface type and the verification code to be instantiated, the logical content of the reference model corresponding to the bare chip is determined, including: Based on the target memory interface type, the behavior code of the memory granule model to be instantiated, or the behavior code corresponding to the verification IP interface, perform mapping or transformation operations on the memory address in the bare chip; Based on the memory address mapping results or address transformation results in the bare chip, the logical content of the reference model corresponding to the bare chip is determined.

[0009] Optionally, the method further includes: The system monitors the signals corresponding to the memory chip input interface, memory controller input interface, and memory physical layer input interface in the AI ​​chip in real time, and records the starting point data and response data corresponding to the signals. The interface monitoring result is generated based on the signal, the corresponding starting point data, and the response data.

[0010] Optionally, based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip, the memory data verification result or memory performance analysis result corresponding to the bare chip is determined, including: In response to the verification requirements filled in by the verification personnel in the standard template, the memory data verification result or memory performance analysis result corresponding to the bare chip is determined based on the verification requirements, the logical content of the reference model, and the interface monitoring results.

[0011] Optionally, based on the verification requirements, the logical content of the reference model, and the interface monitoring results, the memory data verification result or memory performance analysis result corresponding to the bare chip is determined, including: If the verification requirement is design verification, then the logical content of the reference model and the read / write data of the memory particles are verified to obtain the memory data verification result. If the verification requirement is physical verification, then based on the memory data verification results and interface monitoring results, the read and write functions of the memory chip are analyzed to obtain memory performance analysis results.

[0012] According to another aspect of the present invention, a memory verification apparatus for an AI chip is provided. The apparatus is applied to a memory verification platform, the memory verification platform being connected to a bare chip in the AI ​​chip via a memory interface. The apparatus includes: The memory interface selection module is used to respond to the target verification content filled in by the verifier in the standard template according to the content filling specifications, and to determine the target memory interface type and the verification code to be instantiated based on the target verification content. The reference model filling module is used to determine the logical content of the reference model corresponding to the bare chip based on the target memory interface type and the verification code to be instantiated; the reference model is used to simulate the behavior of the real RTL of the bare chip. The data analysis module is used to determine the memory data verification result or memory performance analysis result corresponding to the bare chip based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to said at least one processor; The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute the memory verification method of the AI ​​chip according to any embodiment of the present invention.

[0014] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the memory verification method of the AI ​​chip according to any embodiment of the present invention.

[0015] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the memory verification method for an AI chip according to any embodiment of the present invention.

[0016] The technical solution provided by this invention, in response to the target verification content filled in by verification personnel in a standard template according to the content filling specifications, determines the target memory interface type and the verification code to be instantiated based on the target verification content, determines the logical content of the reference model corresponding to the bare chip based on the target memory interface type and the verification code to be instantiated, and determines the memory data verification result or memory performance analysis result corresponding to the bare chip based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip. This provides a memory verification platform that can quickly adapt to various DDR memory types and uses as many automated scripts as possible in its configuration. It can support verification personnel to verify multiple different memory types and quickly output the memory data verification result or memory performance analysis result corresponding to the bare chip, so that AI chip architects can promptly correct and optimize the chip architecture and save project development time.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a memory verification method for an AI chip according to an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the connection between a memory verification platform and a bare chip according to an embodiment of the present invention; Figure 3 This is a flowchart of another memory verification method for an AI chip provided according to an embodiment of the present invention; Figure 4 This is a flowchart of another memory verification method for an AI chip provided according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a memory verification device for an AI chip according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device that implements the memory verification method for the AI ​​chip in this embodiment of the invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 This is a flowchart illustrating a memory verification method for an AI chip according to an embodiment of the present invention. This embodiment is applicable to memory verification of bare chips within an AI chip. The method can be executed by a memory verification device for the AI ​​chip. This device can be implemented in hardware and / or software and configured on a memory verification platform. The memory verification platform is connected to the bare chip in the AI ​​chip via a memory interface, such as... Figure 1 As shown, the method includes: Step 110: In response to the target verification content filled in by the verification personnel in the standard template according to the content filling specifications, determine the target memory interface type and the verification code to be instantiated based on the target verification content.

[0023] In this embodiment, Figure 2 This could be a schematic diagram illustrating the connection between a memory verification platform and a bare chip, such as... Figure 2 As shown, an AI chip may contain multiple bare chips (e.g., AI bare chip 0, AI bare chip 1, AI bare chip 2, AI bare chip 3, etc.). As the number of bare chips increases, the corresponding memory chips ( Figure 2 (Not shown) is also added accordingly. Each bare chip is connected using chip-to-chip technology, and each bare chip corresponds one-to-one with each memory verification platform. Each memory verification platform is connected to its corresponding bare chip through a memory interface.

[0024] Specifically, the memory chip is a storage unit used for temporary storage of data processed by the bare chip, such as storing training data and intermediate calculation results corresponding to the bare chip.

[0025] In this embodiment, a standard template with fixed rules can be pre-built. Verifiers can fill in forms or documents according to the established rules of the standard template to obtain the target verification content. Then, the target verification content is analyzed, processed, and packaged through a preset script file. Finally, a verification language code that can be recognized and used by the content verification platform is generated, and the subsequent verification simulation process is completed accordingly.

[0026] In a specific embodiment, after obtaining the target verification content in the above manner, the target memory interface type can be extracted from the target verification content, and the verification code to be instantiated corresponding to the memory particle can be determined according to the memory particle associated with the target verification content.

[0027] Optionally, the verification codes corresponding to different memory chips can be pre-stored in the memory verification platform. That is, the verification codes of various DDR types commonly used in AI chips can be stored in one memory verification platform, which facilitates the switching and management of multiple DDR types. Furthermore, as the number of memory chips increases, the number of memory verification platforms can be increased accordingly, thereby improving the flexibility of the memory verification method.

[0028] Step 120: Determine the logical content of the reference model corresponding to the bare chip based on the target memory interface type and the verification code to be instantiated; the reference model is used to simulate the behavior of the real RTL of the bare chip.

[0029] In this embodiment, optionally, the verification code can be instantiated first, and the protocol specifications, timing parameters and interaction signals of the target memory interface can be parsed. Then, feature data of the bare chip storage interaction behavior can be extracted based on the parsing results. Finally, the logical content of the reference model can be generated based on the feature data of the bare chip storage interaction behavior, as well as the stimulus data, read and write operations and verification logic of the verification code.

[0030] Specifically, RTL code can be the low-level code describing the bare chip hardware circuit. The reference model is used to simulate the logical functions of the low-level code, such as simulating the real behaviors of the bare chip, such as address assignment, data throughput, and error checking.

[0031] Step 130: Based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip, determine the memory data verification result or memory performance analysis result corresponding to the bare chip.

[0032] In this step, specifically, the accuracy verification or performance analysis of the memory data corresponding to the bare chip can be performed based on the simulation results of the reference model and the interface monitoring results between the memory verification platform and the bare chip.

[0033] In this embodiment, the method further includes: real-time monitoring of signals corresponding to the memory chip input interface, memory controller input interface, and memory physical layer input interface in the AI ​​chip, and recording the starting point data and response data corresponding to the signals; generating the interface monitoring results based on the signals and the starting point data and response data corresponding to the signals.

[0034] Specifically, such as Figure 2 As shown, the memory interface may include a memory controller input interface and a memory physical layer input interface. The memory controller input interface refers to the top-level interface of each memory controller module in the bare chip, and the memory physical layer input interface refers to the top-level interface of each physical layer module in the bare chip.

[0035] The technical solution provided by this invention, in response to the target verification content filled in by verification personnel in a standard template according to the content filling specifications, determines the target memory interface type and the verification code to be instantiated based on the target verification content, determines the logical content of the reference model corresponding to the bare chip based on the target memory interface type and the verification code to be instantiated, and determines the memory data verification result or memory performance analysis result corresponding to the bare chip based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip. This provides a memory verification platform that can quickly adapt to various DDR memory types and uses as many automated scripts as possible in its configuration. It can support verification personnel to verify multiple different memory types and quickly output the memory data verification result or memory performance analysis result corresponding to the bare chip, so that AI chip architects can promptly modify and optimize the chip architecture, saving project development time. Furthermore, as the number of bare chips in AI chips continues to increase, the technical solution provided by this embodiment can effectively iterate and expand the memory verification platform, making advance plans for saving development and verification costs in the future.

[0036] Figure 3 A flowchart of another memory verification method for an AI chip provided in an embodiment of the present invention is shown below. Figure 3 As shown, the method includes: Step 210: In response to the target verification content filled in by the verification personnel in the standard template according to the content filling specifications, determine the target memory interface type based on the target verification content.

[0037] Step 220: Instantiate the preset interface code corresponding to the target memory interface type, and then connect the memory verification platform to the top layer of the bare chip according to the instantiated interface code.

[0038] Step 230: Based on the target verification content, determine the behavior code of the memory granular model to be instantiated or the behavior code corresponding to the verification IP interface.

[0039] In this step, the verification code to be instantiated corresponding to the memory particle can be determined based on the memory particle associated with the target verification content. For example, the behavior code of the memory particle model provided by the memory particle manufacturer, or the behavior code corresponding to the verification interface provided by a third party.

[0040] The memory particle model and verification IP interface are used to simulate the logical functions of the memory particles.

[0041] The advantage of this setup is that it supports multiple instantiation modes for memory chips, avoiding over-reliance on memory chip manufacturers. Although memory chip model adaptation is more convenient, the verification results obtained using the behavioral models provided by memory chip manufacturers are less convincing. Therefore, by combining the verification IP interface of a third-party unified protocol to perform cross-validation, the accuracy of memory chip verification results can be guaranteed more completely.

[0042] Step 240: Based on the target memory interface type, the behavior code of the memory granule model to be instantiated, or the behavior code corresponding to the verification IP interface, perform mapping or transformation operations on the memory addresses in the bare chip. Based on the memory address mapping results or address transformation results in the bare chip, determine the logical content of the reference model corresponding to the bare chip.

[0043] Step 250: In response to the verification requirements filled in by the verification personnel in the standard template, determine the memory data verification results or memory performance analysis results corresponding to the bare chip based on the verification requirements, the logical content of the reference model, and the interface monitoring results.

[0044] In this embodiment, the memory data verification result or memory performance analysis result corresponding to the bare chip is determined based on the verification requirement, the logical content of the reference model, and the interface monitoring result. This includes: if the verification requirement is Design Verification (DV), the logical content of the reference model and the read / write data of the memory chip are verified to obtain the memory data verification result; if the verification requirement is Physical Verification (PV), the read / write function of the memory chip is analyzed based on the memory data verification result and the interface monitoring result to obtain the memory performance analysis result.

[0045] In one specific embodiment, the simulated memory chip read / write data can be compared with the expected data, and the memory data verification result can be determined based on the comparison result. Additionally, performance analysis can be performed on the data received at different stages in the memory chip based on the memory data verification result and the time parameters of relevant data in the interface monitoring results, to determine whether the AI ​​chip's performance in memory data read / write functions meets the preset development requirements.

[0046] The technical solution provided in this invention responds to the target verification content filled in by the verification personnel in a standard template according to the content filling specifications. Based on the target verification content, the target memory interface type is determined. The preset interface code corresponding to the target memory interface type is instantiated. Then, the memory verification platform is connected to the top layer of the bare chip based on the instantiated interface code. Based on the target verification content, the behavior code of the memory granular model to be instantiated or the behavior code corresponding to the verification IP interface is determined. Based on the target memory interface type, the behavior code of the memory granular model to be instantiated, or the behavior code corresponding to the verification IP interface, a mapping or transformation operation is performed on the memory addresses in the bare chip. The address mapping or address transformation results determine the logical content of the reference model corresponding to the bare chip. Responding to the verification requirements filled in by the verification personnel in the standard template, the platform determines the memory data verification results or memory performance analysis results corresponding to the bare chip based on the verification requirements, the logical content of the reference model, and the interface monitoring results. It provides a memory verification platform that can quickly adapt to various DDR memory types and uses as many automated scripts as possible in its configuration. It can support verification personnel to verify multiple different memory types and quickly output the memory data verification results or memory performance analysis results corresponding to the bare chip, so that AI chip architects can make timely corrections and optimizations to the chip architecture and save project development time.

[0047] Based on the above embodiments, to better explain the technical solution provided in this embodiment, please refer to... Figure 4 The flowchart shown illustrates the memory verification method, and the execution steps of the memory verification method include: Enable the initialization of the memory verification platform, instantiate the memory verification platform according to the number of bare chips set in the current project, and connect the memory verification platform to the top layer of the AI ​​chip according to the DDR interface; Verification personnel fill in the required forms for controlling the memory verification platform in the standard template, including specified parameters and models, etc. The memory verification platform selects the memory model and memory interface type according to the set parameters, and determines the logic content to be executed by the verification model to be instantiated or the logic content to be executed by the verification IP interface to be instantiated based on the selection result. After determining the reference model logic content based on the above-mentioned logic content to be instantiated, the reference model begins to perform simulation work and outputs data simulation results; Given the different focuses of the various verification teams, based on the performance analysis needs of the PV team, a large number of interface data monitoring results were obtained and analyzed; based on the data sensitivity requirements of the DV team, the accuracy of the data simulation results was verified.

[0048] Figure 5This is a schematic diagram of a memory verification device for an AI chip provided in an embodiment of the present invention. The device is applied to a memory verification platform, which is connected to the bare chip in the AI ​​chip via a memory interface, such as... Figure 5 As shown, the device includes: a memory interface selection module, a reference model filling module, and a data analysis module (including a data verification module and a memory performance analysis module).

[0049] The memory interface selection module is used to respond to the target verification content filled in by the verifier in the standard template according to the content filling specifications, and to determine the target memory interface type and the verification code to be instantiated based on the target verification content. The reference model filling module is used to determine the logical content of the reference model corresponding to the bare chip based on the target memory interface type and the verification code to be instantiated; the reference model is used to simulate the behavior of the real RTL of the bare chip. The data analysis module is used to determine the memory data verification result or memory performance analysis result corresponding to the bare chip based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip.

[0050] The technical solution provided by this invention, in response to the target verification content filled in by verification personnel in a standard template according to the content filling specifications, determines the target memory interface type and the verification code to be instantiated based on the target verification content, determines the logical content of the reference model corresponding to the bare chip based on the target memory interface type and the verification code to be instantiated, and determines the memory data verification result or memory performance analysis result corresponding to the bare chip based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip. This provides a memory verification platform that can quickly adapt to various DDR memory types and uses as many automated scripts as possible in its configuration. It can support verification personnel to verify multiple different memory types and quickly output the memory data verification result or memory performance analysis result corresponding to the bare chip, so that AI chip architects can promptly correct and optimize the chip architecture and save project development time.

[0051] Based on the above embodiments, such as Figure 5 As shown, the device also includes: a verification platform control module, an interface monitoring module, a memory logic filling module, a configuration parameter filling module, and a verification platform display module.

[0052] The verification platform control module is the central hub of the entire memory verification platform. Verification personnel only need to fill out forms or documents according to predetermined rules. This module contains script files for processing all forms and documents. These script files are sent to this module for analysis, processing, and packaging, ultimately generating verification language code that the memory verification platform can recognize and use, thus completing the subsequent verification and simulation process.

[0053] The memory interface selection module is also used to instantiate the preset interface code corresponding to the target memory interface type, and then connect the memory verification platform to the top layer of the bare chip according to the instantiated interface code; determine the behavior code of the memory particle model to be instantiated or the behavior code corresponding to the verification IP interface according to the target verification content; the memory particle model and the verification IP interface are used to simulate the logical function of the memory particle.

[0054] The reference model filling module is further configured to perform mapping or transformation operations on the memory addresses in the bare chip according to the target memory interface type, the behavior code of the memory granule model to be instantiated, or the behavior code corresponding to the verification IP interface; and determine the logical content of the reference model corresponding to the bare chip according to the memory address mapping result or address transformation result in the bare chip.

[0055] The interface monitoring module is used to monitor the signals corresponding to the memory chip input interface, memory controller input interface, and memory physical layer input interface in the AI ​​chip in real time, and record the starting point data and response data corresponding to the signals; based on the signals and the starting point data and response data corresponding to the signals, the interface monitoring results are generated. The protocols corresponding to the above interfaces may be DDR interface protocols, Advanced eXtensible Interface (AXI) protocols, Advanced High-performance Bus (AHB) protocols, Advanced Peripheral Bus (APB) interface protocols, DDR memory physical layer interface protocols (DDR PHY Interface (DFI) protocols, etc., and this embodiment does not limit them.

[0056] The memory logic filling module is used to complete the logical functions of the memory chips. It stores all the behavior code of the memory chips and selects to fill the memory chips based on the interface, using either the behavior code of the model or the behavior code corresponding to the verification IP interface.

[0057] The configuration parameter filling module is used to receive all parameters input by the verification platform control module, and uniformly package and distribute them to different modules within the verification platform, so that these modules can accurately instantiate the corresponding verification code and enable related functions in their respective modules when they receive the parameters.

[0058] The data analysis module (including a data verification module and a memory performance analysis module) is used to respond to the verification requirements filled in by the verification personnel in the standard template, and determine the memory data verification result or memory performance analysis result corresponding to the bare chip based on the verification requirements, the logical content of the reference model, and the interface monitoring results.

[0059] The data verification module is used to verify the logical content of the reference model and the read / write data of the memory particles if the verification requirement is design verification, and to obtain the memory data verification result; the memory performance analysis module is used to perform performance analysis on the read / write function of the memory particles based on the memory data verification result and the interface monitoring result if the verification requirement is physical verification, and to obtain the memory performance analysis result.

[0060] The verification platform display module is used to process the output of the entire verification platform through scripts and present it to the verification personnel in a visually appealing way, such as a webpage, bar chart, or line chart, so that the verification personnel can easily view and analyze it.

[0061] The above-described apparatus can execute the methods provided in all the foregoing embodiments of the present invention, and has the corresponding functional modules and beneficial effects for executing the above methods. Technical details not described in detail in the embodiments of the present invention can be found in the methods provided in all the foregoing embodiments of the present invention.

[0062] Figure 6 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0063] like Figure 6As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) or a random access memory (RAM), communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the read-only memory 12 or loaded from the storage unit 18 into the random access memory 13. The random access memory 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, the read-only memory 12, and the random access memory 13 are interconnected via a bus 14. Input / output (I / O) interfaces are also connected to the bus 14.

[0064] Multiple components in electronic device 10 are connected to input / output interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of monitors, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0065] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processing (DSP) processors, and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the memory verification method for an AI chip.

[0066] In some embodiments, the memory verification method for the AI ​​chip can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via read-only memory 12 and / or communication unit 19. When the computer program is loaded into random access memory 13 and executed by processor 11, one or more steps of the memory verification method for the AI ​​chip described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the memory verification method for the AI ​​chip by any other suitable means (e.g., by means of firmware).

[0067] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chips (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0068] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0069] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0070] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0071] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0072] A computing system can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system. It addresses the shortcomings of traditional physical hosts and Virtual Private Servers (VPS) in terms of management difficulty and weak business scalability.

[0073] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0074] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A memory verification method for an AI chip, characterized in that, The method is applied to a memory verification platform, which is connected to a bare chip in an AI chip via a memory interface. The method includes: In response to the target verification content filled in by the verification personnel in the standard template according to the content filling specifications, the target memory interface type and the verification code to be instantiated are determined based on the target verification content. Based on the target memory interface type and the verification code to be instantiated, the logical content of the reference model corresponding to the bare chip is determined; the reference model is used to simulate the behavior of the real RTL of the bare chip. Based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip, the memory data verification result or memory performance analysis result corresponding to the bare chip is determined.

2. The method according to claim 1, characterized in that, After determining the target memory interface type based on the target verification content, the process also includes: The preset interface code corresponding to the target memory interface type is instantiated, and then the memory verification platform is connected to the top layer of the bare chip according to the instantiated interface code.

3. The method according to claim 1, characterized in that, Based on the target verification content, determine the verification code to be instantiated, including: Based on the target verification content, determine the behavior code of the memory granular model to be instantiated or the behavior code corresponding to the verification intellectual property IP interface. The memory particle model and verification IP interface are used to simulate the logical functions of the memory particles.

4. The method according to claim 3, characterized in that, Based on the target memory interface type and the verification code to be instantiated, determine the logical content of the reference model corresponding to the bare chip, including: Based on the target memory interface type, the behavior code of the memory granule model to be instantiated, or the behavior code corresponding to the verification IP interface, perform mapping or transformation operations on the memory address in the bare chip; Based on the memory address mapping results or address transformation results in the bare chip, the logical content of the reference model corresponding to the bare chip is determined.

5. The method according to claim 1, characterized in that, The method further includes: The system monitors the signals corresponding to the memory chip input interface, memory controller input interface, and memory physical layer input interface in the AI ​​chip in real time, and records the starting point data and response data corresponding to the signals. The interface monitoring result is generated based on the signal, the corresponding starting point data, and the response data.

6. The method according to claim 1, characterized in that, Based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip, the memory data verification result or memory performance analysis result corresponding to the bare chip is determined, including: In response to the verification requirements filled in by the verification personnel in the standard template, the memory data verification result or memory performance analysis result corresponding to the bare chip is determined based on the verification requirements, the logical content of the reference model, and the interface monitoring results.

7. The method according to claim 6, characterized in that, Based on the verification requirements, the logical content of the reference model, and the interface monitoring results, determine the memory data verification results or memory performance analysis results corresponding to the bare chip, including: If the verification requirement is design verification, then the logical content of the reference model and the read / write data of the memory particles are verified to obtain the memory data verification result. If the verification requirement is physical verification, then based on the memory data verification results and interface monitoring results, the read and write functions of the memory chip are analyzed to obtain memory performance analysis results.

8. A memory verification device for an AI chip, characterized in that, The device is used in a memory verification platform, which is connected to a bare chip in an AI chip via a memory interface. The device includes: The memory interface selection module is used to respond to the target verification content filled in by the verifier in the standard template according to the content filling specifications, and to determine the target memory interface type and the verification code to be instantiated based on the target verification content. The reference model filling module is used to determine the logical content of the reference model corresponding to the bare chip based on the target memory interface type and the verification code to be instantiated; the reference model is used to simulate the behavior of the real RTL of the bare chip. The data analysis module is used to determine the memory data verification result or memory performance analysis result corresponding to the bare chip based on the logical content of the reference model and the interface monitoring results between the memory verification platform and the bare chip.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to said at least one processor; The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the memory verification method of the AI ​​chip according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the memory verification method of the AI ​​chip according to any one of claims 1-7.

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