Data storage device and operating method for avoiding programming operation delay due to size of parity check buffer

Abstract

A memory system includes a memory device and a controller. The memory device includes a plurality of data storage areas. The controller is configured to, when at least one area among the plurality of data storage areas is in an idle state and a time at which a first parity corresponding to a plurality of first data is stored in a first parity buffer is greater than a reference time, secure an available space in the first parity buffer by migrating the first parity from the first parity buffer to a second parity buffer, generate a second parity corresponding to a plurality of second data, and store the second parity in the available space in the first parity buffer.

Description

Cross-references to related applications

[0001] This patent application claims priority to Korean Patent Application No. 10-2025-0054437, filed on April 25, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The one or more embodiments of this disclosure described herein relate to a data storage device or memory system, and more specifically, to a data storage device and method for avoiding programming operation delays caused by a parity buffer. Background Technology

[0003] A data processing system, comprising a memory system or data storage device, is being developed to store more data in the data storage device, store data in the data storage device faster, and output data stored in the data storage device faster. The data storage device may include non-volatile memory cells and / or volatile memory cells for storing data. Furthermore, each memory cell may store multiple bits of data. The memory system generates and stores a parity check associated with multiple data stored in multiple storage areas, thereby ensuring data security through the parity check. Summary of the Invention

[0004] Embodiments of this disclosure may provide a memory device, a memory system including the memory device, a controller included in the memory system, or a data processing device including the memory system.

[0005] Embodiments of this disclosure may provide an apparatus and method of operation for improving data input / output performance in a memory system during write operations that store large amounts of data in the memory system by reducing or avoiding latency in write operations where the controller generates at least one parity check for multiple data items due to buffer size limitations.

[0006] Embodiments of this disclosure provide an apparatus and operating method that reduce or avoid delays in programming operations performed in multiple regions by identifying at least some regions where programming operations are not performed, and moving or migrating the parity check and associated data from the first buffer to a second buffer when the parity check and associated data are retained or stored in the first buffer for a period of time or longer than a preset reference time, thereby reducing or avoiding delays in programming operations performed in at least some regions where programming operations are not performed.

[0007] In an embodiment, a memory system may include: a memory device including a plurality of data storage areas; and a controller configured to: when at least one of the plurality of data storage areas is idle and the time for which a first parity corresponding to a plurality of first data is stored in a first buffer is greater than a reference time, generate a second parity corresponding to a plurality of second data by migrating the first parity from the first parity buffer to a second parity buffer to ensure available space in the first parity buffer, and store the second parity in the available space in the first parity buffer.

[0008] The first parity buffer can have a faster data input and output (input / output) speed than the second parity buffer.

[0009] A first parity buffer can be set or created in static random access memory (SRAM), and a second parity buffer can be set or created in dynamic random access memory (DRAM).

[0010] The controller can be configured to migrate a first parity group, including a first parity check and a plurality of first data, from a first parity buffer to a second parity buffer.

[0011] The controller can be configured to release the first parity group from the second parity buffer based on a programming completion notification from the memory device for the first parity and a plurality of first data.

[0012] The controller can be configured to receive multiple data from an external device, determine multiple first data from the multiple data, and map the physical addresses of the multiple first data stored in the memory device to the logical addresses of the multiple first data.

[0013] In a memory device, read operations, programming operations, and erase operations can be performed independently in each of multiple data storage areas. When an erase operation is performed in a first storage area among the multiple data storage areas, a programming operation or a read operation can be performed in a second storage area among the multiple data storage areas.

[0014] In a memory system, each of the multiple data storage regions includes a memory die or a memory plane.

[0015] The controller can be configured to transmit multiple first data items to a memory device, and then transmit a first parity check to the memory device. The memory system can be configured to distribute and program the multiple first data items and the first parity check into different data storage areas.

[0016] The controller can be configured to: retain the first parity check in the first parity check buffer and delay the generation of the second parity check when multiple data storage areas are busy; and delay the generation of the second parity check when there is no available space in the first parity check buffer for storing the second parity check.

[0017] The controller can be configured to periodically check the duration for which the first parity check is stored in the first parity buffer. The reference time can be less than the operational margin of an erase operation performed in the memory device and greater than the operational margin of a programming operation.

[0018] In another embodiment, a memory system may include: a memory device including a plurality of memory planes or a plurality of memory dies in which data input and output (input / output) operations are performed independently; and a controller configured to: after transferring a plurality of first data to the plurality of memory planes or the plurality of memory dies, migrate a first parity associated with the plurality of first data from a first buffer to a second buffer to ensure available space in the first buffer, the first parity being retained in the first buffer based on whether the plurality of first data is stored in the plurality of memory planes or the plurality of memory dies; generate a second parity associated with a plurality of second data to be transferred and stored in the plurality of memory planes or the plurality of memory dies, and store the second parity in the available space.

[0019] The controller can be configured to migrate the first parity check from the first buffer to the second buffer when the time the first parity check has been stored in the first buffer is greater than a reference time.

[0020] The first buffer can have a faster data input / output speed than the second buffer.

[0021] The controller can be configured to migrate a first parity group, which includes a first parity check and multiple first data, from a first buffer to a second buffer.

[0022] The controller can be configured to release the first parity group from the second buffer based on a programming completion notification from the memory device for the first parity and multiple first data.

[0023] The controller can be configured to: transmit each of the multiple first data to multiple memory dies or multiple memory planes in a distributed manner; and transmit the first parity check to the memory plane or memory die that has not yet transmitted the multiple first data.

[0024] The controller can be configured to: retain the first parity check in the first buffer and delay the generation of the second parity check when all multiple memory planes or multiple memory dies are busy; and delay the generation of the second parity check when there is no available space in the first buffer for storing the second parity check.

[0025] In another embodiment, a method for operating a memory system may include: determining a plurality of first data distributed and stored in a plurality of memory planes or a plurality of memory dies; calculating a first parity check associated with the plurality of first data; after transferring at least a portion of the plurality of first data to the plurality of memory planes or a plurality of memory dies, determining whether at least one of the plurality of memory planes or a plurality of memory dies is in an idle state; when at least one of the plurality of memory planes or a plurality of memory dies is in an idle state, migrating the first parity check from a first buffer to a second buffer to ensure available space in the first buffer; and generating a second parity check, the second parity check being stored in the available space and associated with the plurality of second data to be distributed and stored in the plurality of memory planes or a plurality of memory dies.

[0026] The method may further include: after storing multiple first data in multiple memory planes or multiple memory dies, transmitting the first parity check in the second buffer.

[0027] The method may further include: when multiple memory planes or multiple memory dies are all busy, retaining the first parity check in the first buffer and delaying the generation of the second parity check.

[0028] The method may further include: delaying the generation of the second parity check when there is no available space in the first buffer to store the second parity check.

[0029] The embodiments described herein can provide apparatus and methods for improving data input / output operations in a memory system or data processing system. Attached Figure Description

[0030] The description herein refers to the accompanying drawings, in which the same reference numerals denote the same parts throughout the drawings.

[0031] Figure 1 Programming operations performed in a data storage device or memory system according to embodiments of the present disclosure are illustrated.

[0032] Figure 2 A data processing system according to an embodiment of the present disclosure is shown.

[0033] Figure 3A redundant array of independent disks (RAID) is shown.

[0034] Figure 4 An example of storing data in units of superblocks within a memory device is shown.

[0035] Figure 5 An embodiment of a memory device is shown in which multiple write data and parity data are distributed and stored in multiple locations.

[0036] Figure 6 The illustration shows a scenario in a memory system according to an embodiment of the present disclosure where parity migration does not occur.

[0037] Figure 7 This illustrates a parity migration scenario occurring in a memory system according to an embodiment of the present disclosure.

[0038] Figure 8 A first operation of a memory system according to an embodiment of the present disclosure is illustrated.

[0039] Figure 9 A second operation of a memory system according to an embodiment of the present disclosure is illustrated.

[0040] Figure 10 A data processing system according to an embodiment of the present disclosure is shown.

[0041] Figure 11 A memory system according to an embodiment of the present disclosure is shown. Detailed Implementation

[0042] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The elements and features of the present disclosure may be configured or arranged in different ways to form other embodiments, which may be variations of any of the disclosed embodiments.

[0043] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiments.

[0044] In this disclosure, the terms “comprising,” “including,” “containing,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the said element but do not exclude the presence or addition of one or more other elements. Furthermore, the terms in the claims do not exclude the device from including additional components, such as interface units, circuitry, etc.

[0045] In this disclosure, various units, circuits, or other components may be described or declared as "configured to" perform one or more tasks. In such a context, "configured to" is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even when a block / unit / circuit / component is not currently running, e.g., not turned on or activated, it can be said that the specified block / unit / circuit / component is configured to perform a task. Examples of blocks / units / circuits / components used with the "configured to" language include hardware, such as circuits, memory storing program instructions that can be executed to perform operations, etc. Furthermore, "configured to" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor running software) to operate in a manner capable of performing the relevant tasks. "Configured to" may also include adjusting manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means (e.g., integrated circuits) suitable for performing or implementing one or more tasks.

[0046] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) a purely hardware circuit implementation (e.g., an implementation of analog and / or digital circuitry only); and (b) a combination of circuitry and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) a processor / software (including digital signal processors), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions; and (c) a circuit, such as a microprocessor or a portion thereof, that requires software or firmware to function, even if the software or firmware is not physically present. The definition of “circuit” or “logic” applies to all uses of the term in this application, including in any claim. As a further example, as used in this application, the terms “circuit” or “logic” also cover implementations of only one or more processors or a portion thereof and their accompanying software and / or firmware. The terms “circuit” or “logic” also cover integrated circuits, for example, for storage devices, if applicable to a particular claim element.

[0047] As used herein, the terms “first,” “second,” “third,” etc., used as prefixes to nouns do not indicate any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must precede the second. Furthermore, while these terms can be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element with the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0048] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that may influence the determination. That is, the determination may be based solely on these factors, or at least partially on them. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0049] Here, a data entry, data item, or data term can be a bit sequence. For example, a data entry may include the contents of a file, a portion of a file, a page in memory, an object in object-oriented programming, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to an embodiment, a data entry may include discrete objects. According to another embodiment, a data entry may include units of information processed or disposed of for data input / output operations. According to yet another embodiment, a data entry may include units of information within a data packet transmitted between two different components.

[0050] Embodiments will now be described with reference to the accompanying drawings, in which the same numbers refer to the same elements.

[0051] Figure 1 Programming operations performed in a data storage device or memory system according to embodiments of the present disclosure are illustrated.

[0052] Reference Figure 1 A data storage device (or memory system) can store data in an internal data storage area through programmable operations. According to an embodiment, the data storage device (or memory system) may include a controller and a memory device. References will follow. Figure 2 , Figure 10 and Figure 11 Describe the specific configuration and operation of the controller and memory devices in the data storage device (or memory system).

[0053] The controller can receive write data from an external device connected to the data storage device (operation 110). For example, the data storage device can receive write commands transmitted along with the write data from the external device.

[0054] The controller can store write data transferred from an external device in a memory device. To do this, the controller can determine the location of the write data to be stored in the memory device (operation 112). According to an embodiment, the controller can associate a logical address used by the external device with a physical address or virtual address used in the data storage device. The location of the write data to be stored in the memory device can be determined based on the configuration and operating characteristics of the memory device.

[0055] According to an embodiment, the controller can group the written data (e.g., configure groups of data to be stored in the memory device). The memory device may include multiple memory regions. Data input / output operations can be performed independently in these multiple memory regions. The data storage device can perform data input / output operations in parallel to improve data input / output performance. The controller can use multiple pipeline structures to control and process data input / output operations for multiple memory regions, thereby improving the throughput of data input / output operations.

[0056] The controller can calculate parity (operation 114) for (grouped) write data distributed and stored across multiple storage areas. By associating parity with multiple data items stored across multiple storage areas, errors included in the multiple data items can be detected or recovered (or corrected). See below for further details. Figures 3 to 5 Describe the application of parity checking.

[0057] The controller may include a computing device for parity calculation and a buffer for storing the results of the parity calculation. Furthermore, the controller may store a parity set, including the parity check and multiple data items, in the buffer, and then retain the parity set in the buffer until it is stored in a memory device. When the operation for storing or transferring at least one of the parity check or multiple data items from a parity set to the memory device is delayed, another parity set (or multiple other parity sets) may accumulate in the buffer. When the buffer size included in the controller is insufficient, the operation for calculating a new parity check may be delayed due to the accumulation of multiple parity sets in the buffer. Improvements to the data processing device (used for parity calculations performed by the controller) with limited buffer size will be referred to below. Figure 2 as well as Figures 6 to 9 describe.

[0058] After performing parity calculation (operation 114), the controller can transfer the programming command C_Prog and programming data D_Prog to the memory device. According to an embodiment, the memory device may include multiple memory regions or multiple memory dies. These multiple memory regions or multiple memory dies can individually transmit commands, data, etc., to the controller or exchange commands, data, etc., with the controller. The controller and the multiple memory regions or multiple memory dies can be connected via at least one channel or at least one data path.

[0059] According to an embodiment, the memory device can perform a programming operation (operation 116) based on programming commands C_Prog and programming data D_Prog transmitted from the controller. When data is stored in non-volatile memory cells included in the memory device, the memory device can sequentially program the data in open memory blocks. According to an embodiment, when data is stored in volatile memory cells within the memory device, the memory device can also store data at a location specified by the controller.

[0060] After completing the internal programming operations, the memory device can notify the controller that programming or storage is complete (operation 118). When the memory device includes multiple memory regions or multiple memory dies, the operations of programming or storing data can be performed individually in each of the multiple memory regions or multiple memory dies. Each of the multiple memory regions or multiple memory dies can individually notify the controller that programming or storage is complete.

[0061] The controller can be configured to receive a programming completion notification or a storage completion notification transmitted from the memory device, and to check or identify whether all the data and parity checks included in a specific parity group have been stored in multiple memory areas or multiple memory dies. After the data and parity checks included in the corresponding parity group have been stored in the memory device, the controller can release or erase the corresponding parity group stored in the buffer.

[0062] The controller may include volatile memory with a fast operating speed (e.g., data input / output speed) and at least one computing device, or may operate in conjunction with the volatile memory and at least one computing device. For example, the volatile memory included in or linked to the controller may include static random access memory (SRAM) and dynamic random access memory (DRAM). Here, SRAM may operate faster than DRAM, which is another example of volatile memory. While SRAM, along with other components, forms a system-on-a-chip (SoC) included on a single chip during the controller's fabrication process, DRAM is typically formed as a separate chip physically separate from the controller. According to embodiments, the controller may access DRAM through a separate drive or a separate input / output interface. Therefore, there may be more limitations or constraints (e.g., technical limitations, manufacturing cost limitations, etc.) in expanding the data storage space of SRAM compared to DRAM. Below, an apparatus and method of operation for setting and managing buffers used for parity checks are described to improve the data input / output performance of a data storage device by utilizing different types of volatile memory.

[0063] Figure 2 A data processing apparatus according to an embodiment of the present disclosure is shown. Specifically, Figure 2This is a block diagram illustrating a data processing apparatus 200, wherein a memory system 210 according to an embodiment of the present disclosure can be used as a data storage device for a host 202.

[0064] Reference Figure 2 The memory system 210 may include a memory device 250. The host 202 may utilize the memory device 250, which includes non-volatile memory cells in the memory system 210, to store and retrieve stored data. For example, the memory device 250 may include at least one type of non-volatile memory, such as magnetoresistive RAM (MRAM), NAND, NOR, and hard disk drive (HDD). In the following description, for simplicity and illustrative purposes, the memory device 250 is described as non-volatile memory (NVM).

[0065] Host 202 may include host memory (e.g., DRAM). According to embodiments, data processing apparatus 200 may include multiple storage devices, such as memory systems 210. For example, data processing apparatus 200 may include multiple memory systems 210 configured as a redundant array of independent disks (RAID) to collectively serve as mass storage for host 202. Furthermore, according to embodiments, data processing apparatus 200 may include multiple computing devices, such as host 202. For example, data processing apparatus 200 may include memory systems 210 configured as shared memory devices, which multiple computing devices (e.g., host 202) can use for data storage and retrieval.

[0066] Data processing apparatus 200 may include host 202, which is capable of storing and / or retrieving data in one or more storage devices (e.g., memory system 210). Figure 2 As shown, host 202 can perform data communication with memory system 210 via host interface (I / F) 220. Host 202 can encompass a variety of devices, including mobile electronic devices (e.g., automobiles), electronic devices (e.g., mobile phones or MP3 players), computer servers, network attached storage (NAS) devices, desktop computers, laptops, tablet computers, set-top boxes, telephones (e.g., "smartphones"), "smart" tablets, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, and so on.

[0067] The memory system 210 may include a controller 230, a memory device 250, and a host interface 220. The controller 230 may include a data input / output (I / O) processing unit 232 and a parity check device 240. The parity check device 240 may include a parity check engine 242, a parity check migrater 248, a first (1st) buffer 238, and a second (2nd) buffer 246. Here, the first buffer 244 and the second buffer 246 may be located or built in different memories. Furthermore, the first buffer 244 and the second buffer 246 may have different data input / output operation speeds. For example, the first buffer 244 may have a faster data input / output operation speed than the second buffer 246. According to an embodiment, the first buffer 244 may be located or built in static random access memory (SRAM), and the second buffer 246 may be located or built in dynamic random access memory (DRAM).

[0068] The parity checking device 240 can be configured to determine the usage of the first buffer 244 and the second buffer 246 based on data input / output operations, the operational state during the execution of the parity generation operation, and the data input / output speed. The parity migration device 248 can migrate parity checks stored in the first buffer 244 to the second buffer 246 based on preset conditions or operational states / environments. Through this scheme, the parity checking device 240 can ensure the availability of space in the first buffer 244 used for parity calculations of other data. The following will refer to... Figures 6 to 9 Describe the specific operation and configuration of the parity check device 240.

[0069] According to an embodiment, the memory system 210 may include Figure 2 Additional components not shown. For example, memory system 210 may include a printed circuit board (PCB) comprising conductive lines to which the components of memory system 210 are mechanically attached and electrically interconnected. In some examples, the physical dimensions and connector configuration of memory system 210 may conform to one or more standard form factors. For example, standard form factors may include, but are not limited to: 2.5-inch data storage devices (e.g., HDDs or solid-state drives (SSDs)), 1.8-inch data storage devices, peripheral component interconnects (PCI), PCI expansion (PCI-X), high-speed PCI (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe mini-cards, mini PCI, etc.). According to embodiments, memory system 210 may be directly connected (e.g., directly soldered) to the motherboard of host 202.

[0070] The host interface 220 of the memory system 210 may include one or both of a data bus for exchanging data with the host 202 and a control bus for exchanging commands with the host 202. The host interface 220 may operate according to any suitable protocol. For example, the host interface 220 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Universal Serial Bus (USB), Multimedia Card (MMC), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), PCI, PCIe, NVMe (High Speed ​​Non-Volatile Memory), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Compute Fast Link (CXL), Open Channel SSD (OCSSD), or similar protocols. Electrical connections (e.g., a data bus, a control bus, or both) to the host interface 220 may be electrically connected to the controller 230 to provide an electrical connection between the host 202 and the controller 230, thereby enabling data exchange between the host 202 and the controller 230. According to an embodiment, the electrical connections to the host interface 220 may allow the memory system 210 to receive power from the host 202. For example, power-dependent devices of the memory system 210 may receive power from the host 202 via the host interface 220.

[0071] The memory system 210 may include a memory device 250, which includes multiple data storage areas. According to embodiments, the memory device 250 may be configured to store and / or retrieve data. For example, a memory die or memory chip included in the memory device 250 may receive data from a controller 230, as well as messages or commands instructing the memory device to store data. Similarly, a memory die or memory chip included in the memory device 250 may receive messages from the controller 230 instructing the memory device 250 to retrieve data. According to embodiments, the memory die or memory chip included in the memory device 250 may be configured to store relatively large amounts of data (e.g., 128 MB, 256 MB, 412 MB, 1 GB, 2 GB, 3 GB, 8 GB, 16 GB, 22 GB, 54 GB, 128 GB, 256 GB, 412 GB, 1 TB, etc.).

[0072] According to embodiments, memory device 250 may include any type of non-volatile memory device, such as read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable ROM (EPROM), electrically erasable ROM (EEPROM), phase-change RAM (PRAM), magnetic RAM (MRAM), NAND or NOR flash memory, phase-change random access memory (PCRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), spin-transfer torque magnetic random access memory (STT-MRAM), holographic memory device, hard disk drive (HDD), and any other type of non-volatile memory device.

[0073] According to an embodiment, memory device 250 may include multiple flash memory devices. The flash memory devices may include NAND-based or NOR-based flash memory devices and may store data based on the amount of charge contained in the floating gate of the transistor in each flash memory cell. In a NAND flash memory device, the flash memory device may be divided into multiple blocks, which may be divided into multiple pages. Each of the multiple blocks in a particular memory device may include multiple NAND cells. Rows of NAND cells may be electrically connected using word lines to create multiple pages. Each cell in each of the multiple pages may be electrically connected to a corresponding bit line. Additionally, the NAND flash memory device may be a 2D or 3D device. The flash memory device may include single-layer cell (SLC), multi-layer cell (MLC), triple-layer cell (TLC), quadruple-layer cell (QLC), or higher-layer cells. Controller 230 may write data to and read data from the NAND flash memory device on a page-by-page basis and may erase data stored in the NAND flash memory device on a block-by-block basis.

[0074] A portion of the memory device 250 can be formatted into logical blocks, partitions, or regions, thereby dividing the storage capacity of the memory device 250 into multiple data streams. Each data stream may include multiple physical blocks or multiple erase blocks of the memory device 250. Each physical block may be associated with multiple logical blocks. Each logical block may be associated with a unique LBA or sector. The size of each data stream can be customized based on the storage capacity of one or more physical blocks in the memory device 250. When the controller 230 receives a command from, for example, the host 202, the controller 230 can read data from and write data to multiple logical blocks associated with multiple physical blocks in the memory device 250.

[0075] The memory system 210 may include a power supply circuit configured to provide power to at least one component. When operating in a standard or normal mode, the power supply circuit may utilize power supplied by an external device (e.g., host 202) to power one or more components. For example, the power supply circuit may use power received from host 202 via host interface 220 to power one or more components. According to an embodiment, the power supply circuit may include one or more power auxiliary devices configured to power one or more components when operating in a shutdown mode (e.g., when power input from an external device is interrupted). Examples of power auxiliary devices may include, but are not limited to, capacitors, supercapacitors, batteries, etc. According to an embodiment, the amount of electricity that one or more power storage components can store may correspond to the cost and / or size (e.g., area / volume) of one or more power storage components. As the amount of electricity stored by one or more power storage components increases, the cost and / or size of one or more power storage components also increases.

[0076] The memory system 210 may also include a volatile memory device that the controller 230 may use to temporarily store data or information. The volatile memory device may include one or more volatile memories. For example, the controller 230 may use the volatile memory as a cache. The controller 230 may store cached data or information in the volatile memory until the cached data or information is completely written to the memory device 250. Examples of volatile memory include, but are not limited to, RAM, DRAM, SRAM, and SDRAM (e.g., Double Data Rate 1 (DDR1), DDR2, DDR3, DDR3L, Low Power Double Data Rate 3 (LPDDR3), DDR4, LPDDR4, DDR5, LPDDR5, etc.).

[0077] Different types of volatile memory can be used based on different access characteristics. For example, DRAM can be arranged for longer burst accesses, thereby increasing the bandwidth of the same access bus. Alternatively, DRAM can be used for smaller accesses, resulting in better latency for random small accesses. Controller 230 may include additional optional SRAM and / or embedded MRAM. Embedded MRAM is another alternative memory that can be used in other embodiments. Similarly, while access to MRAM can be optimized for various design purposes, the amount of embedded MRAM in controller 230 may be constrained by cost factors. Therefore, system trade-offs will affect the choice of how much data and which data is placed in advanced non-volatile memory and advanced volatile memory.

[0078] The controller 230 within the memory system 210 can manage one or more operations of the memory system 210. For example, the data input / output processing unit 232 within the controller 230 can manage or control reading data from and / or writing data to the memory device 250. According to an embodiment, when the memory system 210 receives a write command from the host 202, the controller 230 can begin processing the data write command to store the data in the memory device 250 and monitor the processing progress of the data write command. According to an embodiment, the controller 230 can determine at least one operating characteristic of the data processing device 200 and store at least one operating characteristic in the memory device 250.

[0079] According to an embodiment, the parity check engine 242 in the parity check device 240 can be configured to perform logic and / or functions to generate XOR parity information. XOR parity information is a parity check type and is presented for illustrative purposes only. According to an embodiment, the parity check engine 242 may include circuitry or an engine configured to generate parity types other than XOR parity information. The XOR parity information can be used to improve the stability of the memory system 210, for example, to enable data recovery from failed data writes or reads of the memory device 250, or to enable data recovery in the event of a power outage. The operational reliability of the memory system 210 can be provided based on XOR parity information generated or calculated from data stored in the memory system 210. For example, data stored in the memory device 250 via the data input / output processing unit 232 can be written to the memory device 250 via the parity check engine 242. Before the data and parity are transmitted to the memory device 250, the parity engine 242 can store the generated parity information in the first buffer 244.

[0080] Furthermore, the parity checking device 240 included in the controller 230 can temporarily store data to be written to or read from the memory device 250 in a first buffer 244 and a second buffer 246, where the first buffer 244 and the second buffer 246 are different volatile memories. The first buffer 244 can be used for parity checking operations performed by the parity checking engine 242 in the parity checking device 240. For example, the first buffer 244 can store parity checks generated by the parity checking engine 242 or parity checks used by the parity checking engine 242 when performing verification operations. According to an embodiment, the first buffer 244 can store a parity check set, which includes multiple data and parity checks stored in and read from the memory device 250. If an error occurs when reading multiple data from the memory device 250, the parity checking device 240 can recover the data corresponding to the error based on the parity check set stored in the first buffer 244.

[0081] When a parity check set is stored and held in the first buffer 244, the first buffer 244 may not provide or support sufficient space to perform multiple data input / output operations until the memory device 250 stores all the data and parity checks belonging to that parity check set. Therefore, when the parity check device 240 needs more space in the first buffer 244 to perform parity check operations on other data (or other parity check sets), the parity check migrater 248 can migrate a portion of the data and parity checks stored in the first buffer 244 to the second buffer 246 to ensure available space for parity check operations on other data. According to an embodiment, each of the first buffer 244 and the second buffer 246 can be configured using at least one of DRAM and SRAM.

[0082] Figure 3 A standalone (or low-cost) redundant disk array (RAID) suitable for a memory device is illustrated according to embodiments of this disclosure. Specifically, Figure 3 An example of using five zones (Plane1, Plane2, Plane3, Plane4, Plane5) in a standalone redundant array of disks or a low-cost redundant array of disks (hereinafter referred to as "RAID") is shown.

[0083] The five regions included in a storage device using a RAID scheme can have substantially the same size. According to one embodiment, each of the five regions Plane1, Plane2, Plane3, Plane4, and Plane5 included in the storage device 250 may include a memory plane, a memory block, a memory die, etc. In another embodiment, the five regions Plane1, Plane2, Plane3, Plane4, and Plane5 may be five logical regions created by the user.

[0084] exist Figure 3 In this configuration, the memory system 210 can use a RAID scheme to store four data entries A1, A2, A3, A4 and one parity entry Ap in five areas: Plane1, Plane2, Plane3, Plane4, and Plane5. Even if an error occurs in one of the five areas (Plane1, Plane2, Plane3, Plane4, and Plane5), the data stored in the faulty area can be recovered and restored based on the other data entries and the parity entry stored in the remaining four areas. For example, the parity entry Ap can be generated by performing an XOR operation on the four data entries A1, A2, A3, and A4. Subsequently, when the second data entry A2 among the four data entries A1, A2, A3, and A4 fails, the second data entry A2 can be recovered and restored by performing an XOR operation on the first data entry A1, the third data entry A3, the fourth data entry A4, and the parity entry Ap.

[0085] Furthermore, since it is difficult to predict which of the five regions (Plane1, Plane2, Plane3, Plane4, Plane5) will have a problem, the locations of the four data entries and one parity entry can be changed. For example, a first parity entry Ap corresponding to the four first data entries A1, A2, A3, A4 can be stored in the fifth region (Plane5), while a second parity entry Bp corresponding to the four second data entries B1, B2, B3, B4 can be stored in the fourth region (Plane4).

[0086] To generate parity checks, the memory system 210 may include Figure 2 The parity checking device 240 shown is illustrated. (Refer to...) Figure 3In the five regions Plane1, Plane2, Plane3, Plane4, and Plane5 of the memory device 250, four first data entries A1, A2, A3, and A4, and one first parity entry Ap, can be programmed. The parity engine 242 can generate a first parity entry Ap based on the four first data entries A1, A2, A3, and A4. In the memory system 210, the four first data entries A1, A2, A3, and A4 can be stored in a first non-volatile cell region, and the first parity entry Ap can be stored in a second non-volatile cell region. For programming multi-bit data, when the memory device 250 according to the disclosed embodiment performs a two-step programming operation, parity can be generated and stored according to a RAID scheme, and the size of the aforementioned SLC buffer can be reduced or used more efficiently.

[0087] Reference Figure 3 Four data entries A1, A2, A3, and A4 are used to generate a parity information entry Ap. For memory system 210 to generate a parity information entry Ap, it must have a buffer for storing the four data entries A1, A2, A3, and A4, as well as the parity information entry Ap. If memory system 210 generates a parity based on 63 data entries, then memory system 210 should include a buffer for storing 64 data entries and the parity entry.

[0088] Figure 4 An embodiment of storing data in a memory device according to an embodiment of the present disclosure is shown, using superblocks as units. Specifically, Figure 4 It shows Figure 2 The illustrated memory device 250 includes multiple memory dies. These multiple memory dies are capable of storing multiple data entries distributed across multiple open memory blocks, as well as parity entries associated with these data entries. Here, the multiple open memory blocks can be understood as superblocks.

[0089] Reference Figure 4 The memory device 250 may include multiple memory dies Die0, Die1, ..., Die15. Each memory die Die0 to Die15 may include four memory planes PLN0, PLN1, PLN2, and PLN3. Each of the memory planes PLN0, PLN1, PLN2, and PLN3 may include multiple memory blocks BLK0, BLK1, ..., and each of the memory blocks BLK0, BLK1, ... may include multiple memory cells connected to multiple word lines WL0, WL1, WL2, ..., WLw-1.

[0090] According to an embodiment, the non-volatile memory cells of the memory device 250 can store multiple bits of data. However, for ease of description, as an example, Figure 4 The memory device 250 is shown storing multiple data entries a0, a1, a2, ..., a61, a62, or a63 in multiple memory cells connected to each memory region or each word line within a memory region. The memory system 210 can generate a parity entry pa using a bitwise XOR operation. For example, the parity entry pa can be calculated based on multiple data entries (e.g., pa = a0 + a1 + ... + a63).

[0091] In order to improve Figure 2 The speed of data input / output operations performed in the illustrated memory system 210 is such that the memory system 210 can simultaneously or in parallel read or program multiple data entries of a preset size. The speed of data input / output operations can be improved through interleaving mode, in which multiple data entries of a preset size are read or programmed in parallel in multiple memory regions or memory areas where data input / output operations can be performed independently or individually. Figure 4 In this context, data input / output operations can be performed independently or separately in each of the memory planes PLN0, PLN1, PLN2, and PLN3. For example, the open memory block BLK0 included in each of the multiple memory planes PLN0, PLN1, PLN2, and PLN3 can be included in a super memory block to be programmed with multiple data entries transferred from the controller 230.

[0092] Reference Figures 1 to 4The memory system 210 can program 64 first data entries a0, a1, a2, ..., a61, a62 into memory blocks included in 64 memory regions or memory areas (e.g., memory planes). Additionally, the memory system 210 can calculate and generate a first parity entry pa based on the 64 first data entries a0, a1, a2, ..., a61, a62, a63, and program the first parity entry pa into memory regions or memory areas other than the 64 memory regions or memory areas. The memory system 210 can distribute and store the 64 first data entries a0, a1, a2, ..., a61, a62, a63 in the 64 memory regions or memory areas. The first parity entry pa can be stored in another memory region or memory area. Here, the 64 first data entries a0, a1, a2, ..., a61, a62, a63 and the first parity entry pa can be included in a single chip-level error-correction (chipkill) unit or a single chipkill decoding unit. Even if one of the data entries or the parity entry included in a chipkill unit has an uncorrectable error correction code (UECC) error, the data entry generated by UECC can be restored based on the other error-free data entries and parity entries. According to an embodiment, Figure 10 The ECC circuit 566 described herein can generate parity information corresponding to multiple data or recover data entries generated by UECC based on the chipkill unit.

[0093] Similar to the first data entry, memory system 210 can program 64 second data entries b0, b1, b2, ..., b61, b62, b63 into memory blocks included in 64 memory regions or memory areas (e.g., memory planes). Furthermore, memory system 210 can calculate and generate a second parity entry pb based on the 64 second data entries b0, b1, b2, ..., b61, b62, b63, and program the second parity entry pb into another memory region or memory area besides the 64 memory regions or memory areas. Memory system 210 may include an additional set of data entries with corresponding parity entries.

[0094] According to an embodiment, the first parity entry pa and the second parity entry pb are not stored in the memory device, and are no longer used after the corresponding data set is successfully stored in the memory device. For example, when programming large amounts of data, the first parity entry pa and the second parity entry pb can be used to verify that the corresponding data set has been correctly programmed into the memory device.

[0095] Optionally, according to an embodiment, parity checks pa and pb can be stored in another memory region or memory area within the memory device. When data is stored in the memory device and becomes corrupted due to data retention time or errors or defects in the memory device, parity checks pa and pb can be used to recover the corrupted data.

[0096] The memory system 210 can be configured to store a large amount of data. For example, each of the non-volatile memory cells in the memory device 250 can store 3 bits of data, and eight strings can form a page. Furthermore, data entries and parity entries (a total of 16 entries) can be distributed and stored across 16 open memory blocks of the memory device 250. Data entries can be stored in 15 of the 16 open memory blocks, and parity entries can be stored in the other open memory block. The number of non-volatile memory cells (i.e., the number of strings) connected to a single word line across each of the 16 open memory blocks is 8, and each non-volatile memory cell stores 3 bits of data; therefore, 384 (=16x8x3) bits of data and parity bits can be programmed into the memory device 250. The memory system 210 should include a buffer or cache configured to temporarily store the 384 bits of data and parity so that the controller 230 can generate parity entries based on the data entries during programming operations.

[0097] As the number of open memory blocks, the number of strings, and the number of bits of data stored in each non-volatile memory cell increase in memory device 250, memory system 210 should establish or configure larger buffers or caches for generating parity during programming operations. That is, the size of the buffers or caches increases. Although such parity generation methods and apparatus may involve or perform simple repetitive operations, the size of the buffer used for parity generation should increase with the number of data entries in memory device 250. This increase in buffer size may burden the internal resources of memory system 210. For example, when memory system 210 includes a larger buffer for parity generation, the manufacturing cost of memory system 210 may also increase to ensure or guarantee I / O throughput.

[0098] According to an embodiment, the size of the buffer in the memory system 210 used to generate parity checks and ensure available space can be determined based on the data size of the programming operation and the size of the chipkill unit. However, due to limitations, Figure 2 The parity check device 240 described herein may attempt to reduce the size of the buffer used to generate parity checks and to verify multiple data using parity checks. (See below for further details.) Figures 6 to 9Describe the operation of the parity check device 240.

[0099] Figure 5 An example is shown where multiple write data and parity data are distributed and stored in multiple locations in a memory device. Specifically, Figure 5 The diagram shows the location of data entries stored in memory dies Die0, Die1, ..., Die n-1, which are structured with eight strings String 0 to String 7 connected to each word line WL0, WL1, WL, ..., WL9. Figure 5 This describes parity entries generated based on data entries. Figure 5 In the memory, data entries and parity check entries can be stored in multiple locations of the memory die Die0, Die1, ..., Die n-1, and these locations are determined according to a preset distribution method.

[0100] Reference Figures 1 to 5 The memory device 250 may include multiple memory dies Die 0, Die 1, ..., Die n-1. Each of the memory dies Die 0, Die 1, ..., Die n-1 may include four memory planes Plane0, Plane1, Plane2, Plane3. Each word line WL0, WL1, WL, ..., WL9 may be connected to eight unit strings String0 to String7. Although Figure 5 An example of a memory device 250 including 10 word lines WL0, WL1, WL, ..., WL9 is shown, but the number of word lines included in the memory device 250 can vary based on the storage capacity of the memory device 250. Multiple parity checks (parity0, parity1, ..., parity15) can be generated for multiple data entries stored in different locations in the memory device 250. The multiple parity checks (parity0, parity1, ..., parity15) can be stored in preset locations. For example, each parity check location can specify multiple data locations where data entries corresponding to the parity check entries are stored.

[0101] about Figure 5 The parity generation and storage method shown can be compared with... Figure 4Similar to the example shown. First, based on the positions of the data entries stored in the memory device 250, the combination of data entries used to generate each parity 0, parity 1, ..., parity 15 can be determined. For example, an XOR operation can be performed on multiple data entries s-page0, s-page16, s-page32, s-page72 to calculate the first parity 0, where the multiple data entries s-page0, s-page16, s-page32, s-page72 are stored in each plane included in the n memory dies at positions corresponding to the first string 0 connected to the odd-number lines WL0, ..., WL8. The first parity 0 can be stored in the first string 0 connected to the ninth word line WL8 in the fourth memory plane Plane 3 of the nth memory die. The remaining 15 parities 1, ..., parity 15 can also be generated and stored in their corresponding positions within the memory device 250 in the same manner.

[0102] Reference Figure 5 Sixteen parity groups, parity0, parity1, ..., parity15, can be generated. The combination of data entries used to generate each parity group can be called a parity group. The 16 parity groups can be stored in the memory device 250 at locations corresponding to 10 word lines. Each parity group can correspond to 16 superpages. Here, a superpage can be a way of managing multiple locations distributed within the memory device 250 as a single logical page, such as a supermemory group. Assuming the memory device 250 contains 100 word lines, 160 (=16 x 10) parity groups can be generated and stored. As the number of memory dies in the memory device 250 increases (the larger the value of n), the number of data entries included in each superpage also increases. Moreover, the number of data entries included in each parity group also increases. Therefore, the number of parities stored in the memory device 250 (or the ratio of parities to data entries) can be reduced, allowing more data entries to be stored even with the same storage capacity of the memory device 250.

[0103] Depending on the internal configuration of the memory device 250 or the settings of the parity check group, the number of parity checks stored in the memory device 250 may vary. This may result in differences in error recovery performance when recovering data entries in response to errors (e.g., UECC) occur in the memory device 250.

[0104] According to an embodiment, Figure 2The parity check device 240 described may require buffers to store all data stored in n memory dies (e.g., Die0, Die1, ..., Die n-1) and the parity checks generated during parity check generation (e.g., parity0, parity1, ..., parity15). The size of the buffers used by the parity check device 240 can become very large. If the parity check device 240 uses a significant portion of the limited internal resources of the memory system 210, the data input / output performance of the memory system 210 may deteriorate. To reduce the size of the first buffer 244, the parity check device 240 can perform the parity generation operation according to the order in which the data is stored in the memory device 250, or use a second buffer 246 to ensure available space in the first buffer 244.

[0105] Figure 6 This illustrates a scenario where parity migration does not occur in a memory system according to an embodiment of the present disclosure. Specifically, Figure 6 Described when Figure 2 The operation performed inside the memory system 210 when the parity check device 240 described herein does not use the second buffer 246.

[0106] Reference Figure 2 and Figure 6 The memory device 250 may include multiple memory dies (e.g., Die0 to Die7). For example, among the multiple memory dies (e.g., Die0 to Die7), multiple data may be distributed and stored in seven memory dies (e.g., Die0 to Die6), and parity may be stored in another memory die (e.g., Die7). Each of the parity groups (e.g., PG0 to PG8) that include multiple data and parity may include seven data and a parity corresponding to the seven data. According to an embodiment, the memory system 210 may program the parity corresponding to the seven data into the parity memory die (e.g., Die0 to Die6) after the seven data have been programmed into the seven memory dies (e.g., Die0 to Die6) in the memory device 250.

[0107] Memory device 250 can perform operations such as garbage collection, wear leveling, and read recycling. Memory device 250 can perform erase operations on memory blocks that do not contain valid data. Erase operations can be performed on at least some of the memory dies (e.g., Die0 to Die7) in memory device 250. In memory device 250, the operand margin for read operations is shorter than the operand margin for programming operations (or write operations), and the operand margin for programming operations is shorter than the operand margin for erase operations. When a programming operation is performed on each parity group (e.g., PG0 to PG8) comprising seven data entries and corresponding parity checks, the timing of the programming operation may vary based on the operating state of each memory die (e.g., Die0 to Die7).

[0108] Reference Figure 6 The data and parity checks included in the first parity set PG0 can be programmed into each of a plurality of memory dies (e.g., Die0 to Die7). However, an erase operation can be performed sequentially on the first memory die Die0 and the second memory die Die1 among the plurality of memory dies (e.g., Die0 to Die7). Data belonging to the first parity set PG0 can be programmed into each of the third to seventh memory dies (e.g., Die2 to Die6) other than the first memory die Die0 and the second memory die Die1. After an erase operation is performed on the first memory die Die0 and the second memory die Die1, data belonging to the first parity set PG0 can be programmed into the first memory die Die0 and the second memory die Die1. The parity checks belonging to the first parity set PG0 can be programmed into the eighth memory die Die7, which serves as the parity check memory die, later than the data (e.g., 7 data entries).

[0109] Multiple data points and parity checks belonging to the second parity group PG1 and the third parity group PG2 can also be programmed sequentially in a manner similar to the first parity group PG0. (This is achieved through...) Figure 2After the parity checking device 240 described herein completes the parity checking operation for the first parity check groups to the third parity check groups PG0 to PG2, the multiple data and parity checks belonging to the first parity check groups to the third parity check groups PG0 to PG2 can be stored sequentially. Before all the multiple data and parity checks belonging to each of the first parity check groups to the third parity check groups PG0 to PG2 are programmed into the memory device 250, the data and parity checks belonging to each of the first parity check groups to the third parity check groups PG0 to PG2 can be stored in the first buffer 244. However, if the first buffer 244 included in the parity checking device 240 does not have sufficient storage space, the parity checking device 240 may have difficulty performing parity checking operations on the multiple data belonging to another fourth parity check group PG3 before the multiple data and parity checks belonging to each of the first parity check groups to the third parity check groups PG0 to PG2 are released from or erased from the first buffer 244.

[0110] Even if multiple data belonging to parity groups 4 through 6 (e.g., PG3 through PG5) are identified, the parity checking device 240 may be unable to perform parity checking operations on parity groups 4 through 6 (e.g., PG3 through PG5) due to insufficient available space in the first buffer 244 (e.g., space exhaustion). Therefore, it may be unable to (e.g., cannot) perform programming operations on multiple data belonging to parity groups 4 through 6 (e.g., PG3 through PG5). Consequently, even if programming operations on data belonging to each of parity groups 1 through 3 (e.g., PG0 through PG2) have been completed, it may be unable to (e.g., cannot) perform programming operations on data belonging to another parity group (e.g., PG3, etc.) in memory dies 3 through 7 (e.g., Die2 through Die6).

[0111] Data belonging to the first parity group PG0 is programmed into the first memory die Die0 and the second memory die Die1, and parity checks belonging to the first parity group PG0 are programmed into the eighth memory die Die7, which serves as a parity check memory die. Afterwards, the multiple data and parity checks belonging to the first parity group PG0 stored in the first buffer 244 of the parity check device 240 can be released or erased. When available space is secured in the first buffer 244, the parity check device 240 can perform parity calculations on multiple data belonging to another parity group (e.g., PG3, etc.).

[0112] like Figure 6As shown, if the parity buffer space belonging to parity check device 240 is insufficient, the overall performance of programming operations performed by memory system 210 may degrade. According to embodiments, the number of memory dies included in memory system 250 may differ, and the number of data entries belonging to a single parity group and the number of parities may also differ. Figure 5 As described, the number of data entries belonging to a single parity group can reach dozens. As the number of data entries included in a single parity group increases, the number of data entries stored in the first buffer 244 of the parity checking device 240 also increases. If the volatile memory in the memory system 250 where the first buffer 244 is located does not have sufficient space, the number of parity groups that the parity checking device 240 can perform parity checking operations may be limited.

[0113] like Figure 6 As shown, erase operations may be performed on at least some memory dies (e.g., Die0 to Die5). Due to this erase operation, data input / output operations (e.g., programming and reading operations) performed in parallel on multiple memory dies (e.g., Die0 to Die7) may be delayed. When generating parity during programming operations or checking for or recovering errors based on parity during reading operations, the parity check device 240 may require a larger first buffer 244. However, the configuration of the memory system 210 may not be easily changed. In particular, if the first buffer 244 is set or built in SRAM, the size of the SRAM may be difficult to change after manufacturing. Therefore, the parity check device 240 within the memory system 210 may include or be built as follows: Figure 2 The second buffer 246 is described.

[0114] Figure 7 This illustrates a parity migration scenario occurring in a memory system according to an embodiment of the present disclosure. Specifically, Figure 7 Described when Figure 2 The operations performed in the memory system 210 when the parity checking device 240 described herein uses or operates the first buffer 244 and the second buffer 246.

[0115] Reference Figure 2 and Figure 7The memory device 250 may include multiple memory dies (e.g., Die0 to Die7). For example, among the multiple memory dies (e.g., Die0 to Die7), data may be stored in seven memory dies (e.g., Die0 to Die6), and parity may be stored in another memory die (e.g., Die7). Each of the parity groups (e.g., PG0 to PG7) that include multiple data and parity may include seven data items and a parity associated with those seven data items. According to an embodiment, the memory system 210 may program the parity corresponding to the seven data items into the parity memory die (e.g., Die0 to Die6) after the seven data items have been programmed into them.

[0116] Memory device 250 can perform operations such as garbage collection, wear leveling, and read recycling. Memory device 250 can perform erase operations on memory blocks that do not store valid data. Erase operations can be performed on some of the memory dies (e.g., Die0 to Die7) in memory device 250. In memory device 250, the margin for read operations (i.e., the operation margin) is shorter than the margin for programming operations (or write operations). Furthermore, the margin for programming operations is shorter than the margin for erase operations. Programming operations on parity groups (e.g., PG0 to PG7) can be performed individually in each memory die (e.g., Die0 to Die7), each parity group comprising 7 data items and a parity check corresponding to the 7 data items. The timing of performing programming operations may vary depending on the operating state of each memory die (e.g., Die0 to Die7).

[0117] Reference Figure 7The multiple data entries and parity entries included in the first parity group PG0 can be programmed into each of a plurality of memory dies (e.g., Die0 to Die7). However, the first memory die Die0 and the second memory die Die1 among the plurality of memory dies (e.g., Die0 to Die7) can be erased sequentially. Data entries belonging to the first parity group PG0 can be programmed into each of the third to seventh memory dies (e.g., Die2 to Die6) other than the first memory die Die0 and the second memory die Die1. After the erase operation is performed, the data entries belonging to the first parity group PG0 can be programmed into the first memory die Die0 and the second memory die Die1. The parity entries belonging to the first parity group PG0 can be programmed into the eighth memory die Die7, which is the parity memory die, later than the multiple data entries programmed into the first to seventh memory dies (e.g., Die0 to Die6).

[0118] Multiple data entries and parity entries belonging to the second parity group PG1 and the third parity group PG2 can also be programmed sequentially in a manner similar to the first parity group PG0. (This is achieved through...) Figure 2 After the parity checking device 240 completes the parity checking operation for the first parity check group to the third parity check group (e.g., PG0 to PG2), the data entries and parity entries belonging to the first parity check group to the third parity check group (e.g., PG0 to PG2) can be sequentially transferred and stored in the memory device 250. Before all the data entries and parity entries belonging to each of the first parity check group to the third parity check group (e.g., PG0 to PG2) are programmed into the memory device 250, the data entries and parity entries belonging to each of the first parity check group to the third parity check group (e.g., PG0 to PG2) can be stored and retained in the first buffer 244.

[0119] Because the first buffer 244 included in the parity checking device 240 may not have sufficient storage space, performing parity checks on multiple data belonging to the new fourth parity group PG3 may become difficult. In this case, the parity migration device 248 in the parity checking device 240 can move some of the data or parity checks stored in the first buffer 244 to the second buffer 246. For example, the parity migration device 248 can migrate data and parity checks belonging to the first parity group PG0 from the first buffer 244 to the second buffer 246. Through data migration, available space (e.g., blank or empty space) can be secured in the first buffer 244, allowing the parity checking device 240 to perform parity checks on the fourth parity group PG3.

[0120] Reference Figure 7 After the parity checking device 240 performs a parity check operation on the fourth parity check group PG3, at least a portion of the data belonging to the fourth parity check group PG3 can be transferred to the memory device 250 and programmed into the memory device 250. For example, since the third to seventh memory dies (e.g., Die2 to Die6) are idle after the data belonging to the third parity check group PG2 is programmed, the data belonging to the fourth parity check group PG3 can be transferred to the third to seventh memory dies (e.g., Die2 to Die6) and programmed into the third to seventh memory dies (e.g., Die2 to Die6).

[0121] Furthermore, the parity migration unit 248 in the parity checking device 240 can migrate the data and parity checks belonging to the second parity group PG1 and the third parity group PG2 stored in the first buffer 244 to the second buffer 246. This ensures available space in the first buffer 244, allowing the parity checking device 240 to perform parity checking operations on the fifth parity group PG4 and the sixth parity group PG5. After performing parity checking operations on the fifth parity group PG4 and the sixth parity group PG5, at least a portion of the data belonging to the fifth parity group PG4 and the sixth parity group PG5 can be transferred in response to the operating states of multiple memory dies (e.g., Die0 to Die7).

[0122] Figure 7 The diagram illustrates data belonging to the fifth parity group PG4 and the sixth parity group PG5 being programmed into the fifth through seventh memory dies (e.g., Die4 through Die6). Data belonging to the first through sixth memory dies (e.g., PG0 through PG5) can be sequentially transferred to the first through fourth memory dies (e.g., Die0 through Die3) before or after performing an erase operation ERASE, such that the data transferred to each memory die can be programmed independently and separately. After data belonging to each of the first through sixth parity groups (e.g., PG0 through PG5) is stored in the first through seventh memory dies (e.g., Die0 through Die6), the parity data belonging to each of the first through sixth parity groups (e.g., PG0 through PG5) can be stored in the eighth memory die Die7.

[0123] After the data and parity belonging to each of the first to sixth parity groups (e.g., PG0 to PG5) are programmed into multiple memory dies (e.g., Die0 to Die7), each of the first to sixth parity groups (e.g., PG0 to PG5) migrated from the first buffer 244 to the second buffer 246 by the parity migrationer 248 can be released or erased. The parity migrationer 248 can migrate at least one parity group stored in the first buffer 244 to the second buffer 246 based on the operating state of the first buffer 244 and the operating state of the multiple memory dies (e.g., Die0 to Die7) in the memory device 250. On the other hand, according to an embodiment, since the size of the DRAM included in the memory system 210 is larger than the size of the SRAM, the size of the second buffer 246 established in the DRAM can be larger than the size of the first buffer 244 established in the SRAM, such that the available space in the DRAM that can be used as the second buffer 246 can be relatively larger than the available space in the SRAM.

[0124] like Figure 6 and Figure 7 As shown, the second buffer 246 included in the parity checking device 240 can be used to prevent or avoid the overall performance degradation of programming operations performed by the memory system 210 due to insufficient storage space in the first buffer 244. On the other hand, the parity checking device 240 does not always migrate data and parity checks stored in the first buffer 244 to the second buffer 246. When multiple memory dies (e.g., Die0 to Die7) in the memory device 250 are all busy rather than idle, even if the parity checking device 240 performs parity checks on other data, the other data may not be able to be transferred to the memory device 250. In this case, the overall data input / output performance of the memory system 210 may not be improved, so migrating other data from the first buffer 244 to the second buffer 246 by the parity checking device 240 may result in unnecessary power waste. Therefore, in embodiments of this disclosure, the parity check device 240 can use the second buffer 246 to ensure available space in the first buffer 244 only when at least one of the plurality of memory dies (e.g., Die0 to Die7) in the memory device 250 is in an idle state.

[0125] In addition, regarding Figure 6 and Figure 7The controller 230 can be configured to ensure available space in the first buffer 244 by migrating a first parity group PG0 associated with a plurality of first data entries from the first buffer 244 to the second buffer 246. When at least one of the plurality of memory planes Plane0, Plane1, Plane2, Plane3, or a plurality of memory dies is idle, at least a portion of the first parity group PG0 may not be transferred to at least some of the plurality of memory planes Plane0, Plane1, Plane2, Plane3, or a plurality of memory dies. However, since the controller 230 can migrate the first parity group PG0 to ensure available space for another parity group, the controller 230 can perform parity checks on a second parity group PG1 associated with a plurality of second data entries to be transferred and stored in an idle memory plane or memory die.

[0126] Figure 8 A first operation of a memory system according to an embodiment of the present disclosure is illustrated. Specifically, Figure 8 An operation method is described for storing point-in-time information related to parity checks generated during programming operations based on write commands input to memory system 210.

[0127] Reference Figure 2 and Figure 8 The memory system 210 may include a host interface 220 and a controller 230. The memory system 210 may receive write commands (operation 232A) transmitted from an external device. The data input / output processing unit 232 in the controller 230 may perform internal operations based on the write command. The data input / output processing unit 232 may transmit the task generated based on the write command transmitted from the host interface 220 to the parity check module 234 (①).

[0128] The data input / output processing unit 232, including the parity group module 234, can determine a parity group by grouping multiple write data transmitted along with at least one write command into preset units. The data input / output processing unit 232 can manage programming operations on the parity groups set by the parity group module 234. At this time, the parity manager 236 included in the data input / output processing unit 232 can assign identifiers (e.g., ID, Index) to the parity group module 234 by considering the storage location of the write data in the memory device 250 (②). The parity manager 236 can allocate or establish a first buffer 244 in SRAM for the parity groups assigned identifiers.

[0129] According to an embodiment, the parity group module 234 and the parity manager 236 may use a timer to record a time point (e.g., tParityAllocated) at which parity allocation identifiers (e.g., ID, Index) corresponding to multiple data belonging to the parity group are generated (③). According to an embodiment, by recording a specific time point of the parity check using a timer and then checking that time point, the parity group module 234 and the parity manager 236 can check the time during which the parity check is stored and retained in the controller 230. On the other hand, if another written data has the same logical address as the data associated with the generated parity check, or if another written data belongs to the same parity group, the parity group module 234 and the parity manager 236 may initialize the time point (e.g., tParityAllocated) for the corresponding parity allocation identifier (e.g., ID, Index).

[0130] Once the parity check group module 234 determines the time point of the parity check group, it can transmit the time point of the parity check group to the data input / output processing unit 232 (④) in the controller 230. The data input / output processing unit 232 can set, schedule, and process detailed operations (operation 232B) corresponding to write commands for programming operations to be performed in multiple memory areas (e.g., multiple memory dies) within the memory device 250.

[0131] According to an embodiment, the programming operation manager 238 within the controller 230 can increment the count information (e.g., nProgs) of the parity group (⑤) when programming commands for multiple data and parities belonging to a parity group are transmitted. The programming operation manager 238 may be included in the parity device 240. The count information (e.g., nProgs) of the parity group can be used to manage or control multiple programming operations performed for multiple data and parities belonging to a corresponding parity group, multiple memory regions within the memory device 250, or multiple memory dies. For example, if the number of data and parities belonging to the first parity group is 8, then each time the controller 230 processes multiple programming operations for 8 data entries and parities, the programming operation manager 238 can sequentially increment the count information (e.g., nProgs) of the first parity group from "0" to "8".

[0132] When the programming operation manager 238 transmits programming commands for each of multiple data and parity checks belonging to a parity group to the memory device 250, the corresponding parity group count information (e.g., nProgs) can be reduced. For example, if the number of data and parity checks belonging to the first parity group is 8, the corresponding parity group count information (e.g., nProgs) can be increased to 8. When a data or a parity check belonging to the first parity group is transmitted to the memory device 250 along with a programming command, the count information (e.g., nProgs) can be reduced by 1. On the other hand, even if the parity check operation for the data belonging to the first parity group is not completed (i.e., even if the first parity group count information (e.g., nProgs) is not 8), the programming operation manager 238 can still transmit programming commands for data that has already been used in the parity check operation to the memory device 250. In this case, the first parity group count information (e.g., nProgs) can be increased to a value less than 8. If the data belonging to the first parity group is immediately transmitted to the memory device 250 along with the programming command after being used in the parity operation, the count information of the first parity group (e.g., nProgs) can vary in the range of "0" to "3" or "0" to "2".

[0133] According to the embodiments, refer to Figure 6 and Figure 7 The timing of data or parity being programmed in multiple memory regions or multiple memory dies in the memory device 250 of the controller 230 may be different. When a programming completion notification for data or parity belonging to a parity group is transmitted from multiple memory regions or multiple memory dies, the programming operation manager 238 can sequentially reduce the count information of the parity group from "8" to "0".

[0134] The programming operation manager 238 can perform parity checking operations based on information transmitted from the data input / output processing unit 232 and multiple data belonging to the parity check group. According to an embodiment, the programming operation manager 238 may include... Figure 2 The parity check device 240 described herein. The generated parity check can be stored in a first buffer 244 set or created in SRAM (⑥).

[0135] The programming operation manager 238 can transfer multiple data items belonging to the parity group and the parity check to the memory device 250 (⑦). See reference... Figure 6 and Figure 7The timing of the transfer (parity group migration) of each data entry and parity entry from the controller 230 to each of the multiple memory regions or multiple memory dies in the memory device 250 can be determined based on the operating state of the memory device 250. The timing of the multiple data entries and parity entries being programmed in the multiple memory regions or multiple memory dies in the memory device 250 can be different.

[0136] After multiple data and parity checks have been programmed in multiple memory regions or multiple memory dies in memory device 250, the multiple memory regions or multiple memory dies can notify controller 230 whether programming is complete (⑧). When programming operations for multiple data and parity checks belonging to a specific parity group are completed, programming operation manager 238 in controller 230 can decrement the corresponding parity group count information (e.g., nProgs) (⑨).

[0137] According to an embodiment, when a programming command generated by the controller 230 is received, the programming operation manager 238 in the controller 230 can, in response to the generated programming command, increment the count information (e.g., nProgs) of one of a plurality of parity groups. Furthermore, through the parity group count information (e.g., nProgs), the controller 230 can identify whether there are new parity groups to be programmed into the memory device 250 after the corresponding parity group, or identify the number of new parity groups to be programmed into the memory device 250. As the count information of the plurality of parity groups increases, the controller 230 can identify that the number of other parity groups to be programmed after the corresponding parity group has increased, or the number of programming operations to be performed in the memory device 250 has increased. In this way, it is possible to identify whether the number of programming operations to be processed or performed in the controller 230 and memory device 250 of the memory system 210 has increased or decreased.

[0138] Figure 9 A second operation of a memory system according to an embodiment of the present disclosure is illustrated. Specifically, Figure 9 A method of operation is described as follows: based on and Figure 8 The parity check time information stored in the memory system 210 described herein is used to migrate the parity check from the first buffer 244 to the second buffer 246.

[0139] Reference Figure 2 and Figure 9The parity migration unit 248 in the memory system 210 can periodically check the point in time (e.g., tParityAllocated) for which a parity identifier (e.g., ID, Index) is assigned (①), which is generated for a programming operation performed based on a write command. According to an embodiment, the parity migration unit 248 can check this point in time (e.g., tParityAllocated) whenever other data or other parity sets are ready for parity calculation.

[0140] Parity migrater 248 can determine whether to retain the corresponding parity in the first buffer 244 or migrate it to the second buffer 246 (②) based on the time point at which the identifier was assigned to a specific parity (e.g., tParityAllocated) and at least one criterion or threshold (e.g., 2000) set by controller 230. For example, parity migrater 248 can be configured to determine whether the value obtained by subtracting the time point stored in the parity (e.g., tParityAllocated) from the current time point (e.g., tCurrentTime) is equal to or greater than a reference time (e.g., tThreshold), as shown in Formula 1 below.

[0141] (tCurrentTime - tParityAllocated) ≥ tThreshold [Formula 1] Parity migrater 248 may, based on the comparison result, temporarily prevent parity group module 234 from assigning identifiers (e.g., ID, Index) to new parity groups (③). For example, parity migrater 248 may change information indicating the processing status of the corresponding parity group (e.g., bit values) so that parity group module 234 may not assign identifiers (e.g., ID, Index) to new parity groups. If parity migrater 248 changes the processing status of a parity group, parity group module 234 may not perform the relevant operations that should be performed to store the corresponding parity group in memory device 250.

[0142] The parity migration unit 248 can check the parity group information related to the programming operation being executed or to be executed in the memory device 250 through the programming operation manager 238 (④). The parity migration unit 248 can check the count information (e.g., nProgs) of the parity groups for which the programming operation manager 238 performs parity operations. For example, it can check the count information of the earliest parity group (i.e., the parity group that first transferred the programming command to the memory device 250) among the parity groups managed by the programming operation manager 238. In addition, based on the check result of the count information (e.g., nProgs), the parity migration unit 248 can check whether all programming commands for the corresponding parity group have been generated and whether the parity operation for the corresponding parity group has been completed (⑤).

[0143] According to this embodiment, parity mover 248 can determine that a parity group for which parity checking has been performed can be moved from the first buffer 244 to the second buffer 246. Parity mover 248 can identify that the parity checking operation of the parity group has been completed by checking that the count information (e.g., nProg) of the corresponding parity group no longer increments.

[0144] Furthermore, according to an embodiment, if the parity check operation for a specific parity group is not completed, the parity migration unit 248 can copy the parity calculated so far for that parity group from the first buffer 244 to the second buffer 246 for data backup. The parity migration unit 248 can identify that the parity check operation for that parity group is not completed based on the result that the count information (e.g., nProg) of the corresponding parity group is still increasing.

[0145] Parity migrater 248 can determine whether to migrate or copy the corresponding parity group to the second buffer 246 (⑥) by using the parity group count information (e.g., nProg) stored in the first buffer 244. Based on the decision of parity migrater 248, at least a portion of the parity groups stored in the first buffer 244 can be migrated or copied to the second buffer 246 (⑥).

[0146] Parity group module 234 can check the first buffer 244 or the second buffer 246 to determine whether to assign an identifier (e.g., ID, Index) to perform a parity operation on other data or another parity group (⑦). Parity group module 234 can remove the temporary block of parity migrater 248 from assigning an identifier (e.g., ID, Index) to another new parity group. Afterwards, as... Figure 8As shown, the parity group module 234 and the parity manager 236 can use a timer to record the time points (e.g., tParityAllocated) at which parity allocation identifiers (e.g., ID, Index) are generated corresponding to multiple data belonging to the parity group. Figure 8 ③).

[0147] Reference Figure 8 and Figure 9 The controller 230 within the memory system 210 includes multiple components that can be configured to: set write commands and multiple data transmitted from an external device as parity groups; perform parity checks on data belonging to the corresponding parity groups; and, after the parity check operation, transmit the multiple data and parity checks belonging to the corresponding parity groups to the memory device 250. During the above operations, the controller 230 can generate, control, or manage identifiers (e.g., ID, Index), timestamps (e.g., tParityAllocated), and count information (e.g., nProg) for the corresponding parity groups. Furthermore, the controller 230 can determine whether to migrate or copy the corresponding parity group from the first buffer 244 to the second buffer 246 based on the identifiers (e.g., ID, Index), timestamps (e.g., tParityAllocated), and count information (e.g., nProg) for the parity groups, thereby enabling more efficient use of internal resources for data input / output operations.

[0148] Figure 10 A data processing system according to an embodiment of the present disclosure is shown.

[0149] Reference Figure 10 The data processing system 500 may include a host 502, which is coupled to or connected to the memory system 510. For example, the host 502 and the memory system 510 may be interconnected via a data bus, host cable, etc., to perform data communication.

[0150] The memory system 510 may include a memory device 550 and a controller 530. The memory device 550 and the controller 530 in the memory system 510 can be considered as physically separate components or elements. The memory device 550 and the controller 530 can be connected via at least one data path. For example, the data path may include a channel and / or a way.

[0151] The memory device 550 may include multiple memory chips 552 (e.g., flash memory chips) connected to the controller 530 via multiple channels CH0, CH1, ..., CHn and paths W0, ..., W_k. The memory chips 552 may include multiple memory planes or multiple memory dies. According to embodiments, a memory plane may be considered a logical partition or a physical partition, including at least one memory block, drive circuitry capable of controlling an array comprising multiple non-volatile memory cells, and buffers capable of temporarily storing data input to or output from non-volatile memory cells. Each memory plane or each memory die may support an interleaved mode for parallel or simultaneous execution of multiple data input / output operations. According to embodiments, the memory blocks in each memory plane or each memory die included in the memory device 550 may be grouped into superblocks to input / output multiple data entries. The specific configuration may be modified based on the operational performance of the memory system 510. Figure 10 The internal configuration of the memory device 550 shown is illustrated. Embodiments of this disclosure are not limited to those described herein. Figure 10 The internal configuration described in [the document / document].

[0152] According to an embodiment, the memory device 550 and the controller 530 may be functionally divided components or elements. Further, according to an embodiment, the memory device 550 and the controller 530 may be implemented using a single chip or multiple chips. According to an embodiment, the controller 530 may correspond to... Figure 2 The controller 230 shown.

[0153] The controller 530 can perform data input / output operations (e.g., read operations, programming operations, erase operations, etc.) in response to requests or commands input from an external device, such as the host 502. For example, when the controller 530 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 550 is transferred to the controller 530. Furthermore, the controller 530 can perform operations independently without requests or commands input from the host 502. Regarding the operating state of the memory device 550, the controller 530 can perform operations such as garbage collection (GC), wear leveling (WL), and bad block management (BBM) for checking whether memory blocks are bad and disposing of bad blocks.

[0154] Each memory chip 552 may include multiple memory blocks. A memory block can be understood as a group of non-volatile memory cells in which data is erased together in a single erase operation. Although not shown, a memory block may include pages, which are groups of non-volatile memory cells that store data together during a single programming operation or output data together during a single read operation. For example, a memory block may include multiple pages. The memory device 550 may include voltage supply circuitry capable of supplying at least one voltage to the memory block. The voltage supply circuitry may supply read voltage, programming voltage, pass voltage, or erase voltage to the non-volatile memory cells included in the memory block.

[0155] The host 502 interacting with the memory system 510, or the data processing system 500 including the memory system 510 and the host 502, can be a mobile electronic device (e.g., a vehicle), a portable electronic device (e.g., a mobile phone, MP3 player, laptop, etc.), or a non-portable electronic device (e.g., a desktop computer, game console, television, projector, etc.). The host 502 can provide interaction between the host 502 and the user using the data processing system 500 or the memory system 510 through at least one operating system (OS). The host 502 can transmit multiple commands corresponding to user requests to the memory system 510, and the memory system 510 can perform data input / output operations (e.g., operations corresponding to user requests) corresponding to the multiple commands.

[0156] Reference Figure 10 The controller 530 in the memory system 510 operates together with the host 502 and the memory device 550. As shown, the controller 530 may have a layered structure including a host interface layer (HIL) 520, a flash translation layer (FTL) 540, and a flash interface layer (FIL, or memory interface layer) 560.

[0157] Figure 10 The Host Interface Layer (HIL) 520, Flash Translation Layer (FTL) 540, and Flash Interface Layer (FIL) 560 described herein are illustrated as one embodiment. The HIL 520, FTL 540, and FIL 560 can be implemented in various forms depending on the operational performance of the memory system 510. According to an embodiment, the HIL 520, FTL 540, and FIL 560 can be operated by a multi-core processor or processor with a pipelined architecture included in the controller 530.

[0158] The host 502 and the memory system 510 can use a set of predetermined rules or procedures or a preset interface for data communication to send and receive data between the host 502 and the memory system 510. For example, the host interface layer 520 in the memory system 510 may include means capable of sending signals, data, etc. to the host 502 or receiving signals, data, etc. sent from the host 502. According to an embodiment, as the area for sending and receiving data with the host 502, the host interface layer 520 may be implemented or driven using a technology called the host interface layer (HIL, hereinafter referred to as "HIL").

[0159] The buffer manager 580 included in the controller 530 can work in conjunction with the host interface layer (HIL) 520, flash translation layer (FTL) 540, and flash interface layer (FIL) 560 to control the input / output of data or operational information. To this end, the buffer manager 580 can set up or create various buffers, caches, or queues in memory, and control the data input / output of buffers, caches, or queues, or the data transfer between buffers, caches, or queues, in response to requests or commands generated by the host interface layer (HIL) 520, flash translation layer (FTL) 540, and flash interface layer (FIL) 560. For example, the controller 530 can temporarily store read data from the memory device 550 in response to a request from the host 502 before providing it to the host 502. Furthermore, the controller 530 can temporarily store write data from the host 502 in memory before storing it in the memory device 550. When operations such as read operations, programming operations, and erase operations are performed within the memory device 550, the read or write data transferred or generated between the controller 530 in the memory system 510 and the memory device 550 can be stored in buffers, queues, etc., established in the memory by the buffer manager 580, and managed in the buffers, queues, etc. In addition to read or write data, the buffer manager 580 can also store signals or information (e.g., mapped data, read commands, programming commands, etc., used to perform operations such as programming and read data between the host 502 and the memory device 550) in buffers, caches, queues, etc., established in the memory. The buffer manager 580 can set up or manage command queues, program memory, data memory, write buffers / caches, read buffers / caches, data buffers / caches, mapped buffers / caches, etc. According to an embodiment, the buffer manager 580 can set up or establish a first buffer 244 and a second buffer 246 in different volatile memories.

[0160] The Host Interface Layer (HIL) 520 can process commands, data, etc., transmitted from the host 502. By way of example, and not limitation, the Host Interface Layer 520 may include a command queue manager 522 and an event queue manager 524. The command queue manager 522 may sequentially store commands, data, etc., received from the host 502 in a command queue, and output commands, data, etc., to the event queue manager 524, for example, in the order in which they are stored in the command queue manager 522. The event queue manager 524 may sequentially transmit events for processing commands, data, etc., received from the command queue. According to an embodiment, the event queue manager 524 may classify, manage, or adjust commands, data, etc., received from the command queue. Further, according to an embodiment, the Host Interface Layer 520 may include an Encryption Manager (EncryptionP) 526, which is configured to encrypt response or output data to be transmitted to the host 502 or to decrypt encrypted portions of commands or data received from the host 502.

[0161] Multiple commands or data with the same characteristics can be transmitted from host 502, or multiple commands and data with different characteristics can be transmitted to memory system 510 after being mixed or co-located by host 502. For example, a command for reading data, i.e., a read command, can be transmitted to memory system 510, or a command for reading data, i.e., a read command, and a command for programming / writing data, i.e., a write command, can be transmitted to memory system 510 alternately. The command queue manager 522 of host interface layer 520 can sequentially store commands, data, etc., received from host 502 in a command queue. Then, host interface layer 520 can estimate or predict what type of internal operation controller 530 will perform based on the characteristics of the commands, data, etc., received from host 502. Host interface layer 520 can determine the processing order and priority of commands, data, etc., based on their characteristics. Based on the characteristics of commands, data, etc. received from host 502, the event queue manager 524 in host interface layer 520 is configured to receive events from buffer manager 580. These events should be internally processed or disposed of in memory system 510 or controller 530 according to the commands, data, etc. input from host 502. Then, event queue manager 524 can transfer events, including commands, data, etc., to flash translation layer (FTL) 540.

[0162] According to an embodiment, the Flash Translation Layer (FTL) 540 may include a Host Request Manager (HRM) 542, a Mapping Manager (MM) 544, a State Manager 546, and a Block Manager (BM / BBM) 548. Further, according to an embodiment, the Flash Translation Layer (FTL) 540 may implement a multi-threaded scheme to perform data input / output (I / O) operations. The multi-threaded FTL scheme can be implemented by using a multi-threaded, multi-core processor included in the controller 530. For example, the Host Request Manager (HRM) 542 may manage events transferred from an event queue. The Mapping Manager (MM) 544 may process or control mapped data. The State Manager 546 may perform operations such as garbage collection (GC) or wear leveling (WL) after checking the operational status of the memory device 550. The Block Manager 548 may execute commands or instructions on blocks in the memory device 550.

[0163] The Host Request Manager (HRM) 542 can use the Mapping Manager (MM) 544 and the Block Manager 548 to handle or process requests based on read and program commands and events passed from the Host Interface Layer 520. The HRM 542 can send a query request to the Mapping Manager (MM) 544 to determine the physical address corresponding to a logical address entered along with an event. The HRM 542 can send a read request with the physical address to the Flash Interface Layer 560 to handle the read request, i.e., handle the event. In an embodiment, the HRM 542 can send a program request (or write request) to the Block Manager 548 to program data into a specific blank page in the memory device 550 where no data is stored, and then can transmit a mapping update request corresponding to the program request to the Mapping Manager (MM) 544 to update the item related to the programmed data in the mapping information between the logical and physical addresses.

[0164] Block manager 548 can convert programming requests passed from host request manager (HRM) 542, mapping manager (MM) 544, and / or status manager 546 into flash programming requests for memory device 550 to manage flash blocks in memory device 550. To maximize or enhance the programming or writing performance of memory system 510, block manager 548 can collect programming requests and send them to flash interface layer 560 for multi-plane and one-shot programming operations. In an embodiment, block manager 548 sends several flash programming requests to flash interface layer 560 to enhance or maximize the parallel processing of multi-channel and multi-directional flash controllers.

[0165] In one embodiment, block manager 548 can manage blocks in memory device 550 based on the number of valid pages, selecting and erasing blocks without valid pages when free blocks are needed, and selecting blocks containing the minimum number of valid pages when determining which garbage collection to perform. State manager 546 can perform garbage collection to move valid data stored in the selected blocks to blank blocks and erase data stored in the selected blocks, so that memory device 550 can have enough free blocks (i.e., blank blocks without data).

[0166] When block manager 548 provides information about the block to be erased to state manager 546, state manager 544 can examine all flash pages of the block to be erased to determine if each page of the block is valid. For example, to determine the validity of each page, state manager 546 can identify the logical address recorded in the out-of-band (OOB) area of ​​each page. To determine if each page is valid, state manager 546 can compare the physical address of the page with the physical address mapped to the logical address obtained from the query request. State manager 546 can send a programming request to block manager 548 for each valid page. When the programming operation is complete, mapping manager 544 can update the mapping table.

[0167] Mapping manager 544 can manage mapping data, such as logical-physical mapping tables. Mapping manager 544 can handle various requests generated by host request manager (HRM) 542 or status manager 546, such as query requests, update requests, etc. Mapping manager 544 can store the entire mapping table in memory device 550, such as flash / non-volatile memory, and cache mapping entries according to the storage capacity of memory 544. When a mapping cache miss occurs while processing a query or update request, mapping manager 544 can send a read request to flash interface layer 560 to load the relevant mapping table stored in memory device 550. When the number of dirty cache blocks in mapping manager 544 exceeds a certain threshold, a programming request can be sent to block manager 546 to obtain clean cache blocks and store the dirty mapping table in memory device 550.

[0168] During garbage collection, State Manager 546 copies valid pages to the free block, and Host Request Manager (HRM) 542 can program the latest version of the data for the same logical address of the page and simultaneously issue an update request. Map Manager 544 may not perform a mapping table update if State Manager 546 requests a mapping update while the copying of valid pages has not been properly completed. This is because when State Manager 546 requests a mapping update, the mapping request is issued with old physical information, while the copying of valid pages is completed later. Map Manager 544 may perform a mapping update operation to ensure accuracy, if or only if the latest mapping table still points to the old physical address.

[0169] The Flash Interface Layer (FIL) 560 can exchange data, commands, status information, etc., with multiple memory chips 552 in the memory device 550 via data communication methods. According to an embodiment, the Flash Interface Layer 560 may include a Status Check Scheduler (SM / SC) 562 and a Data Path Manager or Controller (DPC) 564. The Status Check Scheduler 562 can check and determine the operating status of the multiple memory chips 552 connected to the controller 530, the operating status of multiple channels CH0, CH1, ..., CHn and multiple paths W0, ..., W_k, etc. It can schedule the transmission and reception of data or commands in response to the operating status of the multiple memory chips 552 and the multiple channels CH0, CH1, ..., CHn. The Data Path Manager 564 can control the transmission and reception of data, commands, etc., through the multiple channels CH0, CH1, ..., CHn and the paths W0, ..., W_k based on information transmitted from the Status Check Scheduler 562. According to an embodiment, the data path manager 564 may include a plurality of transceivers, each transceiver corresponding to each of a plurality of channels CH0, CH1, ..., CHn. Further, according to an embodiment, the status check scheduler 562 and the data path manager 564 included in the flash interface layer 560 may be implemented as a memory control sequence generator (not shown), or coupled to a memory control sequence generator.

[0170] According to an embodiment, the flash interface layer 560 may further include error correction code (ECC) circuitry 566, which is configured to perform error checking and correction on data transmitted between the controller 530 and the memory device 550. The ECC circuitry 566 may be implemented as a separate module, circuit, or firmware in the controller 530, or, according to an embodiment, in each memory chip 552 included in the memory device 550. The ECC circuitry 566 may include programs, circuits, modules, systems, or devices for detecting and correcting error bits in data processed by the memory device 550.

[0171] To locate and correct any errors in the data transmitted from memory device 550, ECC circuit 566 may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on the data to be programmed into memory device 550 to generate encoded data with parity bits added, and stores the encoded data in memory device 550. When controller 530 reads data stored in memory device 550, ECC decoder can detect and correct error bits contained in the data read from memory device 550. For example, after performing error correction decoding on data read from memory device 550, ECC circuit 566 can determine whether the error correction decoding was successful and output a command signal, such as a correction success signal or a correction failure signal, based on the result of the error correction decoding. ECC circuit 566 can use the parity bits generated during the ECC encoding process for data stored in memory device 550 to correct error bits in the read data entry. When the number of error bits is greater than or equal to the number of correctable error bits, ECC circuit 566 may not correct the error bits, but may instead output a correction failure signal indicating that the correction of the error bits failed.

[0172] According to embodiments, the ECC circuit 566 can perform error correction operations based on coding modulation such as: low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The ECC circuit 566 may include all circuits, modules, systems, and / or devices that perform error correction operations based on at least one of the above codes.

[0173] For example, the encoder in ECC circuit 566 can generate codewords as ECC-applied dataunits. A codeword of length n bits can include k bits of user data and (nk) bits of parity check. The code rate can be calculated as (k / n). The higher the code rate, the more user data can be stored in a given codeword. The longer the codeword length and the lower the code rate, the better the error correction capability of ECC circuit 566. Furthermore, ECC circuit 566 performs decoding using information read from channels CH0, CH1, ..., CHn. Based on the number of bits representing the information to be decoded, the decoder in ECC circuit 566 can be classified as a hard-decision decoder or a soft-decision decoder. A hard-decision decoder uses memory cell output information represented by 1 bit for decoding; this 1 bit of information is called hard-decision information. A soft-decision decoder uses more precise memory cell output information consisting of 2 or more bits; this information is called soft-decision information. ECC circuit 566 can use either hard-decision information or soft-decision information to correct errors included in the data.

[0174] According to an embodiment, to improve error correction capability, the ECC circuit 566 may use a concatenated code employing two or more codes. Alternatively, the ECC circuit 566 may use a product code that divides a codeword into rows and columns, and applies a different, relatively short ECC to each row and column.

[0175] According to an embodiment, the manager included in the host interface layer 520, flash translation layer (FTL) 540, and flash interface layer (FIL) 560 can be implemented using a general-purpose processor, accelerator, dedicated processor, coprocessor, multi-core processor, etc. According to an embodiment, the manager can be implemented using firmware that works with the processor.

[0176] Memory device 550 can correspond to Figure 2 The memory device 250 described herein. According to embodiments, the memory device 550 may include multiple memory devices providing the same characteristics and the same size of storage space, or it may include multiple memory devices providing different characteristics and different sizes of storage space. Furthermore, the memory device 550 may include multiple storage spaces or storage regions capable of distributing and storing data. Figure 2 Similar to the parity check device 240 shown, the ECC circuit 566 can generate parity checks for data distributed and stored in multiple storage spaces or storage areas.

[0177] According to an embodiment, the memory system 510 can support dividing the memory device 550 into storage regions based on a preset standard, and dedicating each of the divided regions to a specific logical block address (LBA) range. When supporting partitioned namespaces, the memory system 510 can improve access efficiency and reduce access time by using a logical block address range dedicated to each region, rather than using a specific logical block address range spanning multiple regions. For example, partitioned namespaces can improve write performance, which is very useful for workloads that require sequential writing of large amounts of data, such as video streaming or data backup.

[0178] Figure 11 A memory system according to an embodiment of the present disclosure is shown. Figure 11 A memory system comprising multiple cores or multiple processors is shown as an example of a data storage system. This memory system may support the High Speed ​​Non-Volatile Memory (NVMe) protocol.

[0179] NVMe is a transfer protocol designed for solid-state storage, offering significantly faster operation speeds than traditional hard drives. NVMe supports higher input / output operations per second (IOPS) and lower latency, resulting in faster data transfer speeds and improved overall data storage system performance. Unlike SATA, designed for hard drives, NVMe leverages the parallelism of solid-state storage, allowing for more efficient use of multiple queues and processors (e.g., CPUs). NVMe is designed to allow hosts to use multithreading to achieve higher bandwidth. NVMe allows full utilization of the parallel processing capabilities offered by SSDs. However, due to limited firmware scalability, limited computing power, and high hardware contention within SSDs, storage systems may not be able to handle large numbers of I / O requests in parallel.

[0180] Reference Figure 11 The host device, acting as an external device, can be connected to the memory system via multiple PCIe Gen 3.0 lanes, a PCIe physical layer (PCIe PHY) 412, and a PCIe core 414. The controller 400 may include three embedded processors 432A, 432B, and 432C, each using multiple cores 402A and 402B. Here, the multiple cores 402A and 402B or the multiple embedded processors 432A, 432B, and 432C may have a pipelined architecture.

[0181] Multiple embedded processors 432A, 432B, and 432C can be connected to an internal DRAM controller (DDR controller) 434 via a processor interconnect. Controller 400 further includes a low-density parity-check (LDPC) sequencer 460, a direct memory access (DMA) controller 420, a temporary storage memory 450 for metadata management, and an NVMe controller 410. Components within controller 400 can be coupled to multiple channels connected to multiple memory packages 480 via a flash physical layer (NAND flash PHY) 440. The multiple memory packages 480 may correspond to... Figure 10 The multiple memory chips 552 described in the document.

[0182] According to an embodiment, the NVMe controller 410 included in controller 400 is a storage controller specifically designed for solid-state drives (SSDs) using an NVMe interface. The NVMe controller 410 can manage data transfer between the SSD and the computer CPU, and can also manage other functions such as error correction, wear leveling, and power management. The NVMe controller 410 can support fast data transfer rates using a simplified, low-overhead protocol.

[0183] According to an embodiment, scratchpad memory 450 can be a temporary storage area set up by NVMe controller 410 to store data. Scratchpad memory 450 can be used to store data waiting to be written to multiple memory packages 480. Scratchpad memory 450 can also be used as a buffer, typically in conjunction with a small amount of dynamic random access memory (DRAM) or static random access memory (SRAM) to accelerate the write process. When a write command is executed, data can first be written to scratchpad memory 450 and then transferred to multiple memory packages 480 in larger blocks. Scratchpad memory 450 can serve as a temporary memory buffer to help optimize write performance across multiple memory packages 480. Scratchpad memory 450 can serve as an intermediate storage device before data is written to non-volatile memory cells.

[0184] The Direct Memory Access (DMA) engine (controller) 420 included in controller 400 is a component that enables data transfer between NVMe controller 410 and host memory in the host system without the intervention of the host processor. DMA engine 420 can enable NVMe controller 410 to directly read data from or write data to host memory without intervention from the host processor. According to embodiments, DMA engine 420 can use DMA descriptors that include data transfer-related information such as buffer address and transfer length, as well as other control information, to implement or support high-speed data transfer between the host and NVMe devices.

[0185] The LDPC sequencer 460 in the controller 400 is a component for error correction of data stored in multiple memory packages 480. LDPC codes are commonly used error correction codes in NAND flash memory to reduce bit error rates. The LDPC sequencer 460 can be designed to process the encoding and decoding of LDPC codes immediately when reading data from or writing data to NAND flash memory. According to an embodiment, the LDPC sequencer 460 can divide data into multiple blocks, encode each block using LDPC codes, and store the encoded data in the multiple memory packages 480. Then, when reading the encoded data from the multiple memory packages 480, the LDPC sequencer 460 can decode the encoded data based on the LDPC codes and correct errors that may occur during write or read operations. The LDPC sequencer 460 can correspond to... Figure 10 The ECC circuit 566 described in the document.

[0186] As described above, embodiments of this disclosure can provide an apparatus and method for dividing write data input from an external device into preset units to determine parity check groups, generating parity checks for the corresponding parity check groups, and migrating the corresponding parity check groups from a first memory with a first buffer supporting fast operation to a second memory with a second buffer supporting slow operation before transmitting and storing multiple data and parity checks into a memory device, thereby ensuring available space in the first buffer. Through this approach, the memory device or memory system can perform parity check operations to store other data in the memory device, thereby improving the data input / output performance (e.g., throughput) of the memory device or memory system.

[0187] Data storage devices, memory devices, or memory systems according to embodiments of the present disclosure can avoid or reduce the degradation of data input / output performance during the storage of large amounts of data without increasing the size of the memory, buffer, or cache that supports fast operation, thereby improving the data input / output performance of the memory system.

[0188] Furthermore, the memory device or memory system according to embodiments of this disclosure can improve the efficiency of internal resource utilization, thereby reducing or avoiding latency in operations that program multiple data by distributing multiple data to multiple storage areas, thereby improving tail latency without increasing the size of the memory system buffer.

[0189] The methods, processes, and / or operations described herein can be executed by code or instructions that run on a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be the apparatus described herein, or an element other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0190] Furthermore, another embodiment may include a computer-readable medium, such as a non-transitory computer-readable medium, for storing the aforementioned code or instructions. The computer-readable medium may be volatile or non-volatile memory or other storage devices that may be removably or permanently coupled to a computer, processor, controller, or other signal processing device to execute code or instructions for performing the operations of the method or apparatus embodiments described herein.

[0191] The controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features disclosed herein can be implemented, for example, as non-transient logic, which may include hardware, software, or both. When at least partially implemented as hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features can be, for example, any of a variety of integrated circuits, including but not limited to application-specific integrated circuits, field-programmable gate arrays, combinations of logic gates, systems-on-a-chip, microprocessors, or other types of processing or control circuitry.

[0192] When implemented at least partially as software, controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be the device described herein or an element other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of the method embodiments can convert the computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods described herein.

[0193] While this teaching has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims. Furthermore, embodiments may be combined to form other embodiments.

Claims

1. A memory system, comprising: A memory device comprising multiple data storage areas; as well as Controller: When at least one of the plurality of data storage areas is in an idle state and the time for which the first parity corresponding to the plurality of first data is stored in the first parity buffer is greater than the reference time, the available space in the first parity buffer is ensured by migrating the first parity from the first parity buffer to the second parity buffer. Generate a second parity check corresponding to multiple second data points; and The second parity check is stored in the available space within the first parity check buffer.

2. The memory system according to claim 1, wherein, The first parity buffer has a faster data input and output speed, i.e., input / output speed, than the second parity buffer.

3. The memory system according to claim 2, wherein, The first parity buffer is set or established in static random access memory (SRAM), and the second parity buffer is set or established in dynamic random access memory (DRAM).

4. The memory system according to claim 1, wherein, The controller migrates a first parity check group, including the first parity check and the plurality of first data, from the first parity check buffer to the second parity check buffer.

5. The memory system according to claim 4, wherein, The controller releases the first parity group from the second parity buffer based on a programming completion notification from the memory device for the first parity and the plurality of first data.

6. The memory system according to claim 1, wherein, The controller receives multiple data from an external device, determines multiple first data from the multiple data, and maps the physical address of the multiple first data stored in the memory device to the logical address of the multiple first data.

7. The memory system according to claim 1, wherein, Read operations, programming operations, and erase operations are performed independently in each of the plurality of data storage regions in the memory device, and When the erase operation is performed in the first storage area among the plurality of data storage areas, the programming operation or the read operation is performed in the second storage area among the plurality of data storage areas.

8. The memory system according to claim 7, wherein, Each of the plurality of data storage regions includes a memory die or a memory plane.

9. The memory system according to claim 1, wherein, The controller transmits the plurality of first data to the memory device, then transmits the first parity check to the memory device, and... The memory system distributes and programs the plurality of first data and the first parity check into different data storage areas.

10. The memory system according to claim 1, wherein, The controller: When the multiple data storage areas are busy, the first parity check is retained in the first parity check buffer and the generation of the second parity check is delayed; as well as If there is no available space in the first parity buffer to store the second parity check, the generation of the second parity check is delayed.

11. The memory system according to claim 1, wherein, The controller periodically checks the duration for which the first parity check is stored in the first parity check buffer; and The reference time is less than the operating margin of an erase operation performed in the memory device and greater than the operating margin of a programming operation.

12. A memory system, comprising: A memory device comprising multiple memory planes or multiple memory dies, wherein data input and output, i.e., input / output operations, are performed independently in the multiple memory planes or multiple memory dies; as well as Controller: After transmitting multiple first data to the multiple memory planes or the multiple memory dies, a first parity check associated with the multiple first data is moved from a first buffer to a second buffer to ensure available space in the first buffer. The first parity check is retained in the first buffer based on whether the multiple first data are stored in the multiple memory planes or the multiple memory dies. A second parity check is generated, which is associated with multiple second data to be transmitted and stored in the plurality of memory planes or the plurality of memory dies; and The second parity check is stored in the available space.

13. The memory system according to claim 12, wherein, When the first parity check has been stored in the first buffer for a longer period than the reference time, the controller moves the first parity check from the first buffer to the second buffer.

14. The memory system according to claim 12, wherein, The first buffer has a faster data input / output speed than the second buffer.

15. The memory system according to claim 12, wherein, The controller migrates a first parity check group, including the first parity check and the plurality of first data, from the first buffer to the second buffer.

16. The memory system according to claim 15, wherein, The controller releases the first parity check group from the second buffer based on a programming completion notification from the memory device for the first parity check and the plurality of first data.

17. The memory system according to claim 12, wherein, The controller: Each of the plurality of first data is transmitted to the plurality of memory dies or the plurality of memory planes in a distributed manner; and The first parity check is transmitted to a memory plane or memory die that has not yet transmitted the plurality of first data.

18. The memory system according to claim 12, wherein, The controller: When all of the multiple memory planes or the multiple memory dies are busy, the first parity check is retained in the first buffer and the generation of the second parity check is delayed; as well as If there is no available space in the first buffer to store the second parity check, the generation of the second parity check is delayed.

19. A method of operating a memory system, comprising: Determine and distribute multiple first data points across multiple memory planes or multiple memory dies; Calculate the first parity check associated with the plurality of first data; After transmitting at least some of the plurality of first data to the plurality of memory planes or the plurality of memory dies, it is determined whether at least one of the plurality of memory planes or the plurality of memory dies is in an idle state; When at least one of the plurality of memory planes or the plurality of memory dies is in an idle state, the first parity check is moved from the first buffer to the second buffer to ensure available space in the first buffer. and A second parity check is generated, which is stored in the available space and associated with multiple second data to be distributed and stored in the multiple memory planes or the multiple memory dies.

20. The method of claim 19, further comprising: After storing the plurality of first data in the plurality of memory planes or the plurality of memory dies, the first parity check stored in the second buffer is transmitted.

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