A dynamic cache control method and system based on FPGA

Abstract

The application discloses a kind of based on FPGA's dynamic cache control method and system, the method includes: the even division of DDR cache space is divided into multiple fixed capacity cache block, the mapping relationship of cache block number and physical address is established;Idle block FIFO queue is set to manage idle cache block, multiple occupied block FIFO queue is set to manage occupied cache block according to data type;Data write, whether current cache block is full based on type block counter and type address counter is judged, if yes, new cache block is applied from idle block FIFO queue and is written in corresponding occupied block FIFO queue, and the address of writing is calculated to complete data storage;Data read, through multiple independent read window, fixed window address is dynamically mapped to the physical address of cache block occupied by different data types, and after reading is completed, cache block is recycled to idle block FIFO queue, and the application has the advantages of simple FPGA implementation, high cache utilization, supporting multi-window parallel readout.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a dynamic cache control method and system based on FPGA, which is suitable for high-speed data cache management in scenarios involving multi-data types and multi-threaded parallel processing. Background Technology

[0002] With the rapid development of new technologies such as big data and artificial intelligence, computer systems need to receive and process increasingly larger amounts of data, and the types of data are becoming more and more diverse. FPGA (Field Programmable Gate Array), as a flexible programmable digital logic device, has a large number of programmable gate circuits and abundant hardware circuit resources, which can flexibly implement various data interfaces, making it very suitable for the acquisition, reception, and storage of various types of high-speed data.

[0003] To achieve high-bandwidth, multi-channel data storage and management, a common approach is to combine a CPU (Central Processing Unit) with an FPGA to store various data types. The FPGA implements the data interface, receiving high-speed data from external inputs, typically including multiple channels and various data types. After processing by the FPGA, the various data types are categorized and cached in DDR memory. Then, the CPU controls the storage of each data type from the DDR cache into the SSD.

[0004] Typically, FPGAs use a fixed partitioning of the DDR cache space to implement multi-type data caching. This method pre-allocates a fixed cache space for each data type, and different types of data are cached cyclically within their respective cache spaces. This method has the advantages of being simple and easy to implement, but its cache space utilization efficiency is low and its flexibility is insufficient when the bandwidth of multiple data types is uneven.

[0005] The invention patent published under CN 119807091A proposes a dynamic memory management system based on FPGA. This system uses a binary tree data structure to represent the usage of FPGA cache resources, enabling centralized allocation of storage resources and avoiding problems caused by instantaneous fluctuations in data channel bandwidth, thus improving the allocation efficiency of cache resources. However, this method uses a binary tree data structure, making the node state judgment logic very complex. Furthermore, because the occupancy status of nodes at different levels of the binary tree varies, the processing latency varies significantly, making it difficult to uniformly control timing.

[0006] To improve the flexibility and efficiency of data caching, this invention proposes a dynamic cache control method based on FPGA, which dynamically controls and manages the DDR cache mounted on the FPGA. This method uses multiple first-in-first-out queues to manage cache blocks, allocating cache spaces of different capacities according to the bandwidth of different input data types, thereby improving cache utilization efficiency. It also has advantages such as simple structure and fixed latency. Summary of the Invention

[0007] One objective of this invention is to provide an FPGA-based dynamic cache control method to address the problem that existing FPGA-based fixed-partition circular caches cannot maximize cache space utilization. This method overcomes the drawbacks of existing FPGA-based dynamic memory management systems, such as complex structures and uncertain processing latency, thereby maximizing cache space utilization. A second objective of this invention is to provide an FPGA-based dynamic cache control system.

[0008] One of the objectives of this invention is achieved through the following technical solution: A dynamic buffer control method based on FPGA, specifically including: The DDR physical cache space attached to the FPGA is logically and evenly divided into N cache blocks, N≥2. Each cache block has a fixed and equal storage capacity BLOCK_SIZE, and a unique cache block number block_num is assigned to each cache block. A one-to-one mapping relationship between the cache block number block_num and the DDR physical address mem_addr is established. An idle cache management module and an occupied cache management module are set up inside the FPGA. The idle cache management module maintains an idle block FIFO queue to store the cache block numbers that are currently idle, and configures an idle block counter idle_block_cnt to record the number of cache block numbers in the idle block FIFO queue. The occupied cache management module maintains M occupied block FIFO queues, M≥1 and M is a configurable parameter. The M occupied block FIFO queues correspond one-to-one with M data types, and each occupied block FIFO queue is used to store the cache block numbers that are currently occupied for the corresponding data type. During data writing, external data is preprocessed to form data packets with a fixed capacity. Each data packet contains the data to be stored and the corresponding data type number (type_num). Based on the data type number (type_num), a corresponding type block counter (type_block_cnt) and a type address counter (type_addr_cnt) are determined. The type block counter (type_block_cnt) records the number of cache blocks already occupied by this data type, and the type address counter (type_addr_cnt) records the written offset within the cache block currently being used by this data type. It is then determined whether the value of the type address counter is equal to the cache value. If the block size BLOCK_SIZE is less than the cache block size, the physical base address corresponding to the current cache block number plus the value of the type address counter is used as the write address; if it is equal to the cache block size, it means that the current cache block is full, so a new cache block number is read from the free block queue to cache the current data packet, and the free block counter idle_block_cnt is decremented by 1. The physical address to be written to the data packet is the newly acquired cache block base address, and the type address counter value is cleared to zero. The actual cache physical address to which the input data packet is written is composed of the cache block number and the type address counter value. The data packet is written to the DDR physical storage location corresponding to the write address. When reading data, K read windows are set, where K ≥ 1 and K is a configurable parameter. Each read window operates independently and in parallel. Each read window has a fixed window access address space, the size of which is consistent with the cache block capacity. The read window number is window_num. When data of a certain data type needs to be read, the data type number type_num is assigned to an idle read window. This read window pops a cache block number block_num from the FIFO queue of the corresponding data type in the cache management module. This cache block number is used as the physical cache address mem_addr=b that the read window actually accesses. The process `lock_num*BLOCK_SIZE` is defined as cache release, and the type block counter `type_block_cnt` corresponding to this data type is decremented by 1. The read window maps the fixed window access address space to the DDR physical address space corresponding to the cache block number, so that the window address `win_addr` accessed by the external read command is converted to the corresponding DDR physical address `mem_addr`, thereby reading the data of this data type. After the data is read, the read window writes the cache block number back to the free block FIFO queue of the free cache management module and increments the free block counter `idle_block_cnt` by 1.

[0009] Specifically, during data writing, after writing the data packet to the DDR physical storage location corresponding to the write address, the cache block number corresponding to the write address is written to the occupied block FIFO queue corresponding to the data type, and the type block counter type_block_cnt corresponding to the data type is incremented by 1.

[0010] Furthermore, the initialization process of the free block FIFO queue is as follows: the free block FIFO queue is reset and cleared, then the cache block numbers 0 to N-1 are written into the free block FIFO queue in sequence, and the free block counter is set to N.

[0011] Furthermore, the M FIFO queues corresponding to the M data types are all empty during initialization, and the type block counter and type address counter corresponding to each data type are cleared to zero. The actual cache space currently occupied by each data type is: type block counter value × cache block capacity + type address counter value, i.e. (type_block_cnt-1)*BLOCK_SIZE+type_addr_cnt.

[0012] Furthermore, during data reading, when the value of the type block counter corresponding to a certain data type reaches a preset reading threshold, the data reading process for that data type is triggered, and the reading threshold is a configurable parameter; Furthermore, during data reading, if a read window has completed data reading, a close command is sent by the external CPU or the internal control logic of the FPGA, and the read window responds to the close command by performing a write-back operation of the cache block number.

[0013] The second objective of this invention is achieved through the following technical solution: A dynamic cache control system for implementing the method includes: DDR memory chips are used as physical cache media. An FPGA chip, wherein the FPGA chip integrates: The free cache management module is used to maintain the free block FIFO queue and the free block counter; The occupancy cache management module is used to maintain M occupancy block FIFO queues, where M is the same as the number of data types; The data write control module is used to receive externally input data packets, calculate the write address based on the data type number and the current cache block occupancy status, and control the write operation to the DDR memory chip. The data readout control module is used to control the allocation, mapping, and release of K readout windows. Each readout window works independently and in parallel. A DDR driver controller is used to drive the read and write operations of the DDR memory chip. The data interaction module is used for the transmission of control and status signals between the FPGA chip and the external CPU.

[0014] Furthermore, the input interface of the data writing control module and the output interface of the data reading control module are both AXI14 interfaces, which are connected to external devices after being converted via PCIe interfaces.

[0015] Furthermore, the data write control module is configured with a set of counting registers for each data type. The counting registers include a type block counter and a type address counter. The type block counter records the number of cache blocks occupied by the corresponding data type, and the type address counter records the write offset within the current cache block of the corresponding data type.

[0016] Furthermore, the readout window includes: The window status register is used to identify whether the current window is in an idle or active state. The window binding register is used to record the data type number and cache block number of the currently bound window; Address translation logic is used to convert window access addresses into DDR physical addresses.

[0017] The beneficial effects of this invention are: (1) This invention divides the DDR cache space evenly into multiple fixed-capacity cache blocks and establishes a deterministic mapping relationship between cache block numbers and physical addresses. This allows the FPGA to manage the cache by maintaining only a FIFO queue of cache block numbers. All FIFO operations do not increase latency with the increase of cache size, significantly reducing the consumption of FPGA logic resources and implementation complexity. The invention adopts a two-layer architecture of "single global idle FIFO queue + multi-way occupied FIFO queue classified by data type", combined with dynamic cache allocation on the write side and release and recycling on the read side, forming a complete closed-loop management of the cache block lifecycle. This ensures the maximum utilization of cache resources and avoids the problems of duplicate allocation or untimely release of cache blocks, achieving zero idle cache space.

[0018] (2) The present invention sets up multiple independent read windows on the read side, each window independently maintains the mapping relationship, and dynamically maps the fixed window address to the physical address of the cache block occupied by different data types. Multiple windows can work in parallel at the same time without interfering with each other. With the writing capability, it can realize full-duplex parallel processing of multiple data streams, which has significant advantages in high-throughput scenarios such as concurrent storage of multiple hard disks and multi-channel video encoding and decoding.

[0019] (3) The present invention supports independent configuration of multiple parameters such as cache block capacity, total number of cache blocks, total number of data types and number of read windows. The system is configured by the external CPU during initialization, and each module automatically completes the internal resource adaptive initialization accordingly. It can flexibly adapt to different application requirements from lightweight data acquisition to high-performance multi-channel parallel processing, with a wide range of applications and high practical value.

[0020] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the dynamic cache management principle of the present invention; Figure 2 Flowchart for requesting cache space for writing data; Figure 3 Schematic diagram of the data readout window; Figure 4 Flowchart for data readout cache release and reclamation process; Figure 5 This is a diagram illustrating the cache allocation process. Figure 6 This is a diagram illustrating the cache release and recycling process. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described below with reference to the accompanying drawings. In the description of this invention, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0023] As shown in the principle block diagram of Figure 1, this invention implements an FPGA-based dynamic cache control method inside an FPGA. This method is implemented by an FPGA-based dynamic cache control system. The FPGA cache dynamic control system provided in this embodiment integrates an idle cache management module, an occupied cache management module, a data write control module, a data read control module, and a DDR driver controller inside the FPGA chip. In addition, it also includes a data interaction module for control and status signal transmission between the FPGA and the CPU.

[0024] The following will provide a further introduction to each functional module: (1) Free Cache Management Module: Used to maintain a global free block FIFO queue. The depth of this FIFO queue is equal to the total number of cache blocks N, and each storage unit stores a cache block number block_num. The free block counter idle_block_cnt is used to record the number of cache block numbers in the current FIFO queue, with an initial value of N; (2) Cache Management Module: Used to maintain M FIFO queues for occupied blocks. Each queue corresponds to a data type. The depth of each FIFO queue for occupied blocks is equal to the total number of cache blocks N. Each storage unit stores a cache block number block_num. The value of M is configured by the external CPU through the data interaction module.

[0025] (3) Data Write Control Module: Receives externally input data packets via the AXI1 interface. The data packets contain the data to be stored and the corresponding data type number. Internally, the data write control module configures a set of registers for each data type: a type block counter (with a bit width of ceil(log2(N+1)) bits) and a type address counter (with a bit width of ceil(log2(cache block capacity+1)) bits). The type block counter records the number of cache blocks occupied by the data type, and the type address counter records the offset of the bytes written within the current cache block.

[0026] (4) Data readout control module: controls K readout windows (window 1 to window K). Each readout window contains: a window status register (1 bit, 0 indicates idle, 1 indicates working), a window binding register (records the data type number and cache block number of the bound window), and address translation logic (combinational logic circuit that converts the window access address to the DDR physical address in real time). The value of K is configured by the external CPU through the data interaction module.

[0027] (5) DDR driver controller: contains the DDR driver control logic inside the FPGA, responsible for driving the read and write operations of the DDR memory chip outside the FPGA chip, and converting the DDR physical address into the access timing of the DDR memory chip.

[0028] (6) Data interaction module: responsible for the control and status signal transmission between FPGA and external CPU, including parameter configuration, status query, reading trigger instructions, etc.

[0029] DDR memory chips serve as physical cache media, exchanging data with FPGA chips through a DDR driver controller.

[0030] In this embodiment, both the input interface of the data write control module and the output interface of the data read control module are AXI14 interfaces. The AXI4 interface can be converted to a PCIe interface within the FPGA and then connected to external devices. (The AXI14 interface refers to a mapped interface designed according to the AXI4 protocol in the AMBA bus standard officially released by ARM. The AXI4 protocol is currently the most mainstream and widely used version in SoC and FPGA design. For ease of distinction, in...) Figure 1 In this diagram, the interfaces involved in the data writing control module are represented by AXI1 and AXI2, and the interfaces involved in the data reading control module are represented by AXI3 and AXI4.

[0031] The FPGA-based dynamic cache control method of the present invention can be divided into three important stages: cache space initialization stage, data writing stage, and data reading stage. The following will focus on the specific content of the three stages.

[0032] Cache space initialization phase: The external DDR physical cache space of the FPGA is logically and evenly divided into N cache blocks, N≥2. Each cache block has a unique cache block number block_num, and the cache block number corresponds to a unique physical cache address mem_addr. The capacity of each cache block BLOCK_SIZE is fixed and is the smallest dynamically allocated unit. A one-to-one mapping relationship between the cache block number and the DDR physical address is established. Specifically, the physical base address corresponding to the cache block number i (i=0, 1, ..., N-1) is: DDR cache space start address + i × cache block capacity.

[0033] Within the FPGA, an idle buffer management module and an occupied buffer management module are configured. The idle buffer management module maintains an idle block FIFO (First-In-First-Out) queue to store the numbers of currently idle buffer blocks, and configures an idle block counter `idle_block_cnt` to record the number of buffer block numbers in the idle block FIFO queue. During initialization, the idle block FIFO queue is reset and cleared. Then, buffer block numbers 0 to N-1 are written sequentially into the idle block FIFO queue, and the idle block counter is set to N, indicating that all buffer blocks are in an idle and available state.

[0034] The cache management module maintains M FIFO queues for occupied blocks, where M ≥ 1 and M is a configurable parameter. Each of the M FIFO queues corresponds one-to-one with one of the M data types. Each FIFO queue stores the currently occupied cache block number for the corresponding data type. Initially, all FIFO queues are empty.

[0035] Data writing phase: After preprocessing, external data is formed into data packets with fixed capacity. Each data packet contains a unique data type number (type_num) in addition to the data to be stored. The data packet is input to the data writing control module via an input interface (such as interface AXI1). After obtaining the actual physical address (mem_addr) of the cache to which the data packet is written, it is written to the corresponding physical cache. The specific process is as follows: Figure 2 As shown. The data write control module configures a set of counter registers for each data type, including a type block counter (type_block_cnt) and a type address counter (type_addr_cnt). The type block counter records the number of cache blocks already occupied by the corresponding data type, and the type address counter records the written offset within the cache block currently in use for the corresponding data type (i.e., the storage capacity already occupied within the current cache block). Therefore, the actual cache space occupied by each data type can be calculated as (type_block_cnt-1)*BLOCK_SIZE+type_addr_cnt. During initialization, all type block counters and type address counters are cleared to zero.

[0036] For the currently input data packet, first determine the corresponding type block counter and type address counter based on its data type number, and then perform the following judgment and write operations: The system checks if the type address counter value equals the cache block capacity (by checking if the type address counter value `type_addr_cnt` for this data type reaches the total cache block capacity `BLOCK_SIZE`, and determining if the currently occupied cache block is full). If the type address counter value is less than the cache block capacity, it means the current cache block is not yet full. The physical address to write the current data packet is then: the physical base address corresponding to the current cache block number + the type address counter value. After writing the data packet to this address, the type address counter is incremented by the data size (in bytes) of the data packet.

[0037] If the type address counter equals the cache block capacity, it means the current cache block is full. A new cache block number is then read from the free block queue to cache the current data packet, and the free block counter `idle_block_cnt` is decremented by 1. The physical address where the data packet is written is the base address of the newly acquired cache block, and the type address counter is reset to zero. The actual cache physical address where the input data packet is written is composed of the cache block number and the type address counter, i.e., `mem_addr = block_num * BLOCK_SIZE + type_addr_cnt`. It's important to note that after obtaining the current cache block number from the free block queue and completing the writing of the current data packet, the current cache block number needs to be written to the occupied block queue corresponding to that data type, and the type block counter `type_block_cnt` is incremented by 1, indicating that the current cache block is occupied by that data type and cannot be used to store other data types.

[0038] The process of obtaining a new cache block number from the free block FIFO queue is defined as "cache request", and the process of writing the cache block number into the corresponding data type occupied block FIFO queue is defined as "cache occupancy".

[0039] The actual cache space currently occupied by each data type is: type block counter value × cache block capacity + type address counter value.

[0040] Data read phase: First, it is necessary to query the type block counters occupied by each data type in the cache management module. If the type block counter type_block_cnt of a certain data type reaches the set read threshold TH, the data read process is initiated. Specifically... Figure 3 As shown, K read windows are set in the data read control module, where K ≥ 1 and K is a configurable parameter. Each read window is independent and can work in parallel. Each read window has a fixed window access address space, and the size of the window access address space is consistent with the cache block capacity.

[0041] like Figure 4As shown in the flowchart, when data of a certain data type needs to be read (e.g., controlled by the CPU or FPGA itself, the read process is triggered when the type block counter value of a certain data type reaches a preset read threshold), the data type number `type_num` is assigned to a currently idle read window. This read window pops a cache block number `block_num` from the head of the FIFO queue corresponding to that data type in the cache management module, removes the cache block number from the FIFO queue, decrements the type block counter `type_block_cnt`, and uses this cache block number as the physical cache address `mem_addr = block_num * BLOCK_SIZE` actually accessed by the read window. This process is defined as "cache release".

[0042] The read window then maps the fixed window access address space to the DDR physical address space corresponding to the above cache block number, so that the window address accessed by the external read command is converted into the corresponding DDR physical address, thereby reading the data of that data type (that is, at this time, all external read command addresses win_addr will be converted into the physical address mem_addr of the data type bound to the window after passing through the window, thereby reading the cached data of that data type).

[0043] After the data reading is complete (e.g., an external CPU or FPGA internal control logic sends a close command), the read window writes the currently used cache block number back to the tail of the free block FIFO queue of the free cache management module and increments the free block counter idle_block_cnt by 1. This process is defined as "cache reclamation".

[0044] Multiple readout windows operate independently, each maintaining its own mapping relationship. Updating the mapping of any window does not affect the current mapping state of other windows or the data transmission being performed. Multiple windows can work in parallel simultaneously.

[0045] It should be noted that in this embodiment, the cache block capacity, the number of cache blocks N, the number of data types M, and the number of read windows K are all externally configurable parameters. During the system initialization phase, the external CPU writes the configuration parameters to each module inside the FPGA through the data interaction module. Cache block capacity BLOCK_SIZE: Used by the write control module and DDR driver controller for address calculation and FIFO depth configuration; Number of cache blocks N: Write to the free cache management module (configure the depth of the free block FIFO queue) and the data write control module (configure the counter bit width); Data type quantity M: Write occupancy cache management module (configures the number of occupancy block FIFO queues) and data write control module (configures the number of counter register groups); Number of read windows K: The write data read control module (configures the number of read window instances).

[0046] After configuration, each module automatically initializes its internal FIFO, counters, and registers according to the configuration parameters. These parameters remain unchanged during system operation; any modifications require system reinitialization.

[0047] Furthermore, in this invention, each cache block undergoes the following state transitions during its lifetime: State 1: Idle State: The cache block number is stored in the free block FIFO queue, and the free block counter records its count. Cache blocks in this state can be requested for use by write operations of any data type.

[0048] State 2: Occupied State: The cache block number is popped from the free block FIFO queue and written into the occupied block FIFO queue of a certain data type, and the type block counter is incremented accordingly. The cache block in this state stores data of that data type and cannot be used by other data types until it is read out and released.

[0049] State 3: Release State: The cache block number is popped from the occupied block FIFO queue, and the type block counter is decremented accordingly. Cache blocks in this state no longer store valid data and are waiting to be reclaimed to the free queue.

[0050] State 4: Reclaimed State: The cache block number is written back to the free block FIFO queue, and the free block counter is incremented accordingly. Cache blocks in this state return to the free state and can be requested again.

[0051] The above state transitions constitute a complete closed-loop management system, ensuring that each cache block can be tracked and managed throughout its entire lifecycle.

[0052] Specific Implementation Example 1: In this example storage system, up to 64 data types are designed, which need to be stored as different files on the SSD. Therefore, a separate cache space needs to be allocated in the FPGA for each type of data. The dynamic cache control method used in this invention manages 64 cache block queues in the FPGA, realizing 64 data caches. The actual storage space for each data type can be dynamically allocated as needed, and all cache space is effectively utilized.

[0053] In a multi-disk storage system example based on an FPGA and CPU combination, external data is first input into the FPGA for caching, and then the CPU controls the final storage in the SSD. The DDR memory mounted on the FPGA serves as the physical data cache, with a data bit width of 64 bits, a total capacity of 4GB, and is driven by an 800MHz clock. The final DDR bandwidth is 64bit * 800MHz * 2 times sampling / 2 (read / write bidirectional channel) = 50Gb / s. This invention uses a FIFO queue to achieve dynamic management of the DDR cache.

[0054] First, set the minimum cache block size to BLOCK_SIZE = 16MB, meaning the smallest unit for dynamic cache allocation is 16MB. Each cache block can be allocated to different data types. Divide the total 4GB DDR cache space into 4GB / 16MB = 256 cache blocks, and then number the cache blocks from 0 to 255. The cache block number is actually the base address of that cache block in DDR. First, instantiate a FIFO with a depth of 256 on the FPGA as a free cache block queue. During initialization, write the cache block numbers from 0 to 255 as block_num into the free cache block queue. At this point, all 256 cache blocks are in the free cache block queue, and the free block counter idle_block_cnt = 256, indicating that all caches are currently in an idle state, unoccupied, and the remaining cache capacity is 4GB. Simultaneously, instantiate 64 more FIFOs with a depth of 256 as occupied cache block queues. Each queue corresponds to a data type, and the occupied cache block queue stores the cache block numbers occupied by that data type. During initialization, all occupied cache block queues are cleared. Each queue of occupied cache blocks is controlled by two counters: a type block counter (type_block_cnt) and a type address counter (type_addr_cnt). The block counter tracks the number of cache blocks occupied for that data type, while the address counter tracks the capacity already used by data in the most recently occupied cache block. Initially, both counters are 0.

[0055] After data is input into the FPGA, it undergoes initial processing and packetization. Each data packet is 4KB in size, and each packet is accompanied by a data type number. Data with the same data type number will ultimately be stored in a single file on the SSD. For example... Figure 5As shown, when the pre-processed data packet is input to the data write control module, the data type number is first obtained, for example, if the data type number type_num is 0. Then, the class address counter type_addr_cnt for data type 0 is read. If type_addr_cnt = 16MB, it means that the cache block occupied by data type 0 is full and a new cache block needs to be requested. A cache block number block_num, for example, 1, is read from the free cache block queue and used as the new cache base address. Thus, the cache physical address for the current data packet to be written is calculated as mem_addr = block_num * 16MB. After the data packet is written, block_num needs to be written to the cache block queue occupied by data type 0, and type_block_cnt is incremented by 1. At the same time, type_addr_cnt needs to be increased by the number of data packets, type_addr_cnt = 0x1000 (4KB). If type_addr_cnt ≠ 16MB, it means that the cache block occupied by data type 0 is not full. Then continue writing to the cache block. After completion, the number of data packets needs to be incremented by one: type_addr_cnt = type_addr_cnt + 0x1000.

[0056] Before reading data, the CPU queries the type block counter (type_block_cnt) and type address counter (type_addr_cnt) of each occupied cache block queue through the data interaction module to determine the capacity of the cached data. For example... Figure 6 As shown, for example, if data type 1 occupies 3 cache blocks (type_block_cnt=3), the data read control flow is initiated, and the data read process is in units of 16MB. The data read control module controls 8 read windows, each independent of the others. Each window has a fixed access address, and its size is consistent with the cache block size, which is 16MB. The function of the read window is to map the window address directly accessed from the outside to the actual DDR physical cache address. When data of data type 1 needs to be read, the data type number 1 is sent to an idle read window 0. Read window 0 then reads the earliest cache block number 2 occupied by this channel data type from the occupied cache block queue 1, and uses this cache block number as the base address of the DDR physical cache actually accessed by the read window. Therefore, the read window address 0MB~16MB is converted to the actual physical address 2*16MB~(2+1)*16MB. After the data is read, the read window writes the currently used cache block number 2 back to the idle cache block queue, completing cache reclamation. The data readout control module contains multiple readout windows, which are independent of each other and can work sequentially to ensure the continuity of data readout.

[0057] Example 2: This example is a 4-channel high-definition video data acquisition and processing system. The 4 video sources correspond to 4 data types (M=4), and each video data is input to the FPGA in frames. The buffer block capacity BLOCK_SIZE is configured as 1MB (to adapt to typical video frame fragment size), the number of buffer blocks N is 1024 (total buffer space 1GB), and the number of read windows K is 8 (to support simultaneous reading of 4 channels and additional windows for reading other data).

[0058] After preprocessing, the four video data streams are formed into fixed-capacity data packets, which are then input into the control module using data type numbers 0, 1, 2, and 3, respectively. Each data type independently maintains its own type block counter and type address counter, requesting and occupying cache blocks without interference. When the writing speed of a particular video data stream is faster, its corresponding type block counter increases rapidly, automatically occupying more cache blocks; other video data streams occupy cache blocks independently according to their respective speeds, without affecting each other, fully demonstrating the dynamic, on-demand allocation of cache resources.

[0059] On the read side, once the complete frame data of a certain video stream has been written (determined by the type block counter reaching a preset threshold), the data read control module allocates this data type to an idle read window. The window maps a fixed window address space to the physical address of the buffer block occupied by that video stream data. Four video streams can be allocated to four different read windows for parallel reading, enabling simultaneous output display or storage of the four video streams.

[0060] Once a read window finishes reading a frame of data, the corresponding buffer block is automatically released and reclaimed, returning it to the free queue for subsequent writing. Through this closed-loop management, the buffer space continuously circulates between writing and reading, achieving pipelined buffer processing of video data.

[0061] Those skilled in the art should understand that the above examples are merely illustrative and that the present invention is not limited to the specific values ​​and scenarios described above. The cache block capacity, the number of cache blocks, the number of data types, and the number of read windows can all be flexibly configured according to actual application requirements.

[0062] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A dynamic buffer control method based on FPGA, characterized in that: The method includes: The external DDR physical cache space of the FPGA is logically and evenly divided into N cache blocks, N≥2. Each cache block has a fixed and equal storage capacity (BLOCK_SIZE), and a unique cache block number (block_num) is assigned to each cache block. A one-to-one mapping relationship between the cache block number (block_num) and the DDR physical address (mem_addr) is established. An idle cache management module and an occupied cache management module are set up inside the FPGA. The idle cache management module maintains an idle block FIFO queue to store the cache block numbers that are currently idle, and configures an idle block counter (idle_block_cnt) to record the number of cache block numbers in the idle block FIFO queue. The occupied cache management module maintains M occupied block FIFO queues, where M≥1 and M is a configurable parameter. The M occupied block FIFO queues correspond one-to-one with M data types, and each occupied block FIFO queue is used to store the cache block numbers that are currently occupied for the corresponding data type. During data writing, external data is preprocessed to form data packets with a fixed capacity. Each data packet contains the data to be stored and the corresponding data type number (type_num). Based on the data type number (type_num), a corresponding type block counter (type_block_cnt) and a type address counter (type_addr_cnt) are determined. The type block counter (type_block_cnt) records the number of cache blocks already occupied by the data type, and the type address counter (type_addr_cnt) records the written offset within the cache block currently being used by the data type. The value of the type address counter is then checked to determine if... If the cache block number is equal to the cache block capacity (BLOCK_SIZE), and less than the cache block capacity, the physical base address corresponding to the current cache block number plus the value of the type address counter is used as the write address; if the cache block number is equal to the cache block capacity, it means that the current cache block is full, so a new cache block number is read from the free block queue to cache the current data packet, and the free block counter (idle_block_cnt) is decremented by 1. The physical address to be written to the data packet is the newly acquired cache block base address, and the type address counter value is cleared to zero. The actual cache physical address to which the input data packet is written is composed of the cache block number and the type address counter value. The data packet is written to the DDR physical storage location corresponding to the write address. When reading data, K read windows are set, where K ≥ 1 and K is a configurable parameter. Each read window operates independently and in parallel. Each read window has a fixed window access address space, and the size of the window access address space is consistent with the cache block capacity. The read window number is (window_num). When data of a certain data type needs to be read, the data type number (type_num) is assigned to an idle read window. This read window pops a cache block number (block_num) from the FIFO queue of the corresponding data type in the cache management module. This cache block number is used as the physical cache address actually accessed by the read window, mem_addr=bl. `ock_num*BLOCK_SIZE`, this process is defined as cache release, and the type block counter (type_block_cnt) corresponding to the data type is decremented by 1; the read window maps the fixed window access address space to the DDR physical address space corresponding to the cache block number, so that the window address (win_addr) accessed by the external read command is converted into the corresponding DDR physical address (mem_addr), thereby reading the data of this data type; after the data is read, the read window writes the cache block number back to the free block FIFO queue of the free cache management module, and increments the free block counter (idle_block_cnt) by 1.

2. The method according to claim 1, characterized in that: When writing data, after writing the data packet to the DDR physical storage location corresponding to the write address, the cache block number corresponding to the write address is written to the occupied block FIFO queue corresponding to the data type, and the type block counter (type_block_cnt) corresponding to the data type is incremented by 1.

3. The method according to claim 1, characterized in that: The initialization process of the free block FIFO queue is as follows: the free block FIFO queue is reset and cleared, then the cache block numbers 0 to N-1 are written into the free block FIFO queue in sequence, and the free block counter is set to N.

4. The method according to claim 1, characterized in that: The M FIFO queues corresponding to the M data types are all empty during initialization, and the type block counter and type address counter corresponding to each data type are all cleared to zero. The actual cache space currently occupied by each data type is: type block counter value × cache block capacity + type address counter value, i.e. (type_block_cnt-1)*BLOCK_SIZE+type_addr_cnt.

5. The method according to claim 1, characterized in that: When reading data, the data reading process for that data type is triggered when the value of the type block counter corresponding to a certain data type reaches a preset reading threshold. The reading threshold is a configurable parameter.

6. The method according to claim 1, characterized in that: When reading data, if a read window has completed reading data, a close command is sent by the external CPU or the internal control logic of the FPGA. The read window responds to the close command by performing a write-back operation of the cache block number.

7. A dynamic cache control system for implementing the method according to any one of claims 1 to 8, characterized in that, The system includes: DDR memory chips are used as physical cache media. An FPGA chip, wherein the FPGA chip integrates: The free cache management module is used to maintain the free block FIFO queue and the free block counter; The occupancy cache management module is used to maintain M occupancy block FIFO queues, where M is the same as the number of data types; The data write control module is used to receive externally input data packets, calculate the write address based on the data type number and the current cache block occupancy status, and control the write operation to the DDR memory chip. The data readout control module is used to control the allocation, mapping, and release of K readout windows. Each readout window works independently and in parallel. A DDR driver controller is used to drive the read and write operations of the DDR memory chip. The data interaction module is used for the transmission of control and status signals between the FPGA chip and the external CPU.

8. The system according to claim 7, characterized in that: The input interface of the data writing control module and the output interface of the data reading control module are both AXI14 interfaces. The AXI4 interface is connected to external devices after being converted by the PCIe interface.

9. The system according to claim 7, characterized in that: The data write control module is configured with a set of counting registers for each data type. The counting registers include a type block counter and a type address counter. The type block counter records the number of cache blocks occupied by the corresponding data type, and the type address counter records the write offset in the current cache block of the corresponding data type.

10. The system according to claim 7, characterized in that: The readout window includes: The window status register is used to identify whether the current window is in an idle or active state. The window binding register is used to record the data type number and cache block number of the currently bound window; Address translation logic is used to convert window access addresses into DDR physical addresses.

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