SRAM memory control system

Abstract

The application relates to the field of memory control, in particular to an SRAM memory control system, the SRAM control system is connected with a processor, a plurality of storage areas with different operation states are arranged in the SRAM storage array of the SRAM control system, including a high-speed storage area, a normal storage area and a low-power consumption storage area, wherein the high-speed storage area is used for storing high-access-frequency data, the normal storage area is used for storing normal-access data, and the low-power consumption storage area is used for storing low-access-frequency data which needs to be kept. In the application, a data access analysis module and a partition control module are arranged in the SRAM memory control system, and the SRAM storage array is divided into the high-speed storage area, the normal storage area and the low-power consumption storage area, so that the data storage area is dynamically adjusted according to the data access frequency, compared with a traditional fixed SRAM control mode, the application can guarantee the high-frequency data access efficiency, reduce the occupation of the high-speed resource by the low-frequency data, and guarantee the resource utilization rate and operation performance of the SRAM storage system.

Description

Technical Field

[0001] This invention relates to the field of memory control technology, and more particularly to an SRAM memory control system. Background Technology

[0002] SRAM (Static Random Access Memory) is a high-speed memory widely used in processor caches, embedded chips, and high-speed computing systems. Existing SRAM memory control systems typically receive data access requests from the processor through a controller and perform read and write control on the SRAM memory array according to fixed addresses. Its memory areas usually adopt a uniform structure, and each memory cell accesses data according to the same operating mode.

[0003] However, in actual operation, there are significant differences in the access frequency, call cycle, and real-time requirements of different data. Fixed storage management cannot be dynamically adjusted according to the actual access status of the data, resulting in high-frequency access data and low-frequency access data occupying the same performance level of storage resources for a long time. This makes it impossible to fully utilize the high-speed storage area. At the same time, the continuous occupation of the working state by low-frequency data will also increase the system power consumption, and the high-speed operation efficiency cannot be guaranteed. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing an SRAM memory control system.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: The SRAM memory control system includes an SRAM control system and its internal data access analysis module and partition control module. The SRAM control system is connected to the processor. The SRAM memory array in the SRAM control system has multiple storage areas with different operating states, including a high-speed storage area, a normal storage area and a low-power storage area. The high-speed storage area is used to store data with high access frequency, the normal storage area is used to store data with regular access, and the low-power storage area stores data with low access frequency that needs to be retained. The data access analysis module is connected to the SRAM control system and is used to obtain data access information from the SRAM control system. It includes an access technology unit, an access cycle analysis unit, and a data level evaluation unit to evaluate the level of stored data based on the number of data accesses, the access cycle, and the access frequency, and generate corresponding data level information. The partition control module includes a partition comparison decision unit, a partition migration control unit, and a partition allocation unit. The partition control module is connected to the data access analysis module and the SRAM storage array, respectively. It is used to determine the storage area corresponding to the stored data based on the data level information output by the data access analysis module, and control the allocation and adjustment of the data between the high-speed storage area, the ordinary storage area, and the low-power storage area. The data access analysis module performs real-time analysis of the data access status inside the SRAM, and controls the data storage area according to the data access level through the partition control module, so that data with different access requirements are matched with the corresponding performance level storage area.

[0006] Preferably, the processor is used to send a data access request to the SRAM control system, and the SRAM control system is used to receive data read / write instructions sent by the processor and perform data access control on the SRAM storage array according to the control instructions.

[0007] Preferably, the access counting unit is used to record the number of data accesses at different storage addresses, including an address counter, an access variable detection unit, and a metering overflow processing unit. The access cycle analysis unit is used to obtain the continuous data access status, including a time recording unit, an access interval calculation unit, and a cycle feature extraction unit. The data level evaluation unit performs a comprehensive calculation on the data access frequency based on the access count information and the access cycle information, and outputs the corresponding data level information.

[0008] Preferably, the partition comparison decision unit is used to receive data level information and determine the target storage area corresponding to the current data through a preset level threshold. The partition migration control unit is used to generate migration control instructions based on the target storage area determination result and control the data to migrate from the current storage area to the target storage area. The partition allocation unit is used to perform data area adjustment operations and allocate data of different levels to the corresponding high-speed storage area, ordinary storage area and low-power storage area respectively.

[0009] Preferably, the partition comparison decision unit includes a threshold comparison unit, a dynamic decision unit, a historical behavior comparison unit, and a data level decision unit. The threshold comparison unit is used to compare data level information with a preset level threshold. The dynamic decision unit is used to adjust the data region selection strategy according to the current access status. The historical behavior comparison unit is used to call historical access records to judge the current data access trend. The data level decision unit is used to output the corresponding region adjustment instruction according to the comparison result.

[0010] Preferably, the partition migration control unit includes a target area determination unit, a resource analysis unit, an allocation scheme consideration unit, and an allocation priority unit. The target area determination unit is used to determine the target storage area after data migration. The resource analysis unit is used to detect the current resource occupancy status of each storage area. The allocation scheme consideration unit is used to generate a data migration scheme based on the target area status. The allocation priority unit is used to determine the data migration order based on the data level and the area load status.

[0011] Preferably, the partition allocation unit includes a data migration execution unit and a migration calibration unit. The data migration execution unit is used to perform data movement between different storage areas, and the migration calibration unit is used to detect the data status after migration and calibrate the information of the corresponding area of ​​the data.

[0012] Preferably, the high-speed storage area operates in a high-response mode to prioritize the storage of data with high access frequency and high real-time requirements, while the ordinary storage area operates in a normal mode to store data with general access needs, and the low-power storage area operates in a low-power retention mode to store data with lower access frequency, thereby reducing the overall power consumption of the SRAM.

[0013] Preferably, the SRAM control system updates the data addresses in the SRAM storage array synchronously according to the area adjustment information output by the partition control module, so that the processor access logic address corresponds to the actual data storage area. The system obtains the SRAM storage array operating status in real time through the data access analysis module, and realizes dynamic adjustment of the data storage area through the partition control module, so that the SRAM storage array can automatically match the corresponding storage area according to different data access requirements.

[0014] The beneficial effects of this invention are as follows: In this invention, by setting a data access analysis module and a partition control module in the SRAM memory control system, and dividing the SRAM memory array into a high-speed storage area, a normal storage area, and a low-power storage area, the data storage area can be dynamically adjusted according to the data access frequency. Compared with the traditional fixed SRAM control method, it can ensure the efficiency of high-frequency data access, reduce the occupation of high-speed resources by low-frequency data, and ensure the resource utilization and operating performance of the SRAM memory system. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall framework of the SRAM memory control system proposed in this invention; Figure 2 This is a schematic diagram of the system framework of the partition control module proposed in this invention; Figure 3 This is a schematic diagram of the data access and analysis module framework proposed in this invention. Detailed Implementation

[0016] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0017] Reference Figure 1-3 The SRAM memory control system includes the SRAM control system and its internal data access analysis module and partition control module. The SRAM control system is connected to the processor. The SRAM memory array in the SRAM control system has multiple storage areas with different operating states, including high-speed storage area, ordinary storage area and low-power storage area. The high-speed storage area is used to store data with high access frequency, the ordinary storage area is used to store data with regular access, and the low-power storage area stores data with low access frequency that needs to be retained. The data access analysis module is connected to the SRAM control system to obtain data access information from the SRAM control system. It includes an access technology unit, an access cycle analysis unit, and a data level evaluation unit to evaluate the level of stored data based on the number of data accesses, access cycle, and access frequency, and generate corresponding data level information. The partition control module includes a partition comparison decision unit, a partition migration control unit, and a partition allocation unit. The partition control module is connected to the data access analysis module and the SRAM storage array, respectively. It is used to determine the storage area corresponding to the stored data based on the data level information output by the data access analysis module, and to control the allocation and adjustment of the data between the high-speed storage area, the ordinary storage area, and the low-power storage area. The data access analysis module performs real-time analysis of the data access status inside the SRAM, and controls the data storage area according to the data access level through the partition control module, so that data with different access requirements are matched with the corresponding performance level storage area.

[0018] Furthermore, the processor sends data access requests to the SRAM control system, which receives data read / write instructions from the processor and performs data access control on the SRAM memory array according to the control instructions.

[0019] Furthermore, the access counting unit is used to record the number of data accesses at different storage addresses, including an address counter, an access variable detection unit, and a metering overflow processing unit. The access cycle analysis unit is used to obtain the continuous data access status, including a time recording unit, an access interval calculation unit, and a cycle feature extraction unit. The data level evaluation unit performs a comprehensive calculation on the data access frequency based on the access count information and the access cycle information, and outputs the corresponding data level information.

[0020] Furthermore, the partition comparison decision unit is used to receive data level information and determine the target storage area corresponding to the current data through a preset level threshold. The partition migration control unit is used to generate migration control instructions based on the target storage area determination result and control the data to migrate from the current storage area to the target storage area. The partition allocation unit is used to perform data area adjustment operations and allocate data of different levels to the corresponding high-speed storage area, ordinary storage area and low-power storage area respectively.

[0021] The partition comparison decision unit includes a threshold comparison unit, a dynamic decision unit, a historical behavior comparison unit, and a data level decision unit. The threshold comparison unit is used to compare data level information with preset level thresholds, and the dynamic decision unit is used to adjust the data region selection strategy according to the current access status. The historical behavior comparison unit is used to retrieve historical access records and determine the current data access trend; The data level decision unit is used to output corresponding regional adjustment instructions based on the comparison results.

[0022] Furthermore, the partitioned migration control unit includes a target area determination unit, a resource analysis unit, an allocation scheme consideration unit, and an allocation priority unit; Among them, the target area determination unit is used to determine the target storage area after data migration, and the resource analysis unit is used to detect the current resource occupancy status of each storage area. The allocation scheme thinking unit is used to generate a data migration scheme based on the target area status, and the allocation priority unit is used to determine the data migration order based on the data level and the area load status.

[0023] Furthermore, the partition allocation unit includes a data migration execution unit and a migration calibration unit. The data migration execution unit is used to perform data movement between different storage areas, and the migration calibration unit is used to detect the data status after migration and calibrate the information of the corresponding area of ​​the data.

[0024] Furthermore, the high-speed storage area operates in a high-response mode to prioritize the storage of data with high access frequency and high real-time requirements, while the ordinary storage area operates in a normal mode to store data with general access needs, and the low-power storage area operates in a low-power retention mode to store data with lower access frequency, thereby reducing the overall power consumption of the SRAM.

[0025] Furthermore, the SRAM control system updates the data addresses in the SRAM storage array synchronously based on the area adjustment information output by the partition control module, ensuring that the processor access logic address corresponds to the actual data storage area. The system obtains the SRAM storage array's operating status in real time through the data access analysis module and dynamically adjusts the data storage area through the partition control module, enabling the SRAM storage array to automatically match the corresponding storage area according to different data access requirements.

[0026] In this embodiment, the processor sends a data access request to the SRAM control system. The SRAM control system receives the address information and read / write instructions generated by the processor and controls the SRAM storage array to complete the corresponding data reading or writing.

[0027] Traditional SRAM control systems typically employ a fixed storage method, storing different types of data at preset addresses. This prevents the storage location from being adjusted based on the actual data access status, resulting in high-frequency and low-frequency access data occupying the same level of storage resources and impacting SRAM operating efficiency.

[0028] In this embodiment, a data access analysis module is set up to detect the data access status in the SRAM storage array. The data access analysis module includes an access counting unit, an access cycle analysis unit, and a data level evaluation unit, which are used to obtain the number of accesses, access frequency, and access cycle of different data, and generate corresponding data level information based on the analysis results.

[0029] Furthermore, the data level information is sent to the partition control module, which then adjusts the storage area corresponding to the data.

[0030] The SRAM memory array contains a high-speed memory area, a normal memory area, and a low-power memory area. The high-speed memory area is used to store high-frequency access data to improve data response speed, the normal memory area is used to store regular access data to meet normal read and write requirements, and the low-power memory area is used to store low-frequency access data to reduce overall operating power consumption.

[0031] The partition control module includes a partition comparison decision unit, a partition migration control unit, and a partition allocation unit. The partition comparison decision unit determines the target storage area based on data level information, the partition migration control unit controls the adjustment of data between different storage areas, and the partition allocation unit performs data storage area allocation operations.

[0032] In actual operation, when the data access analysis module detects that the access frequency of a certain data has increased, the partition control module controls the data to be moved from the ordinary storage area to the high-speed storage area, so that it can obtain a higher data access priority. When it detects that a certain data has been in a low-frequency access state for a long time, it controls the data to be moved to the low-power storage area to release high-speed storage resources.

[0033] Meanwhile, to ensure that the processor can access the data normally after adjustment, the SRAM control system synchronously updates the address information corresponding to the data, so that the logical access address corresponds to the actual storage area.

[0034] In practical applications, by adding a data access analysis module and a partition control module to the traditional SRAM control system, and dividing the SRAM storage array into multiple storage areas with different performance levels, the SRAM can automatically adjust its storage location according to data access requirements.

[0035] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. An SRAM memory control system, comprising an SRAM control system and its internal data access and analysis module and partition control module, characterized in that, The SRAM control system is connected to the processor. The SRAM storage array in the SRAM control system has multiple storage areas with different operating states, including a high-speed storage area, a normal storage area, and a low-power storage area. The high-speed storage area is used to store data with high access frequency, the normal storage area is used to store data with regular access, and the low-power storage area stores data with low access frequency that needs to be retained. The data access analysis module is connected to the SRAM control system and is used to obtain data access information from the SRAM control system. It includes an access data unit, an access cycle analysis unit, and a data level evaluation unit to evaluate the level of stored data based on the number of data accesses, access cycle, and access frequency, and generate corresponding data level information. The partition control module includes a partition comparison decision unit, a partition migration control unit, and a partition allocation unit. The partition control module is connected to the data access analysis module and the SRAM storage array, respectively. It is used to determine the storage area corresponding to the stored data based on the data level information output by the data access analysis module, and control the allocation and adjustment of the data between the high-speed storage area, the ordinary storage area, and the low-power storage area. The data access analysis module performs real-time analysis of the data access status inside the SRAM, and controls the data storage area according to the data access level through the partition control module, so that data with different access requirements are matched with the corresponding performance level storage area.

2. The SRAM memory control system according to claim 1, characterized in that, The processor is used to send data access requests to the SRAM control system, and the SRAM control system is used to receive data read and write instructions sent by the processor and perform data access control on the SRAM storage array according to the control instructions.

3. The SRAM memory control system according to claim 1, characterized in that, The access counting unit is used to record the number of data accesses at different storage addresses, including an address counter, an access variable detection unit, and a metering overflow processing unit. The access cycle analysis unit is used to obtain the continuous data access status, including a time recording unit, an access interval calculation unit, and a cycle feature extraction unit. The data level evaluation unit performs a comprehensive calculation on the data access frequency based on the access count information and the access cycle information, and outputs the corresponding data level information.

4. The SRAM memory control system according to claim 1, characterized in that, The partition comparison decision unit is used to receive data level information and determine the target storage area corresponding to the current data through a preset level threshold. The partition migration control unit is used to generate migration control instructions based on the target storage area determination result and control the data to migrate from the current storage area to the target storage area. The partition allocation unit is used to perform data area adjustment operations and allocate data of different levels to the corresponding high-speed storage area, ordinary storage area and low-power storage area respectively.

5. The SRAM memory control system according to claim 4, characterized in that, The partition comparison decision unit includes a threshold comparison unit, a dynamic decision unit, a historical behavior comparison unit, and a data level decision unit. The threshold comparison unit is used to compare data level information with a preset level threshold. The dynamic decision unit is used to adjust the data region selection strategy according to the current access status. The historical behavior comparison unit is used to call historical access records to judge the current data access trend. The data level decision unit is used to output the corresponding region adjustment instruction according to the comparison result.

6. The SRAM memory control system according to claim 4, characterized in that, The partition migration control unit includes a target area determination unit, a resource analysis unit, an allocation scheme consideration unit, and an allocation priority unit. The target area determination unit is used to determine the target storage area after data migration. The resource analysis unit is used to detect the current resource occupancy status of each storage area. The allocation scheme consideration unit is used to generate a data migration scheme based on the target area status. The allocation priority unit is used to determine the data migration order based on the data level and the area load status.

7. The SRAM memory control system according to claim 4, characterized in that, The partition allocation unit includes a data migration execution unit and a migration calibration unit. The data migration execution unit is used to perform data movement between different storage areas, and the migration calibration unit is used to detect the data status after migration and calibrate the information of the corresponding area of ​​the data.

8. The SRAM memory control system according to claim 1, characterized in that, The high-speed storage area operates in a high-response mode to prioritize the storage of data with high access frequency and high real-time requirements, while the ordinary storage area operates in a normal mode to store data with general access needs, and the low-power storage area operates in a low-power retention mode to store data with lower access frequency, thereby reducing the overall power consumption of the SRAM.

9. The SRAM memory control system according to claim 1, characterized in that, The SRAM control system updates the data addresses in the SRAM storage array synchronously based on the area adjustment information output by the partition control module, ensuring that the processor access logic address corresponds to the actual data storage area. The system obtains the SRAM storage array's operating status in real time through the data access analysis module and dynamically adjusts the data storage area through the partition control module, enabling the SRAM storage array to automatically match the corresponding storage area according to different data access requirements.

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