Page table prefetch method, apparatus, device, and storage medium

Abstract

The application provides a page table prefetching method, device, equipment and storage medium, and relates to the field of graphic processors. The method comprises the following steps: obtaining at least one to-be-processed memory access command; determining a target address located outside a first page table cache range according to address information of the at least one to-be-processed memory access command; wherein the address information is used for indicating an address range to be accessed by the memory access command, and the first page table cache range is a current page table cache range of a memory management unit (MMU); generating a prefetch request according to the target address, wherein the prefetch request is used for prefetching page table data corresponding to a second page table cache range to which the target address belongs into the page table cache of the MMU. The method improves the memory access efficiency of the GPU.

Description

Technical Field

[0001] This application relates to the field of graphics processing unit (GPU) technology, and in particular to a page table prefetching method, apparatus, device and storage medium. Background Technology

[0002] Memory access requests sent by the GPU typically carry a virtual address (VA), while the memory system needs to use the physical address (PA) to perform the actual data read or write. Therefore, before a memory access request is sent to the memory system, the Memory Management Unit (MMU) needs to perform the translation from virtual address to physical address.

[0003] In related technologies, the MMU typically has a page table cache internally to cache page table data, which records the mapping relationship between virtual addresses and physical addresses. When the MMU receives a memory access request, it queries the page table cache: if the cache is hit, it performs address translation based on the cached page table data; if the cache is not hit, it reads the corresponding page table data from the memory system and performs address translation.

[0004] However, during the process of the MMU reading page table data and completing address translation, the corresponding memory access request cannot be sent to the memory system, which leads to a decrease in the GPU's memory access efficiency. Summary of the Invention

[0005] This application provides a page table prefetching method, apparatus, device, and storage medium. The technical solutions provided by this application are as follows.

[0006] According to one aspect of the embodiments of this application, a page table prefetching method is provided, the method comprising: Obtain at least one pending memory access command; Based on the address information of the at least one pending memory access command, a target address located outside the first page table cache range is determined; wherein, the address information is used to indicate the address range to be accessed by the memory access command, and the first page table cache range is the current page table cache range of the memory management unit (MMU). Based on the target address, a prefetch request is generated. The prefetch request is used to prefetch the page table data corresponding to the second page table cache range to which the target address belongs into the page table cache of the MMU.

[0007] According to one aspect of the embodiments of this application, a page table prefetching apparatus is provided, the apparatus comprising: The command acquisition module is used to acquire at least one memory access command to be processed; The address determination module is used to determine a target address outside the first page table cache range based on the address information of the at least one memory access command to be processed; wherein the address information is used to indicate the address range to be accessed by the memory access command, and the first page table cache range is the current page table cache range of the memory management unit (MMU). The request generation module is used to generate a prefetch request based on the target address. The prefetch request is used to prefetch the page table data corresponding to the second page table cache range to which the target address belongs into the page table cache of the MMU.

[0008] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the page table prefetch method described above.

[0009] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer program, which is loaded and executed by a processor to implement the page table prefetching method described above.

[0010] According to one aspect of the embodiments of this application, a chip is provided, the chip including programmable logic circuits and / or program instructions, which, when the chip is running, are used to implement the above-described page table prefetch method.

[0011] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program, the computer program being loaded and executed by a processor to implement the page table prefetching method described above.

[0012] The technical solution provided in this application can bring the following beneficial effects: By determining the target address outside the current page table cache range of the MMU based on the address information of the memory access command to be processed, and generating a prefetch request based on the target address, the page table data corresponding to the page table cache range to which the target address belongs is prefetched into the MMU's page table cache. The technical solution provided in this application can prefetch the required page table data for memory access commands that have not yet been processed, thereby reducing memory access bubbles caused by cache misses when actually processing the memory access command and generating the memory access request, and thus improving the GPU's memory access efficiency. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of the GPU memory access process provided in one possible implementation of related technologies; Figure 2 This is a schematic diagram of a memory access bubble caused by a cache miss, provided in one possible implementation of the related technology; Figure 3 This is a flowchart of a page table prefetching method provided in one possible implementation of this application; Figure 4 This is a schematic diagram of reduced memory access bubbles provided in one possible implementation of this application using page table prefetching; Figure 5 This is a schematic diagram of the prefetch request generation process provided in one possible implementation of this application; Figure 6 This is a structural block diagram of a page table prefetching device provided in one possible implementation of this application; Figure 7 This is a structural block diagram of a computer device provided in one possible implementation of this application. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0016] Before introducing the technical solution proposed in this application, the relevant technical background and related technologies will be briefly described below.

[0017] In the GPU domain, a GPU core can receive and execute a series of commands. For example, in a graphics processing scenario, this command might be a draw command; in a data transfer scenario, it might be a Direct Memory Access (DMA) command. Command execution typically requires accessing one or more memory regions. For instance, a draw command might need to read an index buffer, vertex buffer, or texture buffer, while a DMA command might need to read a source buffer and write to a destination buffer.

[0018] In the following text, for ease of description, a memory access request targeting a contiguous address range will be referred to as a memory access command. Memory access commands are typically not sent as a single bus transaction, but rather broken down by the GPU into one or more burst requests (memory access requests) according to the memory bus protocol. Each memory access request usually includes a starting address transfer and multiple consecutive data tick transfers; the addresses corresponding to each data tick generally increase sequentially according to the bus data width. Compared to transferring the address separately for each data tick, burst transfers reduce the overhead of address and control information transmission, improving memory bus utilization.

[0019] Due to factors such as the maximum burst length allowed by the memory bus, address alignment requirements, boundary limitations, and flow control, a memory access command may be split into multiple memory access requests. For example, a memory access command that accesses a large contiguous address range can be sequentially split into memory access request 1, memory access request 2, memory access request 3, and so on. Each memory access request typically carries a virtual address, while the memory system (such as video memory or random access memory, RAM) needs to perform the actual data read or write based on the physical address. Therefore, before the memory access request reaches the memory system, the MMU needs to perform the virtual address to physical address translation, and the memory system then performs the data read or write based on the translated physical address.

[0020] The MMU relies on page tables for address translation. Page table data records the mapping between virtual and physical addresses. For example, virtual addresses can be divided into virtual pages at a certain granularity, and physical addresses can be correspondingly divided into physical page frames. In some implementations, page table data can contain multiple Page Table Entry (PTE) entries. Each PTE entry contains at least an identifier for the corresponding physical page frame and may also include valid bits, access permissions, and other address translation attributes. For a memory access request, the MMU determines the corresponding virtual page number and page offset based on its virtual address, queries the relevant page table entry to obtain the physical page frame, and combines the physical page frame with the page offset to form the physical address, thus completing the translation from virtual to physical address.

[0021] The MMU typically has multiple levels of page table caches internally to cache page table data needed during address translation. Taking a two-level page table cache implementation as an example, the first level can be a Translation Lookaside Buffer (TLB) to cache the translation result from the resolved virtual page number to the physical page frame number; the second level is a page table entry cache to cache page table data (e.g., page table entries) read from the memory system. When the MMU receives a memory access request, it first checks the TLB. If the TLB is hit, the physical address can be obtained directly. If the TLB is not hit, the MMU further checks the page table entry cache. If the cache is hit, the MMU can complete the address translation and obtain the physical address corresponding to the memory access request based on the cached page table data, without needing to read the page table entry from the memory system. If the cache is not hit, the MMU needs to initiate a page table read request from the memory system, obtain the required page table entry, cache it in the page table entry cache, and then complete the address translation.

[0022] It should be noted that the number of cache layers, names, and organization methods may differ in different MMU implementations. In this application, page table cache refers generally to the various levels of cache structures within the MMU used to cache page table data, but is not limited to specific cache names, levels, or hardware structures. Furthermore, the page table entries mentioned in this application context are one implementation example of page table data, and the page table entry cache mentioned is one implementation example of page table caching, and is not intended to limit the scope of protection of this application; further details will not be elaborated upon below.

[0023] For example, please refer to Figure 1 , Figure 1 This is a schematic diagram illustrating the GPU memory access process provided in one possible implementation of related technologies. For example... Figure 1 As shown, the memory access command issued by GPU 110 is split into a memory access request, which is then transmitted via memory bus 120. Upon receiving the memory access request, MMU 130 first queries its internal page table cache 140. If the cache is hit (i.e., page table cache 140 contains the page table data required for the memory access request), MMU 130 uses this page table data to complete the virtual address to physical address translation. If the cache is missed (i.e., page table cache 140 does not contain the required page table data), MMU 130 initiates a page table read request to memory system 150 via memory bus 120, obtains the corresponding page table data, caches it in page table cache 140, and then performs address translation. After completing the address translation and obtaining the physical address, the memory access request is sent to memory system 150 via memory bus 120. Memory system 150 performs the data read or write operation based on the physical address and returns the read result or write status to GPU 110.

[0024] However, in the GPU memory access process of related technologies, the MMU passively reads the required page table data from the memory system only when it receives a memory access request and the cache misses. This page table data reading process and the subsequent address translation process block current and subsequent memory access requests waiting for address translation, causing memory access requests to fail to be sent to the memory system in a timely manner, thus creating memory access bubbles on the memory bus. For example, a memory access bubble refers to an idle period on the memory bus caused by the inability to send memory access requests in a timely manner; during this period, the memory bus is idle and there is no effective data transmission. The existence of memory access bubbles reduces the effective utilization of the memory bus and limits the GPU's memory access throughput.

[0025] For example, please refer to Figure 2 , Figure 2 This is a schematic diagram of a memory access bubble caused by a cache miss, provided in one possible implementation of related technologies.

[0026] like Figure 2 As shown, taking the GPU sending memory access request 1 and memory access request 2 sequentially as an example, assume that the page table data required by both memory access requests is not found in the MMU's page table cache. For memory access request 1, the MMU needs to read the corresponding page table data from the memory system and cache it in the page table cache before performing virtual address to physical address translation. During this period, an idle period occurs on the memory bus due to the inability to send memory access requests in a timely manner, which is stage A in the diagram, and this stage is called the memory access bubble. When the address translation is completed and the memory access request can be sent to the memory system, it enters stage B, which is the effective data transmission period for the memory access request to be transmitted through the memory bus. After memory access request 1 is sent, memory access request 2 also experiences the idle period A and the effective data transmission period B due to cache miss. Since memory access bubbles are generated in each round, the effective utilization rate of the memory bus is only B / (A+B). The greater the latency of reading page table data from the memory system, or the higher the frequency of cache misses, the lower the effective utilization rate of the memory bus, the lower the GPU's memory access throughput, and ultimately the lower the GPU's memory access efficiency.

[0027] To address the aforementioned problems, this application provides a page table prefetching method. For example, please refer to... Figure 3 , Figure 3 This is a flowchart of a page table prefetching method provided in one possible implementation of this application. The page table prefetching method may include at least one of the following steps 310 to 330.

[0028] Step 310: Obtain at least one memory access command to be processed.

[0029] In this embodiment, the memory access command is generated by a data request source (client) in the GPU. The data request source can be various functional units or engines in the GPU that need to initiate memory access, such as the graphics rendering engine, general computing engine, DMA engine, etc. Multiple memory access commands are arranged sequentially in the order of their generation into a command stream. Each memory access command carries address information, which indicates the address range to be accessed by the memory access command, so that subsequent steps can determine the page table cache range where the required page table data is located. Among them, the memory access commands in the command stream that have not yet been split into memory access requests are the aforementioned memory access commands to be processed.

[0030] In one possible implementation, the data request source generates multiple memory access commands sequentially, each of which can be represented as cmd(addr, size). Here, addr represents the starting address to be accessed by the memory access command, and size represents the access length (i.e., the length or number of bytes of data to be accessed). The range of addresses to be accessed, determined by the starting address and the access length, can be a half-open interval [addr, addr + size]. It should be noted that this application uses an address range representation where all address ranges are half-open intervals as an example. All address ranges mentioned below (such as the address range of the memory access command to be processed, the remaining address range of the currently processed memory access command, and the first page table cache range, etc.) are represented in the form [starting address, starting address + access length). This address range representation is for illustrative purposes only and is not intended to limit the scope of the application. It should be understood that when the address range representation method used changes (e.g., closed range, open range or other endpoint conventions are used), the determination of boundary judgment results such as "the first address located outside the first page table cache range" in various embodiments of this application will also change accordingly with different endpoint attribution rules. This application does not limit the representation convention of address ranges, and they all fall within the protection scope of this application.

[0031] In one possible implementation, the aforementioned memory access commands enter the address detection window in the order they are generated. The address detection window is a queue structure that temporarily stores memory access commands, with each command arranged sequentially from the head to the tail. In this embodiment, the address detection window is used to pre-store at least one pending memory access command and record its address information for subsequent detection of target addresses outside the current page table cache range of the Memory Management Unit (MMU) (i.e., addresses where the required page table data has not yet been cached). For example, the window depth of the address detection window (i.e., the number of memory access commands that can be temporarily stored) can be configured according to actual needs, and each entry can include fields such as "valid bit," "starting address," and "access length" to record the address information of the corresponding memory access command.

[0032] For example, suppose the data request source generates memory access commands cmd(0x1000, 0x1000), cmd(0x3000, 0x2000), and cmd(0x8000, 0x4000) in sequence. These three memory access commands enter the address detection window in sequence and are temporarily stored as memory access commands to be processed. Among them, the memory access command cmd(0x1000, 0x1000) at the head of the queue corresponds to the address range to be accessed [0x1000, 0x2000); while the memory access commands cmd(0x3000, 0x2000) and cmd(0x8000, 0x4000) that follow it correspond to the address ranges to be accessed [0x3000, 0x5000) and [0x8000, 0xC000], respectively. It is worth noting that the above values ​​are merely examples. This application does not impose any restrictions on the specific format of the memory access command, the values ​​of the starting address and access length, or the window depth and table fields of the address detection window. These can all be configured according to the actual application scenario.

[0033] Step 320: Based on the address information of at least one pending memory access command, determine the target address located outside the first page table cache range. The address information indicates the address range to be accessed by the memory access command, and the first page table cache range is the current page table cache range of the Memory Management Unit (MMU).

[0034] In this embodiment, when the MMU performs address translation on the address to be accessed, it needs to determine the mapping relationship between the virtual address and the physical address based on page table data. Page table data is used to record the mapping relationship between virtual and physical addresses. In some embodiments, page table data is in units of page table entries, with each entry corresponding to a range of addresses in the virtual address space, recording the mapping information from that range to the physical address. Whether the page table data required for a certain virtual address has been obtained is reflected in whether the page table entry corresponding to the address range of that virtual address has been cached in the MMU.

[0035] To improve address translation efficiency, the MMU includes a page table cache to cache page table data. The virtual address range covered by the page table data currently cached in the page table cache is the current page table cache range of the MMU, i.e., the first page table cache range. When the page table entry corresponding to an address to be accessed is already cached in the page table cache, the address to be accessed is within the first page table cache range, and address translation can be completed directly. Conversely, when the page table entry corresponding to an address to be accessed is not yet cached in the page table cache, the address to be accessed is outside the first page table cache range, and the corresponding page table data needs to be read from the memory system. The target address is the address or address range located outside the first page table cache range where the corresponding page table entry has not yet been cached.

[0036] To facilitate the explanation of how to determine the page table cache range of any virtual address, in one possible implementation, the MMU reads and caches page table data from the memory system in cache lines, with each cache line covering a contiguous range of virtual addresses. The size of the virtual address range covered by a cache line is denoted as M (M is a positive integer, its value determined by the cache line capacity of the MMU's page table cache). For any virtual address A (A represents any virtual address whose page table cache range to be determined), the identifier, start address, and end address of its page table cache range can be determined as follows: Divide the virtual address A by M and round down; the result is used as the identifier of the page table cache range (denoted as range_id(A)); the start address of the page table cache range (denoted as range_base(A)) is the identifier multiplied by M; the end address of the page table cache range (denoted as range_end(A)) is the start address plus M. Rounding down means discarding the decimal part of the result of dividing A by M and retaining only the integer part. The page table cache range is represented by a half-open interval [range_base(A), range_end(A)). Based on the above cache line partitioning method, the first page table cache range is the virtual address range covered by the page table data currently cached by the MMU page table cache, and its specific boundaries can be determined by the above method.

[0037] In one possible implementation, the process of determining the target address is based on the address information of each pending memory access command temporarily stored in the address detection window. For example, the current boundary of the first page table cache range can be maintained, and the address range of each pending memory access command can be compared with this boundary. Specifically, the pending memory access commands can be traversed sequentially according to their generation order in the address detection window. The address range corresponding to the currently traversed memory access command is determined based on its address information, and this address range is compared with the boundary of the first page table cache range. If the address range exceeds the first page table cache range, the first address in that range outside the first page table cache range is determined as the target address, and the traversal can be stopped accordingly. By traversing the pending memory access commands and comparing them sequentially, it is possible to pre-determine which pending memory access commands require page table data that has not yet been cached before the memory access request actually arrives at the MMU, thus providing a basis for subsequently generating prefetch requests. It is worth noting that the above method for determining the target address will be described in detail in the following embodiments, and will not be repeated here.

[0038] For example, suppose there are two pending memory access commands temporarily stored in the address detection window, namely cmd(0x1000, 0x1000) and cmd(0x3000, 0x2000), with corresponding address ranges of [0x1000, 0x2000) and [0x3000, 0x5000) respectively. Assume the current first page table cache range of the MMU is [0x0, 0x4000]. After comparison, the address range [0x1000, 0x2000) of cmd(0x1000, 0x1000) falls entirely within the first page table cache range; while the address range [0x3000, 0x2000) of cmd(0x3000, 0x5000) crosses the boundary of address "0x4000", with the [0x4000, 0x5000) portion exceeding the first page table cache range. Therefore, it can be determined that there is a target address outside the first page table cache range within the address range [0x4000, 0x5000). It is worth noting that the aforementioned first page table cache range and the specific values ​​of the memory access commands to be processed are merely examples for ease of understanding. This application does not limit the size and starting position of the first page table cache range, nor the mechanism for determining the target address; these can all be determined based on the actual application scenario and the configuration of the MMU page table cache.

[0039] Step 330: Generate a prefetch request based on the target address. The prefetch request is used to prefetch the page table data corresponding to the second page table cache range to which the target address belongs into the MMU's page table cache.

[0040] In this embodiment, after determining the target address based on the address information of the memory access command to be processed, a corresponding prefetch request is generated. The prefetch request is used to cache the required page table data in the MMU's page table cache before the memory access request corresponding to the memory access command to be processed actually arrives at the MMU and needs to be used for address translation using page table data. This reduces memory access bubbles caused by uncached page table data and improves the effective utilization of the memory bus and the memory access throughput of the GPU.

[0041] First, let's explain the structural relationships between the concepts within the page table cache: Page table data consists of multiple page table entries. Each page table entry corresponds to a range of addresses in the virtual address space and records the mapping information from that range to the physical address (as mentioned in the previous example, whether the page table data required for a certain virtual address has been retrieved is reflected in whether the page table entry corresponding to the address range of that virtual address has been cached in the MMU). The MMU's page table cache is used to cache page table data, and the page table cache typically uses cache lines as the basic unit of storage and retrieval: the page table cache organizes the cached page table data by cache lines. Each cache line can hold one or more consecutive page table entries and cover a consecutive range of virtual addresses. Therefore, the virtual address range covered by the page table data currently cached in the page table cache (i.e., the first page table cache range) is formed by concatenating several cached cache lines; correspondingly, the page table data that has not yet been cached is also divided into several segments according to the cache line boundaries, and the virtual address range covered by each cache line segment is a page table cache range. In other words, the page table cache range can be either the address range corresponding to a single page table entry or the address range covered by a cache line containing multiple consecutive page table entries. Its specific granularity depends on the implementation of the page table cache.

[0042] In some embodiments, the second page table cache range to which the target address belongs refers to the virtual address range corresponding to a cache line covering the target address that is not currently cached by the MMU page table cache. For example, the MMU's page table cache typically caches page table data at a fixed cache line granularity. Each cache line covers a continuous virtual address range, denoted as M, where M is a positive integer (its size is determined by the cache line capacity of the page table cache). For any virtual address A (A represents any virtual address to be determined in the cache line, which can refer to the target address mentioned above), the identifier, start address, and end address of its page table cache range can be determined as follows: range_id(A) = A / M ; range_base(A)=range_id(A)×M; range_end(A)=range_base(A)+M; in, · This represents the floor function, where A divided by M is rounded down, discarding the decimal part and retaining only the integer part (i.e., taking the largest integer not greater than A / M). `range_id(A)` is the identifier of the page table cache range to which virtual address A belongs, `range_base(A)` is the starting address of this page table cache range, and `range_end(A)` is the ending address of this page table cache range. The page table cache range is represented by a half-open interval [range_base(A), range_end(A)). As can be seen from the above, virtual address A falls within the page table cache range starting at `range_base(A)` and ending at `range_end(A)`. Therefore, prefetching the page table data corresponding to the second page table cache range into the MMU's page table cache means pre-caching at least one page table entry corresponding to the cache line covering the target address (i.e., the `range_id` (target address) cache line, whose corresponding second page table cache range is [range_base(target address), range_end(target address))).

[0043] For example, the virtual address range corresponding to its cache line can be determined by the following mapping: range_id(A) = A / M The range_id(A) function is a cache line number mapping function that returns the cache line number (i.e., which cache line) to which virtual address A belongs. · This indicates a floor operation (rounding down to the largest integer not greater than the value within the parentheses). From this mapping, we know that virtual address A falls into the... A / M Within the range covered by each cache line. Therefore, prefetching the page table data corresponding to the second page table cache range into the MMU's page table cache means pre-caching at least one page table entry corresponding to the cache line covering the target address (i.e., the cache line with the range_id (target address) th row) into the page table cache.

[0044] In one possible implementation, the process of generating a prefetch request may include, but is not limited to: first, determining the cache line to which the target address belongs, for example, dividing the target address by the cache line size M and rounding down, the result being the cache line number to which the target address belongs; then obtaining the address information of the second page table cache range corresponding to that cache line (e.g., range_base (target address) and range_end (target address) mentioned above; this application does not limit the specific form of the second page table cache range). The address information of the second page table cache range is carried in the prefetch request, and the prefetch request is sent to the MMU. Upon receiving the prefetch request, the MMU reads the corresponding page table data from the memory system based on the address information carried in the prefetch request and prefetches it into the page table cache. Therefore, when a subsequent actual memory access request arrives at the MMU and requires address translation of the target address, the required page table data is already in the page table cache, allowing for direct address translation and avoiding memory access requests being blocked due to cache misses or memory access bubbles being generated on the memory bus.

[0045] In another possible implementation, the prefetch request can directly carry the cache line number of the target address, instead of the address information of the second page table cache range. After receiving the prefetch request, the MMU can determine the address information of the corresponding second page table cache range based on the aforementioned cache line number, then read the page table data from the memory system and prefetch the page table data into the page table cache. In other words, the content carried by the prefetch request can be either the address information of the second page table cache range or the cache line number used to represent that range. The index information carried by the prefetch request in this application is not limited. It is worth noting that the specific process of generating the prefetch request and the method of the MMU reading and prefetching the page table data described above are merely illustrative examples. This application does not limit the format of the prefetch request, the specific form of the information it carries, or the specific implementation method of the MMU performing the prefetch operation. All of these can be adjusted according to the actual application scenario.

[0046] For example, continuing the example from step 320, assume the determined target address is within the address range [0x4000, 0x5000), and the cache line size M of the MMU page table cache is 0x4000. Divide the target address 0x4000 by the cache line size 0x4000 and round down. The result (i.e., the cache line number to which the target address belongs) is 1, meaning the target address falls into the first cache line. The second page table cache range corresponding to this cache line is [0x4000, 0x8000). Based on this, a prefetch request is generated, carrying the address information of the second page table cache range [0x4000, 0x8000) in the prefetch request and sending it to the MMU. The MMU then reads the page table data corresponding to this virtual address range from the memory system and prefetches it into the page table cache. When the memory access request corresponding to the subsequent pending memory access command cmd(0x3000, 0x2000) actually arrives at the MMU and needs to be addressed beyond the range of the first page table cache, the corresponding page table data is already cached in the page table cache. Address translation can be completed directly, avoiding memory access requests being blocked due to cache misses and memory access bubbles being generated on the memory bus. It is worth noting that the cache line size M, the size and starting position of the second page table cache range, etc., mentioned above are merely illustrative examples. This application does not limit the cache line capacity of the page table cache, the method for determining the range of the second page table cache, or the specific format of the prefetch request.

[0047] For example, please refer to Figure 4 , Figure 4 This is a schematic diagram of reduced memory access bubbles provided in one possible implementation of this application via page table prefetching.

[0048] like Figure 4 As shown, taking the GPU sending memory access request 1 and memory access request 2 sequentially as an example, since the page table prefetching method provided in this embodiment can prefetch the required page table data from the memory system to the MMU's page table cache by generating a prefetch request before the memory access request reaches the MMU, when the memory access request reaches the MMU, the MMU can directly obtain the corresponding page table data from the page table cache for address translation. Figure 4 In the MMU's page table cache, phase C represents the period of reading page table data from the memory system, corresponding to the process of prefetching page table data from the memory system to the MMU's page table cache via prefetch requests; phase D represents the period of virtual address to physical address translation, corresponding to the process of the MMU completing address translation using the cached page table data. Numerically, Figure 2 The duration of the memory access bubble (Phase A) caused by a cache miss, assuming the hardware latency for reading page table data and performing address translation is the same, is equal to Figure 4 The sum of the durations of phases C and D (i.e., A = C + D).

[0049] and Figure 2 The comparison shows that: Figure 2 In the related technologies shown, due to cache misses, the memory bus must go through memory access bubbles (stage A) in each round of memory access requests, resulting in an effective utilization rate of only B / (A+B). However, in this embodiment, the page table data reading (stage C) is completed before the memory access request arrives via a prefetch request. After the memory access request arrives at the MMU, it only needs to undergo address translation (stage D) to enter the effective data transfer period (stage B), resulting in an effective memory bus utilization rate of B / (D+B), i.e., a reduction in memory access bubbles. In summary, the page table prefetching method provided in this embodiment improves the effective utilization rate of the memory bus, increases the GPU's memory access throughput, and thus improves the GPU's memory access efficiency.

[0050] The page table prefetching method provided in this application determines a target address outside the current page table cache range of the MMU based on the address information of the memory access command to be processed, and generates a prefetch request based on the target address to prefetch the page table data corresponding to the page table cache range to which the target address belongs into the MMU's page table cache. The page table prefetching method provided in this application can prefetch the required page table data for memory access commands that have not yet been processed, thereby reducing memory access bubbles caused by cache misses when actually processing the memory access command and generating the memory access request, and thus improving the memory access efficiency of the GPU.

[0051] In some embodiments, before determining the target address located outside the first page table cache range based on the address information of at least one pending memory access command, the method further includes: The currently processed memory access command is split into multiple memory access requests, and the address information of the currently processed memory access command is updated according to the memory access requests. During the splitting process, the target address is determined based on the updated address information of the currently processed memory access commands.

[0052] In this embodiment, besides the memory access commands to be processed, the command stream also contains memory access commands currently being processed. For example, for a single memory access command with a large access range, the range of addresses to be accessed may span multiple page table cache ranges. That is, the command itself may access addresses outside the current page table cache range during the splitting and execution process. Even for memory access commands whose access range does not exceed the current page table cache range, as the splitting progresses and their remaining address range gradually moves forward, they may enter a new page table cache range that has not yet cached page table data during the splitting process. Furthermore, in scenarios where the access ranges of multiple memory access commands are relatively dispersed, the address ranges of both the currently processed memory access command and subsequent pending memory access commands may exceed the current page table cache range. Therefore, it is necessary to first split the currently processed memory access command and update its address information in real time during the splitting process, so that the target address can be determined based on the updated address information to cover the prefetching requirements that the currently processed memory access command itself may generate during the splitting process.

[0053] In this embodiment, the currently processed memory access command is split into multiple memory access requests, and the address information of the currently processed memory access command is updated according to the memory access requests. For example, the memory access request generation module splits the address range indicated by the currently processed memory access command into multiple memory access requests according to the memory bus protocol. Since the address range indicated by a single memory access command may exceed the maximum length that the memory bus can carry in a single transmission, it needs to be split into multiple memory access requests so that each memory access request conforms to the transmission requirements of the bus protocol. In one possible implementation, the address information of the currently processed memory access command can be represented as (starting address, access length), i.e., (addr, size), and the corresponding address range to be accessed is a half-open interval [addr, addr+size). The memory access request generation module splits this address range into multiple memory access requests sequentially according to the maximum single transmission length specified by the bus protocol, with each memory access request corresponding to a continuous sub-address interval. During the splitting process, the entire range of addresses to be accessed is not converted into memory access requests all at once. Instead, the range of addresses to be accessed is split into segments and memory access requests are generated one by one. Each time a memory access request is generated, the address information of the currently processed memory access command is updated according to the access range of the memory access request. For example, the starting address is moved to the end of the address range covered by the memory access request, and the access length is reduced accordingly, so that the address information of the currently processed memory access command always reflects the remaining range of addresses to be accessed.

[0054] In this embodiment, the first page table cache range is the current page table cache range of the MMU. In one possible implementation, the first page table cache range is determined by the interval corresponding to the cache line where the starting address of the currently processed memory access command is located. The page table data corresponding to the current starting address of the currently processed memory access command is usually cached in the MMU's page table cache. Therefore, in one possible implementation, the interval corresponding to the cache line where the starting address of the currently processed memory access command is located can be used as the current page table cache range of the MMU (i.e., the first page table cache range).

[0055] In this embodiment, during the splitting process, the target address is determined based on the updated address information of the currently processed memory access command. With each memory access request generated, the address information of the currently processed memory access command is updated synchronously, reflecting the remaining address range of the command under the splitting progress. During this splitting process, the updated address information of the currently processed command, combined with the address information of the memory access command to be processed, can be used as a detection object to determine the target address located outside the first page table cache range.

[0056] For example, assuming the currently processed memory access command is cmd(0x1000, 0x1000), and its access length is 0x1000 (i.e., 4096 bytes), then the range of addresses to be accessed is [0x1000, 0x2000]. Assuming the maximum single transmission length specified by the bus protocol is 0x800 (i.e., 2048 bytes), the memory access request generation module splits it into two memory access requests: the first memory access request corresponds to the address range [0x1000, 0x1800], and the second memory access request corresponds to the address range [0x1800, 0x2000]. As these two memory access requests are generated, the address information of the currently processed memory access command is updated accordingly to reflect that the address range it covers has been gradually split into memory access requests (for example, the updated starting address is pushed forward to 0x2000, indicating that the address range of the currently processed memory access command has been completely converted into memory access requests). It is worth noting that the above-mentioned number of splits, maximum single transmission length and specific values ​​are merely examples for ease of understanding. This application does not limit the splitting method of memory access commands, the specific type of bus protocol, the specific rules for updating the address information of the currently processed memory access command according to the memory access request, or the specific method for determining the range of the first page table cache, etc. They can all be configured according to the actual application scenario and bus specifications.

[0057] For the currently processed memory access command, its address information is updated during the process of splitting it into multiple memory access requests. Based on the updated address information, the corresponding target address is determined and a prefetch request is generated. Therefore, for a single memory access command with a large access range that may span multiple page table caches, the page table data required by the split memory access requests when they reach the MMU can also be prefetched. This avoids cache misses and memory access bubbles caused by the large access range of the memory access command itself, and ensures that the splitting of the currently processed memory access command and the sending of memory access requests can continue.

[0058] In some embodiments, the address information includes a starting address. Updating the address information of the currently processed memory access command according to the memory access request includes: during the splitting process, for each memory access request generated, updating the starting address of the currently processed memory access command according to the access range indicated by the memory access request, to obtain the updated address information of the currently processed memory access command.

[0059] In this embodiment, the address information of the currently processed memory access command is used to indicate the address range to be accessed by the currently processed memory access command, and its specific representation is not limited in this application. In one possible implementation, the address information of the currently processed memory access command can be represented as (starting address, access length), i.e. (addr, size), and the corresponding address range to be accessed is a half-open interval [addr, addr+size).

[0060] In some embodiments, the memory access request generation module splits the currently processed memory access command into multiple memory access requests. Each memory access request indicates its own access range, that is, a continuous sub-address interval corresponding to the memory access request. In one possible implementation, the access range of a memory access request can be represented as (request start address, request access length), and its corresponding address interval is a half-open interval [request start address, request start address + request access length), and this interval falls within the address range [addr, addr + size) of the memory access command to be accessed. In other words, the access range of a memory access request is a continuous sub-interval of the address range to be accessed by the currently processed memory access command.

[0061] During the splitting process, the memory access request generation module does not convert the entire range of addresses to be accessed by the currently processed memory access command into memory access requests all at once. Instead, it splits the range of addresses to be accessed segment by segment and generates memory access requests one by one. Each time a memory access request is generated, the address information of the currently processed memory access command is updated according to the access range indicated by the memory access request, so that it always reflects the remaining range of addresses to be accessed by the currently processed memory access command. Specifically, for each memory access request generated, based on the access range indicated by the memory access request (e.g., the request access length of the memory access request), the starting address of the currently processed memory access command is advanced to the end of the address range covered by the memory access request, and the access length is correspondingly subtracted from the request access length. Thus, the updated starting address represents the starting position of the remaining addresses to be accessed in the currently processed memory access command that have not yet been split into memory access requests, and the updated access length represents the size of the remaining range of addresses to be accessed. Together, they constitute the updated address information of the currently processed memory access command.

[0062] In one possible implementation, the address detection module can synchronously maintain the address information of the currently processed memory access command based on the updated address information provided by the memory access request generation module. This information includes at least the current starting address (denoted as current_addr) and current access length (denoted as current_size) of the currently processed memory access command. Current_addr and current_size are dynamically updated during the partitioning process of the memory access request generation module: after each memory access request (with a requested access length denoted as burst_size) is generated, current_addr is incremented by burst_size, and current_size is decremented by burst_size. Therefore, current_addr and current_size always reflect the remaining address range of the currently processed memory access command at the current partitioning progress.

[0063] For example, suppose the currently processed memory access command is cmd(0x1000, 0x1000), with a starting address of 0x1000 and an access length of 0x1000. Then the address range to be accessed is [0x1000, 0x2000]. Assuming the maximum single transmission length specified by the bus protocol is 0x800, the memory access request generation module splits it into two memory access requests: the first memory access request covers the address range [0x1000, 0x1800), and its requested access length is 0x800; the second memory access request covers the address range [0x1800, 0x2000), and its requested access length is 0x800. After the first memory access request is generated, based on the access range indicated by the memory access request (request access length 0x800), the starting address of the currently processed memory access command is updated from 0x1000 to 0x1800 and the access length is updated from 0x1000 to 0x800, resulting in the updated address information (0x1800, 0x800), reflecting the remaining address range as [0x1800, 0x2000). After the second memory access request is generated, based on the access range indicated by the memory access request (request access length 0x800), the starting address is updated from 0x1800 to 0x2000 and the access length is updated from 0x800 to 0, resulting in the updated address information (0x2000, 0), reflecting that the currently processed memory access command has been completely split into memory access requests. It is worth noting that the specific values ​​of the number of splits, the maximum transmission length per transmission, the starting address, and the access length mentioned above are merely examples for ease of understanding. This application does not limit the splitting method of the memory access command, the specific type of the bus protocol, the specific representation of the address information and the access range of the memory access request, or the specific rules for updating the address information of the currently processed memory access command based on the memory access request.

[0064] In some embodiments, the first page table cache range can be determined by the interval corresponding to the cache line where the starting address of the currently processed memory access command is located. Specifically, the address detection module can redetermine the current page table cache range (i.e., the first page table cache range) based on the synchronously maintained current_addr (i.e., the updated starting address of the currently processed memory access command): current_range_base=range_base(current_addr); current_range_end=current_range_base+M; Where current_range_base is the starting address of the redefined first page table cache range, current_range_end is the ending address of the redefined first page table cache range, and M is the size of the virtual address range covered by a cache line. Each time the starting address of the currently processed memory access command is updated, the boundary of the first page table cache range (from current_range_base to current_range_end) is redefined based on the cache line range into which the updated starting address falls. When the updated starting address of the currently processed memory access command falls into a new cache line, the first page table cache range is redefined accordingly, thus always covering the address range where the updated starting address of the currently processed memory access command is located.

[0065] For example, following the above process of splitting the memory access command cmd(0x1000, 0x1000), let M=0x4000. Then, for any address falling within [0x0, 0x4000), its range_id is 0, range_base is 0x0, and range_end is 0x4000, meaning the corresponding first page table cache range is [0x0, 0x4000). As the splitting progresses, the status maintained by the address detection module is updated as follows: 1. Initially, current_addr = 0x1000 and current_size = 0x1000.

[0066] 2. After the first memory access request (burst_size=0x800) is generated, current_addr is updated to 0x1800 and current_size is updated to 0x800.

[0067] 3. Based on the updated address information of the currently processed memory access command, determine the cache range of the first page table: current_range_base=range_base(0x1800)=0x0; current_range_end=0x0+0x4000=0x4000; The first page table cache range is [0x0, 0x4000].

[0068] 4. After generating the second memory access request, current_addr is updated to 0x2000 and current_size is updated to 0. The first page table cache range is: current_range_base=0x0; current_range_end=0x4000; the first page table cache range is [0x0, 0x4000).

[0069] Therefore, during the aforementioned splitting and updating process, the address information of the currently processed memory access command is updated synchronously with the generation of each memory access request, and the first page table cache range is also redefined with each update of the starting address. It is worth noting that the values ​​of the number of splits, the maximum single transmission length, the size M of the virtual address range covered by the cache line, and other specific values ​​are merely examples for ease of understanding. This application does not limit the splitting method of memory access commands, the specific type of bus protocol, the size of M, or the specific rules for determining the address information of the currently processed memory access command and the first page table cache range based on the memory access request.

[0070] For example, during the splitting process, each time a memory access request is generated, the address information of the currently processed memory access command is updated. Simultaneously, based on the updated address information of the currently processed memory access command and the address information of at least one pending memory access command, it is determined whether a target address exists outside the range of the first page table cache. The triggering method may include, but is not limited to, the following scenarios: In some embodiments, each update of the address information of the currently processed memory access command and the range of the first page table cache based on a memory access request performs an operation to determine a target address outside the range of the first page table cache, based on the updated address information of the currently processed memory access command and the address information of at least one pending memory access command. In other embodiments, the above-mentioned determination operation is not triggered after each update, but is performed according to predetermined conditions. The predetermined conditions may include at least one of the following: First, triggered by the number of splits, for example, when a predetermined number of memory access requests are generated, or when the cumulative number of updates reaches a preset value, the determination is made based on the starting address after the most recent update and the corresponding first page table cache range; Second, triggered by address boundaries, for example, when the updated starting address reaches or exceeds a preset detection boundary, a determination operation is performed; Third, after all the splits of a memory access command are completed, the determination is made based on the starting address obtained from the final update and the corresponding first page table cache range.

[0071] For the memory access command currently being processed, by updating the starting address according to the access range indicated by the memory access request each time a memory access request is generated during the splitting process, the address information of the currently processed memory access command can continuously and accurately reflect its current remaining address range as the splitting progresses. This provides a reliable data foundation for determining the target address in real time during the splitting process and improves the accuracy of page table prefetching.

[0072] In some embodiments, determining the target address based on the updated address information of the currently processed memory access command includes: Based on the updated address information of the currently processed memory access command, determine the remaining address range of the currently processed memory access command; If the remaining address range exceeds the first page table cache range, the first address in the remaining address range that is outside the first page table cache range will be determined as the target address. If the remaining address range does not exceed the first page table cache range, perform the step of determining the target address located outside the first page table cache range based on the address information of at least one pending memory access command.

[0073] In this embodiment, the remaining address range of the currently processed memory access command refers to the remaining address range to be accessed that has not yet been split into a memory access request after the memory access request generation module updates the address information sequentially during the splitting process. In one possible implementation, the remaining address range is determined by the updated starting address and the updated access length, i.e., a half-open interval [updated starting address, updated starting address + updated access length]. The updated starting address and the updated access length are the updated address information of the currently processed memory access command.

[0074] In this embodiment, the first page table cache range is the current page table cache range of the MMU. When determining the target address, the remaining address range of the currently processed memory access command is first compared with the boundary of the first page table cache range: if the remaining address range exceeds the first page table cache range (i.e., there are addresses outside the first page table cache range in the remaining address range, and the page table entries corresponding to these addresses have not yet been cached in the MMU), then the first address outside the first page table cache range in the remaining address range is determined as the target address. The first address outside the first page table cache range refers to the address that first reaches the boundary of the first page table cache range along the address growth direction of the remaining address range.

[0075] If the remaining address range does not exceed the first page table cache range, it indicates that the currently processed memory access command itself does not require prefetching under the current splitting progress. At this point, the process switches to determining the target address outside the first page table cache range based on the address information of at least one pending memory access command (i.e., the process of determining the target address based on the pending memory access command). This forms the sequence of "first judging the currently processed memory access command, then judging the pending memory access commands": in each round, the target address is determined first based on the remaining address range of the currently processed memory access command. If it does not exceed the first page table cache range, the target address is determined based on the pending memory access command, thus ensuring complete coverage of the address ranges of both types of commands.

[0076] For ease of explanation, the following examples are based on the following settings: the size of the virtual address range covered by the cache line of the MMU page table cache is denoted as M, and M = 32KB (kilobyte); for any virtual address falling into [0, 32KB), its page table cache range is [0KB, 32KB), that is, the current first page table cache range is [0KB, 32KB).

[0077] For example, suppose the currently processed memory access command is cmd(0x1000, 0x1000), and its remaining address range is updated as the splitting progresses. After the first memory access request is generated, the remaining address range is [0x1800, 0x2000]. Since both 0x1800 and 0x2000 are less than 32KB (i.e., both fall within the first page table cache range [0KB, 32KB)), the entire remaining address range falls within the first page table cache range [0KB, 32KB), meaning it does not exceed the first page table cache range. Therefore, the step of determining the target address based on the address information of the memory access command to be processed is executed.

[0078] For example, taking the scenario where the address range of the currently processed memory access command crosses the boundary of the first page table cache range as an example, still based on the above settings (M=32KB, the first page table cache range is [0KB, 32KB)). Assume that the currently processed memory access command is cmd(3KB, 96KB), that is, its starting address is 3KB and the access length is 96KB, then its remaining address range is [3KB, 99KB). Since the ending address 99KB of [3KB, 99KB) exceeds the ending address 32KB of the first page table cache range [0KB, 32KB), that is, the remaining address range crosses the boundary of the first page table cache range, the remaining address range exceeds the first page table cache range. Furthermore, the first address in the remaining address range [3KB, 99KB) that is outside the first page table cache range [0KB, 32KB) is 32KB (that is, the address that first reaches the boundary of the first page table cache range along the address growth direction). Therefore, 32KB is determined as the target address outside the first page table cache range. Therefore, by first determining the remaining address range of the currently processed memory access command, when the address range of the currently processed memory access command itself exceeds the range of the first page table cache, the first out-of-bounds address can be accurately identified as the target address, and a prefetch request can be generated accordingly. It is worth noting that this application does not limit the method for determining whether the remaining address range exceeds the range of the first page table cache, nor the method for finding the first address outside the range of the first page table cache. Those skilled in the art can configure these methods according to the MMU page table cache configuration and actual application scenarios. The specific methods for determining the target address based on the remaining address range of the currently processed memory access command, and the specific methods for determining the target address based on the address information of the memory access command to be processed, will be described in detail in the following embodiments, and will not be repeated here.

[0079] By limiting the target address to be determined based on the remaining address range after the current memory access command is updated, and only when it does not exceed the first page table cache range, the process rolls back to determine the target address based on the address information of the pending memory access command. This improves the prefetching efficiency in the above scenarios, especially when the access range of the current memory access command is large and cache misses are possible.

[0080] In some embodiments, determining a target address outside the first page table cache range based on address information of at least one pending memory access command includes: Based on the processing order of at least one pending memory access command, traverse each pending memory access command in sequence; Determine the target address range based on the address information of the memory access commands to be processed currently being traversed; If the target address range exceeds the first page table cache range, stop traversing and determine the first address in the target address range that is outside the first page table cache range as the target address.

[0081] In this embodiment, the memory access commands to be processed are arranged sequentially in the address detection window according to their generation order. When determining the target address, each memory access command to be processed is traversed sequentially from the head to the tail of the queue according to the processing order of the memory access commands to be processed. For the currently traversed memory access command, its corresponding target address range is determined according to its address information (i.e., the starting address and access length of the memory access command to be processed, and the corresponding range of the address to be accessed is a half-open interval [starting address, starting address + access length)). Here, the target address range is the range of the address to be accessed of the currently traversed memory access command, which is used to represent the virtual address range covered by the page table data required by the command.

[0082] In this embodiment, during the traversal process, the target address range of the currently traversed memory access commands is compared with the boundary of the first page table cache range. If the target address range, in whole or in part, exceeds the first page table cache range (i.e., there are addresses outside the first page table cache range within this range, and the page table entries corresponding to these addresses have not yet been cached in the MMU), then it is determined that the target address range exceeds the first page table cache range. At this point, the traversal stops, and the first address outside the first page table cache range within the target address range is determined as the target address. In other words, the traversal terminates when a memory access command outside the first page table cache range is first encountered. The target address is determined for this command first, and a corresponding prefetch request is generated, without continuing to traverse the remaining memory access commands. For example, when the traversal reaches the last memory access command in the processing order, and its corresponding target address range does not exceed the first page table cache range, it is determined that there is currently no target address outside the first page table cache range, and no prefetch request needs to be generated. Furthermore, if the starting address of the target address range of the currently traversed memory access command is already outside the first page table cache range, then the starting address is directly determined as the target address, without needing to align it down to the boundary of the page table cache range where the starting address is located, in order to avoid prefetching an address that the memory access command will not actually access and thus generating a page fault.

[0083] For example, suppose the first page table cache range is [0x0, 0x4000]. In the address detection window, there are two memory access commands to be processed in the order of processing: cmd(0x1000, 0x1000) and cmd(0x3000, 0x2000), the former corresponds to the target address range [0x1000, 0x2000), and the latter corresponds to the target address range [0x3000, 0x5000). Traverse the code in the order of processing. First, traverse cmd(0x1000, 0x1000). Its target address range [0x1000, 0x2000) falls entirely within the first page table cache range [0x0, 0x4000), so the traversal continues. Then, traverse cmd(0x3000, 0x2000). Its target address range [0x3000, 0x5000) crosses the boundary 0x4000. [0x4000, 0x5000) exceeds the first page table cache range, so it is determined that the range is exceeded, the traversal stops, and the first address outside the first page table cache range, 0x4000, is determined as the target address. It is worth noting that this application does not limit the specific method for determining the processing order of at least one pending memory access command (e.g., the order in which commands are received according to the address detection window, or the order determined by the bus scheduling strategy), nor the specific method for detecting whether the target address range exceeds the range of the first page table cache. Those skilled in the art can configure it according to the MMU page table cache configuration and the actual application scenario.

[0084] By sequentially traversing the pending memory access commands according to their processing order, and stopping the traversal when the first pending memory access command whose target address range exceeds the first page table cache range, this embodiment of the application can determine the target address and generate the corresponding prefetch request without traversing all pending memory access commands one by one. Thus, in the case of multiple pending memory access commands, unnecessary traversal overhead is reduced and the efficiency of page table prefetching is improved.

[0085] In some embodiments, determining the first address in the target address range that is outside the first page table cache range as the target address includes: If the starting address of the target address range is outside the first page table cache range, the starting address of the target address range shall be determined as the target address. If the starting address of the target address range is within the first page table cache range and the ending address of the target address range is outside the first page table cache range, then the ending address of the first page table cache range is determined as the target address.

[0086] In this embodiment of the application, the target address range can be the range of addresses to be accessed corresponding to the address information of the memory access command to be processed, and the first address in the target address range that is outside the first page table cache range is determined as the target address, following the following two scenarios: Scenario 1: If the starting address of the target address range is already outside the first page table cache range, then the starting address is directly determined as the target address; Scenario 2: If the starting address of the target address range is within the first page table cache range, but the ending address of the target address range is outside the first page table cache range (i.e., the target address range itself crosses the ending boundary of the first page table cache range), then the ending address of the first page table cache range is the first address in the target address range that is outside the first page table cache range, and therefore it is determined as the target address.

[0087] In one possible implementation, the target address is determined based on the remaining address range of the currently processed memory access command, and also based on the address information of the memory access command to be processed. The specific methods used for both can be consistent, i.e., determining the first address outside the first page table cache range within the target address range according to the two scenarios described above. For ease of explanation, a unified detection process will be used as an example below. For instance, after the memory access request generation module generates a memory access request and updates the starting address and access length (i.e., address information) of the currently processed memory access command, the current starting address can be denoted as current_addr, and the current access length can be denoted as current_size. The address detection module then enters the detection process: First, determine the current first page table cache range using current_addr: current_range_base=range_base(current_addr); current_range_end=current_range_base+M; Where M is the size of the virtual address range covered by a cache line, current_range_base is the starting address of the first page table cache range, and current_range_end is the ending address of the first page table cache range (for details, please refer to the above embodiment, which will not be repeated here).

[0088] Subsequently, the address detection module can sequentially detect the remaining address range of the currently processed memory access command and the target address range corresponding to the address information of at least one pending memory access command.

[0089] For any target address range [addr, addr+size) corresponding to a memory access command to be detected (where addr is the start address of the memory access command to be detected (i.e., the start address of the target address range), and size is the access length of the memory access command to be detected), the detection rules are as follows: Rule 1: If "addr < current_range_base, or addr ≥ current_range_end", it indicates that the start address of the target address range is already outside the range of the first page table cache, then the start address addr of the target address range is directly determined as the target address; Rule 2: If "addr ≥ current_range_base, addr < current_range_end and addr+size > current_range_end", it indicates that the start address of the target address range is within the range of the first page table cache and the end address is outside the range of the first page table cache, then the end address current_range_end of the first page table cache range is determined as the target address; Rule 3: If "addr ≥ current_range_base and addr+size ≤ current_range_end", it indicates that the target address range does not exceed the range of the first page table cache, then the next memory access command is continuously detected. In addition, if the access length of the memory access command to be detected is 0 (the address range is empty), the target address is not determined, and the next memory access command is continuously detected.

[0090] In some embodiments, the above rules are uniformly applicable to the currently processed memory access command and the memory access commands to be processed, that is, no matter the target address range comes from the remaining address range of the currently processed memory access command or from the address information of the memory access command to be processed, the same determination logic is executed according to the above rules 1 to 3. The address detection module detects the remaining address range corresponding to the currently processed memory access command first according to the above detection rules, and then traverses the memory access commands to be processed in sequence according to the processing order. Once the target address is determined, the detection of subsequent commands is stopped.

[0091] For example, let M = 32KB, and the first page table cache range be [0KB, 32KB). Taking the memory access commands to be processed as an example, assume that there are two memory access commands to be processed in the address detection window in the processing order: cmd(10KB, 3KB) and cmd(65KB, 24KB), the target address range of the former is [10KB, 13KB), and the target address range of the latter is [65KB, 89KB). Traversing in the processing order: when traversing cmd(10KB, 3KB), its target address range [10KB, 13KB) falls entirely within the first page table cache range [0KB, 32KB), the target address is not determined, and traversal continues; when traversing cmd(65KB, 24KB), the starting address of its target address range, 65KB, is already outside the first page table cache range [0KB, 32KB), that is, rule 1 is satisfied, so 65KB is directly determined as the target address, and traversal stops.

[0092] Similarly, the above two scenarios and rules 1-3 also apply to the remaining address range of the currently processed memory access command. For example, if the currently processed memory access command itself has a large access range and its remaining address range crosses the boundary of the first page table cache range (e.g., the remaining address range is [3KB, 99KB, and the first page table cache range is [0KB, 32KB)), its ending address of 99KB exceeds 32KB, satisfying rule 2. In this case, the ending address of the first page table cache range, 32KB, is determined as the target address.

[0093] In some embodiments, only the first address that crosses the first page table cache range is selected as the target address, and a corresponding prefetch request is generated. Specifically, the address detection module, according to the above detection rules, first detects the remaining address range corresponding to the currently processed memory access command, and then sequentially traverses at least one pending memory access command in the address detection window according to the processing order. Once the target address is determined according to the above rules, the detection of subsequent commands stops.

[0094] By clearly defining two scenarios for determining "the first address located outside the first page table cache range," this application provides specific and operable rules for determining the target address, avoiding ambiguity. Simultaneously, by clarifying the target address detection logic, a unified judgment logic can be used to accurately detect both currently processed memory access commands and pending memory access commands, generating corresponding prefetch requests when conditions are met, thus improving the practicality of the page table prefetch method.

[0095] In some embodiments, after generating a prefetch request based on the target address, the method further includes: Determine the updated first page table cache range based on the second page table cache range to which the target address belongs; If the starting address of the currently processed memory access command reaches or exceeds the target address, the next target address located outside the updated first page table cache range is determined based on the address information of the currently processed memory access command and the address information of at least one pending memory access command.

[0096] In this embodiment, as described in the previous embodiment, the second page table cache range to which the target address belongs refers to the page table cache range in the MMU page table cache, where the target address falls, on a cache line-by-cache basis. In one possible implementation, after generating a prefetch request, the address detection module updates the first page table cache range to the second page table cache range targeted by the prefetch request, and records the target address corresponding to the prefetch request (denoted as prefetched_addr) and the validity flag of the target address (denoted as prefetched_addr_valid). The specific determination method of the updated first page table cache range is as follows: its starting address is range_base(prefetched_addr), and its ending address is range_base(prefetched_addr) + M (for a detailed explanation of this formula, please refer to the previous embodiment). This update ensures that subsequent detection is based on the new page table cache range boundary, rather than continuing to use the first page table cache range before the update, thereby avoiding repeated prefetch requests for page table data corresponding to the same address range.

[0097] In one possible implementation, `prefetched_addr` and `prefetched_addr_valid` together constitute a prefetch record. When a prefetch request has been issued, and the starting address `current_addr` of the currently processed memory access command has not yet reached or exceeded `prefetched_addr`, it indicates that the current access position of the currently processed memory access command is still within the first page table cache range, and a prefetch request has already been issued for the target address within this range; therefore, no new prefetch request needs to be generated. When `current_addr` reaches or exceeds `prefetched_addr`, it indicates that the currently processed memory access command has progressed to the previously prefetched target address. At this point, the original prefetch record is cleared, and the address information of the currently processed memory access command and the address information of at least one pending memory access command in the address detection window are re-detected. This allows the page table data corresponding to the next page table cache range to be prefetched into the page table cache, i.e., the next target address is generated, and a corresponding prefetch request is generated.

[0098] For ease of explanation, let's assume that a target address detection refers to a complete detection process from the moment the current detection is triggered until the end of the current detection. The end of a detection may include, but is not limited to: the current detection determines the target address and generates a prefetch request, the current detection does not determine the target address, and the current detection no longer determines the target address because there are prefetch records that have not yet been cleared.

[0099] During the splitting process, the starting address (current_addr) and access length (current_size) of the currently processed memory access command are updated progressively as the splitting progresses. Each update triggers a target address check. Whether to continue determining the target address during a triggered check depends on whether the starting address of the currently processed memory access command reaches or exceeds the recorded target address, or whether the prefetched record has been cleared. Specifically, when this check is triggered, if the recorded prefetched record is still valid (e.g., prefetched_addr_valid is True), and current_addr has not yet reached or exceeded prefetched_addr, then the recorded prefetched record remains unchanged, and the check ends. The updated address information of the currently processed memory access command and the address information of at least one pending memory access command are no longer traversed, and no new target address is determined or a new prefetch request is generated. Conversely, when current_addr reaches or exceeds prefetched_addr, it indicates that the currently processed memory access command has progressed to the previously prefetched target address. At this time, the recorded prefetch records are cleared (e.g., prefetched_addr_valid is set to False (invalid), and prefetched_addr is set to None (none)). In this detection, the detection logic continues to be executed. That is, based on the updated first page table cache range, the address information of the currently processed memory access command and the address information of at least one pending memory access command are re-detected to see if there is a target address outside the updated first page table cache range, thereby determining the next target address.

[0100] In some embodiments, besides the case where the starting address of the currently processed memory access command reaches or exceeds the target address, the prefetch record can also be cleared in other situations, such as when the page table data corresponding to the prefetch request has been prefetched, the currently processed memory access command has been split and the process has switched to the next memory access command, or the table entry in the address detection window has been updated. Even when the prefetch record is cleared, subsequent triggered detections will still execute the above detection logic to determine the next target address. In other words, after a prefetch request has been generated, the next target address for generating the prefetch request will only be determined in subsequent detections if the starting address of the currently processed memory access command reaches or exceeds the recorded target address, or if the recorded prefetch record is cleared. It is worth noting that this application does not limit the recording format of the target address, the specific implementation method of the validity flag, or the timing of determining the updated first page table cache range based on the second page table cache range (e.g., updating immediately after the prefetch request is issued, or updating after the page table data has been cached). Those skilled in the art can configure these according to actual application scenarios.

[0101] By determining the next target address only when the starting address of the currently processed memory access command reaches or exceeds the current target address, based on the updated address information of the currently processed memory access command and the address information of the pending memory access command, the prefetch request is not repeatedly generated after each split update. This reduces the frequency and computational complexity of target address detection, thereby reducing detection overhead while ensuring the accuracy of page table prefetching. Furthermore, this mechanism allows the page table prefetching method to continue even when it spans multiple page table cache ranges, improving the continuity and coverage of the prefetching mechanism.

[0102] Next, combine Figure 5 The process of generating a prefetch request is explained. For example, please refer to... Figure 5 , Figure 5 This is a schematic diagram of the prefetch request generation process provided in one possible implementation of this application.

[0103] like Figure 5 As shown, the address detection window 510 receives multiple memory access commands sequentially. The address detection window 510 identifies the memory access command at the head of the queue as the currently processed memory access command and sends it to the memory access request generation module 520; it also sends the address information of at least one subsequent memory access command to the address detection module 530. After the currently processed memory access command is completed, the address detection window 510 sequentially identifies the next memory access command as the new round of currently processed memory access commands and sends it to the memory access request generation module 520.

[0104] After receiving the currently processed memory access command, the memory access request generation module 520 splits the currently processed memory access command into multiple memory access requests, and sends the generated memory access requests to the arbitration module 540. In addition, during the splitting process, the memory access request generation module 520 sends the updated address information of the currently processed memory access command to the address detection module 530.

[0105] During the splitting process, the address detection module 530 determines the target address outside the first page table cache range based on the updated address information of the currently processed memory access command and the address information of at least one pending memory access command; and after determining the target address, it generates a corresponding prefetch request. The specific detection mechanism has been described in the above embodiments and will not be repeated here. If a prefetch request is generated, the address detection module 530 sends the prefetch request to the arbitration module 540.

[0106] Arbitration module 540 receives memory access requests from memory access request generation module 520 and prefetch requests from address detection module 530, and arbitrates the two according to a predetermined strategy, sending the selected memory access request or prefetch request to memory bus 120. For example, arbitration module 540 is a scheduling node that unifies the scheduling of the two types of requests. Specifically, arbitration module 540 can send a prefetch request to memory bus 120 before the memory access request corresponding to the target address actually arrives at the MMU, causing the MMU to prefetch the page table data corresponding to the second page table cache range into the page table cache, thereby reducing memory access bubbles.

[0107] In some embodiments, prefetch requests have a lower priority than memory access requests.

[0108] In one aspect of this embodiment, the purpose of prefetching page table data is to reduce memory access bubbles and improve GPU memory access efficiency. Memory access requests, however, carry the actual memory access demands and are more sensitive to memory access latency and throughput. Therefore, when prefetch requests and memory access requests need to be processed concurrently, the priority of prefetch requests can be set lower than that of memory access requests. This ensures that currently generated memory access requests have priority access to memory bus and MMU processing resources, preventing prefetch operations from preempting resources and blocking current memory access operations, thus affecting memory access performance. In other words, when there are pending memory access requests and prefetch requests in the system simultaneously, and normal memory access responses need to be guaranteed, setting the priority of prefetch requests lower than that of memory access requests can minimize the impact of prefetch requests on normal memory access.

[0109] For example, the following will combine Figure 5 The arbitration module 540 shown illustrates the specific implementation method for prefetch requests having a lower priority than memory access requests. For example... Figure 5As shown, the memory access request generated by the memory access request generation module 520 and the prefetch request generated by the address detection module 530 jointly enter the arbitration module 540. The arbitration module 540 selects the appropriate request (prefetch request or memory access request) based on the request type, queue status, or priority, and sends the selected request to the memory bus 120. In some embodiments, to avoid affecting normal memory access, at least one of the following two implementation methods can be adopted: 1. Priority Setting: Prefetch requests are prioritized lower than memory access requests. In this mode, the arbitration module 540 determines the priority of each request based on its type, ensuring that prefetch requests always follow memory access requests in the scheduling order. When memory access requests and prefetch requests coexist, the arbitration module 540 prioritizes sending memory access requests to the memory bus 120, sending prefetch requests only when there are no memory access requests to process or during memory access request processing intervals. This method is simple to implement and suitable for various scenarios with concurrent memory access requests and prefetch requests, reliably ensuring that normal memory access is not blocked by prefetch requests from the scheduling level.

[0110] 2. Proactive Suppression: Before sending a prefetch request, the arbitration module 540 first queries the MMU's page table cache status or request record to determine whether the prefetch request still needs to be sent. If the page table data corresponding to the prefetch request is already cached in the MMU's page table cache, or if prefetch operations with the same target range (i.e., all within the second page table cache range) have not yet been completed, the prefetch request is suppressed and will not be sent to the memory bus 120 or the MMU. This method actively cancels redundant prefetch requests, preventing prefetch requests from competing for resources with memory access requests. It also achieves the effect of prefetch requests having lower priority than memory access requests and further avoids unnecessary prefetch requests occupying memory bus bandwidth. This method is suitable for scenarios where the corresponding page table data has been cached or where there are prefetch requests with the same target range, reducing bus overhead while reducing invalid operations.

[0111] The two implementation methods described above can be used individually or in combination. For example, by using static priority, redundant prefetch requests can be further suppressed, thereby saving bus resources while ensuring normal memory access. Regardless of the method used, the core principle is to prioritize prefetch requests lower than memory access requests, ensuring that the performance of normal memory access is not affected by prefetch operations.

[0112] It is worth noting that the above combination Figure 5The description of the prefetch request generation process and the description of the prefetch request priority are exemplary descriptions based on one possible implementation of this application. They are used to illustrate the technical concept of this application and should not be construed as limiting the scope of protection of this application. This application does not limit the module division method between the address detection window 510, the memory access request generation module 520, the address detection module 530, and the arbitration module 540, the specific implementation form of the functions of each module, or the signal interaction timing between modules. Those skilled in the art can adopt different methods according to actual needs. Figure 5 The same or different modules can be divided into different modules, or the same or equivalent technical effects can be achieved by merging, splitting or reorganizing the functions of each module.

[0113] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0114] For example, please refer to Figure 6 , Figure 6 This is a structural block diagram of a page table prefetching device provided in one possible implementation of this application. The page table prefetching device 600 includes a command acquisition module 610, an address determination module 620, and a request generation module 630.

[0115] Command acquisition module 610 is used to acquire at least one memory access command to be processed.

[0116] Address determination module 620 is used to determine a target address outside the range of the first page table cache based on the address information of at least one memory access command to be processed. The address information indicates the address range to be accessed by the memory access command, and the first page table cache range is the current page table cache range of the memory management unit (MMU).

[0117] The request generation module 630 is used to generate a prefetch request based on the target address. The prefetch request is used to prefetch the page table data corresponding to the second page table cache range to which the target address belongs into the page table cache of the MMU.

[0118] In some embodiments, the address determination module 620 is configured to: Based on the processing order of at least one pending memory access command, traverse each pending memory access command in sequence; Determine the target address range based on the address information of the memory access commands to be processed currently being traversed; If the target address range exceeds the first page table cache range, stop traversing and determine the first address in the target address range that is outside the first page table cache range as the target address.

[0119] In some embodiments, the address determination module 620 is configured to: If the starting address of the target address range is outside the first page table cache range, the starting address of the target address range shall be determined as the target address. If the starting address of the target address range is within the first page table cache range and the ending address of the target address range is outside the first page table cache range, then the ending address of the first page table cache range is determined as the target address.

[0120] In some embodiments, the page table prefetching device 600 further includes a command splitting module (not shown).

[0121] The command splitting module is used to split the currently processed memory access command into multiple memory access requests, and update the address information of the currently processed memory access command according to the memory access requests.

[0122] The address determination module 620 is also used to: determine the target address based on the updated address information of the currently processed memory access command.

[0123] In some embodiments, the address determination module 620 is configured to: Based on the updated address information of the currently processed memory access command, determine the remaining address range of the currently processed memory access command; If the remaining address range exceeds the first page table cache range, the first address in the remaining address range that is outside the first page table cache range will be determined as the target address. If the remaining address range does not exceed the first page table cache range, perform the step of determining the target address located outside the first page table cache range based on the address information of at least one pending memory access command.

[0124] In some embodiments, the address information includes a starting address. The command splitting module is configured to: during the splitting process, for each memory access request generated, update the starting address of the currently processed memory access command according to the access range indicated by the memory access request, thereby obtaining the updated address information of the currently processed memory access command.

[0125] In some embodiments, the page table prefetching device 600 further includes an update module 640.

[0126] The update module 640 is used to: determine the updated first page table cache range based on the second page table cache range to which the target address belongs.

[0127] The address determination module 620 is further configured to: determine the next target address located outside the updated first page table cache range, based on the address information of the updated currently processed memory access command and the address information of at least one pending memory access command, if the starting address of the updated currently processed memory access command reaches or exceeds the target address.

[0128] In some embodiments, prefetch requests have a lower priority than memory access requests. A memory access request is obtained by splitting the currently processed memory access command.

[0129] The page table prefetching apparatus provided in this application determines a target address outside the current page table cache range of the MMU based on the address information of the memory access command to be processed, and generates a prefetch request based on the target address to prefetch the page table data corresponding to the page table cache range to which the target address belongs into the MMU's page table cache. The page table prefetching apparatus provided in this application can prefetch the required page table data for memory access commands that have not yet been processed, thereby reducing memory access bubbles caused by cache misses when actually processing the memory access command and generating the memory access request, and thus improving the memory access efficiency of the GPU.

[0130] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0131] For example, please refer to Figure 7 , Figure 7 This is a structural block diagram of a computer device provided in one possible implementation of this application. The computer device 700 can be any electronic device with data calculation, processing, and storage functions. The computer device 700 can be used to implement the page table prefetching method provided in the above embodiments.

[0132] Typically, computer device 700 may include a processor 710 and a memory 720.

[0133] Processor 710 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 710 may be implemented using at least one hardware form selected from DSP (Digital Signal Processor), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 710 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 710 may integrate a GPU, which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 710 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0134] The memory 720 may include one or more computer-readable storage media, which may be non-transitory. The memory 720 may also include high-speed random access memory and NVM (Non-Virtual Machine). Volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage medium in memory 720 is used to store a computer program configured to be executed by one or more processors to implement the page table prefetching method described above.

[0135] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on the computer device 700, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0136] In an illustrative embodiment, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor of a computer device, implements the page table prefetching method described above. Optionally, the computer-readable storage medium may be ROM (Read-Only Memory), RAM (Random Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk, and optical data storage device, etc.

[0137] In an exemplary embodiment, a chip is also provided, the chip including programmable logic circuitry and / or program instructions stored in a computer-readable storage medium. A processor of a computer device reads the programmable logic circuitry and / or program instructions from the computer-readable storage medium, and executes the programmable logic circuitry and / or program instructions, causing the computer device to perform the page table prefetch method described above.

[0138] In an exemplary embodiment, a computer program product is also provided, which includes a computer program loaded and executed by a processor to implement the page table prefetching method described above.

[0139] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0140] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A page table prefetching method, characterized in that, The method includes: Obtain at least one pending memory access command; Based on the address information of the at least one pending memory access command, a target address located outside the first page table cache range is determined; wherein, the address information is used to indicate the address range to be accessed by the memory access command, and the first page table cache range is the current page table cache range of the memory management unit (MMU). Based on the target address, a prefetch request is generated. The prefetch request is used to prefetch the page table data corresponding to the second page table cache range to which the target address belongs into the page table cache of the MMU.

2. The method according to claim 1, characterized in that, Determining the target address outside the first page table cache range based on the address information of the at least one pending memory access command includes: According to the processing order of the at least one pending memory access command, each pending memory access command is traversed sequentially; Determine the target address range based on the address information of the memory access commands to be processed currently being traversed; If the target address range exceeds the first page table cache range, stop traversing and determine the first address in the target address range that is outside the first page table cache range as the target address.

3. The method according to claim 2, characterized in that, The step of determining the first address in the target address range that is outside the first page table cache range as the target address includes: If the starting address of the target address range is outside the first page table cache range, the starting address of the target address range shall be determined as the target address; If the starting address of the target address range is within the first page table cache range and the ending address of the target address range is outside the first page table cache range, then the ending address of the first page table cache range is determined as the target address.

4. The method according to claim 1, characterized in that, Before determining the target address outside the first page table cache range based on the address information of the at least one pending memory access command, the method further includes: The currently processed memory access command is split into multiple memory access requests, and the address information of the currently processed memory access command is updated according to the memory access requests. During the splitting process, the target address is determined based on the updated address information of the currently processed memory access command.

5. The method according to claim 4, characterized in that, Determining the target address based on the updated address information of the currently processed memory access command includes: Based on the updated address information of the currently processed memory access command, determine the remaining address range of the currently processed memory access command; If the remaining address range exceeds the first page table cache range, the first address in the remaining address range that is outside the first page table cache range is determined as the target address; If the remaining address range does not exceed the first page table cache range, the step of determining the target address located outside the first page table cache range based on the address information of the at least one pending memory access command is executed.

6. The method according to claim 4, characterized in that, The address information includes the starting address; The step of updating the address information of the currently processed memory access command according to the memory access request includes: During the splitting process, for each memory access request generated, the starting address of the currently processed memory access command is updated according to the access range indicated by the memory access request, so as to obtain the updated address information of the currently processed memory access command.

7. The method according to claim 4, characterized in that, The address information includes the starting address; After generating the prefetch request based on the target address, the process further includes: The updated first page table cache range is determined based on the second page table cache range to which the target address belongs; If the starting address of the updated currently processed memory access command reaches or exceeds the target address, the next target address located outside the updated first page table cache range is determined based on the address information of the updated currently processed memory access command and the address information of the at least one pending memory access command.

8. The method according to any one of claims 1 to 7, characterized in that, The prefetch request has a lower priority than the memory access request; wherein the memory access request is obtained by splitting the currently processed memory access command.

9. A page table prefetching device, characterized in that, The device includes: The command acquisition module is used to acquire at least one memory access command to be processed; The address determination module is used to determine a target address outside the first page table cache range based on the address information of the at least one memory access command to be processed; wherein the address information is used to indicate the address range to be accessed by the memory access command, and the first page table cache range is the current page table cache range of the memory management unit (MMU). The request generation module is used to generate a prefetch request based on the target address. The prefetch request is used to prefetch the page table data corresponding to the second page table cache range to which the target address belongs into the page table cache of the MMU.

10. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the method as claimed in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the method as described in any one of claims 1 to 8.

12. A chip, characterized in that, The chip includes programmable logic circuitry and / or program instructions, which, when the chip is running, are used to implement the method as described in any one of claims 1 to 8.

13. A computer program product, characterized in that, The computer program product includes a computer program that is loaded and executed by a processor to implement the method as described in any one of claims 1 to 8.

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