Method and apparatus for reading and writing processor page table, device, storage medium and program product

Abstract

The application relates to a read-write method, device and equipment of a processor page table, a storage medium and a program product. The method comprises the following steps: reading a first value of a target table item in an entry of a second processor page table; wherein the second processor page table is a mirror page table with the same number of entries and entry width as a first processor page table, the first processor page table is located in the device memory of a processor, and the second processor page table is located in the system memory of a host computer where the processor is located. The method can reduce the access delay of the processor page table.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, device, storage medium, and program product for reading and writing processor page tables. Background Technology

[0002] Currently, in sparse resource (or tiered resource) scenarios, applications can request a large range of graphics processing unit (GPU) virtual addresses (VAs), but only establish real physical mappings for a portion of the memory pages within the large range of GPU VAs.

[0003] In related technologies, a large number of unmapped pages are maintained by the host's kernel-mode driver (KMD) to manage page table states, such as invalid and unmapped states. KMD primarily relies on reading the actual GPU page tables to determine the page table state.

[0004] However, since the actual GPU page tables are located in the GPU's device memory, KMD typically reads the actual GPU page tables from the GPU's device memory through the Base Address Register (BAR), Memory-Mapped I / O (MMIO), Peripheral Component Interconnect Express (PCIe), on-chip interconnect, or device memory access channel, which results in high access latency. Summary of the Invention

[0005] Therefore, it is necessary to provide a method, apparatus, device, storage medium, and program product for reading and writing processor page tables that can reduce the access latency of processor page tables, addressing the aforementioned technical problems.

[0006] Firstly, this application provides a method for reading and writing processor page tables, applied to the kernel-mode driver (KMD) of the host machine where the processor resides, including:

[0007] Read the first value of the target entry from the entry in the second processor's page table;

[0008] The second processor page table is a mirror page table with the same number of entries and entry width as the first processor page table. The first processor page table is located in the device memory of the processor, and the second processor page table is located in the system memory of the host where the processor is located.

[0009] In one embodiment, the method further includes:

[0010] The second value of the target table entry is synchronously written into the entries of the first processor page table and the second processor page table through the target access entry, and the second value is used to update the first value.

[0011] In one embodiment, before reading the first value of the target entry from the entry of the second processor page table, the method further includes:

[0012] Create the first processor page table in the device memory of the processor, and create the second processor page table in the system memory of the host where the processor resides;

[0013] Initialize the first processor page table and the second processor page table to synchronize the initial values ​​of the entries in the first processor page table and the second processor page table;

[0014] Establish a binding relationship between the first processor page table and the second processor page table.

[0015] In one embodiment, reading the first value of the target entry from the entry of the second processor page table includes:

[0016] When a request is made to determine the current state of an entry in the processor page table, the first value of the target entry is read from an entry in the second processor page table.

[0017] In one embodiment, reading the first value of the target entry from the entry of the second processor page table includes:

[0018] The location information of the target entry is determined based on the processor's virtual address;

[0019] Based on the location information of the target entry, the first value of the target entry is read from the entry of the second processor page table.

[0020] In one embodiment, the method further includes:

[0021] Parse the first value of the target table entry to obtain the table entry status field of the target table entry;

[0022] The table status field of the target table entry is updated to obtain the second value of the target table entry;

[0023] The table entry status field includes one or more of the following: validity field, unmapping field, address field, and permission field.

[0024] In one embodiment, updating the table entry status field of the target table entry to obtain a second value for the target table entry includes:

[0025] In response to a sparse resource unmapping request, if the target entry is not in an unmapping state, the unmapping field in the target entry is set, and one or more of the validity field, the address field, and the permission field are adjusted to obtain a second value for the target entry.

[0026] The unmapping request is used to remove the mapping relationship between the entry in the processor page table and the physical video memory, and the unmapping status is the state in which the mapping relationship between the entry in the processor page table and the physical video memory is removed.

[0027] In one embodiment, after synchronously writing a second value of the target table entry into the entries of the first processor page table and the second processor page table through the target access entry, the method further includes:

[0028] If the first propagation condition is met, the unmapping state is propagated upwards level by level, starting from the target entry.

[0029] The first propagation condition includes the number of entries in the current level that are in the unmapping state being equal to the total number of entries in the current level.

[0030] In one embodiment, updating the table entry status field of the target table entry to obtain a second value for the target table entry includes:

[0031] In response to a remapping request for sparse resources, if the target entry is in a demapping state, the demapping field of the target entry is cleared, and one or more of the validity field, the address field, and the permission field are adjusted to obtain a second value for the target entry; wherein, the remapping request is used to re-establish the mapping relationship between the entry in the processor page table and the physical video memory.

[0032] In one embodiment, after synchronously writing a second value of the target table entry into the entries of the first processor page table and the second processor page table through the target access entry, the method further includes:

[0033] If the second propagation condition is met, starting from the target entry, the unmapping state is cleared level by level upwards.

[0034] The second propagation condition includes the number of entries in the current level that are in the unmapping state being equal to zero.

[0035] In one embodiment, after synchronously writing the second value of the target table entry into the entries of the first processor page table and the second processor page table through the target access entry, the method further includes:

[0036] Perform page table maintenance operations on the first processor page table and the second processor page table;

[0037] The page table maintenance operations include one or more of the following: address translation cache refresh operations, memory management maintenance operations, and memory barrier operations;

[0038] The address translation cache refresh operation is used to cache invalid address translations in the processor after updating to the second value of the target table entry; the memory management and maintenance operation is used to maintain the address translations in the processor consistent with the target table entry; and the memory barrier operation is used to synchronize the page table write order of the first processor page table and the second processor page table with the processor.

[0039] In one embodiment, the processor includes a graphics processing unit (GPU).

[0040] Secondly, this application also provides a processor page table read / write device, applied to the KMD of the host where the processor resides, comprising:

[0041] The read module is used to read the first value of the target entry from the entries of the second processor's page table;

[0042] The second processor page table is a mirror page table with the same number of entries and entry width as the first processor page table. The first processor page table is located in the device memory of the processor, and the second processor page table is located in the system memory of the host where the processor is located.

[0043] In one embodiment, the processor page table read / write device further includes:

[0044] The write module is used to synchronously write a second value of a target table entry into the entries of the first processor page table and the second processor page table through the target access entry, and the second value is used to update the first value.

[0045] In one embodiment, the processor page table read / write device further includes:

[0046] A creation module is used to create the first processor page table in the device memory of the processor and the second processor page table in the system memory of the host where the processor is located; initialize the first processor page table and the second processor page table to synchronize the initial values ​​of the entries in the first processor page table and the second processor page table; and establish a binding relationship between the first processor page table and the second processor page table.

[0047] In one embodiment, the reading module is specifically configured to read a first value of the target entry from an entry in the second processor page table when a request is made to determine the current entry status of the processor page table.

[0048] In one embodiment, the reading module is specifically configured to determine the location information of the target entry based on the virtual address of the processor; and read the first value of the target entry from the entry of the second processor page table based on the location information of the target entry.

[0049] In one embodiment, the processor page table read / write device further includes:

[0050] The update module is used to parse the first value of the target table entry to obtain the table entry status field of the target table entry; and update the table entry status field of the target table entry to obtain the second value of the target table entry.

[0051] The table entry status field includes one or more of the following: validity field, unmapping field, address field, and permission field.

[0052] In one embodiment, the update module is specifically used to respond to a demapping request for sparse resources, and when the target entry is not in a demapping state, to set the demapping field in the target entry, and to adjust one or more of the validity field, the address field, and the permission field to obtain a second value of the target entry;

[0053] The unmapping request is used to remove the mapping relationship between the entry in the processor page table and the physical video memory, and the unmapping status is the state in which the mapping relationship between the entry in the processor page table and the physical video memory is removed.

[0054] In one embodiment, the processor page table read / write device further includes:

[0055] The state propagation module is used to propagate the unmapping state upwards from the target entry, level by level, when the first propagation condition is met.

[0056] The first propagation condition includes the number of entries in the current level that are in the unmapping state being equal to the total number of entries in the current level.

[0057] In one embodiment, the update module is specifically used to respond to a remapping request for sparse resources, and when the target entry is in a demapping state, to clear the demapping field of the target entry, and adjust one or more of the validity field, the address field, and the permission field to obtain a second value of the target entry;

[0058] The remapping request is used to re-establish the mapping relationship between entries in the processor page table and physical video memory.

[0059] In one embodiment, the state propagation module is further configured to, when the second propagation condition is met, clear the unmapping state step by step upward from the target entry;

[0060] The second propagation condition includes the number of entries in the current level that are in the unmapping state being equal to zero.

[0061] In one embodiment, the processor page table read / write device further includes:

[0062] The maintenance module is used to perform page table maintenance operations on the first processor page table and the second processor page table;

[0063] The page table maintenance operations include one or more of the following: address translation cache refresh operations, memory management maintenance operations, and memory barrier operations;

[0064] The address translation cache refresh operation is used to cache invalid address translations in the processor after updating to the second value of the target table entry; the memory management and maintenance operation is used to maintain the address translations in the processor consistent with the target table entry; and the memory barrier operation is used to synchronize the page table write order of the first processor page table and the second processor page table with the processor.

[0065] In one embodiment, the processor includes a graphics processing unit (GPU).

[0066] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the processor page table read / write method described in the first aspect.

[0067] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the processor page table read / write method described in the first aspect.

[0068] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the processor page table reading and writing method described in the first aspect.

[0069] The aforementioned method, apparatus, device, storage medium, and program product for reading and writing processor page tables read the first value of a target entry from the entries of a second processor page table. The second processor page table is a mirror image of the first processor page table, with the same number and width of entries. The first processor page table is located in the processor's device memory, while the second processor page table is located in the system memory of the host machine. Because the KMD reads the entries of the processor page table from system memory, the read path is significantly shortened compared to the related art where the KMD reads entries from the processor page table in device memory, thereby reducing the access latency of the processor page table. Attached Figure Description

[0070] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0071] Figure 1 One of the flowcharts illustrating a method for reading and writing a processor page table provided in an embodiment of this application;

[0072] Figure 2 A schematic diagram illustrating the principle of a processor page table read / write method provided in an embodiment of this application;

[0073] Figure 3 A second schematic flowchart illustrating a method for reading and writing a processor page table, provided as an embodiment of this application;

[0074] Figure 4 A third flowchart illustrating a method for reading and writing a processor page table, provided as an embodiment of this application;

[0075] Figure 5 A fourth flowchart illustrating a method for reading and writing a processor page table, provided as an embodiment of this application;

[0076] Figure 6 Fifth flowchart illustrating a method for reading and writing a processor page table provided in this application embodiment;

[0077] Figure 7 A flowchart illustrating a method for reading and writing a processor page table, provided as an embodiment of this application, is shown in Figure 6.

[0078] Figure 8 The seventh flowchart illustrates a method for reading and writing a processor page table, as provided in an embodiment of this application.

[0079] Figure 9 A structural block diagram of a processor page table read / write device provided in an embodiment of this application;

[0080] Figure 10 This is an internal structural diagram of a computer device provided in an embodiment of this application. Detailed Implementation

[0081] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0082] The relevant technologies will be explained below.

[0083] Currently, GPU drivers typically employ multi-level GPU page tables to translate GPU Virtual Addresses (VAs) into GPU Physical Addresses (PAs), Input / Output Virtual Addresses (IOVAs), or IoT Fabric PAs. The actual GPU page tables usually reside in device memory and are directly read by the GPU Memory Management Unit (MMU) during page table walks. Device memory can include, for example, Video Random-Access Memory (VRAM), device memory, and memory mapped by the Base Address Register (BAR).

[0084] For example, the process of KMD managing the GPU virtual address space includes: KMD calculates the page table level and entry index based on the target GPU VA. KMD reads entries from the real GPU page table through the Central Processing Unit (CPU) accessible mapping, including old values ​​of Page Table Entry (PTE), Page Directory Entry (PDE), or higher-level Page Directory Pointer (PML4) Entry (PxE). KMD parses the entry status fields, including valid bit, unmap bit, address field, protection bit, cache attribute bit, and other status fields. Based on the parsed entry status fields, and mapping requests, unmap requests, sparse update requests, or resource release requests, KMD determines whether to retain, clear, or update the corresponding status fields, thereby generating new entries. KMD writes the new entries back to the real GPU page table. When necessary, perform Translation Lookaside Buffer Flush (TLB flush), MMU maintenance, or related synchronization operations; the GPU MMU continues to use the actual GPU page tables to complete address translation.

[0085] In sparse resource scenarios, applications can request a large range of GPU VAs, but only establish actual physical mappings for a portion of the pages within those GPU VAs. The host's KMD maintains the page table state for a large number of unmapped pages, including invalid and unmapped states. If the hardware supports unmapped fields, the KMD may also propagate the unmapped state to the higher-level PxE when all lower-level entries in the current page table are unmapped, allowing the GPU MMU to prematurely terminate page table traversal at a higher level.

[0086] The page table read / write methods in related technologies have the following drawbacks:

[0087] Firstly, KMD primarily relies on reading the actual GPU page tables to determine their status. Since the actual GPU page tables reside in the GPU's device memory, KMD typically reads them through device access paths, including BAR, MMIO, PCIe, on-chip interconnect, or device memory access channels. This results in high access latency, weak caching benefits, and can easily cause blockages in the KMD page table maintenance path.

[0088] Secondly, mapping, unmapping, sparse resource updates, flag checks, and upper-level unmapping propagation are all typical read-modify-write operations. KMD typically needs to read the old value before each PxE modification. If the old value comes from the actual GPU page table, batch updates will generate a large number of device memory reads. In other words, page table read-modify-write operations are amplified by device memory reads.

[0089] Thirdly, sparse resources (or tiered resources) and sparse textures typically contain a large number of unmapped pages. Frequent small-granularity mapping or unmapping repeatedly triggers old PTE value readings, unmapped field (unmap bit) checks, and upper-level state updates, further amplifying the device-side read overhead.

[0090] Fourthly, when the number of unmapped entries at the current page table level reaches the total number of entries, the unmapped state of the parent PxE needs to be set; when an entry is remapped, the unmapped state of the parent needs to be cleared. This process requires reliable reading of the page table states at the current and parent levels, which may result in frequent access to the actual GPU page table.

[0091] Fifthly, while the hardware's unmapping field can help the GPU MMU terminate page table traversal earlier, it cannot reduce the cost for the KMD to read the actual GPU page table when maintaining this unmapping field. Hardware optimization addresses the GPU access path but does not resolve the high latency issue of the CPU maintenance path.

[0092] To address the aforementioned issues, embodiments of this application provide a method, apparatus, device, storage medium, and program product for reading and writing processor page tables. The method involves reading a first value from an entry in a second processor page table. The second processor page table is a mirror image of the first processor page table, with the same number and width of entries. The first processor page table is located in the processor's device memory, while the second processor page table is located in the system memory of the host machine. Because the KMD reads entries from the processor page table in system memory, the read path is significantly shortened compared to related technologies where the KMD reads entries from the processor page table in device memory, thereby reducing the access latency of the processor page table.

[0093] The processor page table read / write method provided in this application embodiment can be applied to the KMD of the host where the processor is located. The device where the processor is located can be any device that includes a host and a processor. The processor can be, for example, a GPU, a data processing unit (DPU), a neural network processing unit (NPU), etc.

[0094] The processor page table read / write method provided in this application embodiment can be applied to scenarios such as sparse resources, sparse textures, sparse caches, virtual memory management, GPU page table dumping, virtual graphics processor (vGPU) monitoring, and video display surface switching.

[0095] In one exemplary embodiment, such as Figure 1 As shown, a method for reading and writing processor page tables is provided. Taking the application of this method to the KMD of the host machine where the processor resides as an example, the method includes the following steps 101. Wherein:

[0096] S101. Read the first value of the target entry from the entry of the second processor page table.

[0097] The processor mentioned above may include a GPU, a data processing unit (DPU), etc. If the processor is a GPU, then the first processor page table is the first GPU page table. The target entry can be any entry in the second processor page table, such as PTE, PDE, PxE, etc. The first value can be the value of the target entry before the update, for example, the old value of PTE.

[0098] In some embodiments, the second processor page table is a mirror page table with the same number of entries and entry width as the first processor page table. The first processor page table is located in the device memory of the processor, and the second processor page table is located in the system memory of the host machine where the processor resides. That is, the first processor page table is the actual processor page table on the processor side, and the second processor page table is a mirror processor page table on the host side.

[0099] It should be noted that the second processor page table involved in this application embodiment is not the shadow page table in a virtualization scenario. It should be understood that the shadow page table is maintained by the hypervisor and used to synthesize the translation relationship between guest virtual addresses, guest physical addresses, and host physical addresses, enabling the hardware to perform virtual machine address translation. The second processor page table involved in this application embodiment is a mirror page table (i.e., a copy) of the first processor page table. Its purpose is not to replace the hardware page table, nor does it directly participate in GPU MMU address translation, but rather to accelerate KMD's reading of table entries and maintenance of sparse mapping states.

[0100] In some embodiments, when requesting to determine the current entry status of a processor page table, the KMD can read the first value of the target entry from an entry in the second processor page table, instead of reading the first value of the target entry from an entry in the first processor page table. That is, the rule for reading the processor page table is that when the KMD needs to determine the current entry status, it only reads entries from the second processor page table on the host's system memory side, thereby reducing access latency.

[0101] For example, Figure 2 A schematic diagram illustrating the principle of a processor page table read / write method provided in this application embodiment is shown below. Figure 2 As shown, when KMD reads the PxE state (i.e., the first value of the target entry), it accesses the page table mirror (i.e., the second processor entry) through the unified read entry, without accessing the real GPU page table (i.e., the first processor entry).

[0102] It should be understood that the embodiments of this application do not limit how the first value of the target entry is read from the entries of the second processor page table. In some embodiments, the KMD can first determine the location information of the target entry based on the processor's virtual address. Then, based on the location information of the target entry, the first value of the target entry is read from the entries of the second processor page table.

[0103] For example, the virtual address includes the GPU VA, and the location information includes the entry level and entry identifier of the target entry. The KMD can determine the entry level and entry identifier of the target entry through the GPU VA, and thus can quickly locate the target entry in the first processor page table based on the entry level and entry identifier, and then read the first value of the target entry in the entry of the second processor page table based on the location located by the entry level and entry identifier.

[0104] For example, the target entry can be an entry state field (i.e., PxE). Accordingly, KMD can locate the entry level and entry identifier of the target entry based on the GPU VA, and then read the old value of PxE (i.e., the first value of PxE) from the second processor page table in system memory based on the entry level and entry identifier of the target entry. Subsequently, KMD performs subsequent processing based on the old value of PxE, including mapping, unmapping, remapping, or state propagation.

[0105] It should be understood that the embodiments of this application do not limit the table entry status field. In some embodiments, the table entry status field may include one or more of the following: valid field, unmap field, address field, and permission field. In other embodiments, the table entry status field may include one or more of the following: valid field, unmap field, address field, permission field, compression field, protection field, and cache attribute field.

[0106] In some embodiments, the processor's memory management unit can read the value of a target entry from an entry in the first processor page table, and then perform hardware address translation based on the read value of the target entry, so as to achieve the same result as the GPU MMU's hardware address translation path, and the GPU MMU still reads the first processor page table in the device memory.

[0107] The processor page table read / write method provided in this application reads the first value of a target entry from the entries of a second processor page table. The second processor page table is a mirror page table with the same number and width of entries as the first processor page table. The first processor page table is located in the device memory of the processor, and the second processor page table is located in the system memory of the host machine where the processor resides. Because the KMD reads the entries of the processor page table from system memory, compared to the KMD reading entries from the processor page table in device memory in related technologies, the read path is greatly shortened, thereby reducing the access latency of the processor page table.

[0108] The following describes how to create the first processor page table and the second processor page table. In an exemplary embodiment, such as... Figure 3 As shown, a method for reading and writing processor page tables is provided. Taking the application of this method to the KMD of the host machine where the processor resides as an example, the method includes the following steps 301 to 304. Wherein:

[0109] S301. Create a first processor page table in the processor's device memory and create a second processor page table in the system memory of the host where the processor is located.

[0110] The processor mentioned above may include GPU, data processor (DPU), etc. When the processor is a GPU, the first processor page table is the first GPU page table, and the second processor page table is the second GPU page table.

[0111] In some embodiments, the second processor page table is a mirror page table with the same number of entries and entry width as the first processor page table. That is, the first processor page table is the actual processor page table on the processor side, and the second processor page table is a mirror processor page table on the host side, with the entry data and entry width of the first and second processor page tables being exactly the same.

[0112] In some embodiments, KMD may create a first processor page table in the device memory of the processor through memory allocation, and create a second processor table that mirrors the first processor page table in the system memory of the host where the processor resides.

[0113] For example, memory allocation methods may include kernel-mode memory allocation functions (e.g., kmalloc, vmalloc), page pools, operating system (OS) kernel memory allocators, etc., and this application embodiment does not limit these methods.

[0114] S302. Initialize the first processor page table and the second processor page table to synchronize the initial values ​​of the entries in the first processor page table and the second processor page table.

[0115] In this step, after creating the first processor page table and the second processor page table, KMD can also initialize the first processor page table and the second processor page table to synchronize the initial values ​​of the entries in the first processor page table and the second processor page table.

[0116] For example, the above-mentioned initialization of the first processor page table and the second processor page table can be achieved by setting all entries in the second processor page table of the first processor page table to default values, so that the second processor page table of the first processor page table has the same initial value.

[0117] S303. Establish the binding relationship between the first processor page table and the second processor page table.

[0118] In this step, after creating the first processor page table and the second processor page table, KMD can also establish a binding relationship between the first processor page table and the second processor page table.

[0119] Among them, the first processor page table and the second processor page table, which have a binding relationship, remain synchronized throughout the creation, initialization, writing, and destruction processes.

[0120] For example, KMD can establish a binding relationship between the first processor page table and the second processor page table by recording the address of the first processor page table and the address of the second processor page table in the corresponding level's page table metadata field table, thereby binding the first processor page table and the second processor page table that are subsequently written synchronously during the read and write process.

[0121] For example, in addition to writing the addresses of the first processor page table and the second processor page table, the page table metadata field table described above can also record various other page table information of the first processor page table and the second processor page table as fields in the page table metadata field table.

[0122] For example, Table 1 is a page table metadata field table provided in an embodiment of this application. As shown in Table 1, the page table metadata field table may also record the width of a single table entry, the total number of table entries in the current level, the pointer to the parent page table level, the index of the parent table entry corresponding to the current level, the number of table entries in the current level that are in the unmapping state, and the current level status flag.

[0123] Table 1

[0124]

[0125] For example, the host-side KMD can first create a process GPU VA space or a resource GPU VA range, and then allocate actual GPU page tables in the processor's device memory for the root level or lower-level page table, thus creating a first processor page table in the processor's device memory. Secondly, KMD can allocate a system memory page table image of the same size in the host's system memory for this page table level, thus creating a second processor page table in the host's system memory. Thirdly, KMD initializes the first and second processor page tables to the same default values ​​and establishes a binding relationship between them. Finally, KMD can record the page table information of the first and second processor page tables in the corresponding level's page table metadata field table and attach the page table metadata field table of that level to the page table management structure.

[0126] S304. Read the first value of the target entry from the entry of the second processor page table.

[0127] The synchronous writing process of the first processor page table and the second processor page table is described below. In an exemplary embodiment, such as... Figure 4 As shown, a method for reading and writing processor page tables is provided. Taking the application of this method to the KMD of the host machine where the processor resides as an example, the method includes the following steps 401 to 402. Wherein:

[0128] S401. Read the first value of the target entry from the entry of the second processor page table.

[0129] The second processor page table is a mirror page table with the same number of entries and entry width as the first processor page table. The first processor page table is located in the device memory of the processor, and the second processor page table is located in the system memory of the host machine where the processor is located.

[0130] S402. The second value of the target table entry is synchronously written into the entries of the first processor page table and the second processor page table through the target access entry.

[0131] The second value is used to update the first value. That is, the first value is the old value of the target entry, and the second value is the new value of the second entry.

[0132] For example, continue to refer to Figure 2 When KMD writes a new PxE value (i.e., the second value of the target table entry), it can simultaneously write to both the page table mirror (i.e., the second processor table entry) and the actual GPU page table (i.e., the first processor table entry) through a unified target access entry, thereby implementing a dual-write mechanism for the processor page table. It should be noted that KMD can guarantee this dual-write mechanism through unified functions, macro encapsulation, page table operation tables, compile-time checks, or runtime assertions.

[0133] It should be understood that reading the first value of the target entry and writing the second value of the target entry can be a read-modify-write process targeting the target entry in the processor page table. This application embodiment does not restrict how the second value of the target entry is obtained during the read-modify-write process. In some embodiments, after the KMD reads the first value of the target entry from the entry in the second processor page table, it can parse the first value of the target entry to obtain the entry status field of the target entry. Subsequently, the KMD updates the entry status field of the target entry to obtain the second value of the target entry. Finally, the KMD synchronously writes the second value of the target entry into the entries of the first and second processor page tables through the target access entry.

[0134] The table entry status field includes one or more of the following: validity field, unmapping field, address field, and permission field.

[0135] For example, the KMD reads the old value of PxE (i.e., the first value of the target entry) from the entry in the second processor page table, then parses the old value of PxE and updates the parsed entry status field to obtain the new value of PxE (i.e., the second value of the target entry). Subsequently, the KMD can write the new value of PxE to both the second and first processor page tables. Finally, the KMD can read the new value of PxE from the second processor page table, and the GPU MMU can read the new value of PxE from the first processor page table.

[0136] In this embodiment of the application, KMD synchronously writes the second value of the target table entry into the entries of the first processor page table and the second processor page table through the target access entry, thereby reducing CPU read overhead while maintaining the correctness of the contents of the first processor page table and the second processor page table.

[0137] In some embodiments, after synchronously writing the second value of the target entry into the entries of the first processor page table and the second processor page table through the target access entry, the KMD can also perform page table maintenance operations on the first processor page table and the second processor page table. The page table maintenance operation ensures that after the second value of the target entry is written into the first processor page table, the GPU can operate according to the new entry state corresponding to the target entry.

[0138] For example, page table maintenance operations include one or more of the following: address translation cache flush (TLBflush); memory management maintenance (MMU maintenance); and memory barrier (Fence or memorybarrier).

[0139] The address translation cache refresh operation is used to cache invalid address translations in the processor after updating to the second value of the target table entry; the memory management maintenance operation is used to maintain the consistency between the address translations in the processor and the target table entry; the memory barrier operation is used to synchronize the page table write order of the first processor page table and the second processor page table with the processor to ensure the correct visibility of page table writes and prevent the GPU or CPU from obtaining out-of-order states.

[0140] In some embodiments, during the process of KMD synchronously writing the second value of the target table entry into the entries of the first processor page table and the second processor page table, write rules, order rules, prohibition rules and maintenance rules may be followed.

[0141] The writing rules stipulate that after KMD generates a new target entry value (i.e., the second value), it must simultaneously write the second value into the entries of both the first and second processor page tables to ensure synchronization. The ordering rule allows writing to the second processor page table first, followed by the first, so that KMD immediately sees the new value when reading the entry. Alternatively, a memory barrier operation can be added based on consistency requirements. The prohibition rule prohibits bypassing the unified target access entry to directly modify the first processor page table, thereby avoiding potential inconsistencies between the second and first processor page tables. The maintenance rules require performing one or more of the following operations according to preset requirements: address translation cache refresh operation, memory management maintenance operation, and memory barrier operation.

[0142] It should be understood that the processor page table read / write method provided in the embodiments of this application can be applied to the process of unmapping sparse resources.

[0143] In some embodiments, updating the target entry's status field to obtain a second value for the target entry includes: in response to a sparse resource unmapping request, if the target entry is not in an unmapping state, setting the unmapping field in the target entry and adjusting one or more of the validity field, address field, and permission field to obtain the second value for the target entry. Subsequently, the second value of the target entry is synchronously written into the entries of the first processor page table and the second processor page table through the target access entry. If the first propagation condition is met, the unmapping state is propagated upwards level by level, starting from the target entry.

[0144] The demapping request is used to remove the mapping relationship between entries in the processor page table and physical video memory. The demapping state is the state in which the mapping relationship between entries in the processor page table and physical video memory is removed. The first propagation condition includes that the number of entries in the current level that are in the demapping state is equal to the total number of entries in the current level.

[0145] For example, KMD first receives a demapping request for a sparse resource and locates the target entry, which can be a leaf PTE. Next, KMD reads the first value (i.e., the old PTE value) of the target entry from the second processor page table. If the target entry is already in a demapping state, the process ends, and the number of entries in the current level that are in a demapping state is not repeatedly increased. If the target entry is not in a demapping state, the demapping field in the target entry is set, and one or more of the validity field, address field, and permission field are adjusted to obtain the second value (i.e., the new PTE value) of the target entry, and the number of entries in the current level that are in a demapping state is incremented by one. Finally, KMD synchronously writes the second value of the target entry into the entries of the first and second processor page tables from the unified target access entry.

[0146] For example, after synchronously writing the second value of the target entry into the entries of the first processor page table and the second processor page table, if the first propagation condition is met (i.e., the number of entries in the current level that are in the unmapping state is equal to the total number of entries in the current level), the unmapping state can be propagated upwards, setting the parent entry of the target entry to the unmapping state, and synchronously writing the updated entry value of the parent entry of the target entry into the first processor page table and the second processor page table. If the parent entry of the target entry also meets the first propagation condition, the unmapping state continues to propagate to a higher level.

[0147] For example, in the process of unmapping sparse resources, adjusting one or more of the validity field, address field, and permission field may include performing one or more of the following operations: unsetting the validity field, unsetting the permission field, and clearing the physical memory address information in the address field.

[0148] It should be understood that the processor page table read / write method provided in the embodiments of this application can be applied to the process of sparse resource remapping.

[0149] In some embodiments, updating the target entry's status field to obtain a second value for the target entry includes: in response to a sparse resource remapping request, if the target entry is in an unmapping state, clearing the unmapping field of the target entry and adjusting one or more of the validity field, address field, and permission field to obtain the second value for the target entry. Subsequently, the second value of the target entry is synchronously written into the entries of the first processor page table and the second processor page table through the target access entry. If the second propagation condition is met, the unmapping state is cleared level by level upwards, starting from the target entry.

[0150] The remapping request is used to re-establish the mapping relationship between entries in the processor page table and physical video memory. The demapping state is the state in which the entries in the processor page table and physical video memory are de-mapped. The second propagation condition includes that the number of entries in the current level that are in the demapping state is equal to zero.

[0151] For example, KMD first receives a remapping request for sparse resources and locates the target entry, which can be a leaf PTE. Next, KMD reads the first value (i.e., the old PTE value) of the target entry from the second processor page table. If the target entry is not in an unmapping state, the process ends, and the number of unmapping entries in the current level is not repeatedly reduced. If the target entry is in an unmapping state, the unmapping field in the target entry is cleared, and one or more of the validity field, address field, and permission field are adjusted to obtain the second value (i.e., the new PTE value) of the target entry, and the number of unmapping entries in the current level is incremented by one. Finally, KMD synchronously writes the second value of the target entry into the entries of the first and second processor page tables from the unified target access entry.

[0152] For example, after synchronously writing the second value of the target entry into the entries of the first processor page table and the second processor page table, if the second propagation condition is met (i.e., the number of entries in the unmapping state in the current level is zero), the unmapping state can be cleared upwards, the unmapping state of the target entry's parent entry can be cleared, and the updated entry value of the target entry's parent entry can be synchronously written into the first processor page table and the second processor page table. If the target entry's parent entry also meets the second propagation condition, the unmapping state can be cleared upwards to a higher level.

[0153] For example, in the process of sparse resource remapping, adjusting one or more of the validity field, address field, and permission field may include performing one or more of the following operations: setting the validity field, setting the permission field, and writing the address information of the remapped physical video memory to the address field.

[0154] This application provides a GPU page table mirror read / write mechanism for sparse resource mapping without changing the GPU MMU's use of real GPU page tables for hardware address translation. This mechanism enables the KMD to avoid accessing the first processor page table on the slow processor side when reading page table entry states, and ensures that the second processor page table on the system memory side remains consistent with the first processor page table when writing page table entries. This reduces the CPU overhead of maintaining the demapping field and propagating the state upwards during the coefficient resource mapping and demapping process.

[0155] The processor page table read / write method provided in this application creates a first processor page table in the processor's device memory and a second processor page table in the host's system memory. The first processor page table is accessed by the processor's memory management unit (MMU), and the second processor page table is a mirrored page table with the same number and width of entries as the first processor page table. A first value of a target entry is read from the entries in the second processor page table. A second value of the target entry is simultaneously written to the entries in both the first and second processor page tables through a target access entry. Because the first processor page table is created in the processor's device memory while a mirrored second processor page table is created in the host's system memory, the KMD (Knowledge Management Unit) can simultaneously write entries of the processor page table in both system memory and device memory, and can also read entries of the processor page table from system memory. Compared to reading entries from the processor page table in device memory, the read path is greatly shortened, thereby reducing the access latency of the processor page table.

[0156] In one exemplary embodiment, such as Figure 5 As shown, a method for reading and writing processor page tables is provided to illustrate how to accelerate the reading and writing of target entries. This method for reading and writing processor page tables includes steps S501 to S507:

[0157] S501 and KMD determine the location information of the target table entry based on the processor's virtual address.

[0158] S502 and KMD read the first value of the target entry from the entry in the second processor page table based on the location information of the target entry.

[0159] S503 and KMD parse the first value of the target table entry to obtain the table entry status field of the target table entry.

[0160] S504 and KMD update the status field of the target table entry to obtain the second value of the target table entry.

[0161] The table entry status field includes one or more of the following: validity field, unmapping field, address field, and permission field.

[0162] S505 and KMD synchronously write the second value of the target table entry into the entries of the first processor page table and the second processor page table through the target access entry.

[0163] The S506 GPU MMU reads the value of the target entry from the first processor page table entry.

[0164] The S507 and GPU MMU perform hardware address translation based on the values ​​of the target entries read.

[0165] The processor page table read / write method provided in this application avoids the KMD reading the value of the target entry from the first processor page table in the device memory, while the GPU MMU still reads the value of the target entry from the first processor page table in the device memory. During writing, two copies are written to the first processor page table and the second processor page table simultaneously, thereby reducing CPU read overhead while maintaining the correctness of the contents of the first processor page table and the second processor page table.

[0166] In one exemplary embodiment, such as Figure 6 As shown, a method for reading and writing processor page tables is provided, illustrating how to propagate the batch unmapping state of invalid page tables with sparse resources. This method for reading and writing processor page tables includes steps S601 to S608:

[0167] S601, Receive the unmapping request for sparse resources.

[0168] The unmapping request is used to remove the mapping relationship between entries in the processor page table and physical video memory.

[0169] S602. Traverse the range of the target GPU VA at the page table granularity to determine the target table entries.

[0170] S603. Read the first value of the target entry from the entry of the second processor page table.

[0171] S604. Determine whether the target entry is in a demapping state. The demapping state is the state in which the entry in the processor page table is demapping from the physical video memory.

[0172] If yes, then execute S602; otherwise, execute S605.

[0173] S605. Set the unmapping field in the target table entry, and adjust one or more of the validity field, address field, and permission field to obtain the second value of the target table entry.

[0174] S606. Increase the number of entries in the current level that are in the unmapping state by one.

[0175] S607. The second value of the target table entry is synchronously written into the entries of the first processor page table and the second processor page table through the target access entry.

[0176] S608. If the first propagation condition is met, start from the target entry and propagate the demapping state upwards level by level.

[0177] The first propagation condition includes the number of entries in the current level that are in the unmapping state being equal to the total number of entries in the current level.

[0178] For example, if the number of entries in the current level that are in the unmapping state equals the total number of entries in the current level, then the first propagation condition is met. In this case, the parent entry of the target entry can be set to the unmapping state. If the level of the parent entry of the target entry also meets the first propagation condition, then the unmapping state continues to propagate to the next higher level, until the highest level.

[0179] In this embodiment, during the batch unmapping process, the old values ​​of the entries are read from the second processor page table in system memory, thereby accelerating the maintenance speed of the unmapping state and the propagation speed of the unmapping state to the upper level. Furthermore, the GPU MMU can terminate page table traversal early at the upper-level unmapping field, thus reducing the number of times device memory values ​​are retrieved during the batch unmapping of sparse resources. In addition, it also improves the utilization rate of CPU cache threads and prefetching mechanisms for continuous entry scanning.

[0180] In one exemplary embodiment, such as Figure 7 As shown, a method for reading and writing processor page tables is provided to illustrate the process of batch remapping of sparse resources. This method for reading and writing processor page tables includes steps S701 to S708:

[0181] S701, Receive remapping requests for sparse resources.

[0182] Among them, the remapping request is used to re-establish the mapping relationship between the entries in the processor page table and the physical video memory.

[0183] S702. Traverse the range of the target GPU VA at the page table granularity to determine the target table entries.

[0184] S703: Read the first value of the target entry from the entry in the second processor's page table.

[0185] S704. If it is determined whether the target entry is in a demapping state, the demapping state is the state in which the entry in the processor page table is demapping from the physical video memory.

[0186] If yes, then execute S705; otherwise, execute S702.

[0187] S705. Clear the unmapping field of the target table entry, and adjust one or more of the validity field, address field, and permission field to obtain the second value of the target table entry.

[0188] S706. Decrease the number of entries in the current level that are in the unmapping state by one.

[0189] S707. The second value of the target table entry is synchronously written into the entries of the first processor page table and the second processor page table through the target access entry.

[0190] S708. If the second propagation condition is met, starting from the target entry, clear the unmapping state level by level upwards.

[0191] The second propagation condition includes the number of entries in the current level that are in the unmapping state being equal to zero.

[0192] For example, if the number of entries in the current level that are in an unmapping state is zero, then the second propagation condition is met, and the unmapping state of the target entry's parent entry can be cleared. If the level of the target entry's parent entry also meets the second propagation condition, then the unmapping state is cleared up to the next higher level, until the highest level.

[0193] In this embodiment, during the batch remapping process, the old values ​​of the entries are read from the second processor page table in system memory, thereby accelerating the maintenance speed of the remapping state and the recovery speed of the mapping state to the upper level. Furthermore, the GPU MMU can terminate the page table traversal early at the upper-level unmapping field, thus reducing the number of times the device memory is accessed during the batch remapping of sparse resources. In addition, it also improves the utilization rate of CPU cache threads and prefetching mechanisms for continuous entry scanning.

[0194] In one exemplary embodiment, such as Figure 8 As shown, a method for reading and writing a processor page table is provided to illustrate how the processor page table is updated during video playback or graphics switching. This method for reading and writing a processor page table includes steps S801 to S804:

[0195] S801: Perform batch page table updates on the GPU VA corresponding to the surface to be switched.

[0196] S802: Read the first value of the target entry to be updated from the entry of the second processor page table.

[0197] S803. The updated second value of the target entry is synchronously written into the entries of the first processor page table and the second processor page table through the target access entry.

[0198] S804, Perform page table maintenance operations on the first processor page table and the second processor page table.

[0199] Page table maintenance operations include one or more of the following: address translation cache refresh operation; memory management maintenance operation; memory barrier operation; wherein, the address translation cache refresh operation is used to cache invalid address translations in the processor after they have been updated to the second value of the target entry; the memory management maintenance operation is used to maintain the address translations in the processor consistent with the target entry; and the memory barrier operation is used to synchronize the page table write order of the first processor page table and the second processor page table with the processor.

[0200] The processor page table read / write method provided in this application embodiment can reduce the CPU's wait time to read device memory and reduce KMD update latency during video playback or graphics switching, while maintaining the GPU MMU address translation behavior unchanged.

[0201] The processor page table read / write method provided in this application reads the first value of a target entry from the entries of a second processor page table. The second processor page table is a mirror page table with the same number and width of entries as the first processor page table. The first processor page table is located in the device memory of the processor, and the second processor page table is located in the system memory of the host machine where the processor resides. Because the KMD reads the entries of the processor page table from system memory, compared to the KMD reading entries from the processor page table in device memory in related technologies, the read path is greatly shortened, thereby reducing the access latency of the processor page table.

[0202] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0203] Based on the same inventive concept, this application also provides a processor page table read / write apparatus for implementing the processor page table read / write method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more processor page table read / write apparatus embodiments provided below can be found in the limitations of the processor page table read / write method described above, and will not be repeated here.

[0204] In one exemplary embodiment, such as Figure 9As shown, a processor page table read / write device 900 is provided, applied to the KMD of the host computer where the processor resides, including:

[0205] The reading module 901 is used to read the first value of the target table entry from the entries of the second processor page table;

[0206] The second processor page table is a mirror page table with the same number of entries and entry width as the first processor page table. The first processor page table is located in the device memory of the processor, and the second processor page table is located in the system memory of the host machine where the processor is located.

[0207] In one embodiment, the processor page table read / write device 900 further includes:

[0208] The write module 902 is used to synchronously write a second value of the target table entry into the entries of the first processor page table and the second processor page table through the target access entry. The second value is used to update the first value.

[0209] In one embodiment, the processor page table read / write device 900 further includes:

[0210] Module 903 is used to create a first processor page table in the processor's device memory and a second processor page table in the system memory of the host where the processor resides; initialize the first and second processor page tables to synchronize the initial values ​​of the entries in the first and second processor page tables; and establish the binding relationship between the first and second processor page tables.

[0211] In one embodiment, the reading module 901 is specifically configured to read a first value of a target entry from an entry in a second processor page table when a request is made to determine the current entry status of the processor page table.

[0212] In one embodiment, the reading module 901 is specifically used to determine the location information of the target entry based on the processor's virtual address; and to read the first value of the target entry from the entry of the second processor's page table based on the location information of the target entry.

[0213] In one embodiment, the processor page table read / write device 900 further includes:

[0214] The update module 904 is used to parse the first value of the target table entry to obtain the table entry status field of the target table entry; and to update the table entry status field of the target table entry to obtain the second value of the target table entry.

[0215] The table entry status field includes one or more of the following: validity field, unmapping field, address field, and permission field.

[0216] In one embodiment, the update module 904 is specifically used to respond to the unmapping request of sparse resources, and when the target entry is not in the unmapping state, set the unmapping field in the target entry, and adjust one or more of the validity field, address field, and permission field to obtain the second value of the target entry.

[0217] The unmapping request is used to remove the mapping relationship between the entry in the processor page table and the physical video memory. The unmapping status is the state in which the mapping relationship between the entry in the processor page table and the physical video memory is removed.

[0218] In one embodiment, the processor page table read / write device 900 further includes:

[0219] The state propagation module 905 is used to propagate the unmapping state upwards from the target entry, level by level, when the first propagation condition is met.

[0220] The first propagation condition includes the number of entries in the current level that are in the unmapping state being equal to the total number of entries in the current level.

[0221] In one embodiment, the update module 904 is specifically used to respond to a remapping request for sparse resources, and when the target entry is in a demapping state, to clear the demapping field of the target entry and adjust one or more of the validity field, address field, and permission field to obtain a second value of the target entry.

[0222] Among them, the remapping request is used to re-establish the mapping relationship between the entries in the processor page table and the physical video memory.

[0223] In one embodiment, the state propagation module 905 is further configured to clear the unmapping state step by step upwards from the target entry, provided that the second propagation condition is met.

[0224] The second propagation condition includes the number of entries in the current level that are in the unmapping state being equal to zero.

[0225] In one embodiment, the processor page table read / write device 900 further includes:

[0226] The maintenance module 906 is used to perform page table maintenance operations on the page tables of the first processor and the second processor.

[0227] Page table maintenance operations include one or more of the following: address translation cache refresh operations, memory management maintenance operations, and memory barrier operations.

[0228] Specifically, the address translation cache refresh operation is used to cache invalid address translations in the processor after they have been updated to the second value of the target entry; the memory management maintenance operation is used to maintain the consistency between the address translations in the processor and the target entry; and the memory barrier operation is used to synchronize the page table write order of the first processor page table and the second processor page table with the processor.

[0229] In one embodiment, the processor includes a graphics processing unit (GPU).

[0230] Each module in the aforementioned processor page table read / write device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.

[0231] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 10 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a method for reading and writing processor page tables.

[0232] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0233] In one exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method for reading and writing processor page tables.

[0234] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the above-described method for reading and writing processor page tables.

[0235] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described method for reading and writing processor page tables.

[0236] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0237] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0238] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0239] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for reading and writing processor page tables, characterized in that, The method for applying a kernel-mode driver (KMD) to the host machine where the processor resides includes: Read the first value of the target entry from the entry in the second processor's page table; The second processor page table is a mirror page table with the same number of entries and entry width as the first processor page table. The first processor page table is located in the device memory of the processor, and the second processor page table is located in the system memory of the host where the processor is located.

2. The method according to claim 1, characterized in that, The method further includes: The second value of the target table entry is synchronously written into the entries of the first processor page table and the second processor page table through the target access entry, and the second value is used to update the first value.

3. The method according to claim 1, characterized in that, Before reading the first value of the target entry from the entry of the second processor page table, the method further includes: Create the first processor page table in the device memory of the processor, and create the second processor page table in the system memory of the host where the processor resides; Initialize the first processor page table and the second processor page table to synchronize the initial values ​​of the entries in the first processor page table and the second processor page table; Establish a binding relationship between the first processor page table and the second processor page table.

4. The method according to claim 1, characterized in that, The step of reading the first value of the target entry from the entry of the second processor page table includes: When a request is made to determine the current state of an entry in the processor page table, the first value of the target entry is read from an entry in the second processor page table.

5. The method according to claim 4, characterized in that, The step of reading the first value of the target entry from the entry of the second processor page table includes: The location information of the target entry is determined based on the processor's virtual address; Based on the location information of the target entry, the first value of the target entry is read from the entry of the second processor page table.

6. The method according to claim 1, characterized in that, The method further includes: Parse the first value of the target table entry to obtain the table entry status field of the target table entry; The table status field of the target table entry is updated to obtain the second value of the target table entry; The table entry status field includes one or more of the following: validity field, unmapping field, address field, and permission field.

7. The method according to claim 6, characterized in that, The step of updating the table status field of the target table entry to obtain the second value of the target table entry includes: In response to a sparse resource unmapping request, if the target entry is not in an unmapping state, the unmapping field in the target entry is set, and one or more of the validity field, the address field, and the permission field are adjusted to obtain a second value for the target entry. The unmapping request is used to remove the mapping relationship between the entry in the processor page table and the physical video memory, and the unmapping status is the state in which the mapping relationship between the entry in the processor page table and the physical video memory is removed.

8. The method according to claim 2, characterized in that, After synchronously writing the second value of the target table entry into the entries of the first processor page table and the second processor page table through the target access entry, the method further includes: If the first propagation condition is met, the unmapping state is propagated upwards level by level, starting from the target entry. The first propagation condition includes the number of entries in the current level that are in the unmapping state being equal to the total number of entries in the current level.

9. The method according to claim 6, characterized in that, The step of updating the table status field of the target table entry to obtain the second value of the target table entry includes: In response to a remapping request for sparse resources, if the target entry is in a demapping state, the demapping field of the target entry is cleared, and one or more of the validity field, the address field, and the permission field are adjusted to obtain a second value for the target entry; wherein, the remapping request is used to re-establish the mapping relationship between the entry in the processor page table and the physical video memory.

10. The method according to claim 2, characterized in that, After synchronously writing the second value of the target table entry into the entries of the first processor page table and the second processor page table through the target access entry, the method further includes: If the second propagation condition is met, starting from the target entry, the unmapping state is cleared level by level upwards. The second propagation condition includes the number of entries in the current level that are in the unmapping state being equal to zero.

11. The method according to claim 2, characterized in that, After synchronously writing the second value of the target table entry into the entries of the first processor page table and the second processor page table through the target access entry, the method further includes: Perform page table maintenance operations on the first processor page table and the second processor page table; The page table maintenance operations include one or more of the following: address translation cache refresh operations, memory management maintenance operations, and memory barrier operations; The address translation cache refresh operation is used to cache invalid address translations in the processor after updating to the second value of the target table entry; the memory management and maintenance operation is used to maintain the address translations in the processor consistent with the target table entry; and the memory barrier operation is used to synchronize the page table write order of the first processor page table and the second processor page table with the processor.

12. The method according to any one of claims 1-11, characterized in that, The processor includes a graphics processing unit (GPU).

13. A device for reading and writing processor page tables, characterized in that, The device is applied to a KMD (Knowledge Management Device) on a host computer where the processor resides, and includes: A reading module is used to read the first value of a target entry from the entries of the second processor page table; wherein the second processor page table is a mirror page table with the same number of entries and entry width as the first processor page table, the first processor page table is located in the device memory of the processor, and the second processor page table is located in the system memory of the host where the processor is located.

14. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 12.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 12.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 12.

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