Cross-chip coherent interconnect mapping method, system, and chip

Abstract

The embodiment of the application relates to the field of semiconductors, and provides a cross-chip consistency interconnection mapping method and system and a chip, which comprises the following steps: receiving a cross-chip access request initiated by a request node in a first chip for a target address; when the request does not have an endpoint order preserving attribute, performing interleaving calculation on the target address by the request node to determine a first cross-chip port; when the request has the endpoint order preserving attribute, determining a preset cross-chip port as the first cross-chip port; sending the request to a second chip through the first cross-chip port; when a home node in the second chip initiates a consistency maintenance transaction for the target address, performing interleaving calculation on the target address by a second address mapping unit in the home node, and determining a second cross-chip port in combination with a physical connection relationship; and sending the consistency maintenance transaction to the first chip through the second cross-chip port, so that the same target address related transactions are transmitted through the same pair of ports which are physically directly connected, thereby improving the utilization rate of the bandwidth of multiple cross-chip ports and ensuring the correctness of consistency transaction processing and related order requirements.

Description

Technical Field

[0001] This application relates to the semiconductor field, and more specifically to a cross-chip coherent interconnect mapping method, system, and chip. Background Technology

[0002] With the increasing demands for system bandwidth and processing power from applications such as high-performance computing, artificial intelligence computing, and data centers, building unified computing systems using multi-chip interconnects has become an important development trend. The ARM AMBA CHI (Coherent Hub Interface) protocol, as an on-chip coherent interconnect protocol, is commonly used for cache coherency maintenance in multi-core processor systems. In multi-chip systems, the CHI protocol can be extended to inter-chip communication via chip-to-chip (C2C) links, ensuring that multiple chips are within the same coherence domain.

[0003] In multi-chip interconnect systems, to improve the overall bandwidth for cross-chip access, multiple C2C physical links can be set up between two chips. For multi-chip systems supporting the CHI consensus protocol, a common architecture is to use the C2C port as a coherent agent to access the on-chip interconnect network. Using the C2C port as a coherent agent can optimize the processing of cross-chip consensus transactions to some extent.

[0004] However, in scenarios involving consistent transactions, different cross-chip ports typically handle relatively independent transaction transmission and processing functions. When multiple ports work in parallel, the collaborative processing of related transactions across ports becomes quite complex. When a multi-chip system distributes cross-chip access traffic across multiple ports, it can increase the difficulty of maintaining consistency and implementing transaction control. If conventional traffic distribution methods are still used when some transactions have additional processing constraints, the requirements for consistent transaction processing and the bandwidth allocation needs of multiple ports can easily become mutually restrictive, making it difficult to simultaneously ensure protocol processing correctness and multi-port bandwidth utilization. Furthermore, in the CHI protocol, order-preserving access and consistency access are different and mutually exclusive access types, thus creating order-preserving issues in specific order request technologies.

[0005] Therefore, in multi-chip system scenarios with multiple chip ports, how to achieve bandwidth balancing across multiple ports by utilizing address interleaving, while resolving consistency conflicts when accessing the same address and the order preservation problem for requests with a specific sequence, has become an urgent technical problem to be solved. Summary of the Invention

[0006] This application provides a cross-chip consistent interconnect mapping method, system, and chip, which can improve the bandwidth utilization of multiple cross-chip ports in multi-chip port scenarios and ensure the correctness of consistent transaction processing and related order requirements.

[0007] In a first aspect, embodiments of this application provide a cross-chip coherent interconnect mapping method. This method is applied to a multi-chip system including a first chip and a second chip, wherein multiple cross-chip ports are provided between the first chip and the second chip. The method includes: Receive cross-chip access requests initiated by the requesting node in the first chip and targeting a target address; In response to the cross-chip access request not having endpoint ordering attribute, the target address is interleaved by the first address mapping unit set in the request node to determine the first cross-chip port corresponding to the cross-chip access request; in response to the cross-chip access request having endpoint ordering attribute, a preset cross-chip port in the first chip is determined as the first cross-chip port, and the first cross-chip port is physically directly connected to the corresponding cross-chip port in the second chip. The cross-chip access request is sent to the second chip via a determined first cross-chip port; In response to the home node in the second chip initiating a consistency maintenance transaction for the target address, the second address mapping unit set in the home node performs interleaving calculation on the target address, and determines the second cross-chip port corresponding to the consistency maintenance transaction based on the physical connection relationship of multiple cross-chip ports between the first chip and the second chip, wherein the second address mapping unit and the first address mapping unit adopt the same interleaving algorithm; The consistency maintenance transaction is sent to the first chip via the second cross-chip port, so that the cross-chip access request and the consistency maintenance transaction are transmitted via the same pair of physically connected cross-chip ports.

[0008] Secondly, embodiments of this application provide a cross-chip consistent interconnect mapping system, which has the functionality to implement the cross-chip consistent interconnect mapping method provided in the first aspect above. The system includes a first chip and a second chip, with multiple cross-chip ports provided between the first chip and the second chip; the first chip includes a request node and a first address mapping unit, the request node being used to initiate a cross-chip access request for a target address.

[0009] The first address mapping unit is configured to: in response to the cross-chip access request not having an endpoint ordering attribute, perform interleaving calculation on the target address to determine the first cross-chip port corresponding to the cross-chip access request; in response to the cross-chip access request having an endpoint ordering attribute, determine a preset cross-chip port in the first chip as the first cross-chip port, wherein the first cross-chip port is physically directly connected to the corresponding cross-chip port in the second chip; The first chip is also configured to send the cross-chip access request to the second chip via a determined first cross-chip port; The second chip includes a home node and a second address mapping unit, wherein the home node is used to initiate a consistency maintenance transaction for the target address; The second address mapping unit is configured to: in response to the home node initiating a consistency maintenance transaction for the target address, perform interleaving calculation on the target address, and determine the second cross-chip port corresponding to the consistency maintenance transaction based on the physical connection relationship of multiple cross-chip ports between the first chip and the second chip, wherein the second address mapping unit and the first address mapping unit adopt the same interleaving algorithm; The second chip is also configured to send the consistency maintenance transaction to the first chip via the second cross-chip port, so that the cross-chip access request and the consistency maintenance transaction are transmitted via the same pair of physically connected cross-chip ports.

[0010] Thirdly, embodiments of this application provide a chip including a processor coupled to a transceiver for executing the cross-chip coherent interconnect mapping method provided in the first aspect of this application. In one possible design, the chip can also be a dedicated hardware structure for implementing the technical solution provided in the first aspect above.

[0011] Fourthly, embodiments of this application provide a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the cross-chip coherent interconnect mapping method as provided in the first aspect.

[0012] Fifthly, embodiments of this application provide a computing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the cross-chip coherent interconnect mapping method provided in the first aspect.

[0013] In a sixth aspect, embodiments of this application provide a computer program product containing instructions that, when run on a computer, cause the computer to execute the cross-chip coherent interconnect mapping method provided in the first aspect.

[0014] Compared to existing technologies, in this embodiment, a first address mapping unit is set on the request node side of the first chip. When a cross-chip access request does not have endpoint ordering attributes, the first address mapping unit performs interleaving calculations on the target address to determine the first cross-chip port for sending the cross-chip access request from multiple cross-chip ports. This allows ordinary cross-chip access traffic to be distributed among multiple cross-chip ports based on address distribution, improving multi-port bandwidth utilization. For cross-chip access requests with endpoint ordering attributes, a preset cross-chip port in the first chip is determined as the first cross-chip port. This ensures that access requests with endpoint ordering requirements are concentrated and transmitted through the determined cross-chip port, preventing such requests from being distributed across multiple relatively independent cross-chip ports and facilitating the maintenance of their ordering requirements. Furthermore, when the home node of the second chip initiates a consistency maintenance transaction for the same target address, the second address mapping unit set in the home node performs interleaving calculations on the target address. The second address mapping unit and the first address mapping unit use the same interleaving algorithm, and the second cross-chip port is determined by combining the physical connection relationship between multiple cross-chip ports between the first and second chips. Therefore, cross-chip access requests and consistency maintenance transactions for the same target address can be transmitted through the same pair of physically connected cross-chip ports, reducing the complexity of collaborative processing caused by related consistency transactions being distributed to different ports.

[0015] This application embodiment enables ordinary cross-chip access traffic to be allocated through interleaving calculation in scenarios where multiple cross-chip ports work in parallel. It allows access requests with endpoint ordering attributes to be processed through preset ports, and converges consistency maintenance transactions related to the same target address and cross-chip access requests to be transmitted on the same pair of physically directly connected cross-chip ports. This reduces the complexity of cross-port collaborative processing of consistency transactions, improves the bandwidth utilization of multiple cross-chip ports, and ensures the correctness of consistency transaction processing and related order requirements. Attached Figure Description

[0016] The objectives, features, and advantages of the embodiments of this application will become readily understood by referring to the accompanying drawings and the detailed description of the embodiments. Wherein: Figure 1 This is a flowchart illustrating the cross-chip coherence interconnect mapping method in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a two-chip four-port interconnect system according to an embodiment of this application; Figure 3 This is a schematic diagram of an address interleaving mapping process according to an embodiment of this application; Figure 4 This is a schematic diagram illustrating a mapping from a port index to a cross-chip port target identifier according to an embodiment of this application; Figure 5 This is a schematic diagram of the cross-chip coherent interconnect mapping system according to an embodiment of this application.

[0017] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0020] It should be understood that, in order to clearly describe the technical solutions of the embodiments of the present invention, the terms "first" and "second" are used in the embodiments of the present invention to distinguish identical or similar items with essentially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0021] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0023] Existing multi-chip interconnect systems typically distribute cross-chip access traffic by setting up multiple cross-chip ports or multiple cross-chip physical links to improve cross-chip access bandwidth. In multi-chip systems that support consensus protocols, cross-chip ports may also act as consensus proxies in the transmission and processing of cross-chip access requests and consensus maintenance transactions. Since different cross-chip ports usually undertake relatively independent transaction transmission and processing functions, the coordinated processing of related consensus transactions across multiple ports becomes more complex when cross-chip access traffic is distributed across multiple ports. For some transactions with sequential requirements, if they are still transmitted across multiple ports using the normal traffic distribution method, it may lead to a mutual constraint between the consensus transaction processing requirements and the multi-port bandwidth allocation requirements.

[0024] This application provides a cross-chip consistency interconnect mapping method, system, and chip, applicable to a multi-chip system including a first chip and a second chip. Multiple cross-chip ports are provided between the first chip and the second chip, which can be used to carry cross-chip access requests, consistency maintenance transactions, and related response transactions. This multi-chip system can be applied to high-performance computing devices, data center servers, artificial intelligence computing systems, on-chip multiprocessor systems, multi-chip packaged systems, or other chip systems requiring cross-chip consistency interconnects; this application does not limit the application to these applications.

[0025] The cross-chip consistency interconnect mapping method provided in this embodiment can be used in scenarios where multiple cross-chip ports operate in parallel. The method sets up a first address mapping unit on the requesting node side of the first chip and a second address mapping unit on the home node side of the second chip. For cross-chip access requests without endpoint ordering attributes, the first address mapping unit performs interleaving calculations on the target address to distribute access traffic among multiple cross-chip ports. For cross-chip access requests with endpoint ordering attributes, they are mapped to a preset cross-chip port in the first chip. For consistency maintenance transactions initiated by the second chip for the same target address, the second address mapping unit uses the same interleaving algorithm as the first address mapping unit, and determines the corresponding second cross-chip port based on the physical connection relationship between the cross-chip ports. Therefore, cross-chip access requests and consistency maintenance transactions for the same target address can be transmitted through the same pair of physically directly connected cross-chip ports, thereby reducing the complexity of cross-port collaborative processing of related consistency transactions and balancing endpoint ordering requirements and multi-port bandwidth utilization needs.

[0026] The following describes the cross-chip coherence interconnect mapping method provided in the embodiments of this application, referring to... Figure 1 As can be seen, the method includes steps 101 to 105, which are detailed below: Step 101: Receive a cross-chip access request initiated by the requesting node in the first chip and targeting the target address.

[0027] In this system, the first chip and the second chip belong to the same multi-chip system, and multiple cross-chip ports (e.g., two, four or more) are provided between the first chip and the second chip. The cross-chip ports can realize transaction transmission between the two chips through physical links, and the cross-chip port agent (C2C agent) can access the on-chip interconnect network (NoC) of each chip.

[0028] The requesting node can be a functional node in the first chip used to initiate an access request, such as a processor core, accelerator, graphics processing unit, or other master device node capable of initiating a cross-chip access request.

[0029] The target address can be the physical address or the coherent address accessed by the cross-chip access request. Further, alternatively, the target address can be generated by the requesting node based on memory access instructions or DMA access, and carried in the cross-chip access request in the form of a physical address or a system coherent address after address mapping or normalization, for the first address mapping unit to perform interleaving calculations and port selection.

[0030] For example, when the target address is a physical address, the requesting node (such as a CPU core, GPU, accelerator, etc.) obtains a virtual address (VA) when performing load / store or DMA access operations. The address translation unit (such as MMU / IOMMU, TLB page table traversal logic) within the requesting node converts the virtual address into a physical address (PA). The requesting node then writes this physical address as the address field of the access transaction into the cross-chip access request (such as the address field of request flit), and this physical address becomes the target address.

[0031] For example, when the target address is a consistent address (system address or interconnect address), in some implementations, the requesting node still carries a physical address. However, before or after entering the on-chip interconnect or SAM (System Address Map), a system address space normalization is performed. For instance, based on system memory mapping (DDR, HBM, MMIO, cross-chip window, etc.), the address is categorized into an address space recognizable by the consistency domain, forming a system address or consistent address used for routing or consistency processing. SAM is essentially an address mapping module that determines the target node or port based on the address. That is, the first address mapping unit on the requesting node side (RN-side SAM) receives the address field carried in the request and uses this address as the input for interleaving calculation; this address has unique semantics within the consistency domain and can be used to map ports.

[0032] Cross-chip access requests can be read requests, write requests, or other access requests that need to be sent to a second chip for processing via a cross-chip port.

[0033] Optionally, it is assumed that the first chip contains multiple request nodes. Based on this, during the system startup phase, the number of cross-chip ports between the first chip and the second chip, as well as the physical connection relationships between the multiple cross-chip ports, are determined. Then, based on the number of cross-chip ports and the physical connection relationships, a consistent interleaving algorithm and mapping parameters are configured for the first address mapping units in the multiple request nodes. The mapping parameters include the interleaving granularity, the number of cross-chip ports participating in the interleaving, and the correspondence between the port index and the target identifier of the first cross-chip port, so that cross-chip access requests from different request nodes targeting the same target address are mapped to the same first cross-chip port.

[0034] In one implementation, configuring consistent interleaving algorithms and mapping parameters for the first address mapping units across multiple request nodes involves writing the same interleaving method, interleaving granularity, and number of ports participating in interleaving into the configuration register of each request node during system startup. The mapping relationship between port indices and cross-chip port target identifiers (targetids) is also written into the first mapping table of each request node. With consistent configuration across request nodes, it ensures that when different request nodes access the same target address, the first address mapping unit obtains a consistent port index and, further, a consistent first cross-chip port target identifier. Therefore, cross-chip access requests related to the same target address will not be assigned to different cross-chip ports due to different request node origins. This helps reduce the collaborative processing complexity caused by cross-port dispersion of co-address transactions and provides a foundation for port correspondence maintenance transactions on the second chip side.

[0035] In one implementation, the first mapping table can be configured using the entry structure in the SAM. The SAM includes multiple entries, each corresponding to an address range, and each entry includes at least an address range configuration and a target identifier configuration. The address range configuration is used to limit the address space corresponding to the entry, and the target identifier configuration is used to indicate the target node or cross-chip port proxy mapped to when a request hits the address space.

[0036] When the address space corresponding to an entry needs to achieve bandwidth balancing across multiple cross-chip ports through address interleaving, the entry also includes an interleaving configuration. The interleaving configuration may include interleaving granularity, interleaving algorithm, number of interleaving results, and target identifiers corresponding to each interleaving result, wherein the number of interleaving results corresponds to the number of target identifiers configured in the entry. The target identifier can be the target ID of the corresponding cross-chip port proxy.

[0037] During system startup, the address ranges corresponding to each entry can be determined based on the system address space planning. Then, the corresponding target identifiers and interleaving configurations can be configured according to the target nodes, the number of cross-chip ports, and bandwidth balancing requirements for each address range. For cross-chip address spaces, a single entry can be used for configuration, containing the address range of the cross-chip address space and the target IDs of one or more corresponding cross-chip port proxies. When interleaving is required, the interleaving granularity, interleaving algorithm, and the number of target IDs participating in the interleaving are also written to this entry.

[0038] After receiving a cross-chip access request, the first address mapping unit matches the address field of the request with the address range configured in each table entry to determine the target table entry to which the address field falls. When the target table entry is not configured for interleaving, the target identifier configured in the target table entry is used for mapping. When the target table entry is configured for interleaving, the requested address field is interleaved according to the interleaving granularity and interleaving algorithm in the target table entry, and the target target ID is determined from multiple target IDs configured in the target table entry based on the interleaving result.

[0039] In one implementation, step 101, receiving a cross-chip access request initiated by a requesting node in the first chip and targeting a target address, includes: sampling or intercepting the access transaction output by the requesting node during the request generation phase of the requesting node or at the exit point from the requesting node to the on-chip interconnect; parsing the access transaction into a cross-chip access request containing the target address and target node information; and submitting the cross-chip access request to the port selection logic entry of the first address mapping unit. Optionally, the first address mapping unit may be integrated with the requesting node or set on the transaction path from the requesting node to the on-chip interconnect to complete port selection before the request enters the on-chip interconnect route.

[0040] For example, suppose the first chip contains two requesting nodes, CPU cores RN0 and RN1, each initiating a read request for the same target address `addr`. Since the first address mapping units of RN0 and RN1 use the same interleaving algorithm and mapping parameters, both read requests will obtain the same port index at the first address mapping unit and be directed to the cross-chip port proxy corresponding to the same first cross-chip port. This cross-chip port proxy then sends the request to the second chip via the physical link. This process enables cross-chip access requests for the same target address to converge to a consistent cross-chip port path on the first chip side, thus providing the conditions for the subsequent transmission of consistent transactions and request paths.

[0041] Step 102: In response to the cross-chip access request not having endpoint ordering attribute, the target address is interleaved by the first address mapping unit set in the request node to determine the first cross-chip port corresponding to the cross-chip access request; In response to the cross-chip access request having endpoint ordering attribute, the preset cross-chip port in the first chip is determined as the first cross-chip port.

[0042] In this embodiment of the application, the endpoint ordering attribute refers to the transaction attribute that requires cross-chip access requests to satisfy a predetermined order constraint when they arrive at the endpoint or are processed by the endpoint proxy.

[0043] For example, endpoint-ordered access requests include, but are not limited to, cross-chip access requests where the Order field has the Endpoint Order attribute and the corresponding order constraints must be met at the target endpoint. The Endpoint Order attribute is used to instruct the target endpoint to process the relevant access requests in the order specified by the CHI protocol, avoiding situations where the processing order of relevant access requests at the target endpoint does not conform to the protocol requirements due to different transmission paths or different port proxies. It should be noted that the Endpoint Order attribute constrains the order relationship of relevant access requests at the target endpoint, and does not represent a global ordering of all access requests in the multi-chip system.

[0044] In the CHI protocol-based implementation, cross-chip access requests carry an Order field segment, which characterizes the order attribute of the cross-chip access request. The first address mapping unit can read the Order field segment when receiving or processing the cross-chip access request and determine whether the cross-chip access request is an endpoint-preserving access request based on the field values ​​of the Order field segment. When the Order field segment has an Endpoint Order attribute, the first address mapping unit determines that the cross-chip access request is an endpoint-preserving access request. For the endpoint-preserving access request, the first address mapping unit does not use the interleaving calculation result based on the target address, but instead determines a preset cross-chip port in the first chip as the first cross-chip port.

[0045] For a consistency access request, the first address mapping unit performs interleaving calculations on the target address according to a pre-configured interleaving algorithm to determine the corresponding first cross-chip port. Endpoint order-preserving access requests and consistency access requests are different and mutually exclusive access types. Therefore, endpoint order-preserving access requests with the Endpoint Order attribute in the Order field do not enter the interleaving processing branch corresponding to the consistency access request, nor do they trigger the consistency maintenance processing corresponding to that consistency access request.

[0046] Optionally, the first address mapping unit may also determine whether the cross-chip access request has endpoint order preservation attributes based on the transaction attribute field, request type field, sequence control field, or internal control signal generated by the requesting node carried in the cross-chip access request. That is, the embodiments of this application do not limit the endpoint order preservation attribute to be represented by a specific field, as long as it can characterize that the cross-chip access request needs to be processed according to the endpoint order requirements.

[0047] Further optionally, a cross-chip port is pre-configured so that cross-chip access requests with the endpoint ordering attribute are centrally transmitted via the same cross-chip port.

[0048] For example, during system startup, a fixed cross-chip port can be selected from multiple interleaved cross-chip ports in the first chip based on the number of cross-chip ports, physical connection relationships, and system configuration requirements between the first and second chips. The port identifier or target identifier of this fixed cross-chip port is then written into the software configuration register corresponding to the first address mapping unit. This fixed cross-chip port is the preset cross-chip port. When the first address mapping unit subsequently detects that a cross-chip access request has endpoint ordering attributes, it can directly read the port identifier in the software configuration register and determine the corresponding preset cross-chip port as the first cross-chip port.

[0049] Specifically, in step 102, the first address mapping unit can be set in the request node of the first chip to determine the cross-chip port corresponding to the cross-chip access request based on the target address. When the cross-chip access request does not have endpoint ordering attribute, the first address mapping unit can perform interleaving calculation on the target address according to a pre-configured interleaving algorithm to obtain the port index, and determine the first cross-chip port based on the port index.

[0050] Interleaving algorithms include, but are not limited to, cache line interleaving, hash interleaving, address segmentation, or other algorithms that can distribute traffic across multiple ports based on addresses. In practical applications, different interleaving algorithms can be selected based on system topology, access patterns, and bandwidth balancing requirements.

[0051] Further optionally, in step 102, performing an interleaving operation on the target address to obtain a port index includes: in response to the interleaving mode being configured as cache line interleaving, extracting address bits in the target address corresponding to the interleaving granularity and the number of cross-chip ports participating in the interleaving, as the port index; in response to the interleaving mode being configured as hash interleaving, performing an XOR folding operation on multiple bit groups in the target address, and determining the port index based on the XOR folding operation result; in response to the interleaving mode being configured as address segmentation, determining the port index based on the address range where the target address is located.

[0052] Specifically, when four cross-chip ports are set between the first and second chips, if the interleaving method is configured as cache line interleaving, the first address mapping unit can extract the address bits corresponding to the interleaving granularity in the target address and take 2 bits as the port index. If the interleaving method is configured as hash interleaving, the first address mapping unit can perform an XOR folding operation on multiple bit groups in the target address and determine the port index based on the low-order bits of the operation result. If the interleaving method is configured as address segmentation, the first address mapping unit can determine the port index based on the address range where the target address is located. After obtaining the port index, the first address mapping unit can query the first mapping table to obtain the target identifier of the first cross-chip port corresponding to the port index, and route the cross-chip access request to the corresponding cross-chip port proxy based on the target identifier.

[0053] The following describes the specific implementation process of the three interleaving operations given in the above embodiments, and introduces the improvements obtained by combining each interleaving operation with the embodiments of this application.

[0054] In one implementation, the interleaving algorithm can be cache line interleaving. Cache line interleaving can be understood as selecting address bits from the target address according to a predetermined interleaving granularity, and using the selected address bits as port indices for selecting cross-chip ports. For example, the interleaving algorithm can be a polling interleaving algorithm based on cache line numbers or a low-order address bit interleaving algorithm. Specifically, the first address mapping unit can first remove the in-line offset bits from the target address according to the interleaving granularity to obtain the cache line number, and then select consecutive low-order bits from the cache line number according to the number of cross-chip ports participating in the interleaving, or perform a modulo operation on the cache line number to obtain the port index.

[0055] Specifically, the first address mapping unit can first determine the starting address bits for port selection in the target address based on the interleaving granularity recorded in the software configuration register, and then determine the address width to be extracted based on the number of cross-chip ports participating in the interleaving. For example, if the interleaving granularity is 64 bytes, the lower 6 bits of the target address can be used to represent the offset within the cache line and do not participate in port selection. If the number of cross-chip ports participating in the interleaving is 4, the first address mapping unit can extract 2 bits from the target address as a port index. This 2-bit port index can correspond to each of the 4 cross-chip ports. This method is simple to implement and suitable for scenarios where cross-chip access traffic is distributed according to cache lines or smaller address granularities.

[0056] For example, if four cross-chip ports (C2C port0, C2C port1, C2C port2, and C2C port3) are configured between the first and second chips, and the interleaving granularity is configured to 64 bytes, the first address mapping unit can extract the two address bits after the cache line offset in the target address as port indices. When the port index is 00, it corresponds to C2C port0. When the port index is 01, it corresponds to C2C port1. When the port index is 10, it corresponds to C2C port2. When the port index is 11, it corresponds to C2C port3. Of course, the above correspondence between port indices and cross-chip ports can also be configured through the first mapping table, and is not limited to the case where the port number and port index are exactly the same.

[0057] Cache line interleaving is characterized by its simple hardware implementation and low port selection latency. Traditional cache line interleaving is typically used to distribute access traffic across multiple storage channels, interconnect ports, or physical links, with a focus on load balancing. In this type of traditional scheme, the address-to-port mapping generally only applies to the request initiation path. Whether the peer chip can obtain the port selection result corresponding to the request path when initiating a consistency maintenance transaction is usually not a primary consideration in this type of scheme.

[0058] In this embodiment, the cache line interleaving rule can be configured simultaneously in the first address mapping unit of the first chip-side requesting node and the second address mapping unit of the second chip-side home node. Specifically, the first address mapping unit and the second address mapping unit can use the same interleaving granularity, the same address bit selection position, and the same port index bit width. In this way, for the same target address, regardless of whether the cross-chip access request corresponding to the address is initiated by the first chip-side requesting node or the consistency maintenance transaction corresponding to the address is initiated by the second chip-side home node, the same or corresponding port index can be obtained.

[0059] Furthermore, since the C2C port identifiers, node identifiers, or on-chip routing target identifiers on the first chip side and the second chip side may not be completely consistent, embodiments of this application can also set a mapping lookup table based on physical connection relationships on the second chip side. After obtaining the port index, the second address mapping unit can convert the port index into the target id of the corresponding C2C port on the second chip side according to the actual physical connection relationship between the C2C ports of the first chip and the second chip. Thus, even if the port numbers on both sides are inconsistent, cross-chip access requests and consistency maintenance transactions related to the same target address can be directed to the same pair of physically directly connected C2C ports.

[0060] For example, in a 4-port scenario, when the first chip-side C2C port0, C2C port1, C2C port2, and C2C port3 are physically directly connected to the second chip-side C2C port0, C2C port1, C2C port2, and C2C port3 respectively, port indices 00 to 11 can be mapped to the corresponding ports. If, in actual wiring, the first chip-side C2C port0 is physically directly connected to the second chip-side C2C port2, and the first chip-side C2C port1 is physically directly connected to the second chip-side C2C port0, then the mapping lookup table on the second chip-side can be configured according to this physical connection relationship. This allows the second address mapping unit to select the C2C port physically corresponding to the request path on the first chip-side after obtaining the same port index, rather than selecting the port solely based on the same port number.

[0061] In this embodiment, cache line interleaving can be used to distribute ordinary cross-chip access traffic and establish a stable port path correspondence for consistency transactions related to the same cache line. For the same target address, cross-chip access requests from the first chip side and consistency maintenance transactions such as snoops initiated by the second chip side for that address can converge to the same physically directly connected pair of C2C ports and be processed in the corresponding C2C agent context. This avoids introducing additional cross-port ordering processing requirements by having transactions related to the same address enter different independent C2C agents, thus achieving both cache line-level bandwidth balancing and consistency transaction path consistency without increasing the protocol layer's cross-link global ordering mechanism.

[0062] In another implementation, the interleaving algorithm can be hash interleaving. Hash interleaving can be understood as performing a pre-defined combination operation on multiple bit groups in the target address and determining the port index based on the result of the combination operation. Specifically, the first address mapping unit can select multiple bit groups from the target address according to the hash parameters configured in the software configuration register, perform an XOR folding operation on the multiple bit groups, and take some low-order bits or specified bits from the XOR folding result as the port index. The bit groups participating in the XOR folding can come from consecutive address bits of the target address or from non-consecutive address bits of the target address. The specific selection method can be configured according to the access mode, address space layout, and number of ports.

[0063] Compared to directly extracting address bits, hash interleaving can reduce the probability of some consecutive addresses or regular accesses falling into the same cross-chip port, thereby improving the uniformity of traffic distribution among multiple cross-chip ports.

[0064] For example, when four cross-chip ports are set between the first and second chips, the port index can have a bit width of 2 bits. The first address mapping unit can select multiple 2-bit groups from the target address, such as the first, second, and third bit groups, and perform an XOR operation on these bit groups to obtain a 2-bit hash result. This 2-bit hash result can be used as a port index to look up the first mapping table and determine the first cross-chip port. In this way, even if the access addresses show a certain continuity or regularity, the port index is not completely determined by a single low-order address, thereby reducing the probability that access traffic will concentrate on a single cross-chip port.

[0065] Hash interleaving itself helps improve the problem of uneven port load caused by uneven address distribution. This application combines hash interleaving with cross-chip consistency transaction path control, further requiring the first address mapping unit and the second address mapping unit to use consistent hash interleaving rules for the same target address. That is, when the home node in the second chip initiates a consistency maintenance transaction for the target address, the second address mapping unit can obtain the corresponding port index using the same bit group selection method and XOR folding method as the first address mapping unit. This not only improves the balance of ordinary cross-chip access traffic across multiple cross-chip ports using hash interleaving, but also ensures that cross-chip access requests and consistency maintenance transactions related to the same target address are not routed to mismatched port paths due to inconsistent hash results. Furthermore, the second chip side converts the hashed port index into a cross-chip port target identifier using a mapping lookup table configured based on physical connection relationships, thereby adapting to situations where the port numbers or node identifiers on both sides are different. The first address mapping unit can perform XOR folding operations on multiple bit groups in the target address, or perform other preset hash operations, and determine the port index based on several bits in the operation result.

[0066] In another implementation, the interleaving algorithm can be address segmentation. Address segmentation can be understood as determining the port index based on the address range containing the target address. Specifically, the first address mapping unit can pre-store or retrieve the correspondence between multiple address ranges and port indices. When a cross-chip access request arrives, the first address mapping unit matches the target address with multiple address ranges to determine the address range to which the target address belongs, and uses the index corresponding to that address range as the port index. Each address range can be a continuous range or a non-contiguous range; different address ranges can be of the same size or set to different sizes according to system address space planning or service access characteristics.

[0067] For example, a first address range can be mapped to port index 0, a second address range to port index 1, a third address range to port index 2, and a fourth address range to port index 3. When the first address mapping unit determines that the target address falls within the first address range, it sets the port index to 0. When it determines that the target address falls within the second address range, it sets the port index to 1. Subsequently, the first address mapping unit queries the first mapping table based on the port index to obtain the target identifier of the corresponding first cross-chip port. This method is suitable for scenarios where cross-chip access traffic needs to be isolated or directed according to storage region, address space type, business data region, or system topology planning.

[0068] Address segmentation inherently provides strong address space management capabilities. In this application's embodiment, when address segmentation is used for cross-chip consistency interconnect mapping, it requires the first chip side and the second chip side to employ consistent segmentation rules for the same address space. That is, when the first address mapping unit obtains the port index based on the address range to which the target address belongs, the second address mapping unit can also obtain the corresponding port index for the same target address based on the same address range. Therefore, while using address segmentation for traffic isolation or regional management, it is still possible to maintain consistency transactions related to the same target address by mapping them to the same physically directly connected pair of cross-chip ports. For systems that require different cross-chip link strategies for different address ranges, this method can maintain the correspondence between consistency maintenance paths and access request paths while achieving traffic isolation.

[0069] It should be noted that all three types of interleaving operations can be configured through configuration registers.

[0070] Further optionally, during the system startup phase, the number of cross-chip ports between the first chip and the second chip, as well as the physical connection relationships between the multiple cross-chip ports, are obtained; the number of cross-chip ports participating in interleaving is determined based on the number of cross-chip ports, and the correspondence between port indexes and cross-chip port target identifiers is determined based on the physical connection relationships; the interleaving method, interleaving granularity, the number of cross-chip ports participating in interleaving, and the correspondence are written into the software configuration registers corresponding to multiple request nodes in the first chip, so that the first address mapping units in the multiple request nodes have a consistent interleaving configuration; the interleaving method and interleaving granularity consistent with the first address mapping unit are written into the software configuration register corresponding to the home node in the second chip, and the mapping lookup table determined based on the physical connection relationships is written into the software configuration register corresponding to the home node to configure the second address mapping unit; wherein, the interleaving granularity is a power of 2 in bytes, and the number of cross-chip ports participating in interleaving is a power of 2.

[0071] For example, during system startup, the interleaving method, interleaving granularity, number of interleaved cross-chip ports, and the correspondence between port indexes and cross-chip port target identifiers can be configured based on the number of cross-chip ports between the first and second chips, their physical connection relationships, and system access characteristics. For multiple requesting nodes in the first chip, the first address mapping unit corresponding to each requesting node can be configured with the same interleaving method and mapping parameters, ensuring that cross-chip access requests from different requesting nodes accessing the same target address receive the same port index. For the home node in the second chip, the second address mapping unit can be configured with the same interleaving method and granularity as the first address mapping unit, and further configure a mapping lookup table based on the physical connection relationships between the first and second chips to convert the port index into the cross-chip port target identifier on the second chip side. In practical applications, the interleaving granularity can be a power of 2 in bytes, and the number of cross-chip ports participating in interleaving can also be a power of 2, facilitating the acquisition of port indexes through hardware logic such as address bit extraction, XOR folding, or range matching.

[0072] In the interleaving algorithm provided in this application embodiment, the first address mapping unit on the first chip side and the second address mapping unit on the second chip side employ the same interleaving algorithm, enabling cross-chip access requests and consistency maintenance transactions targeting the same target address to obtain corresponding port indices. Simultaneously, the second chip side also maps the port indices to the target identifiers of the corresponding cross-chip ports on the second chip side based on the physical connection relationships of multiple cross-chip ports between the first and second chips. Therefore, even if the cross-chip port identifiers on the first and second chip sides are different, it can still ensure that transactions related to the same target address are transmitted via the same physically directly connected pair of cross-chip ports.

[0073] Furthermore, this embodiment of the application combines the aforementioned interleaving algorithm with bypass processing of endpoint ordering requests. For cross-chip access requests without endpoint ordering attributes, the first address mapping unit allocates ports according to the configured interleaving algorithm to achieve bandwidth balancing among multiple cross-chip ports. For cross-chip access requests with endpoint ordering attributes, the first address mapping unit maps the request to a preset cross-chip port without using the target address interleaving calculation result. Thus, while allocating ordinary access traffic to multiple ports, requests with endpoint ordering requirements can be centrally processed through the same cross-chip port, thereby balancing bandwidth utilization and order maintenance requirements.

[0074] As an optional embodiment, in step 102, the first address mapping unit set in the request node performs interleaving calculation on the target address to determine the first cross-chip port corresponding to the cross-chip access request, including: performing interleaving calculation on the target address to obtain a port index; querying a first mapping table according to the port index to obtain the target identifier of the corresponding first cross-chip port; and, according to the target identifier of the first cross-chip port, routing the cross-chip access request to the corresponding cross-chip port proxy via the on-chip interconnect of the first chip, and sending it to the second chip through the cross-chip port proxy.

[0075] In the above embodiments, when the requesting node of the first chip initiates a cross-chip access request, it carries the target address `addr`. The first address mapping unit receives the cross-chip access request and performs an interleaving operation on the target address `addr` to obtain the port index `index`. The interleaving method can be cache line interleaving, hash interleaving, or address segmentation. Specific implementation details are described above and will not be elaborated here.

[0076] For example, in a scenario where four cross-chip ports are set between two chips, the port index can be 2 bits. When cache line interleaving occurs, 2 bits of the target address can be extracted as the index after removing the offset bits within the line. When hash interleaving occurs, the low-order bits can be taken as the index after performing an XOR folding operation on several bit groups of the target address.

[0077] After obtaining the port index, the first address mapping unit queries the first mapping table to obtain the target identifier (target id) of the first cross-chip port corresponding to the port index. Based on the target id, the cross-chip access request is routed to the corresponding cross-chip port agent (C2C agent) via the on-chip interconnect network of the first chip. The cross-chip port agent then sends the cross-chip access request to the second chip through the link that is physically directly connected to the second chip.

[0078] Through the above methods, cross-chip access requests can be controllably distributed among multiple cross-chip ports on the first chip side, enabling ordinary cross-chip access traffic to be distributed across different cross-chip ports to improve the overall bandwidth utilization of multi-links. Simultaneously, the mapping from port index to target identifier allows the port selection result to be directly implemented as the on-chip routing target, facilitating port selection and request forwarding with lower hardware overhead. Furthermore, when the first chip contains multiple request nodes and the first address mapping units in each request node adopt a consistent interleaving configuration and a consistent first mapping table configuration, cross-chip access requests for the same target address can obtain a consistent port index and select the same first cross-chip port. This reduces the collaborative processing complexity caused by co-address transactions being distributed to different cross-chip port proxies on the first chip side, and provides a foundation for establishing a correspondence between transactions and request paths for subsequent consistency maintenance on the second chip side.

[0079] In step 102, when the cross-chip access request is an endpoint-ordered access request, the first address mapping unit does not use the interleaving calculation result based on the target address, but instead determines the preset cross-chip port in the first chip as the first cross-chip port. The endpoint-ordered access request refers to a cross-chip access request whose Order field value is Endpoint Order, indicating that the request has an Endpoint Order attribute. The preset cross-chip port can be pre-configured by software and physically directly connected to the corresponding cross-chip port in the second chip. Therefore, endpoint-ordered access requests can be centrally transmitted via a determined cross-chip port, avoiding the interleaving and mapping of such requests to multiple relatively independent cross-chip port proxies due to different target addresses.

[0080] In the CHI protocol-based implementation, cross-chip access requests carry an Order field, which characterizes the sequential attribute of the cross-chip access request. The first address mapping unit can read the Order field and determine whether the cross-chip access request is an endpoint-preserving access request based on its value. When the value of the Order field is Endpoint Order, the first address mapping unit determines that the cross-chip access request is an endpoint-preserving access request, bypasses or skips the interleaving calculation based on the target address, and determines the pre-configured cross-chip port as the first cross-chip port.

[0081] Optionally, the requesting node can also parse the Order field and generate an internal control signal based on the parsing result. The first address mapping unit receives the internal control signal and determines that the cross-chip access request is an endpoint-preserving access request when the internal control signal indicates that the field value of the Order field is Endpoint Order. Therefore, the first address mapping unit can directly read the Order field or identify the endpoint-preserving access request based on the internal control signal parsed from the Order field.

[0082] Endpoint order-preserving access requests and consistency access requests are different and mutually exclusive access types. For consistency access requests, the first address mapping unit performs interleaving calculations on the target address according to a pre-configured interleaving algorithm. For example, the target address can be calculated using cache line interleaving, hash interleaving, or address segmentation to obtain a port index. The mapping table is then queried based on the port index to obtain the target identifier of the corresponding first cross-chip port. Based on the target identifier, the requesting node or on-chip interconnect network routes the consistency access request to the corresponding cross-chip port proxy and sends it to the second chip through the cross-chip port proxy.

[0083] For an endpoint-preserving access request, the first address mapping unit may choose not to perform interleaving calculations for the target address, or it may perform the interleaving calculations but not use the results, instead reading a pre-configured fixed port configuration item. The fixed port configuration item indicates a preset cross-chip port among multiple cross-chip ports participating in interleaving in the first chip. The first address mapping unit determines the preset cross-chip port as the first cross-chip port and sends the endpoint-preserving access request through the cross-chip port proxy corresponding to the first cross-chip port.

[0084] In one implementation, the first address mapping unit can be located in the requesting node of the first chip, or on the address mapping path where the requesting node sends a cross-chip access request to the on-chip interconnect network. The cross-chip access request generated by the requesting node can carry transaction information such as the target address, request type, and Order field. After receiving the cross-chip access request, the first address mapping unit reads or parses the Order field. When the value of the Order field is Endpoint Order, the first address mapping unit executes the aforementioned preset cross-chip port selection process.

[0085] For example, four cross-chip ports—C2C port0, C2C port1, C2C port2, and C2C port3—can be set between the first chip and the second chip. During system startup, the software can configure C2C port0 as the preset cross-chip port corresponding to the endpoint ordered access request via configuration registers. For a consistent access request, the first address mapping unit can perform interleaving calculations such as cache line interleaving, hash interleaving, or address segmentation based on the target address of the request, and map the consistent access request to one of the ports C2C port0 to C2C port3.

[0086] When a requesting node in the first chip initiates a cross-chip access request with the Order field value being Endpoint Order, even if the port index calculated using the interleaving algorithm for the target address of the request corresponds to C2C port1, C2C port2, or C2C port3, the first address mapping unit does not use that port index. Instead, it determines C2C port0 as the first cross-chip port based on the fixed port configuration item. Subsequently, the endpoint-preserving access request is sent to the second chip via the cross-chip port proxy corresponding to C2C port0.

[0087] Furthermore, the preset cross-chip port can be selected during system startup based on the number of cross-chip ports between the first chip and the second chip, the physical connection relationship, the port availability status, and the link configuration requirements. The software can write the port identifier or target identifier of the selected cross-chip port into the configuration register corresponding to the first address mapping unit. After recognizing an endpoint-preserving access request, the first address mapping unit reads the configuration value in the configuration register to determine the corresponding first cross-chip port.

[0088] If it is determined that the cross-chip access request does not have endpoint ordering properties, the first address mapping unit continues to perform address interleaving calculation on the target address of the cross-chip access request. For example, the first address mapping unit can calculate the target address according to a pre-configured cache line interleaving, hash interleaving, or address segmentation method to obtain a port index, and then look up the mapping table based on the port index to obtain the target identifier of the corresponding first cross-chip port. Subsequently, the requesting node or the on-chip interconnect network can route the cross-chip access request to the corresponding cross-chip port proxy based on the target identifier, and send it to the second chip through the cross-chip port proxy.

[0089] In this way, consistent access requests can be interleaved and mapped according to the destination address to utilize multiple cross-chip ports for access traffic transmission. Endpoint-ordered access requests are centrally transmitted and processed via a pre-defined cross-chip port proxy. Since endpoint-ordered access requests are not distributed to multiple relatively independent cross-chip port proxies due to different destination addresses, the complexity of order coordination among multiple cross-chip port proxies can be reduced, and a unified port proxy processing context can be provided to meet the endpoint-side order requirements corresponding to the EndpointOrder attribute.

[0090] As an optional embodiment, the field value of the Order field segment of the endpoint-preserving access request is EndpointOrder. The field value of the Order field segment of the cross-chip access request can also be detected by the first address mapping unit. In response to the field value of the Order field segment being EndpointOrder, the interleaving calculation for the target address is skipped. A preset cross-chip port among the multiple cross-chip ports participating in interleaving in the first chip is determined as the first cross-chip port. The cross-chip access request is sent through the cross-chip port proxy corresponding to the first cross-chip port, so that cross-chip access requests with the endpoint-preserving attribute are maintained in order by the same cross-chip port proxy. The preset cross-chip port is pre-configured by software.

[0091] In the above optional embodiments, the first address mapping unit can also detect the field value of the Order field segment carried in the cross-chip access request, and determine whether the cross-chip access request has an endpoint order preservation attribute based on the field value of the Order field segment.

[0092] Specifically, in the CHI protocol-based implementation, cross-chip access requests can carry an Order field segment indicating transaction order requirements. Upon receiving a cross-chip access request from a requesting node, the first address mapping unit can first parse the Order field segment in the request. If the Order field segment indicates that the value of the Order field segment in the cross-chip access request is an Endpoint Order attribute, then the first address mapping unit determines that the cross-chip access request has an endpoint ordering attribute. If no Order field segment indicates an Endpoint Order attribute, then the first address mapping unit can determine that the cross-chip access request does not have an endpoint ordering attribute and perform port selection for the target address according to the normal address interleaving process.

[0093] In response to the value of the Order field being Endpoint Order, the first address mapping unit skips the interleaving calculation for the target address, or does not use the port index obtained by performing interleaving calculation for the target address, but instead reads a pre-configured fixed port configuration item. The fixed port configuration item indicates a preset cross-chip port among multiple cross-chip ports participating in interleaving in the first chip. The first address mapping unit identifies this preset cross-chip port as the first cross-chip port and sends the cross-chip access request through the cross-chip port proxy corresponding to the first cross-chip port.

[0094] For example, in a scenario where four cross-chip ports are set between the first chip and the second chip, the first chip includes four cross-chip ports: C2C port0, C2C port1, C2C port2, and C2C port3. During system startup, the software can configure C2C port0 as a preset cross-chip port corresponding to a cross-chip access request with endpoint ordering attributes through configuration registers. When a requesting node in the first chip initiates a normal cross-chip access request, the first address mapping unit can perform interleaving calculations such as cache line interleaving, hash interleaving, or address segmentation based on the target address of the request, and allocate the normal cross-chip access request to one of the ports from C2C ​​port0 to C2C port3 to achieve multi-port bandwidth balancing.

[0095] When a requesting node in the first chip initiates a cross-chip access request with an Endpoint Order attribute, even if the target address carried in the request might correspond to C2C port1, C2C port2, or C2C port3 according to a normal interleaving algorithm, the first address mapping unit uses bypass processing to directly map the cross-chip access request to the pre-configured C2C port0. Subsequently, the cross-chip access request is sent to the second chip via the cross-chip port proxy corresponding to C2C port0.

[0096] In this way, all cross-chip access requests with endpoint ordering attributes are transmitted and processed centrally through the same cross-chip port proxy. Since the same cross-chip port proxy can maintain the order of requests within its own transaction processing context, it can avoid such requests being distributed to multiple independent cross-chip port proxies for processing due to different addresses. This reduces the complexity of cross-port order coordination and satisfies the endpoint ordering constraint required by the Endpoint Order attribute.

[0097] In other words, by bypassing Endpoint Order type accesses and centralizing order-preserving requests to a fixed port, the complexity of cross-port order coordination can be reduced, providing a unified port proxy processing context for meeting the endpoint-side order requirements corresponding to the Endpoint Order attribute in the CHI protocol. Alternatively, the same cross-chip port proxy can process endpoint order-preserving access requests according to the order requirements specified in the CHI protocol, thereby satisfying the endpoint-side order constraints corresponding to the Endpoint Order attribute.

[0098] Furthermore, the preset cross-chip port can be pre-configured during system startup based on system topology, port availability, link load planning, or protocol ordering requirements. For example, after determining the number of cross-chip ports and their physical connections between the first and second chips, a port can be selected from the multiple cross-chip ports involved in interleaving as the fixed port for endpoint ordering requests, and the port identifier or target identifier of this fixed port can be written into the software configuration register corresponding to the first address mapping unit. When the first address mapping unit subsequently detects a cross-chip access request with endpoint ordering attributes, it can directly read the configuration value in the software configuration register to determine the corresponding first cross-chip port.

[0099] The above embodiment is equivalent to setting an endpoint-preserving bypass branch for ordinary address interleaving paths. That is, ordinary cross-chip access requests continue to be distributed to multiple cross-chip ports through target address interleaving to improve link bandwidth utilization; cross-chip access requests with endpoint-preserving attributes are fixedly mapped to a preset cross-chip port to ensure that the order relationship of such requests is uniformly maintained by the same cross-chip port. Therefore, without introducing a global sorting mechanism across multiple cross-chip ports, both bandwidth balancing for ordinary access traffic and the protocol ordering requirements of endpoint-preserving requests can be simultaneously addressed.

[0100] Step 103: Send the cross-chip access request to the second chip via the determined first cross-chip port.

[0101] Specifically, in step 103, after determining the first cross-chip port, the first chip can route the cross-chip access request via the on-chip interconnect network to the corresponding cross-chip port proxy based on the target identifier of the first cross-chip port. The cross-chip port proxy then sends the request to the second chip via the cross-chip physical link. After receiving the cross-chip access request, the corresponding cross-chip port in the second chip that is physically directly connected to the first cross-chip port can inject the request into the on-chip interconnect network of the second chip and further route it to the home node in the second chip for processing.

[0102] Step 104: In response to the home node in the second chip initiating a consistency maintenance transaction for the target address, the target address is interleaved by the second address mapping unit set in the home node, and the second cross-chip port corresponding to the consistency maintenance transaction is determined based on the physical connection relationship of multiple cross-chip ports between the first chip and the second chip.

[0103] The home node can be a functional node in the second chip used to manage the consistency state corresponding to the target address. Consistency maintenance transactions can include probe transactions initiated against the target address, such as snoop transactions. The second address mapping unit is located in the home node, and the second address mapping unit uses the same interleaving algorithm as the first address mapping unit. That is, for the same target address, the second address mapping unit can obtain the port index corresponding to the first address mapping unit.

[0104] Furthermore, since the cross-chip port identifiers on the first chip and the second chip may be different, the second address mapping unit also determines the second cross-chip port corresponding to the consistency maintenance transaction based on the physical connection relationship of multiple cross-chip ports between the first chip and the second chip. For example, if a cross-chip port in the first chip is physically directly connected to a cross-chip port in the second chip, the second address mapping unit can map the port index corresponding to the target address to the target identifier of the corresponding cross-chip port on the second chip side according to the physical connection relationship.

[0105] As an optional embodiment, in step 104, the second address mapping unit set in the home node performs interleaving calculation on the target address to determine the second cross-chip port corresponding to the consistency maintenance transaction. This includes: performing interleaving calculation on the target address using an interleaving algorithm consistent with the first address mapping unit to obtain a target index corresponding to the port index; querying the second mapping table according to the target index to obtain the target identifier of the corresponding second cross-chip port; and routing the consistency maintenance transaction to the corresponding cross-chip port proxy via the on-chip interconnect of the second chip according to the target identifier of the second cross-chip port.

[0106] The second mapping table is configured by the physical connection relationship of multiple cross-chip ports between the first chip and the second chip, so that the second cross-chip port and the first cross-chip port form a pair of cross-chip ports that are physically directly connected.

[0107] For example, the second mapping table can be a lookup table on the second chip side used to convert the target index (or port index) into the cross-chip port target identifier (target id) on the second chip side. Since the cross-chip port identifier and NoC routing target identifier on the first chip side and the second chip side may be inconsistent, after obtaining the target index corresponding to the target address, the second address mapping unit can use the second mapping table to map the target index to the target id of the corresponding cross-chip port agent (C2Cagent) on the second chip side, so that the consistency maintenance transaction can be routed to the correct cross-chip port agent and issued in the second chip intra-chip interconnect.

[0108] Optionally, the second mapping table may contain at least the following information: a target index field and a target identifier field. The target index field represents the result of the interleaving operation performed by the second address mapping unit based on the target address. Its bit width corresponds to the number of cross-chip ports participating in the interleaving; for example, when the number of interleaving ports is 4, the target index can be 2 bits. The target identifier field represents the target id or node id of the cross-chip port proxy on the second chip side, enabling the on-chip interconnect to route consistency maintenance transactions to the corresponding cross-chip port proxy. Optionally, the second mapping table may also contain an enable bit or a valid bit to indicate whether the mapping corresponding to a certain target index is effective, supporting scenarios such as port masking, faulty port degradation, or system reconfiguration.

[0109] In one implementation, the second mapping table can be obtained by firmware or BIOS configuration during system startup. Specifically, the number of cross-chip ports between the first and second chips and the physical connection relationships between these ports can be determined first, and the target IDs proxied by each cross-chip port on the second chip side can be obtained. Subsequently, a mapping relationship between the target index and the target ID on the second chip side is established based on the physical connection relationships, and this mapping relationship is written into the second mapping table. For example, if four cross-chip ports are set up between two chips and a symmetrical direct connection topology is adopted, and the C2C port0, C2C port1, C2C port2, and C2C port3 on the first chip side are physically directly connected to the C2C port0, C2C port1, C2C port2, and C2C port3 on the second chip side, then the second mapping table can be configured as follows: target index 0 is mapped to the target id of C2C port0 on the second chip side, target index 1 is mapped to the target id of C2C port1 on the second chip side, target index 2 is mapped to the target id of C2C port2 on the second chip side, and target index 3 is mapped to the target id of C2C port3 on the second chip side. Alternatively, in asymmetric wiring or port rearrangement scenarios, the second mapping table can also be configured as a cross-mapping according to the actual physical connection relationship. For example, when the first chip side C2C port0 is physically directly connected to the second chip side C2C port2, the target index 0 can be mapped to the target id of the second chip side C2C port2, thereby ensuring that the target index calculated for the same target address is ultimately directed to the corresponding physically connected port.

[0110] In step 104, when the home node (HN) of the second chip needs to initiate a snoop transaction for the target address addr due to consistency maintenance, the second address mapping unit (which can be understood as the SAM module integrated on the HN side) performs an interleaving operation on addr consistent with that on the first chip side to obtain the target index. Subsequently, the second address mapping unit queries the second mapping table to obtain the target id of the cross-chip port agent on the second chip side corresponding to the target index, and uses this target id as the routing target of the snoop transaction, so that the snoop transaction is routed to the corresponding cross-chip port agent via the on-chip interconnect of the second chip. For example, the snoop flit uses the target id as the routing target, and is routed to the corresponding C2C port agent via the NoC on chip B. Then, the cross-chip port agent sends the snoop transaction to the cross-chip port in the first chip that is physically directly connected to it through the physical link. Since the second mapping table is configured based on the actual physical connection relationship between the cross-chip ports of the two chips, the snoop transaction initiated by the second chip can converge with the cross-chip access request issued by the first chip for the same target address to the same pair of physically directly connected cross-chip ports. This reduces the complexity of collaborative processing caused by the dispersion of co-address consistency transactions among multiple independent port proxies and improves the correctness and reliability of cross-chip consistency maintenance.

[0111] Step 105: Send the consistency maintenance transaction to the first chip via the second cross-chip port, so that the cross-chip access request and the consistency maintenance transaction are transmitted via the same pair of physically connected cross-chip ports.

[0112] In the above steps, the second chip can route consistency maintenance transactions to the corresponding cross-chip port proxy via its on-chip interconnect network, using the second cross-chip port as the routing target. The cross-chip port proxy then sends the transactions to the first chip via the cross-chip physical link. Since the second address mapping unit and the first address mapping unit use the same interleaving algorithm, and the second cross-chip port is determined based on the physical connection relationships between multiple cross-chip ports, cross-chip access requests and consistency maintenance transactions targeting the same address can be transmitted via the same pair of physically connected cross-chip ports.

[0113] Further optionally, for the same target address, the cross-chip access request and the probe transaction are restricted to be transmitted via the same pair of physically connected cross-chip ports, so that the consistency transactions related to the target address are ordered within the same port proxy context.

[0114] As an optional embodiment, the consistency maintenance transaction includes a probe transaction initiated for the target address, wherein the probe transaction is a snoop transaction. Based on this, in response to the home node in the second chip initiating the probe transaction, the target address is interleaved using the second address mapping unit to obtain a target index; the target index is used to query the mapping lookup table to obtain the target identifier of the corresponding second cross-chip port on the second chip side; the probe transaction is routed to the corresponding cross-chip port proxy via the on-chip interconnect of the second chip using the target identifier of the second cross-chip port as the routing target; the probe transaction is sent to the first chip via the corresponding cross-chip port proxy; wherein the probe transaction and the cross-chip access request for the same target address are transmitted via the same pair of physically directly connected cross-chip ports.

[0115] In this context, a probe transaction can be understood as a transaction used during consistency maintenance to probe or query the cache status of a target address. It determines whether the data corresponding to the target address is cached by other nodes, the consistency state of the cache, and whether operations such as write-back, invalidation, or privilege revoke are required. Probe transactions are typically initiated by the home node. Before the initiator processes an access request or consistency state change for a target address, it probes the status of other nodes that may hold cached copies of that target address, thereby achieving the state convergence required for consistency maintenance. In other words, probe transactions are a type of maintenance transaction in the consistency protocol, their purpose being to support consistency state management rather than directly completing data read / write transmission.

[0116] Snoop transactions can be understood as a specific implementation of probe transactions. In CHI-based implementations, the home node (e.g., HN) can initiate a snoop against a target address to send probe requests to requesting nodes that may cache data at that target address, in order to obtain or drive the peer node to perform corresponding consistency actions, such as returning cache state information, invalidating, writing back, or returning data. Therefore, in this embodiment, a probe transaction initiated against a target address can be specifically defined as a snoop transaction, that is, a probe transaction is used to detect the cache state related to the target address and trigger consistency actions.

[0117] Based on this, in response to the snoop transaction initiated by the home node in the second chip, the second address mapping unit performs an interleaving calculation on the target address to obtain a target index. The second address mapping unit uses the same interleaving algorithm as the first address mapping unit, so that an index result corresponding to the first chip side can be obtained for the same target address. Subsequently, the second address mapping unit queries the mapping lookup table according to the target index to obtain the target identifier of the second cross-chip port corresponding to the second chip side (e.g., the target id of the C2C port agent on the second chip side). The second chip routes the snoop transaction with the target identifier as the routing target, via the on-chip interconnect network of the second chip to the corresponding cross-chip port agent (C2C port agent), and sends the snoop transaction to the first chip through the cross-chip port agent. In scenarios where multiple cross-chip ports are set between two chips, since the mapping lookup table is configured according to the physical connection relationship of the cross-chip ports between the two chips, the snoop transaction can be directed to the cross-chip port physically corresponding to the cross-chip access request on the first chip side, so that the snoop transaction and the cross-chip access request for the same target address are transmitted through the same pair of physically directly connected cross-chip ports.

[0118] For example, in a scenario where two chips are interconnected across four ports, the HN on the second chip side needs to initiate a snoop to a certain cacheline (addr) on the first chip side for consistency maintenance. The second address mapping unit integrated within the HN performs interleaving calculations on the addr to obtain an index, and queries the mapping lookup table to obtain the target id of the corresponding C2C port on the second chip side. The snoopflit uses this target id as the routing target, routes it through the second chip's intra-chip interconnection network to the corresponding C2C port agent, and then the C2C port agent sends the snoop to the physically directly connected cross-chip port in the first chip via the physical link. Thus, the snoop initiated by the second chip side against addr and the cross-chip access request initiated by the first chip side against addr can both fall into the same pair of physically directly connected cross-chip ports and be processed in the corresponding cross-chip port proxy context.

[0119] In this way, when the home node in the second chip initiates a probe transaction targeting a target address, it can determine the corresponding cross-chip port based on the mapping logic consistent with the first address mapping unit. Then, combining the physical connection relationships between the cross-chip ports, it routes the probe transaction to the physically corresponding cross-chip port proxy, ensuring that the probe transaction and cross-chip access requests targeting the same target address are transmitted via the same physically directly connected pair of cross-chip ports. This reduces the collaborative processing complexity caused by consistency transactions related to the same address being distributed across different cross-chip port proxies, and improves the reliability of cross-chip consistency maintenance and the correctness of protocol processing.

[0120] As an optional embodiment, this application embodiment also includes a return path for the response transaction. In response to the second chip completing the processing of the cross-chip access request, the home node or slave node in the second chip generates a response transaction corresponding to the cross-chip access request. The response transaction may include read response, write response, completion response, or completion response carrying data, etc., and is used to return the access processing result, data, or completion status to the first chip.

[0121] When generating a response transaction, the node identifier of the cross-chip port proxy that receives the cross-chip access request in the second chip is determined as the target identifier of the response transaction. Specifically, after the cross-chip access request issued by the first chip reaches the second chip via the first cross-chip port, it is received by the cross-chip port in the second chip that is physically directly connected to the first cross-chip port. The cross-chip port proxy corresponding to that cross-chip port then injects the cross-chip access request into the on-chip interconnect network of the second chip as a request proxy node. For the home node or slave node in the second chip, the cross-chip port proxy can be identified as the request source node of the cross-chip access request on the second chip side. Therefore, when generating a response transaction, the node identifier of the cross-chip port proxy can be used as the target identifier of the response transaction.

[0122] The second chip routes the response transaction via its on-chip interconnect network to the cross-chip port proxy that receives the cross-chip access request, based on the target identifier of the response transaction. Upon receiving the response transaction, the cross-chip port proxy returns the response transaction to the corresponding cross-chip port in the first chip via its corresponding cross-chip port and the cross-chip link physically connected to the first chip. Thus, the response transaction can return along the cross-chip port proxy that receives the cross-chip access request, forming a request-response closed loop corresponding to the cross-chip access request.

[0123] For example, in a scenario where four cross-chip ports are set up between the first chip and the second chip, if a cross-chip access request for a target address is sent from the first chip via its C2C port1 and received by the cross-chip port proxy corresponding to its physically directly connected C2C port1 in the second chip, then after processing the cross-chip access request, the second chip determines the node identifier of the cross-chip port proxy corresponding to its C2C port1 as the target identifier of the response transaction. Subsequently, the response transaction is routed in the second chip's intra-chip interconnect network to the cross-chip port proxy corresponding to its C2C port1, and then returned to the first chip's C2C port1 via the cross-chip port proxy.

[0124] In this way, the target identifier of the response transaction is bound to the cross-chip port proxy that actually receives the cross-chip access request on the second chip side, eliminating the need to re-perform port selection based on the target address. This leverages the correspondence between the request source node and the response target node in the consistency protocol to ensure that the response transaction can return to the cross-chip port corresponding to the original request path, while avoiding the additional path selection complexity introduced by redistributing the response transaction among multiple independent cross-chip port proxies.

[0125] As an optional embodiment, the embodiments of this application can also be applied to a multi-chip interconnect system including three or more chips. This multi-chip interconnect system can adopt a full interconnect, partial interconnect, or hierarchical interconnect topology. Specifically, for any two chips with a direct cross-chip consistency interconnect relationship, multiple cross-chip ports can be set between the two chips. These multiple cross-chip ports can be C2C ports and act as consistency proxies supporting the CHI consistency protocol, accessing the interconnect network within their respective chips.

[0126] A multi-chip system comprises at least three chips, with multiple cross-chip ports between any two chips. For each of the multiple cross-chip ports between any two chips, a corresponding interleaving algorithm, interleaving granularity, correspondence between port index and cross-chip port target identifier, and mapping lookup table are configured to ensure that the cross-chip consistent interconnect mapping between any two chips is independent of each other.

[0127] In multi-chip expansion scenarios, this application embodiment does not require all chips to adopt a unified global SAM configuration. Instead, it configures the cross-chip port mapping relationship between any two chips independently, using chip pairs as the configuration granularity. Specifically, for any two chips, such as chip i and chip j, a first SAM parameter corresponding to chip i accessing chip j, a second SAM parameter corresponding to chip j accessing chip i, and a port mapping table matching the physical connection relationship between chip i and chip j can be configured respectively. The SAM parameters may include at least one of the following: interleaving algorithm, interleaving granularity, number of cross-chip ports participating in interleaving, address bit range used for port index calculation, hash calculation method, and address segmentation rules. The port mapping table may include the correspondence between port indexes and local cross-chip port target identifiers, and / or the correspondence between port indexes and physically directly connected cross-chip ports on the other side.

[0128] For a regular cross-chip access request between chip i and chip j, the SAM in the requesting node in chip i can perform interleaving calculation on the target address based on the SAM parameters corresponding to the chip pair i and j to obtain the port index. Then, it converts this port index into a cross-chip port target identifier on chip i based on the mapping table on chip i. Correspondingly, when the home node on chip j needs to initiate a consistency maintenance transaction to chip i for the same target address, the SAM on chip j can use the same interleaving algorithm and interleaving granularity as the configuration on chip i to calculate the port index. Based on the mapping table configured independently for the chip pair on chip j, it determines the cross-chip port on chip j that is physically directly connected to the selected cross-chip port on chip i. Thus, cross-chip access requests and consistency maintenance transactions for the same target address can converge to the same physically corresponding pair of cross-chip ports for transmission between chip i and chip j.

[0129] Furthermore, in a system comprising N chips, a set of SAM configuration items and a set of port mapping tables can be maintained for each chip pair requiring cross-chip consistent access. For example, chip 0 and chip 1 can use a first interleaving granularity and a first port mapping table; chip 0 and chip 2 can use a second interleaving granularity and a second port mapping table; and chip 1 and chip 2 can use a third interleaving algorithm and a third port mapping table. The SAM parameters and mapping tables between the different chip pairs are independent of each other. When the number of ports, physical connection order, link bandwidth, address interleaving method, or port mapping relationship of any chip pair changes, only the configuration items corresponding to that chip pair need to be adjusted, without changing the SAM parameters and mapping tables of other chip pairs.

[0130] Through the above methods, the embodiments of this application can extend the symmetric mapping mechanism between two chips to multi-chip interconnect scenarios, and independently maintain the port correspondence between cross-chip access requests and consistency maintenance transactions on an independent basis for any two chips. Since the SAM interleaving parameters and port mapping tables between each chip pair do not affect each other, the embodiments of this application can adapt to situations where the number of ports, physical connection relationships, or service traffic distributions are inconsistent between different chip pairs. Furthermore, it avoids introducing complex global port sorting or cross-chip global consistency arbitration mechanisms into multi-chip systems, thereby improving the topology expansion capability and configuration flexibility of multi-chip systems while ensuring the correctness of the CHI consistency protocol. As a scalable embodiment, the embodiments of this application can also be applied to multi-chip systems including at least three chips. In the multi-chip system, multiple cross-chip ports can be set between any two chips with cross-chip consistency access requirements. The cross-chip ports can be C2C ports and act as consistency proxies to access the on-chip interconnect network within the corresponding chip to support cross-chip transaction transmission based on the CHI consistency protocol.

[0131] In this multi-chip system, this embodiment uses any two chips forming a chip pair as the configuration granularity, configuring the address mapping parameters and port mapping relationships between the chip pairs respectively. Specifically, for any two chips, for multiple cross-chip ports between the two chips, corresponding interleaving algorithms, interleaving granularity, the number of cross-chip ports participating in interleaving, the correspondence between port indices and cross-chip port target identifiers, and mapping lookup tables can be configured respectively. Thus, the cross-chip consistent interconnect mapping between any two chips can be determined independently, and the configurations of each chip pair do not affect each other.

[0132] For example, in a multi-chip system including chip i, chip j, and chip k, a first set of SAM interleaving parameters and a first set of port mapping tables can be configured between chip i and chip j; a second set of SAM interleaving parameters and a second set of port mapping tables can be configured between chip i and chip k; and a third set of SAM interleaving parameters and a third set of port mapping tables can be configured between chip j and chip k. Each of these configurations can be determined based on the physical connection relationship between the corresponding chip pairs, the number of cross-chip ports, link bandwidth, and service traffic distribution, without requiring different chip pairs to use the exact same number of ports or physical connection order.

[0133] For any cross-chip access request between two chips, the requesting node in the initiating chip, or its corresponding first address mapping unit, performs interleaving calculation on the target address according to the interleaving algorithm and interleaving granularity of the chip, obtains a port index, and converts the port index into a target identifier of the cross-chip port on the initiating side through the port mapping table of the chip, so that the cross-chip access request is sent through the determined cross-chip port. Correspondingly, when the home node in the receiving chip needs to initiate a consistency maintenance transaction to the initiating chip for the same target address, the second address mapping unit in the receiving chip calculates the port index using the same interleaving algorithm and interleaving granularity as the initiating side, and converts the port index into a target identifier of the local cross-chip port that is physically directly connected to the cross-chip port selected by the initiating side through the mapping lookup table configured for the chip on the receiving side.

[0134] With the above configuration, for the same target address between any two chips, cross-chip access requests and corresponding consistency maintenance transactions can converge to the same physically corresponding pair of cross-chip ports based on the same port index, thus continuing to guarantee the consistency and coordination of co-address transactions in multi-chip expansion scenarios. Since each chip pair independently maintains SAM interleaving parameters and port mapping tables, when the number of ports, physical connection relationships, interleaving granularity, or mapping relationships between a chip pair change, only the configuration items corresponding to that chip pair need to be adjusted, without affecting the cross-chip consistency interconnection mapping between other chip pairs.

[0135] Furthermore, in a fully interconnected topology consisting of N chips, any two chips can be independently configured with corresponding SAM interleaving parameters and port mapping tables in the manner described above. In partially interconnected or hierarchical interconnected topologies, SAM interleaving parameters and port mapping tables can be configured only for chip pairs with direct cross-chip consistency interconnection relationships. By configuring independently on a chip pair basis, the embodiments of this application can extend the symmetric mapping mechanism between two chips to multi-chip systems. This avoids introducing a complex global port sorting mechanism and can adapt to situations where the physical topology and link resources of different chip pairs are inconsistent, thereby improving the scalability and configuration flexibility of the cross-chip consistency interconnection system.

[0136] In this embodiment, by setting a first address mapping unit on the requesting node side of the first chip and a second address mapping unit on the home node side of the second chip, ordinary cross-chip access requests can be interleaved and mapped according to the target address, thereby being allocated to multiple cross-chip ports. Simultaneously, consistency maintenance transactions initiated by the second chip for the same target address can use a consistent interleaving algorithm and combine physical connection relationships to determine the corresponding port, thus converging with cross-chip access requests onto the same pair of physically directly connected cross-chip ports for transmission. Furthermore, for cross-chip access requests with endpoint ordering attributes, this embodiment maps them to preset cross-chip ports in the first chip to avoid such requests being scattered by ordinary address interleaving. Therefore, this embodiment can reduce the complexity of cross-port collaborative processing of related consistency transactions and balance the correctness of consistency transaction processing, endpoint ordering requirements, and cross-chip port bandwidth utilization in scenarios where multiple cross-chip ports work in parallel.

[0137] See Figure 2 , Figure 2 A schematic diagram of a two-chip four-port interconnect system provided in an embodiment of this application is shown. Figure 2 In this multi-chip system, there are a first chip and a second chip. The first chip can correspond to chip A, and the second chip can correspond to chip B. Four cross-chip ports are provided between the first and second chips: C2C port0, C2C port1, C2C port2, and C2C port3. C2C port0 on the first chip side is physically directly connected to C2C port0 on the second chip side via Link 0; C2C port1 on the first chip side is physically directly connected to C2C port1 on the second chip side via Link 1; C2C port2 on the first chip side is physically directly connected to C2C port2 on the second chip side via Link 2; and C2C port3 on the first chip side is physically directly connected to C2C port3 on the second chip side via Link 3. All four cross-chip ports can act as intermediaries to access the on-chip interconnect network within their respective chips.

[0138] The first chip side may include multiple requesting nodes (RNs), such as RN0, RN1, RN2 to RNn. Requesting nodes can be CPU cores, GPUs, accelerators, or other functional nodes capable of initiating cross-chip access requests. Each requesting node can have a first address mapping unit, which can be implemented as a SAM on the RN side. To ensure consistent port selection results for cross-chip access requests from different requesting nodes targeting the same destination address, the first address mapping units in the multiple requesting nodes on the first chip side can be configured with consistent interleaving algorithms and mapping parameters. The second chip side may include one or more home nodes, each of which can have a second address mapping unit, which can be implemented as a SAM on the HN side. The second address mapping unit uses the same interleaving algorithm as the first address mapping unit and configures a mapping lookup table based on the physical connection relationship between the first and second chips. Thus, cross-chip access requests and consistency maintenance transactions corresponding to the same destination address can be mapped to the same physically directly connected pair of cross-chip ports.

[0139] See Figure 3 , Figure 3 This illustration shows a schematic diagram of an address interleaving mapping process provided in an embodiment of this application. When a requesting node initiates a cross-chip access request, the cross-chip access request carries the target address `addr`. The first address mapping unit first detects whether the cross-chip access request has an endpoint ordering attribute, such as whether the `Order` domain segment belongs to the `Endpoint Order` attribute. If the cross-chip access request has an endpoint ordering attribute, the first address mapping unit bypasses the ordinary address interleaving logic for the target address and directly maps the cross-chip access request to a fixed cross-chip port pre-configured in the software, and uses the target identifier proxied by the corresponding cross-chip port as the routing target. This process is equivalent to performing a bypass process on `Endpoint Order` type access, concentrating ordering requests on fixed ports, thereby ensuring the correct implementation of the CHI protocol's `EndpointOrder` semantics at the hardware level.

[0140] If the cross-chip access request does not have endpoint ordering properties, the first address mapping unit selects the corresponding interleaving method according to the software configuration and performs interleaving calculation on the target address addr. Interleaving methods can include cacheline interleaving, hash interleaving, and address segmentation. For cacheline interleaving, the address bits corresponding to the interleaving granularity and the number of ports participating in the interleaving can be extracted from the target address as the port index, i.e., a specific bit [x:y] of addr can be directly taken as the index; for example, 2 bits can be taken as the index in a four-port scenario. For hash interleaving, multiple bit groups in the target address can be XORed and folded, and the low-order bits or specified bits of the result can be taken as the index, i.e., XORing multiple bit groups of addr can be performed, and the low-order bits can be taken as the index. For address segmentation, the index can be determined according to the address range where the target address is located, i.e., the index is determined according to the addr range. After obtaining the index, the first address mapping unit queries the mapping table, converts the index into the target identifier target id of the cross-chip port agent, and routes the cross-chip access request to the corresponding C2C port agent according to the target id.

[0141] See Figure 4 , Figure 4 This illustration shows a mapping diagram from port indexes of the RN-side SAM and the HN-side SAM to cross-chip port target identifiers, provided in an embodiment of this application. Figure 4 As shown, after receiving the target address `addr`, the RN SAM on the first chip side (chip A side) calculates the port index `index` using an interleaving algorithm such as cache line interleaving, hash interleaving, or address segmentation (e.g., in a four-port scenario, `index` is 0 to 3). When the HN SAM on the second chip side (chip B side) initiates a consistency maintenance transaction (such as a snoop target) for the same target address `addr`, it uses the same interleaving algorithm as the RN SAM on the first chip side to calculate the port index `index` corresponding to that target address. In other words, for the same target address, the RN-side SAM and the HN-side SAM use the same interleaving algorithm, resulting in corresponding co-address indices.

[0142] After obtaining the same port index, both chips use their respective mapping lookup tables to convert the index into a specific cross-chip port target ID. Specifically, the first mapping table (software configuration) on the first chip side maps index 0 to the target ID TID_A0 corresponding to the first chip side C2C Port0, index 1 to TID_A1, index 2 to TID_A2, and index 3 to TID_A3. Correspondingly, the second mapping table on the second chip side, based on the physical connection relationship, maps index 0 to the target ID TID_B0 corresponding to the second chip side C2C Port0, index 1 to TID_B1, index 2 to TID_B2, and index 3 to TID_B3.

[0143] It should be noted that, although Figure 4 The diagram illustrates the ideal situation where the port numbers on both sides correspond one-to-one (i.e., Link0 connects Port0_A and Port0_B, and so on). However, in practical applications, if there is port reordering in the physical connection relationship (e.g., Link0 actually connects Port0_A and Port2_B), the second mapping table can be configured as a cross mapping according to the actual physical connection relationship, without requiring the port numbers on both sides to be completely consistent.

[0144] pass Figures 2 to 4 As illustrated in the example, this embodiment configures a consistent first address mapping unit in multiple request nodes on the first chip side, and a second address mapping unit with the same algorithm as the first address mapping unit in the home node on the second chip side. It then uses a mapping table from port index to target identifier to implement the port selection result as the routing target for on-chip interconnection. This allows ordinary cross-chip access requests to be evenly distributed across multiple cross-chip ports, while simultaneously enabling consistency maintenance transactions related to the same target address to converge with cross-chip access requests to the same physically directly connected pair of cross-chip ports. For cross-chip access requests with endpoint ordering attributes, fixed port bypass processing ensures that such requests are uniformly maintained by the same cross-chip port.

[0145] The above describes a cross-chip coherent interconnect mapping method in the embodiments of this application. The following describes the cross-chip coherent interconnect mapping system that performs the above method.

[0146] See Figure 5 ,like Figure 5The diagram illustrates a cross-chip consistency interconnect mapping system, applicable to multi-chip interconnect scenarios supporting consistency protocols. In this embodiment, the cross-chip consistency interconnect mapping system implements the steps corresponding to the cross-chip consistency interconnect mapping method executed in the above method embodiments. The system's functionality can be implemented in hardware or by executing corresponding software. The hardware or software may include one or more modules corresponding to the above functions, which can be software modules and / or hardware modules. The cross-chip consistency interconnect mapping system in this embodiment may include a first chip and a second chip, with multiple cross-chip ports between them. These ports can facilitate transaction transmission between the first chip and the second chip through corresponding cross-chip physical links.

[0147] The system includes a first chip and a second chip, with multiple cross-chip ports provided between them. The first chip includes a request node and a first address mapping unit. The request node initiates a cross-chip access request for a target address. The request node can be a processor core, graphics processing unit, accelerator, DMA master device, or other functional node capable of initiating cross-chip access requests. The target address can be a physical address, a system-consistent address, or an address that, after address translation, can uniquely identify the accessed location in the consistency domain. The first address mapping unit can be located inside the request node or on the transaction path from the request node to the on-chip interconnect network of the first chip, and is used to perform port selection before the cross-chip access request enters the on-chip interconnect route.

[0148] The first address mapping unit is configured to: in response to the cross-chip access request not having an endpoint ordering attribute, perform interleaving calculation on the target address to determine the first cross-chip port corresponding to the cross-chip access request; in response to the cross-chip access request having an endpoint ordering attribute, determine a preset cross-chip port in the first chip as the first cross-chip port; The first chip is also configured to send the cross-chip access request to the second chip via a determined first cross-chip port; The second chip includes a home node and a second address mapping unit, wherein the home node is used to initiate a consistency maintenance transaction for the target address; The second address mapping unit is configured to: in response to the home node initiating a consistency maintenance transaction for the target address, perform interleaving calculation on the target address, and determine the second cross-chip port corresponding to the consistency maintenance transaction based on the physical connection relationship of multiple cross-chip ports between the first chip and the second chip, wherein the second address mapping unit and the first address mapping unit adopt the same interleaving algorithm; The second chip is also configured to send the consistency maintenance transaction to the first chip via the second cross-chip port, so that the cross-chip access request and the consistency maintenance transaction are transmitted via the same pair of physically connected cross-chip ports.

[0149] For example, if four cross-chip ports are set between the first chip and the second chip, the first address mapping unit obtains port index 1 based on the target address and sends the cross-chip access request to the second chip via C2C port 1 on the first chip side. If C2C port 1 on the first chip side and C2C port 1 on the second chip side are physically directly connected, the second address mapping unit can obtain the corresponding target index according to the same interleaving algorithm when initiating a snoop transaction for the same target address, and map the target index to the target identifier of C2C port 1 on the second chip side through the second mapping table. If C2C port 1 on the first chip side and C2C port 3 on the second chip side are physically directly connected in the actual wiring, the second mapping table can map the target index to the target identifier of C2C port 3 on the second chip side. Thus, even if the port numbers or node identifiers on both sides are different, it can be guaranteed that transactions related to the same target address are directed to the same pair of physically connected cross-chip ports.

[0150] The first cross-chip port is physically directly connected to the corresponding cross-chip port in the second chip.

[0151] The second chip is further configured to send the consistency maintenance transaction to the first chip via the second cross-chip port, so that the cross-chip access request and the consistency maintenance transaction are transmitted via the same pair of physically directly connected cross-chip ports. Specifically, the second chip can route the consistency maintenance transaction to the corresponding cross-chip port proxy via the on-chip interconnect network of the second chip, using the target identifier of the second cross-chip port as the routing target, and then the cross-chip port proxy sends it to the first chip via the corresponding cross-chip physical link. Since the second cross-chip port is determined based on the interleaving calculation result consistent with the first address mapping unit and the physical connection relationship between the cross-chip ports, cross-chip access requests and consistency maintenance transactions for the same target address can converge to the same pair of physically directly connected cross-chip ports.

[0152] In one alternative implementation, the first chip may include multiple request nodes, each with its own corresponding first address mapping unit, or multiple request nodes may share a first address mapping unit capable of performing port selection. During system startup, the same interleaving algorithm, interleaving granularity, number of cross-chip ports participating in interleaving, and the correspondence between port indices and cross-chip port target identifiers can be configured into the first address mapping units corresponding to multiple request nodes. Thus, cross-chip access requests from different request nodes targeting the same target address can obtain a consistent port index and be mapped to the same first cross-chip port, thereby preventing requests related to the same address from being distributed to different cross-chip port proxies due to different request nodes.

[0153] In one alternative implementation, the second chip may further be configured to: generate a response transaction in response to completing the processing of the cross-chip access request; determine the node identifier of the cross-chip port proxy that receives the cross-chip access request in the second chip as the target identifier of the response transaction; and, based on the target identifier of the response transaction, route the response transaction via the on-chip interconnect network of the second chip to the cross-chip port proxy that receives the cross-chip access request, and return it to the first chip via the cross-chip port corresponding to the cross-chip port proxy. In other words, the response transaction can return along the cross-chip port proxy that actually receives the cross-chip access request on the second chip side, without needing to re-select the port based on the target address, thereby forming a request-response closed loop corresponding to the cross-chip access request.

[0154] In one optional implementation, the system may further include a configuration unit. The configuration unit is used to determine the number of cross-chip ports between the first chip and the second chip and the physical connection relationships between the multiple cross-chip ports during the system startup phase, and to configure a first address mapping unit and a second address mapping unit according to the number of cross-chip ports and the physical connection relationships. Specifically, the configuration unit can write the interleaving mode, interleaving granularity, number of cross-chip ports participating in interleaving, and a first mapping table into the software configuration register corresponding to the first address mapping unit; and write the interleaving mode and interleaving granularity consistent with the first address mapping unit, and a second mapping table determined according to the physical connection relationships, into the software configuration register corresponding to the second address mapping unit. The configuration unit may be implemented by firmware, BIOS, boot controller, or system management processor; this application embodiment does not limit this.

[0155] For the parts of the above embodiments that do not overlap with the method embodiments, please refer to the relevant descriptions of the foregoing embodiments.

[0156] In this embodiment, by setting a first address mapping unit on the request node side of the first chip and a second address mapping unit on the home node side of the second chip, ordinary cross-chip access requests can be interleaved and mapped between multiple cross-chip ports according to the target address, thereby improving the bandwidth utilization of multiple cross-chip ports. Simultaneously, the second address mapping unit uses the same interleaving algorithm as the first address mapping unit and determines the second cross-chip port corresponding to the consistency maintenance transaction based on the physical connection relationship of multiple cross-chip ports between the first and second chips, enabling cross-chip access requests and consistency maintenance transactions targeting the same target address to be transmitted via the same pair of physically directly connected cross-chip ports. Furthermore, for cross-chip access requests with endpoint ordering attributes, the first address mapping unit maps them to a preset cross-chip port, allowing such requests to be centrally processed via the same cross-chip port. Therefore, the system provided in this embodiment can balance bandwidth balancing of ordinary cross-chip access traffic, path convergence of co-address consistency transactions, and order maintenance requirements of endpoint ordering transactions in scenarios where multiple cross-chip ports operate in parallel, thereby reducing the complexity of cross-port collaborative processing of related consistency transactions and improving the processing correctness and system scalability of cross-chip consistency interconnection.

[0157] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0158] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and modules described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0159] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, apparatuses, or modules, and may be electrical, mechanical, or other forms.

[0160] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0161] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0162] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0163] The computer program product includes one or more computer instructions. When the computer program is loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)).

[0164] The technical solutions provided in the embodiments of this application have been described in detail above. Specific examples have been used in the embodiments of this application to illustrate the principles and implementation methods of the embodiments of this application. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of the embodiments of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the embodiments of this application. Therefore, the content of this specification should not be construed as a limitation on the embodiments of this application.

Claims

1. A cross-chip coherent interconnect mapping method, characterized in that, The method is applied to a multi-chip system including a first chip and a second chip, wherein multiple cross-chip ports are provided between the first chip and the second chip, and the method includes: Receive cross-chip access requests initiated by the requesting node in the first chip and targeting a target address; In response to the cross-chip access request not having endpoint ordering attribute, the target address is interleaved by the first address mapping unit set in the request node to determine the first cross-chip port corresponding to the cross-chip access request; in response to the cross-chip access request having endpoint ordering attribute, a preset cross-chip port in the first chip is determined as the first cross-chip port, and the first cross-chip port is physically directly connected to the corresponding cross-chip port in the second chip. The cross-chip access request is sent to the second chip via a determined first cross-chip port; In response to the home node in the second chip initiating a consistency maintenance transaction for the target address, the second address mapping unit set in the home node performs interleaving calculation on the target address, and determines the second cross-chip port corresponding to the consistency maintenance transaction based on the physical connection relationship of multiple cross-chip ports between the first chip and the second chip, wherein the second address mapping unit and the first address mapping unit adopt the same interleaving algorithm; The consistency maintenance transaction is sent to the first chip via the second cross-chip port, so that the cross-chip access request and the consistency maintenance transaction are transmitted via the same pair of physically connected cross-chip ports.

2. The cross-chip coherent interconnect mapping method according to claim 1, characterized in that, The first chip is provided with multiple request nodes, and the method further includes: During the system startup phase, the number of cross-chip ports between the first chip and the second chip, as well as the physical connection relationships between multiple cross-chip ports, are determined. Based on the number of cross-chip ports and the physical connection relationship, a consistent interleaving algorithm and mapping parameters are configured for the first address mapping unit in multiple request nodes. The mapping parameters include the interleaving granularity, the number of cross-chip ports participating in the interleaving, and the correspondence between the port index and the target identifier of the first cross-chip port, so that cross-chip access requests from different request nodes for the same target address are mapped to the same first cross-chip port.

3. The cross-chip coherent interconnect mapping method according to claim 1, characterized in that, The step of performing interleaving calculations on the target address using a first address mapping unit configured in the request node to determine the first cross-chip port corresponding to the cross-chip access request includes: The target address is interleaved to obtain the port index; The first mapping table is queried according to the port index to obtain the target identifier of the corresponding first cross-chip port; Based on the target identifier of the first cross-chip port, the cross-chip access request is routed to the corresponding cross-chip port proxy via the on-chip interconnect of the first chip, and then sent to the second chip through the cross-chip port proxy.

4. The cross-chip coherent interconnect mapping method according to claim 3, characterized in that, The step of performing an interleaving operation on the target address to obtain the port index includes: In response to the interleaving mode being configured as cache line interleaving, the address bits corresponding to the interleaving granularity and the number of cross-chip ports participating in the interleaving are extracted from the target address and used as the port index; In response to the interleaving mode being configured as hash interleaving, an XOR folding operation is performed on multiple bit groups in the target address, and the port index is determined based on the XOR folding operation result; In response to the interleaving mode being configured for address segmentation, the port index is determined based on the address range in which the target address is located.

5. The cross-chip coherent interconnect mapping method according to claim 3, characterized in that, The step of performing interleaving calculations on the target address through a second address mapping unit set in the home node to determine the second cross-chip port corresponding to the consistency maintenance transaction includes: The target address is interleaved using the same interleaving algorithm as the first address mapping unit to obtain the target index corresponding to the port index; The second mapping table is queried according to the target index to obtain the target identifier of the corresponding second cross-chip port; Based on the target identifier of the second cross-chip port, the consistency maintenance transaction is routed to the corresponding cross-chip port proxy via the on-chip interconnect of the second chip; The second mapping table is configured by the physical connection relationship of multiple cross-chip ports between the first chip and the second chip, so that the second cross-chip port and the first cross-chip port form a pair of cross-chip ports that are physically directly connected.

6. The cross-chip coherent interconnect mapping method according to claim 1, characterized in that, The method further includes: During the system startup phase, the number of cross-chip ports between the first chip and the second chip, as well as the physical connection relationships between multiple cross-chip ports, are obtained. The number of cross-chip ports participating in interleaving is determined based on the number of cross-chip ports, and the correspondence between port indexes and cross-chip port target identifiers is determined based on the physical connection relationship. The interleaving method, interleaving granularity, number of cross-chip ports participating in interleaving, and the corresponding relationship are written into the software configuration registers corresponding to multiple request nodes in the first chip, so that the first address mapping units in multiple request nodes have a consistent interleaving configuration. Write the interleaving method and interleaving granularity consistent with the first address mapping unit into the software configuration register corresponding to the home node in the second chip, and write the mapping lookup table determined according to the physical connection relationship into the software configuration register corresponding to the home node to configure the second address mapping unit; Wherein, the interleaving granularity is a power of 2 in the number of bytes, and the number of cross-chip ports participating in the interleaving is a power of 2.

7. The cross-chip coherent interconnect mapping method according to claim 1, characterized in that, The consistency maintenance transaction includes a probe transaction initiated against the target address, wherein the probe transaction is a snoop transaction, and the method further includes: In response to the probe transaction initiated by the home node in the second chip, the target address is interleaved and calculated by the second address mapping unit to obtain the target index; The target identifier of the second cross-chip port corresponding to the second chip side is obtained by querying the mapping lookup table according to the target index. The probe transaction is routed to the corresponding cross-chip port proxy via the on-chip interconnect of the second chip, using the target identifier of the second cross-chip port as the routing target. The probe transaction is sent to the first chip via the corresponding cross-chip port proxy; The probe transaction and the cross-chip access request for the same target address are transmitted via the same pair of physically connected cross-chip ports.

8. The cross-chip coherent interconnect mapping method according to claim 1, characterized in that, The endpoint order preservation attribute includes the Endpoint Order attribute, and the method further includes: The field value of the Order field segment of the cross-chip access request is detected by the first address mapping unit; In response to the value of the field "Endpoint Order" in the Order field, the interleaving calculation for the target address is skipped; The preset cross-chip port among the multiple cross-chip ports involved in interleaving in the first chip is determined as the first cross-chip port; The cross-chip access request is sent through the cross-chip port proxy corresponding to the first cross-chip port, so that the cross-chip access requests with the endpoint ordering attribute are maintained in order by the same cross-chip port proxy. The preset cross-chip port is pre-configured by software.

9. A cross-chip coherent interconnect mapping system, characterized in that, The system includes a first chip and a second chip, with multiple cross-chip ports provided between the first chip and the second chip; the first chip includes a request node and a first address mapping unit, the request node being used to initiate a cross-chip access request for a target address; The first address mapping unit is configured to: in response to the cross-chip access request not having an endpoint ordering attribute, perform interleaving calculation on the target address to determine the first cross-chip port corresponding to the cross-chip access request; In response to the cross-chip access request having an endpoint ordering attribute, a preset cross-chip port in the first chip is determined as the first cross-chip port, wherein the first cross-chip port is physically directly connected to the corresponding cross-chip port in the second chip; The first chip is also configured to send the cross-chip access request to the second chip via a determined first cross-chip port; The second chip includes a home node and a second address mapping unit, wherein the home node is used to initiate a consistency maintenance transaction for the target address; The second address mapping unit is configured to: in response to the home node initiating a consistency maintenance transaction for the target address, perform interleaving calculation on the target address, and determine the second cross-chip port corresponding to the consistency maintenance transaction based on the physical connection relationship of multiple cross-chip ports between the first chip and the second chip, wherein the second address mapping unit and the first address mapping unit adopt the same interleaving algorithm; The second chip is also configured to send the consistency maintenance transaction to the first chip via the second cross-chip port, so that the cross-chip access request and the consistency maintenance transaction are transmitted via the same pair of physically connected cross-chip ports.

10. A chip, characterized in that, The chip includes a processor coupled to a transceiver for performing the cross-chip coherent interconnect mapping method as described in any one of claims 1-8.

Images