FPGA-based software and hardware cooperative dual-channel HyperRAM storage system

Abstract

The application discloses a kind of based on FPGA's software and hardware cooperation dual-channel HyperRAM storage system, comprising: FPGA chip, algorithm logic module is integrated in FPGA chip, soft core CPU and multi-bus address controller;FPGA chip is connected with first HyperRAM chip and second HyperRAM chip respectively, first HyperRAM chip and second HyperRAM chip adopt independent addressing mode, and the address range of two does not overlap each other;Multi-bus address controller according to the high level of access address, access request is routed to first HyperRAM chip or second HyperRAM chip;Multi-bus address controller is connected with algorithm logic module, soft core CPU, first HyperRAM chip and second HyperRAM chip respectively.The application uses two independent HyperRAM, and each interface bandwidth is independent, and the theoretical bandwidth of aggregation is 2 times of single-chip scheme.In multi-module concurrent access scene, effective aggregation bandwidth is close to two times of single-chip scheme, eliminates the memory access error, frame loss, CPU jam and other problems caused by insufficient bandwidth.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and more specifically to an FPGA-based hardware and software co-operated dual-channel HyperRAM storage system. Background Technology

[0002] Currently, existing storage systems employing a single HyperRAM chip and arbitration control, such as the published document "Design and Verification of HyperRAM Controller with Cache Acceleration" and the patent with publication number CN117906762A, use a single HyperRAM chip as external storage. They use a "HyperRAM multi-channel read / write arbitration module" built into the FPGA chip to arbitrate access requests from multiple hardware processing modules to the same chip. Each hardware module occupies the data bus in a time-sharing manner according to a preset infrared image processing flow to complete a fixed image processing task.

[0003] Although some solutions or FPGA development boards have two HyperRAM physical chips on board, they are logically treated as a unified memory pool or a shared address space. All access requests from hardware modules still need to be serialized through a central arbiter. When multiple modules request access simultaneously, bus conflicts and waiting occur, making it impossible to achieve independent and concurrent access to the two chips.

[0004] The single-chip HyperRAM used in the existing technology often suffers from insufficient bandwidth due to the hard upper limit of the physical bandwidth of a single HyperRAM chip, which makes it impossible to support high-resolution real-time processing. The single-chip architecture can only barely support applications with lower frame rates or lower resolutions, and cannot meet the actual needs of high-end infrared imaging systems.

[0005] Existing solutions using two physical HyperRAM chips often logically address them as a shared memory pool. Multiple hardware modules still need to access them serially through an arbitrator, inevitably resulting in waiting when multiple modules request access simultaneously. The arbitration mechanism introduces additional latency, making efficient parallel access impossible, and the actual aggregated bandwidth is lower than the sum of the theoretical bandwidths of the two chips.

[0006] Furthermore, when new image processing functions need to be added, the hardware logic module and its interface with the arbitrator need to be redesigned. It lacks general and scalable platform capabilities, resulting in long development cycles and low reusability.

[0007] Therefore, how to overcome the bandwidth limitations of a single chip under limited chip resources, achieve efficient parallel access of dual HyperRAM by multiple processing modules, and balance hardware processing performance with software control flexibility are technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0008] In view of the above problems, the present invention proposes an FPGA-based hardware and software co-operated dual-channel HyperRAM storage system to overcome or at least partially solve the above problems.

[0009] To achieve the above objectives, the present invention adopts the following technical solution:

[0010] This invention provides a hardware-software co-working dual-channel HyperRAM storage system based on FPGA, comprising: an FPGA chip, wherein the FPGA chip integrates an algorithm logic module, a soft-core CPU, and a multi-bus address controller; The FPGA chip is connected to a first HyperRAM chip and a second HyperRAM chip respectively. The first HyperRAM chip and the second HyperRAM chip use independent addressing methods and their address ranges do not overlap. The multi-bus address controller routes the access request to the first HyperRAM chip or the second HyperRAM chip according to the high bit level of the access address. The multi-bus address controller is connected to the algorithm logic module, the soft-core CPU, the first HyperRAM chip, and the second HyperRAM chip, respectively, to enable the algorithm logic module and the soft-core CPU to access the two HyperRAM chips in parallel and in a hybrid manner.

[0011] Furthermore, the FPGA chip also integrates a first HyperRAM controller and a second HyperRAM controller. The first HyperRAM controller is connected between the multibus address controller and the first HyperRAM chip, and the second HyperRAM controller is connected between the multibus address controller and the second HyperRAM chip.

[0012] Furthermore, the multi-bus address controller internally includes: The first AXI interconnect IP core and the second AXI interconnect IP core each have at least one Master interface and multiple Slave interfaces. The Master interface of the first AXI interconnect IP core is connected to the second AXI bus interface of the multi-bus address controller, which is used to connect to the first HyperRAM controller. The Master interface of the second AXI interconnect IP core is connected to the third AXI bus interface of the multi-bus address controller, which is used to connect to the second HyperRAM controller. The third AXI interconnect IP core has multiple Master interfaces and at least one Slave interface. The Slave interface of the third AXI interconnect IP core is connected to the first AXI bus interface of the multi-bus address controller. The first AXI bus interface is used to connect to the soft-core CPU. The multiple Master interfaces of the third AXI interconnect IP core are respectively connected to the input terminal of the first AXI interconnect IP core and the Slave interface of the second AXI interconnect IP core. The system also includes multiple bus conversion modules. The custom parallel bus interface of the bus conversion module is connected to the custom parallel bus interface of the multi-bus address controller. The custom parallel bus interface is used to connect to the algorithm logic module. The AXI ports of the multiple bus conversion modules are respectively connected to the Slave interface of the first AXI interconnect IP core and the Slave interface of the second AXI interconnect IP core.

[0013] Furthermore, the algorithm logic module includes multiple algorithm sub-modules, and there are multiple custom parallel bus interfaces. Each algorithm sub-module is connected to the multi-bus address controller through one of the custom parallel bus interfaces. The multiple algorithm sub-modules achieve concurrent access to the two HyperRAM chips through their respective custom parallel buses.

[0014] Furthermore, the bus conversion module is a MAXI_FifoRW_Bas module. Each MAXI_FifoRW_Bas module maintains an independent FIFO buffer for each custom parallel bus. When multiple custom parallel buses request to access the same HyperRAM chip, the access is non-blocking queuing is achieved through the FIFO buffer.

[0015] Furthermore, each of the aforementioned custom parallel bus interfaces includes a write operation signal group and a read operation signal group; The write operation signal group includes: write operation base address signal, write operation clock signal, write operation reset signal, write operation address offset signal, write operation enable signal, and write operation data signal; The read operation signal group includes: read operation base address signal, read operation clock signal, read operation reset signal, read operation address offset signal, read operation enable signal, and read operation data signal.

[0016] Furthermore, the soft-core CPU accesses the multi-bus address controller through the first AXI bus interface of the multi-bus address controller, and routes the access request to the AXI bus corresponding to the first HyperRAM chip or the AXI bus corresponding to the second HyperRAM chip through address high-order bit decoding, thereby achieving selective access to the two HyperRAM chips.

[0017] Furthermore, the algorithm logic module is an infrared image processing module, used to execute infrared image processing algorithms including detector driving, non-uniformity correction, filtering enhancement, and video output driving.

[0018] Furthermore, the soft-core CPU is a RISC-V soft core, running a lightweight operating system, used to dynamically configure the working parameters of the algorithm logic module based on the image parameter information fed back by the algorithm logic module.

[0019] Furthermore, the multi-bus address controller is also connected to a fourth AXI bus interface for expanding the connection to the third HyperRAM chip and the corresponding third HyperRAM controller, so as to form a three-channel or more HyperRAM storage system.

[0020] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a hardware and software co-operated dual-channel HyperRAM storage system based on FPGA, which has the following beneficial effects: This invention employs two independent HyperRAM chips, each with independent interface bandwidth, resulting in a theoretical aggregate bandwidth that is twice that of a single-chip solution. In scenarios with concurrent access from multiple modules, the effective aggregate bandwidth is nearly twice that of a single-chip solution, eliminating problems such as memory access errors, frame drops, and CPU lag caused by insufficient bandwidth. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 This is a structural diagram of the HyperRAM storage system provided in an embodiment of the present invention; Figure 2 This is a diagram of the internal structure of the FPGA chip provided in an embodiment of the present invention; Figure 3 This is a diagram showing the internal structure of the multi-bus address controller provided in an embodiment of the present invention; Figure 4 This is a flowchart illustrating the hardware and software collaboration process provided in this embodiment of the invention. Figure 5 The image provided in this embodiment of the invention is a 1280×1024@50fps infrared image. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] This invention discloses a hardware-software co-operated dual-channel HyperRAM storage system based on FPGA, such as... Figure 1 As shown, it includes: FPGA chip, HyperRAM chip, FLASH, crystal oscillator and power module.

[0025] In one embodiment, two HyperRAM chips are respectively connected to the dedicated memory interface pins of the FPGA chip, the output of the crystal oscillator XTAL is connected to the dedicated clock input pin of the FPGA chip to provide a reference clock for the entire system, and the FLASH is connected to the general-purpose I / O pins of the FPGA chip through the SPI interface to store the FPGA configuration bitstream file and user data.

[0026] In this embodiment, an active crystal oscillator is used, with an output clock frequency of 50MHz or 100MHz, which can directly provide a reference clock for the PLL inside the FPGA. The HyperRAM chip used is Winbond W958D6NW, the FPGA chip used is EileenTi120, and the FLASH uses NOR FLASH with an SPI interface. The specific model is not described here.

[0027] The power module provides a stable DC power supply to all components of the system. Specifically, the power module receives an externally input 12V or 5V DC power and steps it down to the required voltage rail via a DC-DC converter or LDO. The power module provides the FPGA chip with a core voltage of 0.85V (VCCINT) and a voltage of 1.8V (VCCIO) for matching the levels of the HyperRAM chip, FLASH chip, and crystal oscillator interface. The power module provides a 1.8V operating voltage for the two HyperRAM chips; The power module provides a 1.8V operating voltage to the FLASH chip; The power module provides a 1.8V operating voltage for the crystal oscillator.

[0028] The power module also includes a power-on timing control circuit to ensure that the FPGA's core voltage VCCINT powers on before the I / O voltage VCCIO, or powers on according to the timing sequence specified in the Ti120 datasheet, to guarantee reliable FPGA configuration. Simultaneously, the power module includes a power monitoring chip that outputs a reset signal to the FPGA after monitoring the core voltage to ensure correct system power-on reset timing.

[0029] In one embodiment, the internal composition of the FPGA chip is as follows: Figure 2 As shown, it includes an infrared image processing module (IR_ISP), a soft core (CPU), two HyperRAM controllers (HPRAM_RW), and a multi-bus address controller (RamBus_Multport).

[0030] The infrared image processing module (IR_ISP) is implemented in hardware logic and is used to execute infrared image processing algorithms, including but not limited to detector drive timing control, non-uniformity correction, filtering enhancement, and video output driving. This module can be internally divided into multiple algorithm sub-modules, which are connected through internal data flow pipelines to form a pipelined processing architecture.

[0031] In one embodiment, the infrared image processing module is internally divided into four parts: a raw data acquisition submodule, a correction submodule, an enhancement submodule, and an output submodule.

[0032] Soft-core CPUs use RISC-V architecture soft-core processors, such as RISC-V soft cores, and run lightweight embedded operating systems, responsible for control-intensive tasks such as system scheduling, parameter configuration, and instruction parsing.

[0033] Both the first and second HyperRAM controllers are hardware logic modules implemented within the FPGA, connected to the physical pins of the first and second HyperRAM chips, respectively. Each HyperRAM controller is responsible for generating read / write timing sequences conforming to the HyperRAM interface protocol, such as the 8-bit serial interface protocol of the Winbond W958D6NW, to perform functions such as serial-to-parallel data conversion, command parsing, and refresh control.

[0034] The multi-bus address controller is the core module of this invention, and it provides three types of interfaces: Multiple custom parallel bus interfaces, 10 in this embodiment, are used to directly connect to the various algorithm sub-modules of the infrared image processing module; The first AXI bus interface is used to connect to the soft-core CPU; The second and third AXI bus interfaces are used to connect to the first HyperRAM controller and the second HyperRAM controller, respectively.

[0035] The multi-bus address controller is responsible for coordinating the access of each algorithm submodule and the soft-core CPU to the two HyperRAM chips, enabling parallel hybrid access.

[0036] In this embodiment, the first HyperRAM chip and the second HyperRAM chip have completely independent address spaces and are not logically unified in addressing. This is a fundamental feature compared to the "arbitration shared unified memory pool" scheme in the prior art.

[0037] In this invention, the independent address space of the two HyperRAM chips means that the address ranges of the two chips can be the same, but they can be distinguished by chip select signal or high-order address decoding through the RamBus_Multport multi-bus address controller inside the FPGA, thereby forming two completely independent channels on the physical access path.

[0038] In one embodiment, the address range of the first HyperRAM can be set to 0x0000_0000~0x00FF_FFFF, and the address range of the second HyperRAM can be set to 0x0100_0000~0x01FF_FFFF. The actual address range depends on the chip capacity; the two chips have the same capacity but completely independent address spaces. The multi-bus address controller decodes the high-order bits of the access address and routes the access request to the corresponding HyperRAM chip, thereby enabling independent concurrent access to the two chips.

[0039] like Figure 3 As shown, the multi-bus address controller (RamBus_Multport) includes: a first AXI interconnect IP core, a second AXI interconnect IP core, a third AXI interconnect IP core, and multiple bus conversion modules (MAXI_FifoRW_Bas modules).

[0040] The Master interface of the first AXI Interconnect IP core is connected to the second AXI bus interface of the multi-bus address controller, which in turn connects to the first HyperRAM controller. The Master interface of the second AXI Interconnect IP core is connected to the third AXI bus interface of the multi-bus address controller, which in turn connects to the second HyperRAM controller. The first and second AXI Interconnect IP cores are each used to arbitrate multiple AXI master device requests accessing their Slave interfaces and convert them into accesses to a single AXI slave device, i.e., accesses to the first HyperRAM chip and the second HyperRAM chip, respectively.

[0041] The Slave interface of the third AXI Interconnect IP core is connected to the first AXI bus interface of the multi-bus address controller, which is connected to the soft-core CPU. Multiple Master interfaces of the third AXI Interconnect IP core are respectively connected to the Slave interfaces of the first and second AXI Interconnect IP cores. The third AXI Interconnect IP core receives AXI access requests initiated by the soft-core CPU, decodes them based on the high-order bits of the access address, and distributes the request to either the first or second AXI Interconnect IP core, thereby enabling the soft-core CPU to selectively access the two HyperRAM chips.

[0042] In this embodiment, the first AXI Interconnect IP core and the second AXI Interconnect IP core each have one Master interface and six Slave interfaces, and the third AXI Interconnect IP core has two Master interfaces and one Slave interface.

[0043] The number of bus conversion modules (MAXI_FifoRW_Bas modules) corresponds to the number of custom parallel bus interfaces; in this embodiment, there are 10. The input of each bus conversion module is connected to a custom parallel bus interface of the multi-bus address controller. This interface connects to an algorithm submodule of the infrared image processing module, and its output is connected to the inputs of the first and second AXI interconnect IP cores, respectively. Each MAXI_FifoRW_Bas module maintains an independent dual-clock FIFO for each custom parallel bus to isolate the user clock (W_Clk / R_Clk) from the AXI bus clock (M_AXI_AClk). Write direction: The user writes data and offset address (W_Adr) via the W_Wr signal. The module assembles the narrow-width data into an AXI data width (G_M_AXI_DATA_WIDTH) according to the G_FIFO_DATA_WIDTH_DIV parameter and stores it in the FIFO. When the amount of valid data in the FIFO reaches the preset burst length (G_M_AXI_BURST_LEN), the internal state machine automatically initiates an AXI burst write transaction, adding the base address (W_BasAdr) and the offset as the AXI address, and sequentially driving the AWVALID, WVALID, and other handshake signals until a BVALID response is received, completing one burst. Read direction: The module automatically initiates an AXI burst read transaction when there is enough free space in the FIFO, storing the read data (RData) in the FIFO. When the user reads via the R_Rd signal, the module splits the wide-width data into narrow-width outputs (R_Dat) according to the reverse rule, and the address is also composed of the base address (R_BasAdr) and the offset (R_Adr). On the user side, only simple write enable / read enable is required. The handshake of the address channel, data channel, and response channel on the AXI side is automatically completed by the module state machine without user intervention. When multiple custom parallel buses request access to the same HyperRAM chip, each FIFO buffer can queue and pipelining the requests, allowing access from different modules to be staggered in time, but without blocking or waiting for each other, thus achieving non-blocking access.

[0044] In this embodiment, all AXI Interconnect IP cores use the standard AXIInterconnect IP core provided by the Efinix FPGA platform. Their parameter configurations, such as address mapping, arbitration priority, and data bit width, are set according to actual needs. The bus conversion module MAXI_FifoRW_Bas is custom-developed logic. Its function is to convert a custom parallel bus protocol to the AXI bus protocol, while utilizing FIFO for cross-clock domain processing and request buffering. The custom parallel bus protocol is shown in Table 1.

[0045] Table 1. Signal Definitions for a Custom Parallel Bus (R / W_BUS) Each custom parallel bus (R / W_BUS) contains two sets of signals: write and read. The base address BasAdr and the address offset Adr together constitute the complete access address: actual physical address = base address + address offset. Each algorithm submodule can independently set its base address to access different HyperRAM chips or different address regions. Write and read operations each have independent clock, reset, and control signals, allowing the algorithm module to be driven independently according to its own operating frequency.

[0046] In this embodiment, both the base address signal W_BasAdr and the address offset signal W_Adr are 32 bits wide. The actual physical address is obtained by adding the base address and the address offset. When the high-order bit of the sum is 0, the first HyperRAM chip is accessed; when it is 1, the second HyperRAM chip is accessed. The high-order bits of the base address are pre-configured by the soft-core CPU to limit the access range of each algorithm submodule to the address range of the target HyperRAM chip.

[0047] Algorithm logic module access path and soft-core CPU access path; Algorithm logic module access path: In this embodiment, the aforementioned algorithm logic module is specifically implemented as an infrared image processing module (IR_ISP). Each algorithm submodule of the infrared image processing module accesses the corresponding custom parallel bus interface of the multi-bus address controller through its own custom parallel bus (R / W_BUS). Inside the multi-bus address controller, the request first enters the corresponding MAXI_FifoRW_Bas module, is converted into an AXI bus transaction, and then, based on the high-order bits of the address, is routed to the first or second AXI interconnect IP core. After arbitration by the AXI interconnect IP core, the request is output to the corresponding HyperRAM controller through the second or third AXI bus interface, and finally, the HyperRAM controller completes the physical read / write operation on the corresponding HyperRAM chip. Throughout the entire path, each algorithm submodule can initiate requests simultaneously, and multiple requests are independently buffered in the FIFOs of different bus conversion modules, without blocking each other.

[0048] Soft-core CPU Access Path: The soft-core CPU connects to the multi-bus address controller via the first AXI bus interface. Inside the multi-bus address controller, the soft-core CPU's access request first enters the third AXI interconnect IP core. This IP core decodes the request based on the high-order bits of the access address and distributes it to either the first AXI interconnect IP core (corresponding to the first HyperRAM) or the second AXI interconnect IP core (corresponding to the second HyperRAM). Subsequently, similar to the algorithm module's access path, the request passes through the corresponding AXI bus interface and the HyperRAM controller, ultimately accessing the target HyperRAM chip. By decoding the high-order bits of the address, the soft-core CPU can flexibly choose to access either HyperRAM chip, enabling selective access to the two chips.

[0049] Since the algorithm module and the soft-core CPU share the same AXI interconnect IP core and HyperRAM controller, but each has its own independent access channel, the algorithm module accesses different HyperRAM chips simultaneously or the same HyperRAM chip through a custom bus conversion module and the soft-core CPU accesses the same HyperRAM chip through a third AXI interconnect IP core. The order of access is determined by the arbitration mechanism of the AXI interconnect IP core, but the FIFO buffer can reduce waiting. This architecture is called "parallel hybrid access".

[0050] like Figure 4 As shown, the hardware-software collaborative workflow in this invention is as follows: Infrared image data is output from the detector and then enters the FPGA. Each algorithm submodule of the infrared image processing module caches the image data in the first and second HyperRAMs via a multi-bus address controller. During processing, the CPU can access the image data cached in the first and second HyperRAMs through the multi-bus address controller, perform the mathematical calculations required for algorithms such as non-uniformity correction and OCC correction, and cache the calculation results in the first and second HyperRAMs. The CPU can also periodically read this image data, execute scene adaptive analysis algorithms, dynamically adjust the operating parameters of each algorithm submodule based on the analysis results, and send these parameters to each algorithm submodule via the FPGA's internal control bus.

[0051] When an algorithm needs to be changed, the FPGA supports partial reconfiguration. On an FPGA platform that supports partial reconfiguration, the soft-core CPU can load the new algorithm logic bitstream from FLASH into a designated area of ​​the FPGA, enabling online replacement of algorithm submodules without power interruption and restart. This close collaboration between hardware and software balances the high throughput of hardware acceleration with the flexibility of software control.

[0052] In other embodiments of the present invention, the multi-bus address controller can also be connected to a fourth AXI bus interface for expanding the connection to the third HyperRAM chip and the corresponding third HyperRAM controller. Based on the same independent addressing principle, the third HyperRAM chip has an independent address range, and the multi-bus address controller can add corresponding AXI interconnect IP cores and bus conversion modules to form a three-channel or more HyperRAM storage system. This expansion scheme is particularly suitable for applications requiring higher storage bandwidth.

[0053] This invention is not limited to the specific models and interface standards described above. In alternative embodiments: When using other FPGA platforms, such as Intel / Altera or Xilinx, the corresponding Avalon bus or custom bus interconnect can be used instead of the AXI bus, as long as the same multi-bus address control logic is implemented.

[0054] Soft-core CPUs can be selected from other architectures such as Nios II and MicroBlaze.

[0055] If a single HyperRAM chip with two independent access ports emerges in the future, the idea of ​​"two independent chips" in this invention can be directly transplanted, and the two ports of the chip can be regarded as two independent logical channels, thus achieving independent addressing and concurrent access.

[0056] The FLASH chip can be any non-volatile memory with other capacities or interface standards, as long as it can communicate normally with the FPGA and store configuration data.

[0057] Based on the above embodiments, this invention has been prototyped and verified on the EileenTi120 FPGA platform and applied to mass-produced infrared imaging products. Experimental results show that: The system can stably support real-time processing of 1280×1024@50fps infrared images, with no memory access errors, no frame drops, and smooth CPU operation; In scenarios with concurrent access from multiple modules, the effective aggregated bandwidth is nearly twice that of a single-chip HyperRAM solution; Compared to existing single-chip HyperRAM solutions, this invention completely eliminates memory access errors and CPU lag issues at the same image specifications.

[0058] Infrared image results processed using this architecture are as follows: Figure 5 As shown, the image is clear and complete, demonstrating the feasibility and superiority of the present invention.

[0059] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A hardware-software co-operated dual-channel HyperRAM storage system based on FPGA, characterized in that, include: An FPGA chip, which integrates an algorithm logic module, a soft-core CPU, and a multi-bus address controller. The FPGA chip is connected to a first HyperRAM chip and a second HyperRAM chip respectively. The first HyperRAM chip and the second HyperRAM chip use independent addressing methods and their address ranges do not overlap. The multi-bus address controller routes the access request to the first HyperRAM chip or the second HyperRAM chip according to the high bit level of the access address. The multi-bus address controller is connected to the algorithm logic module, the soft-core CPU, the first HyperRAM chip, and the second HyperRAM chip, respectively, to enable the algorithm logic module and the soft-core CPU to access the two HyperRAM chips in parallel and in a hybrid manner.

2. The FPGA-based hardware and software co-operated dual-channel HyperRAM storage system as described in claim 1, characterized in that, The FPGA chip also integrates a first HyperRAM controller and a second HyperRAM controller. The first HyperRAM controller is connected between the multibus address controller and the first HyperRAM chip, and the second HyperRAM controller is connected between the multibus address controller and the second HyperRAM chip.

3. The FPGA-based hardware and software co-operated dual-channel HyperRAM storage system as described in claim 2, characterized in that, The multi-bus address controller internally includes: The first AXI interconnect IP core and the second AXI interconnect IP core each have at least one Master interface and multiple Slave interfaces. The Master interface of the first AXI interconnect IP core is connected to the second AXI bus interface of the multi-bus address controller, which is used to connect to the first HyperRAM controller. The Master interface of the second AXI interconnect IP core is connected to the third AXI bus interface of the multi-bus address controller, which is used to connect to the second HyperRAM controller. The third AXI interconnect IP core has multiple Master interfaces and at least one Slave interface. The Slave interface of the third AXI interconnect IP core is connected to the first AXI bus interface of the multi-bus address controller. The first AXI bus interface is used to connect to the soft-core CPU. The multiple Master interfaces of the third AXI interconnect IP core are respectively connected to the input terminal of the first AXI interconnect IP core and the Slave interface of the second AXI interconnect IP core. The system also includes multiple bus conversion modules. The custom parallel bus interface of the bus conversion module is connected to the custom parallel bus interface of the multi-bus address controller. The custom parallel bus interface is used to connect to the algorithm logic module. The AXI ports of the multiple bus conversion modules are respectively connected to the Slave interface of the first AXI interconnect IP core and the Slave interface of the second AXI interconnect IP core.

4. The FPGA-based hardware and software co-operated dual-channel HyperRAM storage system as described in claim 3, characterized in that, The algorithm logic module includes multiple algorithm sub-modules, and there are multiple custom parallel bus interfaces. Each algorithm sub-module is connected to the multi-bus address controller through one of the custom parallel bus interfaces. The multiple algorithm sub-modules achieve concurrent access to the two HyperRAM chips through their respective custom parallel buses.

5. The FPGA-based hardware and software co-operated dual-channel HyperRAM storage system as described in claim 3, characterized in that, The bus conversion module is a MAXI_FifoRW_Bas module. Each MAXI_FifoRW_Bas module maintains an independent FIFO buffer for each custom parallel bus. When multiple custom parallel buses request to access the same HyperRAM chip, the access is non-blocking queuing is achieved through the FIFO buffer.

6. The FPGA-based hardware and software co-operated dual-channel HyperRAM storage system as described in claim 4, characterized in that, Each of the aforementioned custom parallel bus interfaces includes a write operation signal group and a read operation signal group; The write operation signal group includes: write operation base address signal, write operation clock signal, write operation reset signal, write operation address offset signal, write operation enable signal, and write operation data signal; The read operation signal group includes: read operation base address signal, read operation clock signal, read operation reset signal, read operation address offset signal, read operation enable signal, and read operation data signal.

7. The FPGA-based hardware and software co-operated dual-channel HyperRAM storage system as described in claim 3, characterized in that, The soft-core CPU accesses the multi-bus address controller through the first AXI bus interface of the multi-bus address controller, and routes the access request to the AXI bus corresponding to the first HyperRAM chip or the AXI bus corresponding to the second HyperRAM chip by decoding the high-order bits of the address, thereby achieving selective access to the two HyperRAM chips.

8. The FPGA-based hardware and software co-operated dual-channel HyperRAM storage system as described in claim 1, characterized in that, The algorithm logic module is an infrared image processing module, used to execute infrared image processing algorithms including detector driving, non-uniformity correction, filtering enhancement, and video output driving.

9. The FPGA-based hardware and software co-operated dual-channel HyperRAM storage system as described in claim 1, characterized in that, The soft-core CPU is a RISC-V soft core, running a lightweight operating system, used to dynamically configure the working parameters of the algorithm logic module based on the image parameter information fed back by the algorithm logic module.

10. The FPGA-based hardware and software co-operated dual-channel HyperRAM storage system as described in claim 1, characterized in that, The multi-bus address controller is also connected to a fourth AXI bus interface, which is used to extend the connection to the third HyperRAM chip and the corresponding third HyperRAM controller to form a three-channel or more HyperRAM storage system.

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