1553b bus controller with dynamic storage and online recovery and control method

Abstract

The application belongs to the technical field of 1553B bus controllers, and provides a 1553B bus controller with dynamic storage and online recovery and a control method to solve the problem of poor data stability and reliability of the existing 1553B bus controller. The 1553B bus controller with dynamic storage and online recovery comprises a control core, a time management module, a channel selection module, a register group and an error detection and correction module. The register group is expanded with spare bits, and the configuration segment of the spare bits selects the offset bit width of the controller / remote terminal descriptor stack capacity. The error detection and correction module generates single-bit error and double-bit error check bits for the data expanded bit of the shared memory, and performs error detection and correction when reading. For single-bit error, the correction is completed when reading, and the corrected data is written back. For double-bit error, the error is detected and reported, which improves the data stability and reliability of the 1553B bus controller.

Description

Technical Field

[0001] This invention belongs to the technical field of 1553B bus controllers, and particularly relates to a 1553B bus controller and control method with dynamic storage and online recovery. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] MIL-STD-1553B is a command / response serial data bus primarily used in avionics systems. The bus network consists of terminals, subsystems, and the bus transmission medium. There are three different types of terminals, which also correspond to the three operating modes of the 1553B: Bus Controller (BC), Remote Terminal (RT), and Bus Monitor (MT). The BC is a crucial component of the 1553B bus, responsible for sending commands to participate in data transmission, receiving status responses, and monitoring the bus system. The RT is the interface between each subsystem and the entire 1553B bus network; only when the BC issues a command to a specific RT can it initiate a response, send back a status word, and complete the corresponding action. The MT is a terminal that monitors and records various conditions on the bus; it is controlled by the bus controller but does not participate in any 1553B bus network transmissions.

[0004] When the 1553B system requires high-throughput and continuous scenarios and is configured with modes such as circular buffers suitable for these scenarios, the system becomes limited by the stack capacity for storing four-word descriptors. This leads to a mismatch between the amount of data and hardware resources within the 1553B system. When the message descriptor stack of the BC overflows, it may cause an interrupt, halt the process, or cause a rollback that overwrites the original message descriptor. Conversely, the same applies when the RT sends data to the BC, affecting system debuggability and hindering long-term system stability. Furthermore, in the 1553B system, data is statically stored in RAM (Random Access Memory) for most of the time. Both register initialization configurations and RAM status or data information are highly susceptible to interference in a space environment, leading to bit flips and potentially causing the 1553B system to malfunction. Summary of the Invention

[0005] To address the technical problems existing in the background art, the present invention provides a 1553B bus controller and control method with dynamic storage and online recovery, which can improve the data stability and reliability of the 1553B bus controller.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: The first aspect of the present invention provides a 1553B bus controller for dynamic storage and online recovery.

[0007] A 1553B bus controller for dynamic storage and online recovery, connected to an external processor; comprising: The control core includes three operating modes: bus controller, remote terminal, and bus monitor. The time management module, which is connected to the control core, is used to manage the timeout and message interval of the control core. The channel selection module is connected to the control core at one end and to the transceiver modules of the two channels at the other end. It is used to initialize the active configuration or passively switch the transceiver modules of the corresponding channels. A register set connected to the control core; the register set is extended with spare bits, and the configuration segment of the spare bits is used to select the offset bit width of the controller / remote terminal descriptor stack capacity; The error detection and correction module is located in the path of the external processor and the control core accessing the shared memory. It is used to expand the bits of the data written to the shared memory by generating Hamming check codes and total parity bits, and to perform error detection and correction during reading. For single-bit errors, the correction is completed during reading and the corrected data is written back. For double-bit errors, the error is detected and reported.

[0008] In one implementation, the error detection and correction module is equipped with independent upstream and downstream storage ports; the upstream storage port is used to receive enable, read / write direction, shared memory address and write data, and return read data and read data valid signal; the downstream storage port is used to output encoded write data or receive read data.

[0009] In one implementation, the error detection and correction module is used to map the 16-bit original data to bits 2, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, and 20 of the 22-bit data according to fixed positions, place the check bits at bits 0, 1, 3, 7, and 15, and generate the 21st total check bit based on the first 21 bits of data; the five Hamming check bits respectively cover the corresponding parity check, thereby forming a check element for locating the error position in the 21-bit data.

[0010] In one implementation, during a read operation, the error detection and correction module simultaneously calculates the total check result and the 5-bit checksum for the mapped 22-bit data. When the total check result is 0 and the checksum is 0, it is determined that there is no error. When the total check result is 1 and the checksum is non-zero, the corresponding bit is flipped according to the position indicated by the checksum to achieve single-bit error detection and correction and determine it as a single-bit error. When the total check result is 1 and the checksum is 0, it is determined that there is a total check bit error. When the total check result is 0 and the checksum is non-zero, it is determined that there is a two-bit uncorrectable error.

[0011] As one implementation, the 1553B bus controller with dynamic storage and online recovery also includes an interrupt management module for managing interrupt requests for the bus controller's operating modes in the control core.

[0012] A second aspect of the present invention provides a control method for a 1553B bus controller with dynamic storage and online recovery.

[0013] A control method for a 1553B bus controller with dynamic storage and online recovery includes: Before the 1553B bus controller starts, the control core is initialized, and the register group is configured for function selection. The spare bits of the register group are used to configure the offset bit width of the controller / remote terminal descriptor stack capacity. The registers inside the error detection and correction module are configured for interrupts and initialized to zero. Data written to the shared memory by the external processor is encoded by the error detection and correction module and the extended bits are processed to generate the total parity bit and parity chip. The extended bits are then stored in the shared memory. After the 1553B bus controller starts up, the control core updates the four-word descriptor in the descriptor stack according to the configuration, and then locates the control word and the command word that indicate the subsequent behavior of the bus controller according to the pointer. When the control core performs a read operation, the error detection and correction module performs error detection and correction. The data output by the error detection and correction module flows to the corresponding transceiver module through the channel selection module, is synchronized across clocks, then Manchester encoded, and finally sent to the remote terminal corresponding to the specified command word sub-address.

[0014] As one implementation method, the data corrected by the error detection and correction module is then processed by the decoding logic to extract the corresponding number of bits of valid data.

[0015] In one implementation, when the 1553B bus controller accesses shared memory, if a single-bit error occurs while reading data, it corrects the error and writes it back, then pulls the single-bit error interrupt high; if a double-bit error occurs, it pulls the double-bit error interrupt high.

[0016] In one implementation, after the error detection and correction module corrects the refresh logic, it will read data from the shared memory one by one, starting from address 0 and incrementing the address. After the error detection and correction module decodes the data, it will correct single-bit errors and perform write-back, or detect and report double-bit errors, and so on.

[0017] As one implementation, when the error detection and correction module refresh logic scans to the address boundary, it will wait for the next round of refresh according to the programmable refresh interval.

[0018] The beneficial effects of this invention are: This invention improves the ability of the 1553B bus controller to continuously process large numbers of messages by expanding the spare bits in the register group and using the configuration segment of the spare bits to select the offset bit width of the controller / remote terminal descriptor stack capacity. In addition, by combining the error detection and correction module set in the path of accessing shared memory between the external processor and the control core, the total parity bit and parity digit are generated by expanding the bits of the data written to shared memory, and error detection and correction are performed during reading. This reduces the impact of single-event impacts on the controller's valid data in the aerospace environment, thereby improving the data stability and reliability of the 1553B bus controller.

[0019] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0021] Figure 1 This is a schematic diagram of the 1553B bus controller structure for dynamic storage and online recovery according to an embodiment of the present invention; Figure 2 This describes the read / write process of the error detection and correction module in this embodiment of the invention. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0024] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0025] Bus networks typically employ dual redundant channels, usually A / B dual channels. Transmitted words include command words, data words, and status words. Each word is transmitted using Manchester Type II encoding and includes parity checking; parity checking during transmission can detect some errors. Existing controllers typically include core control logic (BC, RT, MT), a Manchester codec, cross-clock domain processing, timeout detection, message retry, channel switching, interrupt management, and shared memory. After system startup, message descriptors and register configurations are extracted based on the shared memory initialization of BC to read control information and command words. Then, the data to be sent or received is accessed based on the message data block address within the descriptor. After message completion, the block status word, timestamp, and stack pointer are updated.

[0026] A typical BC / RT uses shared memory to store the stack pointer, message counter, message descriptor stack, and message data blocks. Each message internally writes four consecutive 16-bit words to form a descriptor. After each message is completed, the stack pointer is incremented by 4, thus updating the next four-word descriptor.

[0027] In the 1553B bus controller, the RT can be configured in three modes: single-message mode, double-buffered mode, and circular-buffered mode. When the 1553B system requires high throughput and continuous operation, such as in the circular-buffered mode of the RT, the amount of data sent from the BC to the RT is determined by configuring the buffer size using the three valid bits of the RT sub-address control word register, with settings of 128 words, 256 words, 512 words, 1024 words, 2048 words, 4096 words, and 8192 words. Due to the memory mapping of the BC in the standard 1553B bus controller, the BC stores a stack of four-word message descriptors, with a capacity of only 256 words. A message is written to the stack consecutively in groups of four words to form a descriptor, thus limiting storage to a maximum of 64 four-word descriptors at a time. However, in circular-buffered mode, the RT can receive a maximum of 256 messages of 32 words each. This creates a mismatch between the data volume and hardware resources in the 1553B system. When the BC message descriptor stack overflows, an interrupt may occur, stopping the process or causing a rollback that overwrites the original message descriptor. Conversely, the same applies when RT sends data to BC, which has a certain impact on the system's debuggability and is not conducive to the long-term stability of the system.

[0028] This invention expands the free bits in the 1553B register set and changes the stack address offset width through the register configuration segment, allowing the BC / RT descriptor stack capacity to be selected between 256 words, 512 words, 1024 words, and 2048 words, corresponding to storing 64, 128, 256, and 512 four-word message descriptors, respectively. This scheme can adjust the descriptor stack capacity according to the actual transmission task, improving the BC / RT's ability to execute continuous and large-data-volume tasks without changing the four-word descriptor format. It reduces the possibility of premature overflow and rollback due to a small fixed stack capacity, and improves the utilization of shared memory in the system.

[0029] This invention incorporates an Error Detection and Correction (EDAC) module into the shared memory access path of the control core of the external processor and the 1553B bus controller. This module generates a single-bit parity bit for the extended bits of the 16-bit data written to shared memory and performs error detection and correction during data retrieval. For single-bit errors, the EDAC module corrects the error during retrieval and writes the corrected data back; for double-bit errors, the EDAC module detects the error and reports it to the host computer. This protects the reliability of data during static storage and dynamic access in shared memory, overcoming the limitation of the 1553B bus, which can only detect errors during data transmission.

[0030] according to Figure 1 This invention provides a 1553B bus controller for dynamic storage and online recovery, which is connected to an external processor; it includes: a control core, a time management module, a channel selection module, a register group, and an error detection and correction module.

[0031] The control core includes three operating modes: Bus Controller (BC), Remote Terminal (RT), and Bus Monitor (MT). The BC control logic includes processes such as reading and writing configuration initialization information in shared memory and register sets, sending command words and receiving data and status words, writing back command words, recording runtime status, and retrying. The RT control logic includes processes such as parsing command words and sending data and status words, and recording runtime status. RT supports three memory management modes: single-message, double-buffered, and circular-buffered. MT supports selective message monitoring mode.

[0032] The time management module, connected to the control core, is used to manage the timeout and message intervals of the control core, such as the BC message time gap (Bus Controller Inter-message Gap), no-response timeout, RT2RT response timeout (Remote Terminal to Remote Terminal Response Timeout), and transmitter timeout (i.e., watchdog time).

[0033] The channel selection module connects to the control core on one end and to the transceiver modules of the two channels on the other. It is used to initialize active configuration or passive switching (such as timeout retries or other unexpected situations) to connect the corresponding channel's transceiver module. The Manchester encoding rate output by the 1553B bus controller is 1Mbps, which is incompatible with the internal high-speed clock, resulting in a cross-clock domain issue. The transceiver module includes an asynchronous FIFO (Asynchronous First In First Out) for transmitting and receiving to handle multi-bit data across clock domains. It also includes Manchester encoding and decoding modules, involving synchronization header generation and detection, parity bit generation, and serial-to-parallel conversion.

[0034] A register set, which is connected to the control core; the register set is extended with spare bits, and the configuration segment of the spare bits is used to select the offset bit width of the controller / remote terminal descriptor stack capacity.

[0035] The register set controls the mode and behavior of the entire 1553B bus controller, and includes 16 registers: configuration registers 1 to 5, interrupt mask register, start / reset register, BC / RT instruction stack pointer register, BC control word / RT sub-address control word register, time tag register, interrupt status register, data stack pointer counter register, BC frame time hold register, BC frame time hold to next frame register, RT previous command word register, RT status word register, and RT bit word register.

[0036] In the register set, the stack capacity can be expanded through register configuration, as shown in Table 1.

[0037] Table 1 Stack Capacity Expansion Table

[0038] Configuration register 3 extends the BC / RT stack capacity by 2 bits (BCRT_STK_SIZE), which is used to select the offset width of the BC / RT descriptor stack. When a message sequence starts, the BC / RT control logic reads the initial stack pointer (STACK_PTR) from shared memory. The capacity configured by CFG3 determines that the high N+1 bits of STACK_PTR are the stack base address (STACK_BASE), and the low N bits are stored as the current stack offset (STACK_OFFSET). The current descriptor address STACK_PTR is obtained by concatenating STACK_BASE and STACK_OFFSET. After a message is completed, STACK_OFFSET is incremented by 4. If the incremented offset reaches the capacity limit, STACK_BASE remains unchanged while STACK_OFFSET is rolled back to 0 within the stack. The address of the next descriptor is still concatenated by STACK_BASE and the new STACK_OFFSET, and the updated stack pointer is written back to the specified location in shared memory.

[0039] This embodiment expands the free bits in the 1553B register set and changes the stack address offset width through the register configuration segment, allowing the BC / RT descriptor stack capacity to be selected between 256 words, 512 words, 1024 words, and 2048 words, corresponding to storing 64, 128, 256, and 512 four-word message descriptors, respectively. This scheme can adjust the descriptor stack capacity according to the actual transmission task, improving the BC / RT's ability to execute continuous and large-data-volume tasks without changing the four-word descriptor format. It reduces the possibility of premature overflow and rollback due to a fixed stack capacity, and improves the utilization of shared memory in the system.

[0040] The error detection and correction module is located in the path of the external processor and the control core accessing the shared memory. It is used to expand the bits of the data written to the shared memory by generating Hamming check codes and total parity bits, and to perform error detection and correction during reading. For single-bit errors, the correction is completed during reading and the corrected data is written back. For double-bit errors, the error is detected and reported.

[0041] The error detection and correction module completes the function selection by configuring the register table. It includes functions such as initialization, refreshing (i.e., traversing memory), writing 1-bit (single bit) and 2-bit (double bit) error annotation at a specified address, writing 1-bit and 2-bit error annotation for all writes, error detection interrupt, error detection counting, and writing back after reading an error, which facilitates subsequent debugging and verification.

[0042] The error detection and correction module has independent upstream and downstream storage ports. The upstream storage port is used to receive enable, read / write direction, shared memory address and write data, and returns read data and read data valid signal. The downstream storage port is used to output encoded write data or receive read data.

[0043] For example, the upstream storage port is responsible for receiving enable, read / write direction, shared memory address, and 16-bit write data, and returning 16-bit read data and a read data valid signal; the downstream storage port outputs encoded 22-bit write data or receives 22-bit read data. The upstream access data width is 16 bits, and the downstream shared memory stores 22-bit data with ECC extension.

[0044] Combination Figure 2 The error detection and correction module maps the 16-bit raw data to bits 2, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, and 20 of the 22-bit data at fixed positions, places check bits at bits 0, 1, 3, 7, and 15, and generates a 21st total check bit (P) based on the first 21 bits of data. Five Hamming check bits cover the corresponding parity checks, thus forming a checksum (Syndrome) to locate the error position in the 21-bit data. Figure 2 (The accompanying check bit S).

[0045] During read operations, the error detection and correction module simultaneously calculates the total check result and the 5-bit checksum for the mapped 22-bit data. When the total check result is 0 and the checksum is 0 (i.e., P=0, S=0), it is considered error-free; when the total check result is 1 and the checksum is non-zero (i.e., P=1, S=0), it is considered error-free. When the total parity is 1 and the checksum is 0 (i.e., P=1, S=0), the corresponding bit is flipped according to the position indicated by the checksum, realizing single-bit error detection and correction and determining it as a single-bit error; when the total parity is 1 and the checksum is 0 (i.e., P=1, S=0), it is determined as a total parity bit error; when the total parity result is 0 and the checksum is non-zero (i.e., P=0, S=0), it is determined as a total parity bit error. 0), which is determined to be a two-bit uncorrectable error.

[0046] according to Figure 1 Shared memory is the internal storage space of the bus controller. It is a shared dual-port memory with a bit width extension to be compatible with the EDAC module interface. It can read and write data from the CPU (external processor) and IP (control core) simultaneously without interference.

[0047] In some specific embodiments, the 1553B bus controller with dynamic storage and online recovery also includes an interrupt management module, which manages interrupt requests for the bus controller's operating modes in the control core, including seven types of interrupts, such as end of frame, end of message, format error, retry, status set, timestamp overflow, and instruction stack overflow.

[0048] The control method for the 1553B bus controller based on the above-mentioned dynamic storage and online recovery includes: Before the 1553B bus controller starts, the control core is initialized, and the register group is configured with function selection (including working mode, channel, retry, A / B area, etc.). Afterwards, raw data including the initial stack pointer, message counter, message data block address in the four-word descriptor, and control word command word data word are written to the shared memory. The offset bit width of the controller / remote terminal descriptor stack capacity is selected by configuring the free bits of the register group. The registers inside the error detection and correction module are configured with interrupts and initialized by clearing them. Data written to the shared memory by the external processor is encoded by the error detection and correction module and the extended bits are processed to generate the total parity bit and parity chip. The extended bits are then stored in the shared memory. After the 1553B bus controller starts up, the control core updates the four-word descriptor in the descriptor stack according to the configuration, and then locates the control word and command word indicating the subsequent behavior of the bus controller according to the pointer. When the control core performs a read operation, the error detection and correction module performs error detection and correction. The data output by the error detection and correction module flows to the corresponding transceiver module through the channel selection module. After being synchronized across clocks by the asynchronous first-in-first-out buffer, it is then Manchester encoded and finally sent to the remote terminal corresponding to the specified command word sub-address.

[0049] The data word determines whether BC or RT is the sender and receiver based on the content of the command word. If BC sends a data word to RT, BC will write back the last data word after sending it and store it in shared memory, while waiting to receive the status word from RT. Finally, the four-word descriptor in the stack is updated again, and the stack pointer address is incremented by 4 and the message counter is incremented by 1 to determine whether the frame is complete.

[0050] In this embodiment, the data corrected by the error detection and correction module is then processed by the decoding logic to extract the corresponding number of bits of valid data.

[0051] In the 1553B bus controller, the error detection and correction module protects the A / B area stack pointers, message counters, four-word descriptors, message block addresses, command words, control words, status words, timestamps, and data words of BC and RT. Regardless of whether it's a single-bit or double-bit error, an interrupt can be enabled and reported to the host computer for processing based on the error detection and correction module's initialization configuration. When the 1553B bus controller accesses shared memory, if a single-bit error occurs during data reading, it corrects the error, writes it back, and pulls a single-bit error interrupt high; if a double-bit error occurs, it pulls a double-bit error interrupt high.

[0052] When the error detection and correction module corrects the refresh logic, it will read data from the shared memory one by one, starting from address 0 and incrementing the address. After the error detection and correction module decodes the data, it will correct single-bit errors and perform write-back, or detect and report double-bit errors, and so on.

[0053] When the error detection and correction module's refresh logic scans to an address boundary, it will wait for the next refresh according to the programmable refresh interval. This prevents bit flips caused by particle impacts on data that has been stationary in storage for a long time in extreme space environments.

[0054] An error detection and correction module is incorporated into the path of shared memory access by the external processor and control core. This module extends the 16-bit data written to shared memory to generate a total parity bit and a checksum, and performs error detection and correction during data retrieval. For single-bit errors, the module corrects the error during retrieval and writes the corrected data back; for double-bit errors, it detects the error and reports it to the host computer. This protects the reliability of data during static storage and dynamic access in shared memory, compensating for the limitation of the 1553B bus, which can only detect errors during data transmission.

[0055] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A 1553B bus controller for dynamic storage and online recovery, connected to an external processor; characterized in that, include: The control core includes three operating modes: bus controller, remote terminal, and bus monitor. The time management module, which is connected to the control core, is used to manage the timeout and message interval of the control core. The channel selection module is connected to the control core at one end and to the transceiver modules of the two channels at the other end. It is used to initialize the active configuration or passively switch the transceiver modules connected to the corresponding channels. A register set connected to the control core; the register set is extended with spare bits, and the configuration segment of the spare bits is used to select the offset bit width of the controller / remote terminal descriptor stack capacity; The error detection and correction module is located in the path of the external processor and the control core accessing the shared memory. It is used to expand the bits of the data written to the shared memory by generating Hamming check codes and total parity bits, and to perform error detection and correction during reading. For single-bit errors, the correction is completed during reading and the corrected data is written back. For double-bit errors, the error is detected and reported.

2. The 1553B bus controller with dynamic storage and online recovery as described in claim 1, characterized in that, The error detection and correction module is equipped with independent upstream and downstream storage ports; The upstream storage port is used to receive enable, read / write direction, shared memory address, and write data, and returns read data and a read data valid signal; the downstream storage port is used to output encoded write data or receive read data.

3. The 1553B bus controller with dynamic storage and online recovery as described in claim 1, characterized in that, The error detection and correction module is used to map the 16-bit original data to the 2nd, 4th, 5th, 6th, 8th, 9th, 10th, 11th, 12th, 13th, 14th, 16th, 17th, 18th, 19th, and 20th bits of the 22-bit data according to fixed positions, place the check bits at the 0th, 1st, 3rd, 7th, and 15th bits, and generate the 21st total check bit based on the first 21 bits of data; the five Hamming check bits respectively cover the corresponding parity check, thereby forming a check element to locate the error position in the 21-bit data.

4. The 1553B bus controller with dynamic storage and online recovery as described in claim 3, characterized in that, During the read operation, the error detection and correction module is used to simultaneously calculate the total check result and the 5-bit checksum for the mapped 22-bit data. When the total check result is 0 and the checksum is 0, it is determined that there is no error. When the total check result is 1 and the checksum is not 0, the corresponding bit is flipped according to the position indicated by the checksum to realize single-bit error detection and correction and determine it as a single-bit error. When the total check result is 1 and the checksum is 0, it is determined that the total check bit is wrong. When the total check result is 0 and the checksum is not 0, it is determined that it is a two-bit uncorrectable error.

5. The 1553B bus controller with dynamic storage and online recovery as described in claim 1, characterized in that, The 1553B bus controller with dynamic storage and online recovery also includes an interrupt management module, which manages interrupt requests for the bus controller's operating modes in the control core.

6. A control method for a 1553B bus controller with dynamic storage and online recovery as described in any one of claims 1-5, characterized in that, include: Before the 1553B bus controller starts, the control core is initialized, and the register group is configured for function selection. The spare bits of the register group are used to configure the offset bit width of the controller / remote terminal descriptor stack capacity. The registers inside the error detection and correction module are configured for interrupts and initialized to zero. Data written to the shared memory by the external processor is encoded by the error detection and correction module and the extended bits are processed to generate the total parity bit and parity chip. The extended bits are then stored in the shared memory. After the 1553B bus controller starts up, the control core updates the four-word descriptor in the descriptor stack according to the configuration, and then locates the control word that indicates the subsequent behavior of the bus controller and the command word to be sent according to the pointer. When the control core performs a read operation, the error detection and correction module performs error detection and correction. The data output by the error detection and correction module flows to the corresponding transceiver module through the channel selection module. After cross-clock synchronization, Manchester encoding is performed, and finally the data is sent to the remote terminal corresponding to the specified command word sub-address.

7. The control method as described in claim 6, characterized in that, After the error detection and correction module corrects the data, it extracts the corresponding number of bits of data from the valid data bits according to the decoding logic.

8. The control method as described in claim 6, characterized in that, When the 1553B bus controller accesses shared memory, if a single-bit error occurs while reading data, it will correct the error and write it back, and then pull up the single-bit error interrupt. If a two-bit error occurs, the two-bit error interrupt is pulled high.

9. The control method as described in claim 6, characterized in that, When the error detection and correction module corrects the refresh logic, it will increment the address from 0 one by one and read the data from the shared memory one by one. After the error detection and correction module decodes the data, it will correct single-bit errors and perform write-back or detect double-bit errors and report the error. This process will continue.

10. The control method as described in claim 6, characterized in that, When the error detection and correction module refresh logic scans to the address boundary, it will wait for the next round of refresh according to the programmable refresh interval.

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