A flow control coupled multi-lane AXI direct memory access controller and data flow scheduling method

Abstract

The application discloses a flow control coupled multi-channel direct memory access controller and a data flow scheduling method, and is applied to a system on chip and an FPGA. The controller comprises a configuration interface unit, a descriptor buffer unit, a channel data buffer unit, a shared memory bus access unit and a flow control aware arbitration unit. The flow control aware arbitration unit takes the end-to-end flow control state of each channel as a bus request gating condition, takes the near-full channel data buffer in the memory read direction as a request suppression condition to avoid storing read data, and takes the data ready flag of the ring buffer subzone in the memory write direction as a request suppression condition to avoid covering the unconsumed data. The downlink direction transmission descriptor is stored in an on-chip asynchronous FIFO, a hardware self-driven multi-section AXI read burst is generated, and a super-long transmission is automatically split; the uplink direction is completed by hardware setting a half-zone completion flag and rewriting self-descriptive information containing a write round and a packet length, and software is used to clear the flag in an exclusive or manner to realize a lock-free ping-pong consumption. The application realizes single IP multi-channel bidirectional concurrent, cross-clock domain adaptation, significantly reduces CPU interrupt and polling overhead, and improves the shared bus utilization.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and high-performance data transfer technology, specifically relating to a multi-channel direct memory access (DMA) controller and data flow scheduling method applied in System-on-Chip (SoC) and Field-Programmable Gate Array (FPGA) systems, connecting external memory and multiple programmable logic streaming data channels. More particularly, it relates to a DMA engine that couples end-to-end flow control information into multi-channel arbitration decisions and provides data transfer services for multiple streaming channels using a single shared memory bus port. This invention can be widely applied to high-speed real-time transfer scenarios of heterogeneous data streams such as multi-channel video, radar, 5G baseband, and industrial sensors. Background Technology

[0002] Direct Memory Access (DMA) technology allows data to be moved between memory and peripherals without the central processing unit (CPU) participating byte-by-byte, making it a key means of improving data throughput and reducing processor load. In heterogeneous on-chip systems such as Xilinx Zynq, the ARM processor core and programmable logic (PL) share the same physical memory (such as DDR memory). DDR is typically accessed by the DMA engine on the PL side via a high-performance (HP) AXI bus port, while the processor configures the DMA engine's registers via a general-purpose (GP) AXI bus port.

[0003] As the number of system data channels increases, single-port, multi-channel DMA architectures have become mainstream. In this architecture, multiple independent streaming data channels (typically using the AXI-Stream protocol) need to compete for the same shared AXI memory bus master port to access DDR. Existing technologies typically use fixed-priority arbitration, round-robin arbitration, or weighted round-robin arbitration to determine which channel occupies the bus at any given time. However, existing multi-channel DMA schemes still have significant technical shortcomings in areas such as arbitration, descriptor management, uplink handshake, and handling across clock domains and burst lengths.

[0004] One drawback is the disconnect between arbitration decisions and downstream receiving capabilities, leading to wasted shared bus bandwidth and the risk of buffer overflow. In the memory-to-stream channel (downstream read) direction, existing arbitrators typically generate bus requests based solely on whether there are pending transfer tasks on that channel. However, even if a channel has pending descriptors, if its downstream AXI-Stream receiving logic is currently under backpressure and the channel's data buffer FIFO is nearly full, the data read from DDR by the DMA engine will have nowhere to be stored. This can result in data buffer FIFO overflow and data loss, or even force the DMA engine to pause during the read process, wasting shared bus bandwidth that could have been used to serve other channels.

[0005] The second drawback is the lack of lock-free coordination between producers and consumers, which poses a risk of data overwriting. In the streaming channel to memory (uplink write) direction, the DMA engine, acting as a data producer, writes streaming data to a memory area in DDR, and the processor, acting as a consumer, reads data from that area. Existing technologies mostly rely on software to maintain read and write pointers and use mutexes or memory barriers to ensure that the producer does not overwrite data that the consumer has not yet read. This approach suffers from high lock overhead, poor real-time performance, and susceptibility to data overwriting due to software oversight in high-speed, continuous, and multi-channel scenarios. In addition, after each DMA transfer, the CPU needs to read the status register and update the descriptor chain, resulting in high interrupt frequency and heavy CPU load.

[0006] Furthermore, regarding arbitration mechanisms, the published Chinese patent CN102231142B proposes a multi-channel DMA controller with an arbitrator. This controller includes a channel arbitrator, which can select the next channel for data transmission based on the priority of each channel when multiple DMA channels simultaneously initiate DMA requests. However, this scheme still falls under the category of traditional priority-based arbitration. The arbitration decision is based solely on channel priority and does not consider the end-to-end flow control status of each channel (such as the backpressure status of the downstream receiver, the occupancy status of the channel data buffer, and the consumption progress of the ring buffer) as effective gating conditions for the arbitration request. When a channel is under backpressure or its data buffer FIFO is nearly full, this scheme may still allocate bus bandwidth to that channel, resulting in no place to store the read data or FIFO overflow.

[0007] The third drawback is that descriptor management relies on external DDR memory access, resulting in low efficiency. Traditional DMA solutions often employ two modes: "register sequential configuration" or "descriptor chain resident in DDR". The former requires the CPU to write to registers for each transfer, generating frequent interrupts and high CPU utilization; the latter stores the descriptor chain in DDR, requiring DMA to repeatedly read descriptors, introducing additional memory access, complicating link management, and making recovery difficult after errors. CN113986533B discloses a data transmission method that uses an AXI bus with separate read and write channels for simultaneous data writing and descriptor acquisition, but its descriptors still reside in DDR memory. DMA needs to repeatedly retrieve descriptors from memory through the AXI read channel, additionally consuming DDR bandwidth and AXI bus resources. CN121029654B discloses a multi-channel DMA implementation method based on FPGA, using a doorbell register for automatic descriptor chain management and proposing interrupt aggregation and weighted fair queues. However, its descriptor chain still resides in DDR, relying on a doorbell mechanism to trigger DMA to read the descriptor chain from DDR. CN112835829B discloses a method for transmitting measurement and control signals via multi-channel DMA. External device data is buffered and processed by the PL unit and then written to the external DDR of the PS using AXI-Bus. The PL enqueue pointer is updated and the PS unit is notified via an interrupt. This method still relies on the interrupt mechanism to notify the data transmission completion.

[0008] Fourthly, it is difficult to balance data integrity and transmission unit boundaries across clock domains. In FPGAs, the configuration interface clock, storage bus clock, and various streaming channel clocks often have different sources and frequencies. When moving data across clock domains, existing designs often struggle to balance efficient storage access in bursts with streaming transmission boundaries in packets (such as TLAST signals), easily leading to problems such as packet boundary loss and length mismatch.

[0009] Regarding circular buffer management, the published Chinese patent CN112765054A proposes a high-speed data transmission and acquisition system based on FPGA, which uses a circular buffer to store data and manages data through a mechanism where read and write pointers rotate along the circular buffer. However, this scheme still requires software to maintain the read and write pointers and for the upper-layer application to call the DMA driver for read operations. Essentially, it still belongs to the traditional circular buffer management method involving software, failing to solve the lock-free collaboration problem between producers and consumers, and posing a risk of data overwriting due to software negligence. In contrast, this invention uses a half-area completion flag with hardware setting and software XOR clearing to achieve lock-free production and consumption collaboration, fundamentally eliminating data overwriting.

[0010] Fifthly, long packet transmission requires software splitting. The AXI protocol limits the maximum length of a single burst to 256 beats, requiring software splitting for long packet transmission, which limits efficiency and real-time performance.

[0011] Furthermore, in terms of publicly available academic literature, the paper "Design and Implementation of a PCIe-Based Chained DMA Controller" (Computer Research and Development, 2024) proposes a multi-channel DMA architecture for domestic FPGA PCIe heterogeneous accelerator scenarios, which combines an independent descriptor controller, a shared data mover, chained descriptors, and tag reordering. However, it still relies on chained descriptors in host memory and depends on descriptor interrupts and PCIe tag mechanisms, which is fundamentally different from the end-to-end flow coupling arbitration, on-chip descriptor FIFO, and ring ping-pong lockless handshake techniques of this invention. Regarding commercial solutions, Xilinx's multi-channel DMA (MCDMA) IP has been marked as deprecated, and related driver support is limited. While CAST's multi-channel streaming DMA controller (MC-SDMA) supports multiple bidirectional channels, its publicly available information does not disclose mechanisms such as flow coupling arbitration, on-chip descriptor FIFO, hardware self-descriptor write-back, and XOR clear handshake.

[0012] In summary, none of the existing solutions simultaneously achieve: ① low resource overhead for single-IP multi-channel bidirectional concurrency; ② downlink descriptor resident on-chip FIFO for DDR-free access; ③ lock-free, low-overhead handshake between uplink hardware self-write descriptors and ring ping-pong half-zone flags; ④ flow control-aware arbitration (coupling end-to-end backpressure state into arbitration gating); ⑤ cross-domain bridging with independent clocks for each channel; and ⑥ automatic burst splitting for ultra-long transmissions. Therefore, there is an urgent need for a multi-channel DMA method and apparatus that can directly couple end-to-end flow control information into arbitration decisions, maximizing shared memory bus utilization while ensuring data integrity and no overwriting.

[0013] In academic research, the paper "Design and Implementation of a Crossbar-Based Multi-Channel DMA Controller" (China Integrated Circuits, 2013, Z1) proposes a crossbar-based multi-channel DMA controller design. It achieves data routing between multiple channels through a crossbar switch matrix, but does not disclose a flow control-aware arbitration mechanism. Its arbitration decision still relies on the existence of channel requests and does not incorporate downstream backpressure or buffer occupancy status into the gating conditions. The paper "A High-Speed ​​Multi-Channel DMA Controller Design" (China Integrated Circuits, 2016, 06) introduces a hardware design for a multi-channel DMA controller based on a standard AXI interface, but does not address on-chip descriptor caching or hardware self-descriptor write-back mechanisms. None of the aforementioned academic documents disclose the complete technical solution of this invention. Summary of the Invention

[0014] To address the technical problems in existing technologies, such as the disconnect between arbitration decision-making and downstream receiving capabilities, the lack of lock-free coordination between producers and consumers, the reliance on DDR memory access for descriptor management, the difficulty in balancing cross-clock domain packet boundaries, and the limitations of long packet transmission, this invention provides a flow control-coupled multi-channel direct memory access (DMA) controller and data flow scheduling method.

[0015] The technical problems to be solved by this invention include the following three levels.

[0016] First layer, defects of general DMA technology: (1) Multi-channel implementation relies on DMA multi-instance, resulting in redundancy of logic and interconnect resources; (2) Cross-clock domain data transfer requires external clock or bit width conversion IP, increasing latency and resource consumption; (3) Long packet transmission requires software splitting of AXI bursts, which limits efficiency and real-time performance.

[0017] The second layer has inherent defects in multi-channel streaming: (4) the arbitration decision is disconnected from the downstream receiving capability, and the reverse pressure channel still occupies the bus, resulting in bandwidth waste and FIFO overflow risk; (5) the descriptor management depends on DDR memory access, which occupies additional storage bus bandwidth and the link management is complicated; (6) under cross-clock domain conditions, it is difficult to balance large burst access on the storage side with the integrity of the packet boundary on the streaming side.

[0018] The third layer is the comprehensive defects in high-speed continuous multi-channel scenarios: (7) Producers and consumers lack lock-free collaboration. In high-speed continuous multi-channel scenarios, the lock overhead is large, the real-time performance is poor, and data overwriting is easily caused by software negligence; (8) Each DMA transfer requires CPU interrupt processing. In multi-channel scenarios, the interrupt frequency is high and the CPU load is heavy, which affects the real-time performance of the system.

[0019] To achieve the above objectives, the present invention adopts the following technical solution.

[0020] A flow control-coupled multi-channel direct memory access device includes: a configuration interface unit, a descriptor buffer unit, a flow control-aware arbitration unit, a shared memory bus access unit, and multiple channel data buffer units. The configuration interface unit receives a transfer descriptor and channel base address issued by the processor for each channel via a configuration bus (AXI4-Lite). The descriptor buffer unit corresponds one-to-one with each channel, buffers the transfer descriptor across clock domains, and provides the arbitration unit with the descriptor's empty / not empty state. The shared memory bus access unit accesses external memory (DDR) through a single memory bus master port (AXI3 / AXI4 HP) and performs memory read or memory write operations based on the descriptor of the selected channel.

[0021] The flow control sensing arbitration unit is the core of this invention. When a bus request is generated for each channel, it is used to gate the end-to-end flow control status of the channel as one of the conditions for the validity of the request, and to arbitrate among multiple channels based on the requests of each channel after gated request, and select the channel that can be effectively promoted without causing data loss or overwriting to occupy the main port of the shared storage bus.

[0022] In the downlink read direction, the channel data buffer unit includes an asynchronous data FIFO (e.g., 64-bit wide, 1024-bit deep) located between the storage bus clock domain and the streaming channel clock domain. This FIFO provides a near-full indication signal indicating that its occupancy has reached a preset threshold (in this embodiment, the threshold is set to 512, approximately half of the total capacity). The gating condition for the flow control sensing arbitration unit to generate a downlink channel bus request is: the channel descriptor buffer is not empty, and the channel's asynchronous data FIFO is not in a near-full state. Thus, when a downstream streaming receiver of a channel applies back pressure and its data FIFO is close to being full, the channel automatically withdraws from contention for the shared read port, preventing the read data from having nowhere to be stored.

[0023] In the uplink write direction, each channel is allocated a circular storage area in external memory, which is divided into at least two sub-areas (a front half and a back half in this embodiment). The flow control-aware arbitration unit maintains a 17-bit write pointer `addr_point`, a 3-bit write cycle count `des_cycle`, and a 2-bit data ready flag `up_flow_updata` corresponding to each sub-area for each channel. The data ready flag is set by hardware (DMA write engine) when the corresponding sub-area is full, and cleared by software (processor) after consuming the data in the corresponding sub-area. The gating condition for uplink channel bus requests is: the channel has data packets to be processed (the length FIFO is not empty), and the data ready flag of the sub-area currently pointed to by the write pointer is not set. This constitutes a lock-free production and consumption collaboration of hardware setting and software clearing, ensuring that the DMA engine will never write data to a sub-area that has not yet been consumed, fundamentally preventing data overwriting.

[0024] The clearing of the data ready flag employs an XOR clear handshake: flag updates are performed according to the logic of (set value XOR clear value) and the set value, allowing the software to accurately clear the flags of consumed sub-regions by writing the clear bit corresponding to the currently set bit, without mistakenly clearing the flags of other sub-regions or other channels. The shared memory bus access unit writes each data packet and its self-description information to the circular memory area in the uplink write direction. The self-description information includes at least a round field `des_cycle` representing the write round to which the data packet belongs, and a length field `des_len` representing the length of the data packet.

[0025] Specifically, the AXI DDR write engine employs an 8-state finite state machine, including the states AXI_WIDLE (idle), AXI_WINFOR (read length information), AXI_WRADDR (send write address), AXI_WDAT (send write data), AXI_WRESP (receive write response), AXI_DES_WRADDR (descriptor write-back - send write address), AXI_DES_WDAT (descriptor write-back - send write data), and AXI_DES_WRESP (descriptor write-back - receive write response). After data transmission is complete, it automatically enters the last three descriptor write-back states, writing back the 64-bit self-descriptor containing the round and length to the beginning of the corresponding data block in the DDR, forming a complete self-descriptor information chain without CPU intervention. In the default 64-bit data width embodiment, bits [63:61] of the self-descriptor are des_cycle, and bits [44:32] are des_len.

[0026] The transmission descriptor is a 32-bit fixed-length word, and its fields include: the lower 16 bits [15:0] are the offset field (representing the offset of the data packet relative to the channel base address, in 4KB granularity, which the hardware shifts left by 12 bits for address calculation); bits [28:19] are a 10-bit length main counter (in 8-byte units); and bits [18:16] are the margin flag (adding 1 to the total length count when it is not 0). The shared memory bus access unit concatenates the base address and the offset field after shifting left by a predetermined number of bits according to the memory area granularity to obtain the target physical address.

[0027] When the amount of data corresponding to a single descriptor exceeds the maximum number of cycles in a single burst specified by the storage bus protocol (the maximum burst size for the AXI protocol INCR is 256 cycles), the shared storage bus access unit automatically segments the transmission into multiple bursts. Between each burst, the target address is incremented by the maximum number of cycles in a single burst multiplied by the number of bytes corresponding to the data width (0x800 = 2048 bytes in a 64-bit width), and an operation completion flag is generated after all bursts are completed.

[0028] The shared memory bus access unit performs byte order rearrangement between memory bus data and channel data, reordering the bytes of the memory bus wide word in reverse order before writing to or reading from the channel data buffer to adapt to the byte order convention of the streaming channel. Before writing to DDR, a 64-bit little-endian to big-endian byte order is performed; after reading from DDR, a big-endian to little-endian byte order is performed.

[0029] The downstream readout channel data buffer unit includes independent data FIFOs (64 bits wide, 1024 depths) and length FIFOs (13 bits wide, 256 depths): the data FIFO buffers data packets, and the length FIFO buffers the length of the corresponding data packet. The streaming channel transmit controller first obtains the data packet length from the length FIFO, then reads data from the data FIFO packet by packet, and generates a streaming transport tail (TLAST) indication on the correct data packet based on the length, while simultaneously carrying this length in the streaming user-defined field (TUSER). When downstream backpressure occurs, the transmit controller stops reading data from the data FIFO and maintains the current output unchanged, continuing transmission only after readiness is achieved, thus avoiding data loss.

[0030] The flow control sensing arbitration unit employs a rotating priority fair arbitrator in the downlink direction, using a two-stage priority encoding strategy: In the first stage, a bitwise AND operation is performed between the input request and the rotating mask pointer, and priority encoding is performed within the masked range; in the second stage, priority encoding is performed across the entire request range as a backup. After each authorization, the rotating pointer is updated, ensuring the authorized channel is masked in the next round, thus achieving fair round-robin scheduling of multiple channels. The arbitration unit enters an operation in progress state when it detects a channel being selected, and releases the bus and returns to the arbitration idle state upon receiving an operation completion flag.

[0031] The DMA controller adopts a three-level asynchronous FIFO architecture across clock domains: a configuration interface clock domain (axi_slite_clk), a storage bus clock domain (axi_clk), and an independent streaming channel clock domain for each channel (axis_up_clk / axis_dn_clk). All channels' data FIFO, length FIFO, and descriptor FIFO are asynchronous, supporting independent read / write clocks, enabling secure data transmission between the three clock domains without metastability risks.

[0032] The uplink channel supports an automatic clearing mechanism for software reset: when the software writes to the reset register, it first clears the channel enable flag to stop DMA operation; when the channel is detected to be in an idle state (FIFO is empty and there is no ongoing operation), it automatically clears the reset flag and enable flag, and triggers the statistical counter to be cleared, without the need for the software to write to clear the reset flag again.

[0033] The device also includes a system register unit, which aggregates the half-zone completion flags of all uplink channels and maps them to read-only registers. The processor can obtain the half-zone data consumption status of all channels through a single register read operation, reducing the number of register accesses and lowering the software polling overhead.

[0034] This invention also provides a flow-controlled coupled multi-channel direct memory access method, comprising: receiving and buffering the transfer descriptor of each channel across clock domains; in each arbitration cycle, gating bus requests according to the end-to-end flow control state of each channel—whereby the downstream read direction uses the near-fullness of the channel data buffer as a condition for suppressing the request, and the upstream write direction uses the setting of the data ready flag of the sub-area pointed to by the write pointer as a condition for suppressing the request; arbitrating the gated channel requests and selecting the channel that can currently proceed effectively; having the selected channel occupy the shared memory bus master port and performing a memory read or memory write operation according to its descriptor; and releasing the bus and returning to arbitration after the operation is completed.

[0035] The present invention also provides a system-on-a-chip, including a processor, a memory, and programmable logic, wherein the programmable logic implements the above-mentioned means, and the processor issues descriptors through the configuration interface unit and consumes data by clearing the data ready flag. Beneficial effects

[0036] First, based on flow control-aware arbitration, the utilization rate of shared bus bandwidth is significantly improved. By coupling the near-full channel data buffer and the occupancy status of the ring half-zone into the arbitration request gating, the arbitrator only allows channels that can proceed without data loss, ensuring that the shared storage bus bandwidth always serves the transmissions that can actually proceed, and avoiding backpressure channels from occupying bus bandwidth.

[0037] Second, based on the on-chip asynchronous descriptor FIFO, descriptor acquisition does not consume storage bus bandwidth. Downlink transfer descriptors are sent by the processor to the on-chip asynchronous FIFO in one go via the configuration bus, and the DMA engine reads them from the chip, eliminating the contention between descriptor memory access and data memory access, and enabling parallel acquisition of multiple data streams without preempting storage resources.

[0038] Third, based on the hardware-based set and XOR clear handshake of the uplink ping-pong half-zone, lock-free collaboration is achieved and data overwriting is prevented. In the uplink direction, the hardware automatically sets the flag when the sub-zone is full, and the software clears it by XOR after consumption, without the need for mutex locks or memory barriers; DMA never writes data to unconsumed sub-zones, fundamentally preventing data overwriting, while significantly reducing the frequency of CPU interrupts and polling.

[0039] Fourth, hardware self-descriptor write-back reduces software burden. The hardware writes back self-descriptor information containing the write rounds and lengths while writing data packets. Software can correctly parse data packet boundaries and order without real-time exchange of read / write pointers with the hardware, simplifying driver and firmware design.

[0040] Fifth, based on a single-IP bidirectional multi-channel architecture and a three-level asynchronous FIFO cross-clock domain bridging, hardware resource overhead is reduced and system design is simplified. A single IP core has built-in independent downlink and uplink clusters, enabling multi-channel bidirectional concurrency without the need for multi-instance DMA; each channel's independent clock is natively bridged via an asynchronous FIFO, eliminating the need for external clock or bit-width conversion IPs.

[0041] Sixth, hardware-based automatic AXI burst splitting and byte order adaptation reduces software development difficulty. When a single transmission exceeds the AXI protocol burst limit, it is automatically segmented by hardware, and the software does not need to handle protocol fragmentation; the byte order between the storage bus and the streaming channel is rearranged by hardware to adapt to the little-endian format of the memory and the data format of the streaming channel. Attached Figure Description

[0042] Figure 1 This is a block diagram of the overall structure of the multi-channel DMA device with flow control coupling according to the present invention.

[0043] Figure 2 This is a schematic diagram of the downlink readout direction data path and near-full backpressure sensing arbitration of the present invention.

[0044] Figure 3 This is a schematic diagram of the uplink write direction data path and the sub-region ping-pong flow control for hardware setting / software clearing in this invention.

[0045] Figure 4 This is a schematic diagram of the state transition and self-describing information write-back process of the uplink DMA write DDR state machine of the present invention.

[0046] Figure 5 This is a schematic diagram illustrating the working principle of the downlink AXIS output reverse pressure processing state machine and the fair rotation arbitrator of the present invention.

[0047] Figure 6 This is a flowchart of the multi-channel DMA method with flow control coupling of the present invention.

[0048] [Figure Labeling Explanation] 1-Processor System PS; 2-AXI-Lite Configuration Bus; 3-AXI-HP Read Channel; 4-AXI-HP Write Channel; 5-web_dma_top Top-Level IP; 6-axi_lite_ctrl; 7-sys_reg_cfg; 8-dn_top Downlink Channel Cluster; 9-up_top Uplink Channel Cluster; 10-Downlink AXI-Stream Interface; 11-Uplink AXI-Stream Interface; 12-DDR Memory; 13-Algorithm Core; 14-Acquisition Core; 15-dn_reg_cfg; 16-dn_des_buf Descriptor Asynchronous FIFO; 17-dn_arb Downlink Arbitration; 18-axi_rd_ddr AXI Read Engine; 19 - Channel Data Asynchronous FIFO; 20 - Channel Length FIFO; 21 - dn_axis_ctrl Downlink Flow Controller; 22 - Near Full Indicator Feedback Line; 23 - Byte Order Reversal Logic; 24 - tlast / tuser Generation; 25 - up_reg_cfg; 26 - up_axis_ctrl Uplink Flow Controller; 27 - up_arb Uplink Arbitration; 28 - axi_wr_ddr AXI Write Engine; 29 - Ring Pointer Management Unit; 30 - Half-area Completion Flag up_flow_updata; 31 - DDR Ring Buffer (First Half / Second Half); 32 - Self-Descriptor Write-back Branch. Detailed Implementation

[0049] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are based on a Zynq heterogeneous system-on-a-chip, using an AXI3 / AXI4 bus, a 64-bit data width, and supporting up to 8 downlink channels and 8 uplink channels, but the present invention is not limited to this specific implementation.

[0050] like Figure 1As shown, the multi-channel DMA device (web_dma_top, label 5) provided in this embodiment is deployed in programmable logic (PL). It presents a configuration slave interface (AXI4-Lite GP, label 2) to the processor (label 1), a shared memory master interface (AXI3 / AXI4 HP, label 3 read / label 4 write) to the off-chip DDR (label 12), and multiple downlink streaming master interfaces (AXI-Stream Master, label 10) and multiple uplink streaming slave interfaces (AXI-StreamSlave, label 11) to the user logic within the PL. The address space is divided as follows: 0x0000-0x0FFF is the system register area, 0x1000-0x1FFF is the downlink channel register area (256 bytes per channel), and 0x2000-0x2FFF is the uplink channel register area. The device comprises two symmetrical data transfer directions: a downlink subsystem (DDR to streaming channel) and an uplink subsystem (streaming channel to DDR). The downlink subsystem (labeled 8) consists of a configuration register set, an asynchronous FIFO per channel descriptor (32 bits wide, 512 depth), a flow control-aware arbiter, a shared AXI read engine, an asynchronous data FIFO and a length FIFO per channel, and a streaming send controller per channel. The uplink subsystem (labeled 9) consists of a configuration register set, a streaming receive controller per channel, an asynchronous data FIFO per channel (64 bits wide, 1024 depth, near full threshold 512) and a length FIFO (13 bits wide, 256 depth), a flow control-aware arbiter, and a shared AXI write engine.

[0051] Table 1 lists the configurable core parameters for this embodiment. DN_CHANNEL Total number of downlink MM2S channels 4 1~8 UP_CHANNEL Total number of uplink S2MM channels 4 1~8 C_S_AXI_DATA_WIDTH AXI-HP data width 64bit 32 / 64 / 128 / 256bit C_S_AXI_ADDR_WIDTH AXI address width 30bit Configure as needed C_S_AXI_ID_WIDTH AXI ID bit width 4bit Configure as needed Maximum length of a single AXI burst INCR sudden limit 256 shots AXI protocol fixed dn_des_buf depth Asynchronous FIFO for each channel downlink descriptor 512×32bit Capacity can be expanded as needed. asyn_data_fifo depth Channel data asynchronous FIFO 1024×64bit Near full threshold 512 asyn_len_fifo depth Channel Packet Length FIFO 256×13bit Capacity can be expanded as needed. Ring-shaped particle size addr_point address offset unit 4KB fixed des_cycle bit width Circular Counting 3-bit (1→7 rollback) fixed Note: The above parameter configurations are adaptable to high-speed real-time migration scenarios involving heterogeneous data streams, such as multi-channel video stream migration, parallel radar echo acquisition, 5G baseband signal exchange, synchronous acquisition of industrial sensors, and medical image transmission. Each parameter can be flexibly configured according to the resource constraints and throughput requirements of the specific application scenario.

[0052] Table 2 shows the global address partitioning. 0x0000_0000 - 0x0000_0FFF System area SYS Summary of Project Time / Version / Number of Channels / Half-Zone Flags 0x0000_1000 - 0x0000_1FFF Downlink DN Each channel occupies 0x100 (256 bytes) of space. 0x0000_2000 - 0x0000_2FFF Upward Zone UP Each channel occupies 0x100 (256 bytes) of space.

[0053] Table 3 shows the downlink channel registers (single channel base address: 0x1000 + chan×0x100). 0x00 Reading / Writing Channel DDR transfer base address dn_base_addr 0x04 Write only Descriptor write port, 32-bit descriptor stored in asynchronous FIFO 0x08 Read-only FIFO descriptor state count dn_used_des (10 bits) 0x0C Read-only Total descriptor write count dn_des_wcnt 0x10 Read-only Total descriptor read count dn_des_rcnt 0xFC Write only Enable channel state clearing using dn_clr_sta_en

[0054] Table 4 shows the uplink channel register (single channel base address: 0x2000 + chan×0x100). 0x00 Reading / Writing Circular buffer DDR base address up_base_addr 0x04 Reading / Writing Total size of the annular region: zone_size (9 bits, in 4KB granularity) 0x08 Reading / Writing Channel transmission enable up_en 0x0C Reading / Writing Channel soft reset control up_rst 0x10 Read-only Channel reset status rst_state 0x80 Read-only Uplink cumulative packet count up_packet_num 0x84 Read-only The circular buffer loop iteration count up_it_num 0xFC Write only Uplink channel status clearing enable up_clr_sta_en Application configuration example: Taking a 4-channel uplink sensor network as an example, the base address (up_base_addr) of channel 0 is configured as 0x10000000, and the total size of the ring region (zone_size) is configured as 0x040 (i.e., 64 4KB units, totaling 256KB). Each channel's ring region has a 128KB front and rear half. Channel enable (up_en) is set to 1 after configuration to start transmission. The near-full threshold uses the default value of 512 (50% of the total data FIFO depth of 1024). When the CPU detects that the up_flow_updata flag is set, it reads the corresponding half-zone data in batches and writes a clear bit to the up_flow_clear register, thus releasing the half-zone for DMA to continue writing.

[0055] Table 5 lists the key registers in the system area. 0x000 Read-only PRJ_TIME is the project compilation time. 0x004 Read-only PRJ_VERSION Hardware version number 0x008 Read-only DN_CHANNEL Total number of downlink channels 0x00C Read-only UP_CHANNEL: Total number of uplink channels 0x100 Write only Upflow half-zone flag XOR clear control register up_flow_clear

[0056] like Figure 2 As shown, the data flow and arbitration process in the downlink direction are as follows: Step S201 (Descriptor Distribution and Caching): The processor writes a 32-bit transfer descriptor from the interface to a downlink channel via configuration. The lower 16 bits of the descriptor are the offset field (in 4KB granularity), bits [28:19] are the 10-bit length main counter (in 8 bytes), and bits [18:16] are the margin flag (the total length count is incremented by 1 when it is not 0). The descriptor FIFO (labeled 16) is a 32-bit wide, 512-bit deep asynchronous FIFO. The write clock is the configuration interface clock, and the read clock is the storage bus clock. Step S202 (arbitration request gating - the core of this invention): For the kth downlink channel, the arbitrator (label 17) generates a bus request according to the following logic: arb_req[k] = !(descrip_fifo_empty[k] OR dn_data_fifo_afull[k]), that is, a request is only made when the channel descriptor FIFO is not empty and its data FIFO (label 19) is not nearly full; Step S203 (Fair Arbitration): The arbitrator uses a rotating priority fair arbitration circuit, which updates the rotating pointer whenever a channel is selected. Step S204 (Burst Read and Segmentation): The shared AXI read engine (label 18) concatenates the base address and offset to obtain the target address base+{offset,12'h0}. When the length exceeds 256 frames, it is automatically segmented, and the inter-segment address is incremented by 0x800. Step S205 (byte order reordering): The read engine reorders the 64-bit wide word in reverse byte order and writes it into the data FIFO; In step S206 (streaming and packet boundary recovery), the streaming controller (labeled 21) first obtains the packet length from the length FIFO (labeled 20), then reads data from the data FIFO packet by packet, generates a TLAST packet tail based on the length, and carries the length in the TUSER field. When the downstream tready is pulled low, the controller stops reading from the FIFO and maintains the current output unchanged, continuing to transmit after tready recovers. The near-full indication of the data FIFO (labeled 22) is fed back to step S202, forming an end-to-end backpressure closed loop.

[0057] Example 3: Uplink write direction and hardware set / software clear sub-region ping-pong flow control like Figure 3 As shown, the data flow and arbitration process in the uplink direction are as follows: Step S301 (Streaming reception and cross-clock domain buffering): The streaming reception controller (label 26) of the uplink channel receives AXIS data with tready = !data_fifo_afull and writes it into the asynchronous data FIFO. When tlast is detected, the length of the current packet is obtained from TUSER and written into the asynchronous length FIFO. Step S302 (Ring Memory Area and Sub-area Division – Core of the Invention): Each uplink channel is allocated a ring memory area (labeled 31) in DDR, with its capacity configured by zone_size (in 4KB granularity), and is equally divided into two sub-areas (half-areas). The pointer management unit (labeled 29) maintains for each channel: a 17-bit write pointer addr_point (pointing to the 4KB slot to be written, returning to zero after wrapping around), a 2-bit data ready flag up_flow_updata[2k] (first half-area, labeled 30) and up_flow_updata[2k+1] (second half-area, labeled 30), and a 3-bit write cycle des_cycle (initial value 1, incrementing during wrapping, returning to 1 after reaching 7). Step S303 (arbitration request gating - the core of this invention): The uplink arbitrator (label 27) generates a bus request according to the following logic: arb_req[k] = !up_len_fifo_empty[k] AND ((!up_flow_updata[2k] AND addr_point < zone / 2) OR (!up_flow_updata[2k+1] AND addr_point >= zone / 2)); Step S304 (Hardware Set): When the DMA completes writing to the last slot of a half-region, the corresponding half-region flag is set by hardware. Step S305 (Software Clear - XOR Clear Handshake): After the processor finishes consuming the data, it writes a clear bit to the up_flow_clear register. The flag is updated according to the (set xor clear) and set logic, accurately clearing the flag of the consumed half-region. Step S306 (Burst Write and Self-Description Information): The shared AXI write engine (label 28) first writes packet data at base+{addr_point,12'h0}+8 (if it exceeds 256 cycles, it is segmented, and the inter-segment address is incremented by 0x800). Then, at base+{addr_point,12'h0}, the self-description word {des_cycle[2:0],16'h0,des_len[12:0],32'h0} is written through the self-description write-back branch (label 32).

[0058] Example 4: Uplink DMA write to DDR state machine and write-back of self-describing information like Figure 4 As shown, the AXI write DDR engine for uplink DMA uses an 8-state finite state machine. In the AXI_WIDLE state, the state machine waits for the arbiter start signal `opera_begin_flag`; upon receiving it, it enters the AXI_WINFOR state to read the transmission length from the length FIFO and calculate the total length `axi_total_wlen`; in the AXI_WRADDR state, it sends the write address (base + {addr_point, 12'h0} + 8, with an 8-byte offset to skip the self-descriptor position); in the AXI_WDAT state, it sends the write data (written after 64-bit byte order reversal, with a maximum burst of 256 cycles); in the AXI_WRESP state, it receives the write response, and if the total length is greater than 256, it returns to AXI_WRADDR to continue the next burst. After data transmission is complete, it enters the descriptor write-back three-state: AXI_DES_WRADDR sends the write-back address (base + {addr_point, 12'h0}, without offset); AXI_DES_WDAT sends the 64-bit self-descriptor; and AXI_DES_WRESP receives the write-back response. After the write-back is complete, an opera_comp_flag signal is generated to notify the arbiter. The 64-bit self-descriptor field is defined as follows: bit[63:61] = des_cycle (write cycle, 1→7 rollback); bit[44:32] = des_len (packet length, 13 bits); the remaining bits are filled with 0.

[0059] Example 5: Downlink AXIS Backpressure Processing and Fair Rotation Arbitration like Figure 5As shown, the downlink AXIS transmit controller drives data output based on the packet length in the length FIFO. In transmit mode, data is read from the data FIFO and sent to the AXIS bus every clock cycle. When tvalid is high but tready is low, the transmit controller stops reading from the data FIFO and maintains the current output; transmission resumes when tready recovers. The fair round-robin arbitrator wt_arb employs a two-stage priority encoding: the first stage involves ANDing the request with the round-robin mask pointer and encoding it within the mask range; the second stage encodes all requests as a backup. After each grant, the round-robin pointer is updated so that the granted channel is masked in the next round.

[0060] Example 6: Numerical Example of Working Process (Used to fully understand the present invention, and does not constitute a limitation on the scope of protection) Downlink transmission example: Taking downlink channel 0 as an example, the software writes a descriptor to the channel through the AXI-Lite configuration interface. The offset field is 0x10 (i.e., 16 4KB units, offset from the channel base address by 0x10000), the length main count [28:19] is 0x20 (32 8-byte units, totaling 256 bytes), and the margin flag [18:16] is 0. The downlink arbiter detects that the channel descriptor FIFO is not empty and the data FIFO is not nearly full, generates a request, and authorizes it. The AXI read engine calculates the read address = dn_base_addr + 0x10000 and initiates an AXI read burst to the DDR; 256 bytes = 32 cycles (64 bits / cycle), and a single burst of up to 256 cycles is completed. The read data is written to the data FIFO after byte order reversal. The downlink flow controller retrieves data from the data FIFO and outputs it on the AXI-Stream interface. When the count reaches 256 bytes, tlast is generated, completing one downlink transmission. The software does not need to intervene on a packet-by-packet basis. Uplink Transmission Example: An AXI-Stream interface on uplink channel 0 receives a data packet (including tlast), with the TUSER carrying a packet length of 512 bytes (64 cycles). The uplink flow controller writes the data to the data FIFO and the packet length of 512 bytes to the length FIFO. The uplink arbitrator detects that the channel length FIFO is not empty and the half-cell flag pointed to by the ring write pointer addr_point is not set, authorizing the AXI write engine. The write engine calculates the write address = up_base_addr + (addr_point << 12) + 8, writes 64 cycles of data to the DDR ring buffer, and then writes back the self-descriptor {des_cycle[2:0], 16'h0, des_len[12:0] = 9'h200, 32'h0} at up_base_addr + (addr_point << 12). addr_point increments. When addr_point crosses the half-cell boundary, the corresponding up_flow_updata half-cell is set. The CPU polls this flag (instead of each data packet) to determine if the data in the half-area is ready for consumption. After a batch read, it writes the corresponding bit of up_flow_clear to clear the flag, and the DMA resumes writing to the half-area, achieving low-overhead lock-free handshake.

[0061] Example 7: Parameters and Extensions The key parameters of this embodiment are: 64-bit data width, AXI protocol, maximum burst size of 256 cycles, inter-segment address increment of 0x800, descriptor FIFO of 32×512, data FIFO of 64×1024 (near full threshold of 512), length FIFO of 13×256, ring granularity of 4KB, write rounds of 3 bits (1 to 7 rollbacks), and a maximum of 8 downlink channels and 8 uplink channels.

[0062] Alternative Implementation Example 1: Three-Subregion Ring Buffer Scheme Based on the bipartition ping-pong scheme of the above embodiments, the circular storage area can also be divided into three sub-areas, with the corresponding data ready flag extended to 3 bits, and the write pointer cyclically advancing between the three sub-areas. This scheme is suitable for scenarios with large fluctuations in data consumption rates, and further reduces the risk of data overwrite by increasing the buffer depth.

[0063] Alternative Implementation Example 2: Four-Sub-Region Scheme and Extended Channel Count When the ring-shaped storage area is divided into four sub-areas, the data ready flag is expanded to 4 bits, and the XOR clear logic is expanded accordingly. In addition, the number of downlink channels can be expanded to 16 or more, and the number of uplink channels can also be increased as needed. The number of bits of the arbitrator and the width of the rotating pointer are adjusted accordingly, and the fairness of arbitration is not affected by the number of channels.

[0064] Alternative Example 3: Different Data Bit Width Configurations The data bit width can be configured to 32 bits, 128 bits, or 256 bits, corresponding to inter-segment address increments of 0x400, 0x1000, and 0x2000, respectively, with the self-description word field bit width adjusted accordingly. In the 128-bit bit width configuration, the data volume per frame is 16 bytes, and a 256-frame burst can transmit 4096 bytes, suitable for efficient transfer of large frame image data.

[0065] Alternative Implementation Example 4: Equivalent Replacement of Arbitration Strategy The above embodiments employ rotating priority fair arbitration, but weighted round-robin arbitration or a hybrid arbitration combining fixed priority and round-robin can also be used. Under any arbitration strategy, flow control-aware gating conditions (near-full suppression, half-zone flag suppression) take effect independently as preconditions for request validity, and changing the arbitration strategy does not affect the core mechanism of flow-coupled arbitration.

[0066] Those skilled in the art can make equivalent transformations to the above-mentioned bit width, depth, number of channels, number of sub-regions, arbitration strategy, etc., without departing from the concept of the present invention, and all such transformations fall within the protection scope of the present invention. Comparison and Differentiation Demonstration of Existing Technologies and Literature

[0067] To more clearly illustrate the substantial features and significant advancements of this invention compared to existing technologies and published literature, Table 6 compares the key technical features of this invention with those of similar published patents, academic literature, and commercial IP item by item, and provides a comprehensive analysis at the end of this section: CN113986533B (Shandong Yunhai Guochuang, authorized in 2025) The descriptor resides in DDR, and DMA repeatedly retrieves the descriptor via the AXI read channel. Single transmission engine Undisclosed flow coupling gating Depends on CPU response Not disclosed Not disclosed CN121029654B (Jilin University, licensed 2026) The descriptor chain resides in DDR, and the doorbell register triggers the descriptor retrieval. Single engine + weighted fair queue Weighted fair queue (non-end-to-end backpressure coupling) Doorbell + interrupt aggregation (still per descriptor granularity) Not disclosed Not disclosed CN112835829B (Zhu Daoshan, Journal) The specific descriptor mechanism has not been disclosed. Virtual channel + multi-channel continuous DMA storage Undisclosed flow coupling gating Packet interrupt + enqueue pointer Not disclosed Not disclosed Academic: "Design and Implementation of a PCIe-based Chained DMA Controller" (Computer Research and Development, 2024) Chained descriptors reside in host memory Independent descriptor controller + shared data mover Polling scheduling Depends on PCIe Tag+ interrupt Within PCIe domain Chained autoloading Xilinx AXI DMA / CDMA (commercial) Descriptor chain resides in DDR Single-channel is unidirectional; multi-channel requires multiple instantiation. Uncoupled gating Dependency interrupt Requires bit width / clock conversion IP stack-up Software splitting required Xilinx MCDMA (deprecated) Descriptor Resident DDR Multi-channel but with limited drive Undisclosed flow coupling gating Dependency interrupt Undisclosed native multi-asynchronous clock Not disclosed CAST MC-SDMA (commercial) Not disclosed Multi-way bidirectional Undisclosed flow coupling gating Not disclosed Not disclosed Not disclosed CN102231142B (Zhejiang University, authorized in 2013) Undisclosed descriptor management Multi-channel arbitrator + priority arbitration Traditional arbitration based on priority (non-flow coupled) Not disclosed Not disclosed Not disclosed CN112765054A (High-speed data transmission and acquisition system) Not disclosed Single-channel DMA Undisclosed flow coupling gating Software maintenance read / write pointers Asynchronous FIFO (single-level) Not disclosed Design and Implementation of a Crossbar-Based Multichannel DMA Controller (Academic Paper, 2013) Not disclosed Crossbar Multichannel Undisclosed flow coupling gating Interruption Aggregation Not disclosed Not disclosed [This Invention] Descriptor resides in an on-chip asynchronous FIFO, with no DDR memory access. Single IP, multi-channel, bidirectional concurrency (up to 8 downstream + 8 upstream) Flow control sensing arbitration: Downlink near-full suppression + Uplink half-zone flag suppression Hardware set / software XOR clear ping-pong half-zone lockless handshake + hardware self-descriptor write-back Three-level asynchronous FIFO bridge (configuration / storage / each AXIS clock) Hardware automatically splits 256 bursts + 0x800 address step

[0068] Comparative conclusions and differentiated arguments

[0069] (I) Differences in Descriptor Management: CN113986533B and CN121029654B both reside descriptors in DDR, requiring DMA to repeatedly read descriptors via the shared memory bus, consuming DDR bandwidth and AXI bus resources; CN112835829B also relies on external storage for pointer maintenance; the academic chained DMA scheme is based on host memory chained descriptors. This invention stores descriptors entirely in an on-chip asynchronous FIFO (dn_des_buf), which is issued by the CPU in one go via a dedicated configuration bus (AXI-Lite). The DMA read engine reads from the on-chip FIFO, and descriptor acquisition does not consume AXI-HP memory bus bandwidth, fundamentally eliminating the contention between descriptor memory access and data memory access.

[0070] (II) Differences in Multi-Channel Implementation: CN113986533B and CN112835829B are single-engine / single-channel, requiring multiple instantiation for multi-channel implementation; CN121029654B, although a single-engine, uses weighted fair queue scheduling for multiple channels, which is still a software-adjustable weighted scheduling rather than a physical concurrency guarantee; the academic chain scheme adopts a separate structure of independent descriptor controller + shared data mover. This invention uses a single IP core to build mutually independent downlink and uplink clusters. The downlink and uplink clusters are completely hardware independent and can synchronously and concurrently perform bidirectional data transfer. N downlink and M uplink share a single memory bus master port but physically perform concurrent transmission simultaneously, avoiding the redundancy of BRAM, LUT, and AXI interconnect resources caused by multiple instantiation DMA.

[0071] (III) Differences in Arbitration Mechanisms: None of the aforementioned comparative documents / commercial solutions use end-to-end flow control status as a valid gating condition for arbitration requests. CN113986533B and CN112835829B only initiate requests based on the existence of pending transmission tasks; CN121029654B's weighted fair queue has software-configurable weights and is not coupled with real-time backpressure signals such as FIFO near full or half-area occupancy. This invention feeds back the near-full indication of the channel data FIFO to the arbitrator (downlink direction) and feeds back the data ready flag of the circular half-area pointed to by the write pointer to the arbitrator (uplink direction), so that the arbitrator only allows the currently effective channel to proceed in each cycle, maximizing the utilization of shared bus bandwidth and avoiding FIFO overflow and data overwriting from the hardware level.

[0072] (iv) Differences between uplink notification and anti-overwrite: CN113986533B and CN112835829B rely on CPU response to interrupts or polling of the status register; although CN121029654B proposes interrupt aggregation, it still triggers at the descriptor level; the academic chain scheme relies on PCIe tags and interrupts. This invention automatically writes back a 64-bit self-descriptor (including the write round and packet length) by hardware after each packet is written to DDR. The hardware automatically sets the half-segment completion flag based on the write pointer crossing the half-segment boundary. The CPU only needs to clear the flag through a single XOR write operation after the entire half-segment is completed, without the need for mutexes, memory barriers, or packet-by-packet interrupts, fundamentally preventing data overwrite and significantly reducing CPU load.

[0073] (v) Cross-clock domain differences: Existing commercial solutions typically require stacking AXI Data Width Converter and Clock Converter IPs between the configuration bus clock, storage bus clock, and each streaming channel clock, introducing additional latency and resource consumption; the aforementioned comparative patents also do not disclose native multi-asynchronous clock bridging solutions. This invention natively supports cross-clock domain data buffering with a three-level asynchronous FIFO architecture (configuration bus clock domain / storage bus clock domain / each AXIS independent clock domain), without requiring external clocks or bit-width conversion IPs.

[0074] (vi) Differences in Extremely Long Bursts: CN113986533B and CN112835829B do not disclose a hardware automatic splitting mechanism; CN121029654B involves chained loading but does not disclose hardware automatic segmentation with a 256-buzz limit. The AXI read engine and write engine of this invention both have built-in hardware automatic splitting logic. When the data volume corresponding to a single descriptor exceeds the AXI protocol INCR burst limit (256 bursts), it is automatically segmented, with each segment address incremented by 0x800. The software does not need to pay attention to the protocol length limit.

[0075] (VII) Comprehensive Conclusion: None of the aforementioned prior art documents / commercial solutions / academic literature discloses the complete technical combination of this invention: "downlink descriptor on-chip asynchronous FIFO + flow control-aware arbitration (including near-full and half-zone dual gating) + uplink hardware self-descriptor write-back and ring-shaped ping-pong half-zone lock-free XOR clear handshake + independent clock three-level asynchronous FIFO bridging per channel + AXI hardware automatic burst splitting + 8-state write engine". Significant synergistic effects exist among these features: the on-chip descriptor FIFO eliminates downlink DDR memory access dependency → combined with near-full backpressure arbitration → ensures read data never overflows; hardware self-descriptor write-back eliminates CPU interrupt-per-packet requirement → combined with ring-shaped half-zone XOR clear handshake → ensures lock-free uplink consumption without overwriting. The combined effect of these three features—resource saving, CPU load reduction, bandwidth maximization, and no packet loss or overwriting—is not a simple superposition of existing technologies. It possesses outstanding substantive characteristics and significant progress, meeting the inventiveness examination standards for invention patents. Industrial applicability

[0076] This invention has been implemented and verified in Verilog on the Xilinx Zynq-7000 / UltraScale+ platform (PS-side AXI_GP configuration + AXI_HP data). The source code includes modules such as the top-level web_dma_top, downlink cluster dn_top, uplink cluster up_top, AXI-Lite slave axi_lite_ctrl, system register sys_reg_cfg, and general polling arbitration wt_arb. The accompanying asynchronous FIFO IP is generated by a commercial FIFO generator. Data bit width, number of channels, FIFO depth, and ring size are all configurable by parameters. This invention can be widely applied to the following scenarios: (1) Video processing: High-speed transfer of multiple video streams between the PL algorithm core and the PS-end DDR; (2) Radar signal processing: parallel acquisition and real-time transmission of multi-channel radar echoes; (3) Baseband processing: Real-time exchange of 5G / wireless multi-channel baseband signals between FPGA and processor; (4) Industrial control: High-speed synchronous acquisition and storage of data from multiple sensors; (5) Medical Imaging: FPGA-accelerated board for transmitting multi-channel medical imaging data such as CT / ultrasound.

[0077] The hardware modules of this invention are all parameterized, requiring no custom chip manufacturing process. They can be integrated and implemented on the entire range of Xilinx Zynq-7000, UltraScale, Artix, and Kintex FPGAs, possessing complete industrial application and mass commercial value, and meeting the requirements for patent industrial applicability.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A flow control coupled multichannel direct memory access (DMA) controller, characterized in that, include: The configuration interface unit is used to receive the transmission descriptor and channel base address issued by the processor for each channel through the configuration bus; A descriptor buffer unit, configured corresponding to each channel, is used to buffer the transfer descriptor across clock domains and output a descriptor empty state indication; multiple channel data buffer units, configured corresponding to each channel, are used to buffer the data to be moved across clock domains between the storage bus clock domain and the streaming channel clock domain, and output a near-full indication indicating that its occupancy has reached a preset threshold. The shared memory bus access unit accesses external memory through a single shared memory bus master port and is used to perform memory read or memory write operations based on the transfer descriptor of the selected channel. The system includes a flow control-aware arbitration unit, which, when generating a bus request for each channel, uses the end-to-end flow control status of that channel as a condition for request validity, arbitrates the requests of each channel after gating, and selects the channel that can currently be effectively advanced to occupy the main port of the shared memory bus. Specifically, in the memory read direction, the gating condition for the flow control-aware arbitration unit to generate the k-th channel bus request is: the channel descriptor buffer is not empty and the channel data buffer unit is not in a near-full state. When a channel data buffer unit is in a near-full state, the bus request for that channel is suppressed, causing that channel to withdraw from accessing the shared memory. Contention at the master port of the storage bus; in the storage write direction, each channel is allocated a ring-shaped storage area in the external memory, the ring-shaped storage area is divided into at least two sub-areas, the flow control sensing arbitration unit maintains a write pointer and a data ready flag corresponding to each sub-area for each channel, the data ready flag is set by the shared storage bus access unit when the corresponding sub-area is full, and is cleared by the processor after consuming the data in the corresponding sub-area, the gating conditions for the k-th channel bus request include: the channel has a data packet to be processed, and the data ready flag of the sub-area currently pointed to by the write pointer is in an unset state.

2. The controller according to claim 1, characterized in that, The preset threshold is 50% of the total depth of the channel data buffer unit; the flow control sensing arbitration unit adopts rotation priority fair arbitration in the storage read direction, and updates the rotation pointer after each channel is selected, so that each channel gets an equal opportunity to occupy the bus.

3. The controller according to claim 1, characterized in that, The circular storage area is divided into two sub-areas. The write pointer returns to zero when it circles back to the starting point of the circular storage area. The two sub-areas are used alternately for writing and consumption, forming a ping-pong lockless production and consumption collaboration. The clearing of the data ready flag adopts an XOR clear handshake. The flag is updated according to the logic of (set value XOR clear value) and set value, so that the processor can clear the flag of the consumed sub-area by writing the clear bit corresponding to the target flag bit without affecting the flags of other sub-areas or other channels.

4. The controller according to claim 1, characterized in that, While writing each data packet, the shared memory bus access unit writes self-description information in the slot where the data packet is located. The self-description information includes at least a round field representing the writing round to which the data packet belongs and a length field representing the length of the data packet. The round field advances when the write pointer returns to the starting point of the circular memory area and rolls back after reaching the upper limit. The shared memory bus access unit uses an 8-state finite state machine to perform uplink write operations. In the data write phase, the write address, write data, and write response states are used sequentially to complete the packet data writing. In the descriptor write-back phase, the descriptor write-back address, descriptor write-back data, and descriptor write-back response states are used sequentially to complete the write-back of self-description information.

5. The controller according to claim 1, characterized in that, The transmission descriptor is a fixed-length word, including at least an offset field and a length field. The shared memory bus access unit concatenates the channel base address and the offset field by shifting them left by a predetermined number of bits according to the memory area granularity to obtain the target physical address. The memory area granularity is fixed at 4KB, and the offset field is represented in 4KB units. The hardware shifts the offset field left by 12 bits and concatenates it with the channel base address to obtain the target physical address. The descriptor buffer unit is an on-chip asynchronous FIFO. The write-side clock is the configuration bus clock, and the read-side clock is the memory bus clock. Each streaming channel interface is configured with an independent working clock. The channel data buffer unit and the length FIFO use an asynchronous FIFO to bridge the memory bus clock domain and the corresponding channel streaming clock domain.

6. The controller according to claim 1, characterized in that, When the amount of data corresponding to a single descriptor exceeds the maximum number of cycles in a single burst as specified by the storage bus protocol, the shared storage bus access unit segments the transmission into multiple bursts. Between each burst, the target address increments by the product of the maximum number of cycles in a single burst and the number of bytes corresponding to the data bit width. After all bursts are completed, an operation completion flag is generated. The shared storage bus access unit rearranges the bytes between the storage bus data and the channel data in reverse order to adapt to the little-endian format of the memory and the streaming channel data format.

7. The controller according to claim 1, characterized in that, In the storage read direction, the channel data buffer unit includes independent data FIFOs and length FIFOs. The length FIFO has a storage width of 13 bits, covering a single packet length range of up to 8191 bytes. The streaming controller first obtains the packet length from the length FIFO, then reads data from the data FIFO step by step, and generates a streaming transmission packet tail indication on the corresponding data step according to the length. Simultaneously, it carries the length in a user-defined streaming field. When backpressure occurs at the downstream streaming receiver, the streaming controller stops reading data from the data FIFO and maintains the current output. When the downstream is ready, it continues sending, achieving zero-data-loss transmission. The device supports... The software reset automatic clearing mechanism, after the software writes to the reset register, first clears the channel enable flag to stop DMA operation. When the channel is detected to be in an idle state, it automatically clears the reset flag and enable flag and triggers the statistical counter to be cleared. The device also includes a system register unit, which summarizes the half-zone completion flags of all uplink channels and maps them to read-only registers. The processor can obtain the half-zone data consumption status of all channels through a single register read operation. The controller is integrated into the programmable logic of the heterogeneous on-chip system and is used for real-time transfer of multi-channel sensor streaming data. The sensors include at least one of image sensors, vibration sensors, and radar sensors.

8. A flow-controlled coupled multi-channel direct memory access method, applied to a DMA engine that provides memory access to multiple streaming data channels through a single shared memory bus master port, characterized in that, include: Receive and buffer the transport descriptor for each channel across clock domains; In each arbitration cycle, bus requests are gated based on the end-to-end flow control status of each channel. Specifically, in the storage read direction, the condition for suppressing a request is that the channel data buffer is nearly full, and in the storage write direction, the condition for suppressing a request is that the data ready flag of the sub-area pointed to by the write pointer is set. Arbitrate requests from each channel after gating and select the channel that can currently proceed effectively; The selected channel occupies the main port of the shared storage bus and performs storage read or storage write operations according to its transfer descriptor. After the storage read or write operation is completed, the bus is released and the arbitration is returned. Specifically, in the storage write direction, the following measures are included: allocating a ring-shaped storage area divided into at least two sub-regions in external memory for each channel; setting a data ready flag for the corresponding sub-region by hardware when it is full; clearing the flag via an XOR clear handshake after the processor has consumed the data in that sub-region; suppressing bus requests for that channel when the write pointer points to a sub-region with the flag set to avoid overwriting unconsumed data; and writing self-descriptive information containing a write round field and a length field while writing each data packet. In the storage read direction, the following measures are included: using independent data FIFOs and length FIFOs to buffer data and packet length across clock domains; retrieving the length first and then the data; generating a streaming packet tail indication based on the length; stopping reading from the data FIFO and maintaining the current output when backpressure occurs at the downstream streaming receiver; and continuing transmission after recovery.

9. A system-on-a-chip, characterized in that, The system includes a processor, a memory, and programmable logic, wherein the programmable logic implements the controller as described in any one of claims 1 to 7; the processor issues a transfer descriptor through the configuration interface unit and consumes data in the ring memory area by clearing the data ready flag.

Images