Media data transmission system and method

Abstract

The application discloses a media data transmission system and method, wherein a barrier module corresponding to each producer is arranged on a write address channel of an AXI bus, a barrier module corresponding to each consumer is arranged on a read address channel of the AXI bus, each barrier module is connected in series through a barrier bus, each consumer presets a target ID of required media data, each producer writes barrier data into the corresponding barrier module and broadcasts the barrier data when writing each channel of media data into a memory, each consumer identifies the barrier data, obtains a flow ID and a data address range, and reads media data in the data address range from media data corresponding to the target ID. The application can simplify internal connection of an SOC, reduce consumption of hardware resources, reduce media data transmission delay, and improve reliability in a media data transmission process.

Description

Technical Field

[0001] This application relates to the field of media data transmission technology, specifically to a media data transmission system and method. Background Technology

[0002] In a System-on-Chip (SoC), media processing modules (such as image signal processors, video codecs, and display processors) typically use a frame as the basic unit of data interaction when handling video image data. Specifically, after the upstream producer module completes the processing of an entire frame of data, it is then handed over to the downstream consumer module for reading and processing. The operations of the producer and consumer are independent of each other, and this design can better ensure the integrity of data during transmission between modules.

[0003] However, the aforementioned frame-based processing mode suffers from significant latency issues. When the data volume of a single frame is large, the processing latency is directly related to the frame duration. For example, with 4K@30fps processing capability, the processing time for one frame is approximately 1 / 30th of a second (i.e., 33.3ms). This level of latency is insufficient for applications with high latency requirements, such as video calls, real-time monitoring, and autonomous driving assistance.

[0004] To reduce processing latency, some solutions divide each frame of image data into multiple segments (or subframes) for processing, thereby reducing the data granularity of a single processing operation. However, this segmentation method requires additional frame segmentation and reassembly logic, increasing the complexity of the system design. Furthermore, under different data read / write orders (such as Raster scan order and Tile order), it is difficult to guarantee that the data read by the consumer is the data that the producer has safely written into memory, which can easily lead to data read errors.

[0005] Furthermore, within a SoC, there are typically complex business flow relationships between multiple producer modules and multiple consumer modules, and the upstream and downstream combinations between modules need to be flexibly configured. Establishing a dedicated "point-to-point" connection for each pair of producers and consumers would result in numerous internal wirings, high hardware resource consumption, and would be detrimental to the dynamic adjustment and expansion of business flows.

[0006] In summary, how to effectively reduce the latency of media data processing in SoC chips while ensuring data accuracy, and how to achieve flexible and economical connectivity in complex scenarios with multiple producers and consumers, are technical problems that urgently need to be solved in this field. Summary of the Invention

[0007] In view of this, this application provides a media data transmission system and method to simplify the internal wiring of the SOC, reduce hardware resource consumption, reduce media data transmission latency, and improve the reliability of media data transmission.

[0008] This application provides a media data transmission system, which includes a group of producers, a group of consumers, and a Barrier module corresponding to each producer and each consumer. The Barrier module corresponding to each producer is located on the write address channel of the AXI bus, and the Barrier module corresponding to each consumer is located on the read address channel of the AXI bus. Each Barrier module is connected in series through the Barrier bus. Each consumer is pre-set with the target ID of the required media data. Each producer writes Barrier data, including the stream ID and data address range of the media data being written, to the corresponding Barrier module when writing media data to the memory, and broadcasts the Barrier data to each consumer. Each consumer is used to identify the Barrier data, obtain the stream ID and data address range carried in the Barrier data, and read the media data within the data address range from the media data represented by the stream ID corresponding to the target ID in the memory.

[0009] Optionally, the Barrier data may also include the sequence number and verification parameters of the data packet.

[0010] Optionally, each of the producers is also used to obtain the working clock received by the corresponding Barrier module, and write the Barrier data into the time slice corresponding to the Barrier module according to the working clock.

[0011] Optionally, each producer is also used to acquire a start signal and an end signal; the start signal is used to indicate the start of the corresponding message, and the end signal is used to indicate the end of the corresponding message.

[0012] Optionally, each of the producers is provided with a first CSR register, which stores information on whether it is the first node; each producer is also used to write the corresponding time slice to the corresponding Barrier module according to the working clock when it is the first enabled media data stream, starting from the first enabled media data stream, until the time slices corresponding to all enabled media data streams have been sent.

[0013] Optionally, each of the producers is also configured to, when not being the first node, after receiving Barrier data from the upstream, write the corresponding time slice to the corresponding Barrier module, starting from the first media data stream enabled by itself, following the constraint of increasing stream ID.

[0014] Optionally, each consumer is provided with a second CSR register, which stores information on whether it is the end node; each consumer is also used to read the time-slice-limited data corresponding to the target ID when it is the end node.

[0015] Optionally, each of the consumers is also used to read the time-slice-limited data corresponding to the target ID when it is not the end node, and to continue to pass the Barrier data of the corresponding Barrier module to the downstream Barrier module.

[0016] This application also provides a media data transmission method, which is implemented through any of the aforementioned media data transmission systems. The media data transmission system includes a group of producers, a group of consumers, and barrier modules corresponding to each producer and each consumer. The barrier modules corresponding to each producer are located on the write address channel of the AXI bus, and the barrier modules corresponding to each consumer are located on the read address channel of the AXI bus. Each barrier module is connected in series via the barrier bus. Each consumer has a preset target ID for the required media data. The media data transmission method includes: When each producer writes media data to the memory, it writes Barrier data, including the stream ID and data address range of the media data being written, to the corresponding Barrier module, and broadcasts the Barrier data to each consumer. Each consumer is used to identify the Barrier data, obtain the stream ID and data address range carried in the Barrier data, and read the media data within the data address range from the media data represented by the stream ID corresponding to the target ID in the memory.

[0017] Optionally, writing Barrier data, including the stream ID and data address range of the media data to the corresponding Barrier module, includes: obtaining the operating clock received by the corresponding Barrier module, and writing the Barrier data into the time slice corresponding to the Barrier module according to the operating clock.

[0018] The media data transmission system and method described in this application establish a Barrier bus by setting up Barrier modules for each producer on the write address channel of the AXI bus and Barrier modules for each consumer on the read address channel of the AXI bus. This reduces the number of connections between modules and enables multiple pairs of producers and consumers to share this bus to transmit information. This simplifies the internal wiring of the SoC and reduces hardware resource consumption. On the Barrier bus, each producer can broadcast its generated Barrier data, which is then obtained by the corresponding consumer. The consumer then reads the corresponding media data from the memory based on the Barrier data, allowing for timely media data retrieval without exceeding the range of media data written to the memory by the producer. This reduces media data transmission latency and improves the reliability of media data transmission. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of a media data transmission system according to an embodiment of this application; Figure 2 This is a schematic diagram of the data structure corresponding to Barrier data in one embodiment of this application; Figure 3 This is a schematic diagram of the relevant signal timing according to an embodiment of this application; Figure 4 This is a schematic flowchart of a media data transmission method according to an embodiment of this application. Detailed Implementation

[0021] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0022] The first aspect of this application provides a media data transmission system that can be integrated into a SoC (System-on-a-Chip). (Reference) Figure 1As shown, the media data transmission system includes a set of producers, a set of consumers, and barrier modules corresponding to each producer and each consumer. Producers include modules that write media data into memory (such as DDR), producing media data such as image data and / or video frame data to be processed. Consumers include modules that read data from memory, reading and processing the data already written by the producers. A set of producers includes at least one producer, and a set of consumers includes at least one consumer. Each producer or consumer may process more than one media data stream, therefore a "stream ID" is needed to distinguish the pairing of each individual media data stream. The stream ID includes each pair of "producer + consumer" streams; each stream needs to be distinguished using a globally unique ID (i.e., stream ID), which is allocated based on the configuration of upstream and downstream services.

[0023] Optionally, the Barrier module can be implemented using components such as digital logic circuits to transmit the corresponding Barrier data and determine whether the read address of the corresponding consumer exceeds the allowed range.

[0024] Each producer's corresponding Barrier module is located on the write address channel of the AXI bus. It monitors the producer's write address and records the current memory location. Each consumer's corresponding Barrier module is located on the read address channel of the AXI bus. It monitors the consumer's read address and blocks the current read operation if the read address exceeds the allowed range, thus creating a barrier to ensure the reliability of read and write operations between producers and consumers. Each Barrier module is cascaded through the Barrier bus, allowing Barrier data to be transmitted forward along the bus. This enables producers to broadcast Barrier data to consumers after writing it. Each consumer has a pre-defined ID for the required media data, i.e., a target ID, allowing consumers to find the media data corresponding to the target ID using the target ID and the stream ID.

[0025] Each producer writes Barrier data, including the stream ID and data address range of the media data being written, to the corresponding Barrier module when writing media data to the memory, and broadcasts the Barrier data to each consumer.

[0026] Each consumer is used to identify the Barrier data, obtain the stream ID and data address range carried in the Barrier data, and read the media data within the data address range from the media data represented by the stream ID corresponding to the target ID in the memory.

[0027] In practical applications, the upstream and downstream relationships in a SoC are quite complex, and there may be flexible combinations of service flows between multiple modules, for example... Figure 1 As shown, multiple producers and consumers exist simultaneously, and establishing a point-to-point dedicated connection for each pair of producers and consumers is an uneconomical implementation. This embodiment sets up a Barrier module corresponding to each producer on the write address channel of the AXI bus, and a Barrier module corresponding to each consumer on the read address channel of the AXI bus. By connecting these Barrier modules in series via the Barrier bus, the number of interconnections between modules can be reduced. This mechanism allows multiple pairs of producers and consumers to share this bus to transmit information, simplifying the internal wiring of the SoC and reducing hardware resource consumption. On the Barrier bus, each producer can broadcast its generated Barrier data, which the corresponding consumer can then obtain and read the corresponding media data from memory based on the Barrier data. This ensures timely media data reading without exceeding the range of media data written to memory by the producer, reducing media data transmission latency and improving the reliability of media data transmission. The continuous broadcasting by the producer allows consumers to continuously update their allowed address range, thus enabling an automatic operation mechanism.

[0028] Optionally, each producer writes media data to the memory in a linear order. As long as the data used by the consumer is safely placed into the memory by the producer, the consumer will not make a mistake when reading the corresponding data according to the data address range, which can significantly reduce the latency of the entire process.

[0029] Optionally, each producer writes media data to the memory in a tile order. The consumer reads the media data in a linear order. In this case, the consumer can preset a gap parameter. The consumer determines the endpoint address corresponding to the media data to be read based on the data address range. Before the producer finishes writing the corresponding media data, the consumer only reads data that is more than the gap parameter away from the endpoint address (i.e., data before the gap parameter), to ensure that the data read by the consumer is definitely the data written to the memory by the producer. This improves the reliability of data transmission while ensuring writing efficiency and low latency processing.

[0030] The aforementioned media data transmission system sets up barrier modules for each producer on the write address channel of the AXI bus and barrier modules for each consumer on the read address channel of the AXI bus, forming a barrier bus. This reduces the number of connections between modules and allows multiple pairs of producers and consumers to share this bus to transmit information. This simplifies the internal wiring of the SoC and reduces hardware resource consumption. On the barrier bus, each producer can broadcast its generated barrier data, which is then retrieved by the corresponding consumer. The consumer then reads the corresponding media data from the memory based on the barrier data, enabling timely media data retrieval without exceeding the range of media data written to the memory by the producer. This reduces media data transmission latency and improves the reliability of media data transmission.

[0031] In some embodiments, the Barrier data further includes the packet sequence number (Seq_num) and a checksum parameter (Xor_checksum). The packet sequence number can be filled in by the producer when generating the Barrier data, and is used for message ordering and problem localization. The checksum parameter includes the checksum of the Barrier data, and the checksum parameter is confirmed by filling this field with the value obtained by performing an XOR check on the values ​​of all preceding fields.

[0032] In some examples, the data structure of the barrier data can be referenced. Figure 2 As shown, the data includes the packet sequence number, flow ID, checksum parameter, and data address range. The data address range includes addr[7:0], ..., addr[39:32]. Through this data address range, the producer can inform the consumer of the end address value of the accessible address range. One Barrier data corresponds to one time slot. That is, a time slot includes a complete data structure such as the packet sequence number, flow ID, checksum parameter, and data address range to transmit a complete Barrier data.

[0033] In some embodiments, each producer is further configured to acquire the operating clock received by the corresponding Barrier module, and write the Barrier data into the time slice corresponding to the Barrier module according to the operating clock. The operating clock can be a 200MHz clock signal. A time slice can refer to a fixed-length time slot allocated cyclically according to the increasing order of the stream ID. This fixed-length time slot can be used to allow each producer to take turns broadcasting its write address progress information (or placeholder empty packets) within the time slot, thereby enabling address synchronization of multiple data streams using a time-division multiplexing bus.

[0034] Specifically, each producer is also used to acquire a start signal (sop) and an end signal (eop); the start signal indicates the start of the corresponding message, and the end signal indicates the end of the corresponding message. The start signal (sop) and end signal (eop) can be generated by the first producer and sent to other producers; alternatively, they can be generated by the relevant control module and sent to each producer.

[0035] Optionally, the operating clock, start signal sop, end signal eop, and barrier data can be referenced. Figure 3 As shown, the Barrier bus includes a 1-bit start signal (sop), a 1-bit end signal (eop), and 8 bits of addr_info (data representing the address range). It operates using a 200MHz clock. The start signal (sop) indicates the beginning of each message, and the end signal (eop) indicates the end of each message. Each flow occupies one time slot, and each time slot is sent in ascending order of flow_ID (from 0 to N-1). If a flow is not enabled, it also occupies a time slot and sends a dummy time slot with an address value of all "1".

[0036] In some examples, each producer has a CSR (Configuration Channel) register to indicate whether it is the first node of the entire Barrier bus. Specifically, each producer has a first CSR register, which stores information about whether it is the first node.

[0037] Specifically, each producer, when acting as the lead node, writes the corresponding time slice to the corresponding Barrier module according to the working clock, starting from the first enabled media data stream, until the time slices corresponding to all enabled media data streams have been sent, so as to send the corresponding data that it needs to send in an orderly and complete manner.

[0038] Specifically, each producer, when not acting as the first node, receives Barrier data from the upstream Barrier module, and starting from its first enabled media data stream, writes the corresponding time slice to the corresponding Barrier module following the constraint of increasing stream ID, and then sends out the time slice corresponding to the media data stream. Furthermore, the Barrier module corresponding to a non-first node is an intermediate node; intermediate nodes only replace the time slice of the media data streams they enable, and cannot delete time slices.

[0039] In some examples, if the first physical node in the Barrier bus does not have any flow that needs to send a time slice, this physical node will generally not be configured by software as the first node of the Barrier bus; if it is indeed configured by software as the first node, then it needs to periodically generate dummy time slots (i.e., the address value is always all "1") to trigger the downstream nodes to broadcast.

[0040] In some examples, each consumer has a CSR register that configures whether it is the last node on the entire Barrier bus. Specifically, each consumer also has a second CSR register that stores information about whether it is the last node.

[0041] Each consumer, when acting as the end node, ceases to transmit Barrier data downstream. Instead, it captures data from the time slice where the stream ID equals its own pre-stored ID, i.e., reads the data within the time slice corresponding to the target ID. The target ID is a pre-set ID for each consumer, which can be assigned and generated by the relevant control module. For example, the control module can assign and send corresponding target IDs to each consumer, enabling each consumer to pre-store the corresponding target ID.

[0042] In some examples, each consumer is also used to read the time-slice-limited data corresponding to the target ID when it is not the end node, and to continue to pass the Barrier data of the corresponding Barrier module to the downstream Barrier module, that is, to continue to pass the Barrier data to the downstream module without modification.

[0043] Specifically, the barrier data transmitted on the barrier bus forms corresponding media data streams, and each media data stream can represent a barrier data stream. Each media data stream has a globally unique ID value (i.e., stream ID) to avoid confusion between different streams. If the ID corresponding to a certain media data stream has already been used between a pair of "producers + consumers" on the barrier bus, then as long as confusion can be avoided, other downstream "producers + consumers" can reuse the stream ID to reuse the stream ID without affecting the reliability of data transmission. Optionally, the control module of the media data transmission system can also set the maximum number of streams N used on the barrier bus to determine the number of transmission time slices.

[0044] The aforementioned media data transmission system sets up barrier modules for each producer on the write address channel of the AXI bus and barrier modules for each consumer on the read address channel of the AXI bus, forming a barrier bus. This reduces the number of connections between modules and allows multiple pairs of producers and consumers to share this bus to transmit information. This simplifies the internal wiring of the SoC and reduces hardware resource consumption. On the barrier bus, each producer can broadcast its generated barrier data, which is then retrieved by the corresponding consumer. The consumer then reads the corresponding media data from the memory based on the barrier data, enabling timely media data retrieval without exceeding the range of media data written to the memory by the producer. This reduces media data transmission latency and improves the reliability of media data transmission. Through relevant experiments, the inventors verified that the above-mentioned media data transmission system can significantly reduce the processing latency of media data inside the SoC chip. For example, at 30fps, the processing time for one frame of data is 1 / 30 of a second ≈ 33.33ms. If the media data transmission system provided in this application is used, and the producer notifies the consumer to start working after writing 1 / 30 of a frame, then the processing latency for one frame of data can be reduced to 33.33 / 30 = 1.11ms.

[0045] A second aspect of this application provides a media data transmission method, which is implemented by the media data transmission system described in any of the above embodiments. The media data transmission system includes a group of producers, a group of consumers, and a Barrier module corresponding to each producer and each consumer. The Barrier module corresponding to each producer is located on the write address channel of the AXI bus, and the Barrier module corresponding to each consumer is located on the read address channel of the AXI bus. Each Barrier module is connected in series through the Barrier bus. Each consumer presets the target ID of the required media data. The media data transmission method includes steps S110 to S120.

[0046] S110, when each producer writes media data to the memory, it writes Barrier data, including the stream ID and data address range of the media data being written, to the corresponding Barrier module, and broadcasts the Barrier data to each consumer.

[0047] S120, each consumer identifies the Barrier data, obtains the stream ID and data address range carried in the Barrier data, and reads the media data within the data address range from the media data represented by the stream ID corresponding to the target ID in the memory.

[0048] Optionally, writing Barrier data, including the stream ID and data address range of the media data to the corresponding Barrier module, includes: obtaining the operating clock received by the corresponding Barrier module, and writing the Barrier data into the time slice corresponding to the Barrier module according to the operating clock.

[0049] The above-described media data transmission method is implemented through the media data transmission system described in any of the above embodiments, and has all the beneficial effects of the media data transmission system described in any of the above embodiments, which will not be repeated here.

[0050] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0051] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0052] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0053] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. A media data transmission system, characterized in that, The media data transmission system includes a group of producers, a group of consumers, and a Barrier module corresponding to each producer and each consumer. The Barrier module corresponding to each producer is located on the write address channel of the AXI bus, and the Barrier module corresponding to each consumer is located on the read address channel of the AXI bus. Each Barrier module is connected in series through the Barrier bus. Each consumer is pre-set with the target ID of the required media data. Each producer writes Barrier data, including the stream ID and data address range of the media data being written, to the corresponding Barrier module when writing media data to the memory, and broadcasts the Barrier data to each consumer. Each consumer is used to identify the Barrier data, obtain the stream ID and data address range carried in the Barrier data, and read the media data within the data address range from the media data represented by the stream ID corresponding to the target ID in the memory.

2. The media data transmission system according to claim 1, characterized in that, The Barrier data also includes the data packet's sequence number and verification parameters.

3. The media data transmission system according to claim 1, characterized in that, Each of the producers is also used to obtain the working clock received by the corresponding Barrier module, and write the Barrier data into the time slice corresponding to the Barrier module according to the working clock.

4. The media data transmission system according to claim 3, characterized in that, Each producer is also used to acquire start and end signals; the start signal is used to indicate the start of the corresponding message, and the end signal is used to indicate the end of the corresponding message.

5. The media data transmission system according to claim 3, characterized in that, Each of the aforementioned producers has a first CSR register, which stores information about whether it is the first node; Each producer is also used to write the corresponding time slice to the corresponding Barrier module according to the working clock, starting from the first enabled media data stream when it is the first node, until the time slices corresponding to all enabled media data streams have been sent.

6. The media data transmission system according to claim 5, characterized in that, Each of the aforementioned producers is also used to write the corresponding time slice to the corresponding Barrier module after receiving Barrier data from the upstream when it is not the first node. This is done starting from the first media data stream it enables and following the constraint of increasing stream ID.

7. The media data transmission system according to claim 3, characterized in that, Each of the aforementioned consumers is provided with a second CSR register, which stores information on whether it is the end node; Each consumer is also used to read data with a time slice limit corresponding to the target ID when it is the end node.

8. The media data transmission system according to claim 7, characterized in that, Each consumer is also used to read the time-slice-limited data corresponding to the target ID when it is not the end node, and to continue to pass the Barrier data of the corresponding Barrier module to the downstream Barrier module.

9. A media data transmission method, characterized in that, The media data transmission method is implemented by the media data transmission system according to any one of claims 1 to 8; the media data transmission system includes a group of producers, a group of consumers, and a Barrier module corresponding to each producer and each consumer; the Barrier module corresponding to each producer is located on the write address channel of the AXI bus, and the Barrier module corresponding to each consumer is located on the read address channel of the AXI bus, and each Barrier module is connected in series through the Barrier bus; each consumer is pre-set with the target ID of the required media data; the media data transmission method includes: When each producer writes media data to the memory, it writes Barrier data, which includes the stream ID and data address range of the media data being written, to the corresponding Barrier module, and broadcasts the Barrier data to each consumer. Each consumer is used to identify the Barrier data, obtain the stream ID and data address range carried in the Barrier data, and read the media data within the data address range from the media data represented by the stream ID corresponding to the target ID in the memory.

10. The media data transmission system according to claim 9, characterized in that, The step of writing barrier data, including the stream ID and data address range of the media data to the corresponding barrier module, includes: obtaining the working clock received by the corresponding barrier module, and writing the barrier data into the time slice corresponding to the barrier module according to the working clock.

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