Display interface control system and medical ultrasound device

Abstract

The application discloses a display interface control system and a medical ultrasonic equipment. When a hot plug signal of a first display interface is detected as a high level, a mutual exclusion control unit in a priority control module actively pulls down a detection signal of a second display interface, so that the primary and secondary displays do not report to the system and compete for extended display communication at the same time. A delay enable unit outputs an enable signal to an auxiliary interface after a preset delay after the primary or secondary display completes the extended display data communication, so that each auxiliary display interface is activated and outputs an auxiliary hot plug detection signal only after the primary and secondary displays complete the expansion negotiation and are stable. Through mutual exclusion priority and delay cascade, the design prevents the enumeration / identification conflict and error mapping caused by the simultaneous triggering of multiple hot plug signals, ensures the correct identification and stable display mapping of the extended display data, and improves the display reliability and system stability of the medical ultrasonic equipment in a multi-screen output scene.

Description

Technical Field

[0001] This invention relates to the field of electrical equipment technology, and in particular to a display interface control system and a medical ultrasound device. Background Technology

[0002] In modern medical ultrasound diagnostic equipment, to balance the mobility of portable devices with the high-performance display requirements of trolley-type devices, the industry generally adopts an integrated medical motherboard design. This design supports the expansion of one integrated graphics output signal into multiple homogeneous video signals via a multi-display splitter circuit. In existing solutions, one signal is directly used as the main display interface for high-resolution imaging on trolley-type devices, while another signal is converted to a secondary display interface via an adapter chip for the integrated small screen on portable devices. An auxiliary display interface is also included to support extended applications such as dual-screen split-screen.

[0003] In this multi-output architecture, the CPU integrated graphics reads the extended display identification data (EDID) of the extended displays through the display data channel to automatically identify parameters such as the display's resolution and refresh rate and configure video output. The EDID reading process relies on the hot-plug detection signal of the display interface; when the HPD signal is high, it indicates a display is connected, and the integrated graphics immediately initiates the EDID reading process. However, the multi-display circuit itself lacks interface priority arbitration capabilities; its output HPD signals are parallel and independent. This means that when the system powers on or a display is connected, the reading of the EDID information depends entirely on which HPD signal is detected first by the integrated graphics, exhibiting significant randomness. This makes the EDID identification process susceptible to interference from unwanted interfaces, leading to errors and failing to ensure that the high-priority main display receives the correct configuration. This becomes a key technical bottleneck restricting the performance of multi-functional medical ultrasound equipment. Summary of the Invention

[0004] The embodiments of the present invention provide a display interface control system and a medical ultrasound device, which aim to solve the technical problem of incorrect recognition of expanded display data caused by multiple display outputs from the same source in the prior art medical ultrasound device.

[0005] In a first aspect, the present invention provides a display interface control system, the system connecting a main display and a secondary display, the system comprising: a first display interface connected to the main display and outputting a first hot-plug detection signal; a second display interface connected to the secondary display and outputting a second hot-plug detection signal; an auxiliary interface group including at least one auxiliary display interface, each of the auxiliary display interfaces being connected to a corresponding auxiliary display and outputting an auxiliary hot-plug detection signal; and a priority control module including a mutual exclusion control unit and a delay enable unit, the mutual exclusion control unit being connected to the first display interface and the second display interface, the mutual exclusion control unit pulling down the second hot-plug detection signal in response to the first hot-plug detection signal being high, the delay enable unit being connected to each of the interfaces, the delay enable unit outputting an auxiliary enable signal after a preset delay in response to the first hot-plug detection signal or the second hot-plug detection signal being high; wherein, the auxiliary display interface is activated to output the auxiliary hot-plug detection signal after the first display interface or the second display interface completes extended display representation data communication.

[0006] In the display interface control system provided by the present invention, the delay enable unit includes an OR gate, an RC circuit, a first MOS transistor and a second MOS transistor. The OR gate includes two input pins and one output pin. The two input pins of the OR gate are respectively connected to the first display interface and the second display interface. The input terminal of the RC circuit is connected to the output pin of the OR gate. The gate of the first MOS transistor is connected to the RC circuit, and the gate of the second MOS transistor is connected to the drain of the first MOS transistor.

[0007] In the display interface control system provided by the present invention, the auxiliary interface group includes a third display interface, a fourth display interface and a dual-channel diode. The third display interface outputs a third hot-plug detection signal, the fourth display interface outputs a fourth hot-plug detection signal, the common terminal of the dual-channel diode is connected to the drain of the second MOS transistor, and the two output terminals of the dual-channel diode are respectively connected to the third display interface and the fourth display interface.

[0008] In the display interface control system provided by the present invention, the mutual exclusion control unit includes a third MOS transistor, a current-limiting resistor and a clamping diode. One end of the current-limiting resistor is connected to the first display interface, the gate of the third MOS transistor is connected to the other end of the current-limiting resistor, the anode of the clamping diode is connected to the drain of the third MOS transistor, and the cathode of the clamping diode is connected to the second display interface.

[0009] In the display interface control system provided by the present invention, when the OR gate outputs a high level, the first MOS transistor is turned on and the second MOS transistor is turned off after a delay by the RC circuit, so that the auxiliary enable signal output by the drain of the second MOS transistor is high.

[0010] In the display interface control system provided by the present invention, when the first hot-plug detection signal is high, the third MOS transistor is turned on and pulls the second hot-plug detection signal low.

[0011] In the display interface control system provided by the present invention, the delay enable unit further includes a first pull-up resistor, a second pull-up resistor and a third pull-up resistor. The first pull-up resistor is connected to the gate of the first MOS transistor, the second pull-up resistor is connected to the drain of the first MOS transistor, and the third pull-up resistor is connected to the drain of the second pull-up resistor.

[0012] In the display interface control system provided by the present invention, the mutual exclusion control unit further includes a fourth pull-up resistor connected to the anode of the clamping diode.

[0013] In the display interface control system provided by the present invention, the display allocation module is an HDMI 1-to-4 chip, the first display interface is a 4K HDMI interface, the second display interface is an LVDS interface, and the auxiliary interface group includes at least one HDMI interface and at least one VGA interface.

[0014] Secondly, the present invention provides a medical ultrasound device, including the aforementioned display interface control system.

[0015] Compared with the prior art, the beneficial effects of the present invention are: In the technical solution of this invention, the mutual exclusion control unit in the priority control module actively pulls down the detection signal of the second display interface when the hot-plug signal of the first display interface is detected to be high, thus preventing the primary and secondary displays from simultaneously reporting to the system and competing for extended display communication. Simultaneously, the delay enable unit outputs the enable signal for the auxiliary interface after a preset delay following the completion of extended display data communication by the primary or secondary display. This ensures that each auxiliary display interface is activated and outputs the auxiliary hot-plug detection signal only after the primary and secondary displays have completed and stabilized the extended display negotiation. This design, through mutual exclusion priority and delay cascading, prevents enumeration / recognition conflicts and incorrect mappings caused by simultaneous triggering of multiple hot-plug signals, ensuring correct recognition and stable display mapping of extended display data, and improving display reliability and system stability in multi-screen output scenarios of medical ultrasound equipment. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the delay enable unit circuit of the priority control module of the display interface control system according to an embodiment of the present invention; Figure 2 This is a circuit diagram of the mutual exclusion control unit of the priority control module of the display interface control system according to an embodiment of the present invention; Figure label explanation: 10. Delay enable unit; 11. OR gate; 12. RC circuit; 121. RC resistor; 122. RC capacitor; 131. First MOSFET; 132. Second MOSFET; 141. First pull-up resistor; 142. Second pull-up resistor; 143. Third pull-up resistor; 15. Interstage coupling resistor; 16. Dual diode; 21. First display interface; 22. Second display interface; 23. Third display interface; 24. Fourth display interface; 30. Mutual exclusion control unit; 31. Current limiting resistor; 32. Third MOSFET; 33. Clamping diode; 34. Fourth pull-up resistor. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0020] This invention provides a display interface control system, aiming to solve the technical problem of data recognition errors caused by multiple simultaneous display outputs in existing medical ultrasound equipment. (Refer to...) Figure 1 and Figure 2The system connects a main display and a secondary display. The system includes: a first display interface 21, connected to the main display and outputting a first hot-plug detection signal; a second display interface 22, connected to the secondary display and outputting a second hot-plug detection signal; an auxiliary interface group, including at least one auxiliary display interface, each auxiliary display interface connected to its corresponding auxiliary display and outputting an auxiliary hot-plug detection signal; and a priority control module, including a mutual exclusion control unit 30 and a delay enable unit 10. The mutual exclusion control unit 30 is connected to the first display interface 21 and the second display interface 22. When the first hot-plug detection signal is high, the mutual exclusion control unit 30 pulls down the second hot-plug detection signal. The delay enable unit 10 is connected to each of the interfaces. When either the first or second hot-plug detection signal is high, the delay enable unit 10 outputs an auxiliary enable signal after a preset delay. The auxiliary display interface is activated to output the auxiliary hot-plug detection signal after the first display interface 21 or the second display interface 22 completes extended display representation data communication. The display interface control system is applied to the motherboard of the medical ultrasound equipment. The first display interface 21 is a built-in 4K HDMI interface, connected to the main display of the trolley-type ultrasound device, and its hot-plug detection pin outputs a first hot-plug detection signal (HPD1). The second display interface 22 is an LVDS interface, connected to the secondary display of the portable ultrasound device, and its hot-plug detection pin outputs a second hot-plug detection signal (HPD2). The signal path of this secondary display is pre-connected to an LVDS adapter chip RTD2281CL, which has a built-in 1080P EDID. The auxiliary interface group includes an exposed HDMI interface and an HDMI-to-VGA interface, used to connect external auxiliary displays. The mutual exclusion control unit 30 of the priority control module is connected to HPD1 and HPD2 through a third MOSFET 32. When HPD1 is high, the third MOSFET 32 is turned on, pulling the HPD2 signal low, thereby shielding the EDID of the secondary display. The delay enable unit 10 responds to the rising edge of HPD1 or HPD2 through OR gate 11 and RC delay circuit, and outputs a high-level auxiliary enable signal after delay to control the HPD signal path of the auxiliary interface group, ensuring that the auxiliary display is only recognized by the system after the main or secondary display has completed EDID communication, thereby realizing reliable management of display priority.

[0021] In one embodiment, reference is made to Figure 1The delay enable unit 10 includes an OR gate 11, an RC circuit 12, a first MOSFET 131, and a second MOSFET 132. The OR gate 11 has two input pins and one output pin. The two input pins of the OR gate 11 are respectively connected to the first display interface 21 and the second display interface 22. The input terminal of the RC circuit 12 is connected to the output pin of the OR gate 11. The gate of the first MOSFET 131 is connected to the RC circuit 12, and the gate of the second MOSFET 132 is connected to the drain of the first MOSFET 131. The OR gate 11, model SN74AHC1G32, is used as the logic control core. Its two input pins are respectively connected to the hot-plug detection pins of the first display interface 21 and the second display interface 22, and are used to output a high-level signal when either the primary or secondary display is connected. The output signal, after passing through the RC circuit 12 composed of RC resistor 121 and RC capacitor 122, is connected to the gate of the first MOSFET 131. The RC resistor 121, acting as a current-limiting resistor 31, is connected in series between the output of the OR gate 11 and the gate of the first MOSFET 131. One end of the RC capacitor 122 is connected to the gate of the first MOSFET 131, and the other end is grounded, forming a charging and discharging circuit. The product of the resistor and capacitor sets the preset delay required by the system, ensuring that the EDID information of the primary or secondary display can be transmitted preferentially. The source of the first MOSFET 131 is grounded, and its drain is connected to the +5.0V power supply through the second pull-up resistor 142, and further connected to the gate of the second MOSFET 132. In addition, an interstage coupling resistor 15 is provided between the drain of the first MOSFET 131 and the gate of the second MOSFET 132. When the RC circuit 12 completes charging and the first MOSFET 131 is turned on, its drain level is pulled low, thereby turning off the second MOSFET 132. The drain of the second MOSFET 132 serves as the output terminal of the auxiliary enable signal, connected to the power supply via the third pull-up resistor 143. When the second MOSFET 132 is turned off, its drain is at a high level, serving as an effective enable signal output to activate the HPD path of the subsequent auxiliary interface. By cascading two MOSFETs, level conversion of the control signal and enhanced driving capability are achieved, ensuring the stability and reliability of timing control.

[0022] In one embodiment, reference is made to Figure 1The auxiliary interface group includes a third display interface 23, a fourth display interface 24, and a dual-channel diode 16. The third display interface 23 outputs a third hot-plug detection signal, and the fourth display interface 24 outputs a fourth hot-plug detection signal. The common terminal of the dual-channel diode 16 is connected to the drain of the second MOSFET 132, and the two output terminals of the dual-channel diode 16 are respectively connected to the third display interface 23 and the fourth display interface 24. The auxiliary interface group is configured to support external extended display functions. Specifically, it includes the third display interface 23 and the fourth display interface 24, which are respectively implemented as an exposed HDMI interface and a VGA interface implemented through an HDMI to VGA converter chip, such as ADM1182, for connecting to external monitors or teaching displays. The dual-channel diode 16 is a common-cathode dual Schottky diode of model BAT54RC, and its common terminal is connected to the drain of the second MOSFET 132 as the receiving end of the auxiliary enable signal. When the second MOSFET 132 is turned off, its drain is at a high level. This high level is transmitted through the common terminal of the dual diode 16, causing both diodes to be in a reverse cutoff state. At this time, the hot-plug detection pins of the third display interface 23 and the fourth display interface 24 can be normally pulled up to a high level through their respective pull-up resistors, thereby announcing to the system that the auxiliary display has been connected and realizing the normal output of the third and fourth hot-plug detection signals. When the second MOSFET 132 is turned on, its drain is pulled low, and the common terminal of the dual diode 16 is forced low. Regardless of whether the external device is connected, the HPD signals of the third and fourth display interfaces 24 are clamped at a low level and cannot be recognized by the system. The synchronous enable control of the two auxiliary interfaces is achieved through a single dual diode 16. The circuit is simple, low-cost, and highly reliable, effectively ensuring that the auxiliary display function is only activated after the main or secondary display completes EDID communication.

[0023] In one embodiment, reference is made to Figure 2The mutual exclusion control unit 30 includes a third MOSFET 32, a current-limiting resistor 31, and a clamping diode 33. One end of the current-limiting resistor 31 is connected to the first display interface 21, the gate of the third MOSFET 32 is connected to the other end of the current-limiting resistor 31, the anode of the clamping diode 33 is connected to the drain of the third MOSFET 32, and the cathode of the clamping diode 33 is connected to the second display interface 22. The mutual exclusion control unit 30 is implemented as a hardware interlock circuit composed of the third MOSFET 32, the current-limiting resistor 31, and the clamping diode 33. One end of the current-limiting resistor 31 is connected to the hot-plug detection pin of the first display interface 21 to receive the first hot-plug detection signal, and the other end is connected to the gate of the third MOSFET 32 to limit the input current and protect the gate of the MOSFET. The third MOSFET 32 is an N-channel enhancement-type MOSFET of model 2N7002, with its source grounded and its drain connected to the anode of the clamping diode 33. The clamping diode 33 is a Schottky diode LBAT54HT1G, whose cathode is connected to the hot-plug detection pin of the second display interface 22 to transmit the second hot-plug detection signal. When the main display is connected and the first hot-plug detection signal is high, this high level is applied to the gate of the third MOSFET 32 through the current-limiting resistor 31, turning on the third MOSFET 32 and pulling its drain level low. This, in turn, forces the HPD2 signal low through the anode of DA1, thereby shielding the secondary display interface and preventing its internally fixed 1080P EDID from being read by the CPU integrated graphics. When the main display is not connected and the first hot-plug detection signal is low, the third MOSFET 32 is in the off state, and its drain is in a high-impedance state. The second hot-plug detection signal is controlled by the normal drive circuit of the secondary display interface, and EDID communication can be performed normally. The clamping diode 33 achieves unidirectional isolation of the level, avoiding the signal from the secondary display from affecting the control loop in reverse, and ensuring the stability and reliability of the mutual exclusion logic.

[0024] In one embodiment, reference is made to Figure 1When the OR gate 11 outputs a high level, after a delay by the RC circuit 12, the first MOSFET 131 is turned on and the second MOSFET 132 is turned off, making the auxiliary enable signal output from the drain of the second MOSFET 132 high. When a display is connected to the first display interface 21 or the second display interface 22, its first or second hot-plug detection signal becomes high, making any input pin of the OR gate 11 high, and the OR gate 11 outputs a high-level signal. This high-level signal slowly charges the gate of the first MOSFET 131 through the RC circuit 12. After a preset delay determined by the parameters of the RC resistor 121 and the RC capacitor 122, the gate voltage of the first MOSFET 131 rises above its turn-on threshold, thereby turning on the first MOSFET 131. At this time, the drain of the first MOSFET 131, pulled up to the power supply level through the second pull-up resistor 142, is pulled down to a low level by the conduction channel of the first MOSFET 131. This low level is applied as a control signal to the gate of the second MOSFET 132, causing the second MOSFET 132 to turn off. Since the drain of the second MOSFET 132 is connected to the +5.0A power supply through the third pull-up resistor 143, when the second MOSFET 132 is turned off, its drain level rises to a high level, which is output as an auxiliary enable signal. This auxiliary enable signal, through the common terminal of the dual diodes 16, releases the clamping of the hot-plug detection signals of the third display interface 23 and the fourth display interface 24, allowing them to establish a high level normally through their respective pull-up resistors, thereby activating the auxiliary interface group and enabling the external auxiliary display to be detected by the system and perform EDID communication. This process ensures that the activation of the auxiliary display interface strictly lags behind the main or secondary display interface, effectively avoiding EDID reading competition and errors when multiple outputs originate from the same source.

[0025] In one embodiment, reference is made to Figure 2When the first hot-plug detection signal is high, the third MOSFET 32 is turned on and pulls the second hot-plug detection signal low. When the main display is connected to the first display interface 21, the first hot-plug detection signal is high, and this high-level signal is transmitted to the gate of the third MOSFET 32 via the current-limiting resistor 31. Since the third MOSFET 32 is an N-channel MOSFET, when its gate voltage reaches the turn-on threshold, the third MOSFET 32 changes from the cutoff state to the on state, and a low-resistance path is formed between its drain and source. At this time, the anode of the clamping diode 33 connected to the drain of the third MOSFET 32 is directly pulled low. Since the cathode of the clamping diode 33 is connected to the hot-plug detection pin of the second display interface 22, when the anode of the clamping diode 33 is pulled low, its cathode level is also clamped to a low level, thereby forcibly pulling the second hot-plug detection signal low. Regardless of whether the secondary display is actually connected, the system cannot detect a valid HPD signal. This process prevents the CPU integrated graphics from reading the EDID information of the secondary display interface, ensuring priority recognition by the primary display. When the primary display is disconnected and the first hot-plug detection signal returns to a low level, the gate of the third MOSFET 32 is low, the MOSFET is turned off, and its drain returns to a high-impedance state. At this time, the anode of the clamping diode 33 is pulled high by the fourth pull-up resistor 34, the clamping diode 33 is cut off, and the second hot-plug detection signal of the second display interface 22 is no longer forcibly pulled low. It can change normally according to the actual connection status of the secondary display, thereby realizing hardware-level mutual exclusion control between the primary and secondary display interfaces.

[0026] In one embodiment, reference is made to Figure 1The delay enable unit 10 further includes a first pull-up resistor 141, a second pull-up resistor 142, and a third pull-up resistor 143. The first pull-up resistor 141 is connected to the gate of the first MOSFET 131, the second pull-up resistor 142 is connected to the drain of the first MOSFET 131, and the third pull-up resistor 143 is connected to the drain of the second MOSFET 132. The delay enable unit 10 further includes the first pull-up resistor 141, the second pull-up resistor 142, and the third pull-up resistor 143 to ensure the stable and reliable switching of the levels of each MOSFET node under different operating conditions. The first pull-up resistor 141 is connected between the power supply +5.0A and the gate of the first MOSFET 131. When the OR gate 11 outputs a low level and the RC circuit 12 is in a discharging state, the first pull-up resistor 141 provides a discharge path for the RC capacitor 122 and ensures that the gate of the first MOSFET 131 is reliably pulled high when there is no driving signal, accelerating the turn-off process of the first MOSFET 131 and improving the stability of the circuit response. The second pull-up resistor 142 is connected between the +5.0A power supply and the drain of the first MOSFET 131. When the first MOSFET 131 is off, the second pull-up resistor 142 pulls the drain of the first MOSFET 131 to a high level, ensuring that this node has the ability to drive the second MOSFET 132. When the first MOSFET 131 is on, the second pull-up resistor 142 and the first MOSFET 131 form a voltage divider. Its resistance value must be designed to effectively pull the drain of the first MOSFET 131 low enough to turn off the second MOSFET 132. The third pull-up resistor 143 is connected between the +5.0A power supply and the drain of the second MOSFET 132. When the second MOSFET 132 is off, the third pull-up resistor 143 pulls the auxiliary enable signal to a high level as an effective enable output. When the second MOSFET 132 is on, the resistance value of the third pull-up resistor 143 must be large enough to limit the current flowing through it, while ensuring that the second MOSFET 132 can sufficiently pull its drain low. The introduction of these three pull-up resistors improves the electrical environment of the entire delay enable unit 10, effectively prevents false triggering or oscillation that may be caused by floating nodes, and significantly improves the reliability of control timing and the anti-interference capability of the circuit.

[0027] In one embodiment, reference is made to Figure 2The mutual exclusion control unit 30 further includes a fourth pull-up resistor 34, connected to the anode of the clamping diode 33. One end of the fourth pull-up resistor 34 is connected to a +5.0A power supply, and the other end is connected to the anode of the clamping diode 33. When the first hot-plug detection signal is low and the third MOSFET 32 is off, the fourth pull-up resistor 34 provides a stable high-level pull-up to the anode of the clamping diode 33, ensuring that the node is not in a floating state. At this time, if the secondary display is already connected, its second hot-plug detection signal can be kept high through its own pull-up mechanism, and the system can normally identify the secondary display and perform EDID communication. Once the main display is connected, the first hot-plug detection signal goes high, the third MOSFET 32 turns on, and its drain level is pulled low. At this time, the fourth pull-up resistor 34 forms a path with the third MOSFET 32. The resistance value of the fourth pull-up resistor 34 must be designed to ensure that the current flowing through it is within the safe range of the MOSFET, while also being effectively pulled low by the third MOSFET 32. This allows the clamping diode 33 to reliably force the HPD2 signal low, achieving complete shielding of the secondary display. The introduction of the fourth pull-up resistor 34 not only ensures a stable high-level output from the mutual exclusion control unit 30 when the third MOSFET 32 is turned off, but also optimizes the power consumption and switching response speed of the circuit through its reasonable resistance value (specifically 10kΩ). This ensures the smoothness and reliability of the switching process between the main and secondary display interfaces, effectively avoiding display recognition abnormalities caused by uncertain node levels.

[0028] In one embodiment, the display distribution module is an HDMI 1-to-4 splitter chip. The first display interface 21 is a 4K HDMI interface, the second display interface 22 is an LVDS interface, and the auxiliary interface group includes at least one HDMI interface and at least one VGA interface. The display distribution module uses an HDMI 1-to-4 splitter chip of model LT86104UX, which synchronously distributes one HDMI video signal from the CPU integrated graphics into four outputs from the same source. The first output is directly connected to the first display interface 21, which is a standard 4K HDMI interface used to connect to the main display of a trolley-type ultrasound diagnostic instrument, supporting 4K@60Hz high-resolution display to meet the high image detail requirements of hospital departments. The second output is connected to the LVDS converter chip RTD2281CL, which converts the HDMI signal into an LVDS signal and outputs it to the second display interface 22. This interface is used to connect to the small to medium-sized LCD screen built into the portable ultrasound instrument, supporting 1080P resolution, suitable for mobile scenarios such as outpatient visits and bedside examinations. The third output, as part of the auxiliary interface group, is directly led out as an exposed HDMI interface, which can be used to connect to an external monitor for teaching demonstrations or dual-screen triage. The fourth output is connected to a VGA interface via an HDMI to VGA conversion circuit to ensure compatibility with VGA interface display devices still widely used in hospitals. This conversion circuit includes a conversion chip such as ADV7623 and an external filtering and matching circuit. The mutual exclusion control unit 30 and delay enable unit 10 of the priority control module are respectively connected to the hot-plug detection lines of these interfaces to ensure that the 4K HDMI main interface has the highest priority during system power-on or hot-plugging, which can forcibly shield the EDID interference of the LVDS interface. At the same time, the exposed HDMI and VGA auxiliary interfaces are only activated after a delay after the main or secondary interface has successfully established a connection and completed EDID communication, thereby ensuring that the system always reads the correct display capability information first, achieving stable and reliable operation in complex multi-display scenarios.

[0029] This invention also provides a medical ultrasound device, which includes the display interface control system described in the above embodiments. The medical ultrasound device includes a main unit housing, an ultrasound imaging processing unit, an operation panel, and the display interface control system. The device is designed to be adaptable to both trolley-type and portable usage scenarios. The CPU integrated graphics in the main unit outputs one high-definition video signal, which is connected to an HDMI 1-to-4 splitter chip in the display interface control system. This chip splits the signal into four paths, connecting them to a first display interface 21 (4K HDMI interface), a second display interface 22 (LVDS interface), and an auxiliary interface group (exposed HDMI and VGA interfaces). When the device is used as a cart-type ultrasound diagnostic instrument in a hospital department, the user connects a 4K monitor to the first display interface 21. Its first hot-plug detection signal is high, triggering the mutual exclusion control unit 30 of the priority control module. This, through the conduction of the third MOSFET 32, forces the second hot-plug detection signal of the second display interface 22 low, shielding the 1080P EDID of the built-in LVDS screen. Simultaneously, the delay enable unit 10 responds to the first hot-plug detection signal, and after a delay by the RC circuit 12, activates the auxiliary enable signal. This ensures that the exposed HDMI and VGA interfaces can only be connected and used after the main display is stable, guaranteeing that the CPU prioritizes reading the 4K EDID and outputs the best image. When the device is used as a portable ultrasound instrument for field emergency or bedside examinations, the first display interface 21 is not connected, the first hot-plug detection signal is low, and the mutual exclusion control unit 30 releases the shielding of the second hot-plug detection signal. The built-in LVDS screen operates normally, and the system runs at 1080P resolution. At the same time, the auxiliary interface still needs to be activated after a delay after the LVDS screen is connected to ensure the stability of the display configuration. This integrated design enables a single device to intelligently identify usage scenarios without software configuration, achieving automatic priority management of display output, significantly improving the versatility, reliability, and user experience of medical ultrasound equipment.

[0030] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display interface control system, characterized in that, The system connects a main display and a secondary display, and the system includes: A first display interface is connected to the main display and outputs a first hot-plug detection signal. The second display interface is connected to the secondary display and outputs a second hot-plug detection signal. An auxiliary interface group includes at least one auxiliary display interface, each of which is connected to the corresponding auxiliary display and outputs an auxiliary hot-plug detection signal. The priority control module includes a mutual exclusion control unit and a delay enable unit. The mutual exclusion control unit is connected to the first display interface and the second display interface. When the first hot-plug detection signal is high, the mutual exclusion control unit pulls down the second hot-plug detection signal. The delay enable unit is connected to each of the interfaces. When the first hot-plug detection signal or the second hot-plug detection signal is high, the delay enable unit outputs an auxiliary enable signal after a preset delay. The auxiliary display interface is activated after the first display interface or the second display interface completes the extended display representation data communication to output the auxiliary hot-plug detection signal.

2. The display interface control system according to claim 1, characterized in that, The delay enable unit includes an OR gate, an RC circuit, a first MOSFET, and a second MOSFET. The OR gate includes two input pins and one output pin. The two input pins of the OR gate are respectively connected to the first display interface and the second display interface. The input terminal of the RC circuit is connected to the output pin of the OR gate. The gate of the first MOSFET is connected to the RC circuit, and the gate of the second MOSFET is connected to the drain of the first MOSFET.

3. The display interface control system according to claim 2, characterized in that, The auxiliary interface group includes a third display interface, a fourth display interface, and a dual-channel diode. The third display interface outputs a third hot-plug detection signal, and the fourth display interface outputs a fourth hot-plug detection signal. The common terminal of the dual-channel diode is connected to the drain of the second MOS transistor, and the two output terminals of the dual-channel diode are respectively connected to the third display interface and the fourth display interface.

4. The display interface control system according to claim 1, characterized in that, The mutual exclusion control unit includes a third MOSFET, a current-limiting resistor, and a clamping diode. One end of the current-limiting resistor is connected to the first display interface, the gate of the third MOSFET is connected to the other end of the current-limiting resistor, the anode of the clamping diode is connected to the drain of the third MOSFET, and the cathode of the clamping diode is connected to the second display interface.

5. The display interface control system according to claim 3, characterized in that, When the OR gate outputs a high level, the first MOS transistor is turned on and the second MOS transistor is turned off after a delay by the RC circuit, so that the auxiliary enable signal output from the drain of the second MOS transistor is high.

6. The display interface control system according to claim 4, characterized in that, When the first hot-plug detection signal is high, the third MOS transistor is turned on and pulls the second hot-plug detection signal low.

7. The display interface control system according to claim 3, characterized in that, The delay enable unit further includes a first pull-up resistor, a second pull-up resistor, and a third pull-up resistor. The first pull-up resistor is connected to the gate of the first MOS transistor, the second pull-up resistor is connected to the drain of the first MOS transistor, and the third pull-up resistor is connected to the drain of the second MOS transistor.

8. The display interface control system according to claim 4, characterized in that, The mutual exclusion control unit also includes a fourth pull-up resistor connected to the anode of the clamping diode.

9. The display interface control system according to claim 1, characterized in that, The display distribution module is an HDMI 1-to-4 chip, the first display interface is a 4K HDMI interface, the second display interface is an LVDS interface, and the auxiliary interface group includes at least one HDMI interface and at least one VGA interface.

10. A medical ultrasound device, characterized in that, The display interface control system includes any one of claims 1 to 9.

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