A low-latency data transmission method, device, apparatus and storage medium

Abstract

The application discloses a low-latency data transmission method applied to a FPGA PCIe optical fiber card and a Linux system cooperative interaction scene, and comprises the following steps: receiving to-be-transmitted data issued by an external device through a fiber transceiver interface of the PCIe optical fiber card, analyzing the to-be-transmitted data and performing reordering, and writing the reordered data into a cache area; using a built-in DMA engine to extract the to-be-transmitted data in the cache area and recording data state information; synchronously writing the to-be-transmitted data and the data state information into shared memory, so that a user real-time task of the Linux system reads the data state information in the shared memory at a preset polling period, and judges whether the data is successfully arrived according to the data state information; and if the judgment is successful arrival, reading the to-be-transmitted data from the shared memory. The application can eliminate the latency and jitter introduced by interrupt notification and frequent system calls in the data transmission process, reduce the data transmission latency, and meet the hard real-time scene requirement.

Description

Technical Field

[0001] This invention relates to the field of PCIe communication technology, and in particular to a low-latency data transmission method, apparatus, device, and storage medium. Background Technology

[0002] In hard real-time data transmission scenarios, the scenarios have stringent microsecond-level deterministic requirements for end-to-end transmission latency and latency jitter. However, existing Linux systems are limited by software interrupt response latency, too many kernel preemption points, and large task scheduling jitter, which have obvious shortcomings.

[0003] Existing technologies use FPGA or ASIC accelerator cards to interact with Linux systems, but they typically employ loose coupling methods, such as through PCIe character devices, ioctl, and system function calls. This results in significant hardware-software interaction overhead. System calls trigger user-mode / kernel-mode context switching, and PCIe interrupts, MMIO register reads and writes, and driver protocol stacks all introduce additional delays at the microsecond level with significant fluctuations. Furthermore, existing solutions lack a unified hardware-software real-time task partitioning and collaborative scheduling mechanism. Even if the data processing latency within the FPGA can reach the nanosecond level and the timing is deterministic, the end-to-end transmission latency of the entire system is still entirely constrained by CPU-side scheduling jitter and hardware-software interaction losses, failing to meet the stringent latency deterministic requirements of hard real-time services.

[0004] Overall, there is a lack of a method to address the uncertainty of latency in Linux systems when processing hard real-time events, and to reduce the data path and synchronization overhead between FPGA hardware acceleration units and Linux real-time tasks. Summary of the Invention

[0005] This invention provides a low-latency data transmission method that can eliminate latency and jitter introduced by interrupt notifications and frequent system calls during data transmission, reduce end-to-end data transmission latency, and meet the requirements of hard real-time scenarios.

[0006] In a first aspect, embodiments of the present invention provide a low-latency data transmission method applied to a scenario of collaborative interaction between an FPGA PCIe fiber optic card and a Linux system, including: The PCIe fiber optic card receives data to be transmitted from external devices via its fiber optic transceiver interface, parses the data to be transmitted and reorders it, and writes the reordered data into the buffer. The built-in DMA engine is used to extract the data to be transferred from the buffer and record the data status information. The data to be transmitted and the data status information are synchronously written into the shared memory so that the user real-time task of the Linux system reads the data status information in the shared memory at a preset polling period and determines whether the data has been successfully delivered based on the data status information. If the arrival is determined to be successful, the data to be transmitted is read from the shared memory; wherein, the shared memory is a pre-allocated, user-accessible physical contiguous memory on the Linux host.

[0007] Furthermore, the PCIe fiber optic card has a built-in SRIO IP core, which is divided into three protocol processing units: physical layer, transport layer, and logical layer. Therefore, parsing and reordering the data to be transmitted includes: Based on the physical layer, transport layer and logic layer of the SRIO IP core, the protocol parsing of the data to be transmitted is completed layer by layer; Based on the sequence number and timestamp carried in the parsed data packet, the data to be transmitted is reordered.

[0008] Furthermore, the shared memory is mapped to the virtual address space of the process to which the user's real-time task belongs through a memory mapping mechanism, so that the user's real-time task can directly read and write the shared memory based on the mapped virtual address pointer, thereby achieving zero-copy data access.

[0009] Furthermore, the data status information includes at least a data arrival flag, a memory write pointer, a buffer rollback count, a data packet length, a data packet sequence number, and a timestamp.

[0010] Furthermore, the polling and judgment logic for the user's real-time tasks is as follows: Read the memory write pointer stored in the shared memory and compare the memory write pointer with the locally maintained consumption offset; If the memory write pointer moves forward relative to the consumption offset, it is determined that there is newly arrived data to be transmitted in the shared memory that has not yet been read.

[0011] Furthermore, the method also includes a hard real-time environment configuration step before the user's real-time task runs, including: Set the user's real-time task to the SCHED_FIFO real-time scheduling policy and set the system's highest real-time priority; The user's real-time task is bound to a dedicated CPU core that is isolated by the kernel, and the CPU idle sleep power-saving state of that core is disabled.

[0012] Furthermore, the FPGA PCIe fiber optic card is electrically connected to the PCIe slot of the Linux host through a PCIe gold finger connector, thereby enabling PCIe bus data interaction between the FPGA PCIe fiber optic card and the Linux host.

[0013] Secondly, embodiments of the present invention provide a low-latency data transmission apparatus, comprising: The fiber optic receiving module is used to receive data to be transmitted from external devices through the fiber optic transceiver interface of the PCIe fiber optic card, parse the data to be transmitted and reorder it, and write the reordered data into the buffer area. The DMA engine module is used to extract the data to be transferred from the buffer using the built-in DMA engine and record the data status information. The status polling and judgment module is used to synchronously write the data to be transmitted and the data status information into the shared memory, so that the user real-time task of the Linux system reads the data status information in the shared memory at a preset polling period and judges whether the data has been successfully delivered based on the data status information. The data reading module is used to read the data to be transmitted from the shared memory if the arrival is determined to be successful; wherein, the shared memory is a physical contiguous memory pre-allocated by the Linux host and accessible in user space.

[0014] Thirdly, embodiments of the present invention provide an electronic device, comprising: Memory, used to store computer programs; A processor for executing the computer program; Wherein, when the processor executes the computer program, it implements the low-latency data transmission method described in any of the first aspects above.

[0015] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program, which, when executed, implements the low-latency data transmission method described in any of the first aspects above.

[0016] Compared with existing technologies, the low-latency data transmission method provided by this invention has the following advantages: It receives data to be transmitted from an external device through the fiber optic transceiver interface of a PCIe fiber optic card, parses and reorders the data, and writes the reordered data into a buffer; it uses a built-in DMA engine to extract the data to be transmitted from the buffer and records data status information; it synchronously writes the data to be transmitted and the data status information into shared memory, so that the Linux system's user real-time task reads the data status information in the shared memory at a preset polling cycle, and determines whether the data has successfully arrived based on the data status information; if it is determined that the data has successfully arrived, it reads the data to be transmitted from the shared memory; wherein, the shared memory is a pre-allocated, user-accessible physical contiguous memory of the Linux host. This invention can eliminate the latency and jitter introduced by interrupt notifications and frequent system calls during data transmission, reduce end-to-end data transmission latency, and meet the requirements of hard real-time scenarios. Attached Figure Description

[0017] To more clearly illustrate the technical features of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a low-latency data transmission method provided in an embodiment of the present invention; Figure 2 This is an overall architecture diagram of a low-latency data transmission method provided in an embodiment of the present invention; Figure 3 This is a hardware architecture diagram of an FPGA PCIe fiber optic card for a low-latency data transmission method provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of a low-latency data transmission device provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing embodiments of the invention only and is not intended to limit the invention.

[0022] It should be noted that the low-latency data transmission method of this invention is applied to the collaborative interaction scenario between FPGA PCIe fiber optic cards and Linux systems. See [link / reference]. Figure 2 This is the overall system architecture diagram.

[0023] The left frame in the diagram represents a Linux real-time host. The host contains a CPU, northbridge and southbridge chips, memory modules, and PCIe slots. The Linux real-time host is equipped with a PREEMPT_RT real-time kernel or a similar real-time Linux kernel, and deploys dedicated kernel driver modules and user-space real-time program libraries.

[0024] The right frame in the diagram is the FPGA PCIe fiber optic card. The FPGA PCIe fiber optic card is connected to the PCIe slot of the Linux real-time host through the PCIe gold fingers, establishing a high-speed PCIe x8 communication link between the two. The middle block diagram is the FPGA chip, which is the core processing device of the fiber optic card. The two blocks on the right are two QSFP28 fiber optic interfaces, used to connect to external remote devices to realize fiber optic data transmission and reception.

[0025] For example, see Figure 3 This is a hardware architecture diagram of an FPGA PCIe fiber optic card.

[0026] The FPGA PCIe fiber optic card hardware architecture includes two QSFP28 fiber optic transceiver interfaces, an SRIO controller, an FPGA logic module, a QSPI configuration memory, a multi-channel DDR4 controller, four-channel DDR4 cache, a PCIe endpoint controller, and a PCIex16 gold finger connector.

[0027] The left side of the diagram shows QSFP28 fiber optic transceiver interface #1 and QSFP28 fiber optic transceiver interface #2, which serve as the physical ports for high-speed fiber optic communication on the board. Each QSFP28 fiber optic transceiver interface is connected to an SRIO controller. The SRIO controller is based on the internal GTH high-speed serial transceiver of the FPGA and interfaces with the optical module to realize the data transmission and reception of the SRIO high-speed serial communication link.

[0028] The middle block diagram in the attached figure shows the FPGA logic module, which is the core logic unit inside the FPGA. It is used to complete functions such as message response maintenance, buffer scheduling, and transaction management. The user logic establishes internal data paths with two SRIO controllers, multiple DDR4 controllers, and PCIe endpoint controllers to realize data interaction and control between various interfaces.

[0029] The upper block diagram in the attached figure shows the configuration interface and the QSPI 128MB configuration memory. The configuration interface enables communication between the user logic and the QSPI configuration memory. The QSPI configuration memory serves as the FPGA configuration memory, used to embed the FPGA firmware program, enabling the FPGA logic to be automatically loaded and started when the board is powered on.

[0030] The right side of the attached diagram shows a multi-DDR4 controller. The multi-DDR4 controller is connected to four independent DDR4 4GB cache chips to form a large-capacity onboard cache. User logic accesses the DDR4 cache through the multi-DDR4 controller for local temporary storage and buffering queuing of business data.

[0031] The attached diagram shows the PCIe Endpoint Controller (PCIe EP Controller). The PCIe Endpoint Controller is connected to the user logic and implements the PCIe Gen3 x8 protocol function. The PCIe Endpoint Controller is connected to the PCIe x16 Finger connector. The FPGA PCIe fiber optic card is plugged into the host PCIe slot through the PCIe x16 Finger connector to complete the PCIe bus data interaction between the board and the host.

[0032] It should be noted that the Linux real-time system consists of two parts: the kernel module and the user-space real-time library. It works in conjunction with the FPGA PCIe fiber optic card to provide host-side software support for low-latency data transmission.

[0033] The kernel module includes a PCIe driver module, a shared memory manager, and a scheduling auxiliary interface. The PCIe driver module is used to initialize the FPGA PCIe fiber optic card device, allocate DMA buffers, and establish user-space memory mapping to ensure zero-copy data transmission, thereby meeting the requirements of low latency and high performance. The shared memory manager is responsible for mapping the FPGA DMA buffer and in-band transfer status information area to user space addresses. Based on this mapping mechanism, the FPGA can directly write data to the user-space accessible buffer via DMA, avoiding secondary data copying between kernel and user space and reducing data transmission latency. The scheduling auxiliary interface provides an ioctl interface or a sysfs file interface, opening up configuration capabilities to upper-layer user-space programs and supporting the setting of real-time parameters such as real-time scheduling priority, CPU affinity, and polling cycle for user-space tasks.

[0034] The user-space real-time library is custom-developed to work with FPGA PCIe fiber optic cards. It works in conjunction with the underlying kernel module to ensure microsecond-level deterministic low-latency data transmission for the entire system. Its core external interface functions include: 1) adc_system_init(ip, port, ch0, ch1): Completes system initialization and initializes the communication link between the FPGA PCIe fiber optic card and the acquisition hardware system; 2) adc_system_config(ADCConfig* config): Sends configuration parameters, completes hardware register configuration, and starts the data acquisition process; 3) adc_read_data(ch, buf, count): Reads data packets from the DMA shared buffer and reads the latest data packets into the application layer buffer.

[0035] The Linux real-time host and the FPGA PCIe fiber optic card rely on the PCIe x8 bus to complete high-speed data interaction, together forming the hardware system platform of this invention, providing complete hardware support for low-latency data transmission.

[0036] In a first aspect, embodiments of the present invention provide a low-latency data transmission method, see [link to previous document]. Figure 1 This is a flowchart illustrating an embodiment of a low-latency data transmission method provided by the present invention.

[0037] like Figure 1 As shown, the method includes the following steps: S1: Receive data to be transmitted from an external device through the fiber optic transceiver interface of the PCIe fiber optic card, parse the data to be transmitted and reorder it, and write the reordered data into the buffer area. Specifically, data from external devices is sent to the QSFP28 fiber optic transceiver interface via a fiber optic link. The data enters the fiber optic interface controller inside the FPGA. The fiber optic interface controller has a built-in SRIO IP core to parse and reorder the data, ensuring that out-of-order data is restored to the correct order. The reordered data packets are stored in the buffer unit.

[0038] S2: Use the built-in DMA engine to extract the data to be transferred from the buffer and record the data status information; Specifically, the FPGA's internal multi-channel DMA engine continuously reads the reordered data to be transmitted from the buffer unit and generates data status information simultaneously while extracting data packets.

[0039] S3: Synchronously write the data to be transmitted and the data status information into the shared memory, so that the user real-time task of the Linux system reads the data status information in the shared memory at a preset polling period, and determines whether the data has been successfully delivered based on the data status information; Specifically, the FPGA uses a DMA engine to write the service data to be transmitted and the data status information into the pre-allocated shared memory of the Linux host. The shared memory is physically contiguous. The Linux host uses a memory mapping mechanism to map the shared memory to the virtual address space of user processes, supporting direct access by user-mode processes.

[0040] The host starts a real-time user task, which continuously polls the data status information in the shared memory at a preset period and determines whether there are any new data packets based on the data status information.

[0041] S4: If the arrival is successful, read the data to be transmitted from the shared memory; wherein the shared memory is a physical contiguous memory pre-allocated by the Linux host and accessible in user space.

[0042] Specifically, when a user's real-time task determines that there is newly arrived data to be transmitted, it directly reads the business data from the shared memory based on the mapped virtual address pointer. The entire data reading process does not require system calls or data copying between kernel mode and user mode, achieving zero-copy access.

[0043] In summary, the FPGA fiber optic card of this invention writes service data and status information together into the shared memory accessible to the host user space. User real-time tasks read status information in a polling manner, abandoning the traditional interrupt notification and ioctl register access methods, eliminating the latency jitter caused by system calls and context switching. Combined with the Linux user space zero-copy access mechanism, it can control end-to-end latency jitter at the microsecond level, meeting the needs of hard real-time business scenarios such as industrial control and scientific experiments.

[0044] In one optional implementation, the PCIe fiber optic card has a built-in SRIO IP core, which is divided into three protocol processing units: physical layer, transport layer, and logical layer. Therefore, parsing and reordering the data to be transmitted includes: Based on the physical layer, transport layer and logic layer of the SRIO IP core, the protocol parsing of the data to be transmitted is completed layer by layer; Based on the sequence number and timestamp carried in the parsed data packet, the data to be transmitted is reordered.

[0045] Specifically, the PCIe fiber optic card is equipped with a fiber optic interface controller, which is interconnected with the standardized SRIO IP core hardware logic to fully implement the SRIO full message protocol processing flow in a layered manner. The SRIO IP core is divided into three layers of hardware pipeline logic from top to bottom: logic layer, transport layer and physical layer. The three layers of logic synchronously and in parallel complete the full-link protocol parsing of the fiber optic data stream.

[0046] The physical layer is responsible for performing 8B / 10B serial-to-parallel encoding and decoding operations on the high-speed differential serial data stream input from the optical fiber. It simultaneously completes the link clock recovery at both ends of the transmission and reception, continuous monitoring of the link status, transmission error verification, and automatic retransmission, ensuring the stability of long-distance optical fiber transmission links and the reliability of data transmission. The transmission layer identifies the routing field in the parsed message header, realizing multi-path optical fiber message routing distribution, port flow control, and multi-channel data stream isolation and forwarding. The logic layer standardizes various data interaction transaction types and standardizes message encapsulation formats. After stripping the SRIO protocol encapsulation header, it outputs clean original service messages to the user logic inside the FPGA, where the user logic performs pre-processing operations such as message field extraction and buffering.

[0047] Data parsed layer by layer by the fiber optic interface controller and SRIO IP core is uniformly sent to the built-in packet parsing and sorting unit of the PCIe fiber optic card for hardware timing regularization. During the packet transmission phase, the external acquisition device pre-embeds a globally incrementing packet sequence number and the original timestamp of the sending end in the packet payload header. The packet parsing and sorting unit extracts the sequence number and remote timestamp carried in the packet as the sorting criterion. It uses the on-chip high-speed cache resources of the FPGA to perform hardware-level enqueueing and buffering management on the out-of-order packets received in parallel. It strictly follows the original transmission timing of the external device to complete the reordering and regularization of multiple packets. The ordered service data after being regularized by the sorting unit is uniformly stored in the on-chip cache area of ​​the FPGA, providing a timing-regulated and out-of-order original service data stream for the integrated in-band writing of the back-end DMA engine to the host shared memory.

[0048] In one optional implementation, the shared memory is mapped to the virtual address space of the process to which the user's real-time task belongs through a memory mapping mechanism, so that the user's real-time task can directly read and write the shared memory based on the mapped virtual address pointer, thereby achieving zero-copy data access.

[0049] Specifically, the Linux host pre-allocates a segment of physical contiguous memory as shared memory to carry business data and data status information. The physical address of this shared memory segment is issued by the host kernel to the DMA engine built into the PCIe fiber optic card, allowing the DMA engine to directly complete data write operations. The host kernel driver provides a standardized memory mapping interface mmap. The driver program calls this interface to complete the address mapping configuration of the shared memory, directly mapping the entire segment of physical contiguous shared memory to the independent virtual address space of the process to which the user's real-time task belongs. After the mapping is completed, a one-to-one binding relationship is formed between the process virtual address and the underlying physical address of the shared memory.

[0050] During the execution of real-time tasks, there is no need to call system calls such as read, write, and ioctl to complete data interaction. The program can directly address, read and write all information stored in the underlying shared memory, such as business data packets, data arrival flags, write pointers, and hardware timestamps, simply through the virtual address pointer defined within the program. The entire data reading process does not involve data copying between the kernel buffer and the user process buffer. The host kernel only undertakes address mapping management and does not participate in the transfer of business data and status information, thus fully realizing a zero-copy data access path.

[0051] This embodiment establishes a direct access path between user processes and the host's underlying shared memory through a memory mapping mechanism, eliminating the data copying steps between kernel mode and user mode in traditional acquisition schemes, and eliminating bandwidth loss and additional transmission delay caused by data copying.

[0052] In one optional implementation, the data status information includes at least a data arrival flag, a memory write pointer, a buffer rollback count, a data packet length, a data packet sequence number, and a timestamp.

[0053] Specifically, the PCIe fiber optic card has a built-in status register set that stores data status information including at least the data arrival flag, memory write pointer, buffer rollback count, data packet length, data packet sequence number, and timestamp.

[0054] In a single PCIe transfer transaction, the DMA engine encapsulates all data status information in the status register group and the service data packet into a single data block, and synchronously writes it to a fixed offset storage area of ​​the Linux host's shared memory, so that various timing, transmission control metadata and service data coexist in the same physical contiguous shared memory.

[0055] After the host-side user real-time task maps shared memory to the process virtual address space via mmap, it can directly read all data status information and business payload through ordinary memory access operations, without having to call the ioctl system to access the PCIe device hardware registers, thus saving the additional latency caused by PCIe MMIO bus read / write and user-mode kernel-mode context switching.

[0056] In one optional implementation, the polling logic for the user's real-time task is as follows: Read the memory write pointer stored in the shared memory and compare the memory write pointer with the locally maintained consumption offset; If the memory write pointer moves forward relative to the consumption offset, it is determined that there is newly arrived data to be transmitted in the shared memory that has not yet been read.

[0057] Specifically, the user real-time task running on the Linux host side uses a polling mechanism to identify newly arrived business data in the shared memory. The task will independently maintain a consumption offset variable in local memory. This consumption offset is used to record the access position of the circular shared memory buffer when the user real-time task last completed the read processing, as a local reference identifier for determining new data.

[0058] The user's real-time task continuously executes the loop judgment logic according to the pre-configured microsecond-level fixed polling cycle. In each round of polling, the task directly reads the data status information stored in the shared memory through the mapped virtual address, extracts the memory write pointer updated in real time by the hardware DMA, and then compares the read hardware memory write pointer value with the consumption offset value continuously maintained locally by the task.

[0059] If the memory write pointer value is greater than the local consumption offset when no buffer rollback occurs, or if buffer rollback occurs, the number of rollbacks increases, and the memory write pointer value is less than the local consumption offset, then it is uniformly determined that the hardware memory write pointer has moved forward relative to the consumption offset. This indicates that the PCIe fiber optic card has written new service data packets to the shared memory, and there is valid data that has not been read and processed. After determining that new data exists, the user's real-time task directly reads the complete data from the corresponding storage location in the shared memory. After reading, the local consumption offset is synchronously updated to the current hardware write pointer position, and the next round of periodic polling is initiated.

[0060] The entire polling and judgment process only performs memory reads and numerical comparison operations, does not initiate system calls such as read and ioctl, does not trigger context switching between user mode and kernel mode, and does not rely on PCIe hardware interrupts or inter-core Mailbox interrupts to complete data readiness notifications. The polling thread keeps running throughout the process without entering a process sleep state.

[0061] In this embodiment, the user's real-time task reads data status information directly from memory without accessing the PCIe device's IO registers via ioctl, which can eliminate interrupt latency and scheduling jitter and stably maintain microsecond-level data response latency.

[0062] In an optional implementation, the method further includes a hard real-time environment configuration step before the user's real-time task runs, including: Set the user's real-time task to the SCHED_FIFO real-time scheduling policy and set the system's highest real-time priority; The user's real-time task is bound to a dedicated CPU core that is isolated by the kernel, and the CPU idle sleep power-saving state of that core is disabled.

[0063] Specifically, the thread real-time scheduling parameters are configured first. The program calls the sched_setscheduler system call to configure the scheduling strategy of the user's real-time polling task as the SCHED_FIFO first-in-first-out real-time scheduling mechanism, and sets the task's real-time priority to 99, which is the highest real-time priority supported by the Linux system. Based on the SCHED_FIFO scheduling rule, as long as the polling task is in the ready running state, all ordinary time-sharing scheduling processes and low-priority real-time processes on the same CPU core cannot preempt the current task's execution right, thus preventing other business programs from interrupting the polling loop at the scheduling rule level.

[0064] Secondly, complete the CPU core exclusive binding configuration. During the device host boot phase, a dedicated isolated CPU core is pre-specified through the kernel boot parameter isolcpus. The Linux kernel will not automatically schedule system daemons, kernel background threads, or general business processes to this core. When the program runs, it calls the sched_setaffinity system call to forcibly bind the user's real-time polling task to the aforementioned dedicated CPU core that is isolated by the kernel. This ensures that the computing resources of this core are only used by this data polling task, avoiding execution interruptions and timing fluctuations caused by multi-task resource contention.

[0065] At the same time, the program calls the mlockall system call to physically lock the entire memory space of the process, completely eliminating millisecond-level stuttering caused by page faults and memory page swapping operations.

[0066] Finally, the target CPU core's power idle power-saving state is disabled. The program opens the kernel file node / dev / cpu_dma_latency and writes the minimum latency threshold to it. Through PM QoS power quality service, it declares to the kernel that this task has extremely high deterministic requirements for transmission latency. After receiving the instruction, the kernel continues to maintain the exclusive CPU core running at full speed, avoiding the nanosecond to microsecond level random wake-up latency generated when the CPU wakes up from a low-power sleep state, and eliminating the latency jitter variable caused by the power management mechanism.

[0067] After all configurations are completed, the user's real-time task continuously executes a busy polling loop in a hardware and software environment free from preemption, page faults, and CPU hibernation interference. It stably reads data status information in shared memory according to the preset cycle, ensuring that the execution time of the polling judgment process is highly predictable.

[0068] This embodiment eliminates multiple sources of latency jitter across the entire chain, from operating system scheduling and memory management to CPU hardware power consumption control, effectively reducing end-to-end transmission latency jitter and ensuring hard real-time data reading capabilities.

[0069] In one optional implementation, the FPGA PCIe fiber optic card is electrically connected to the PCIe slot of the Linux host via a PCIe gold finger connector, thereby enabling PCIe bus data interaction between the FPGA PCIe fiber optic card and the Linux host.

[0070] Secondly, embodiments of the present invention provide a low-latency data transmission device, see [link to previous document]. Figure 4 This is a schematic diagram of an embodiment of a low-latency data transmission device provided by the present invention.

[0071] like Figure 4 As shown, the device includes: The fiber optic receiving module 21 is used to receive data to be transmitted from an external device through the fiber optic transceiver interface of the PCIe fiber optic card, parse the data to be transmitted and reorder it, and write the reordered data into the buffer area. DMA engine module 22 is used to extract the data to be transferred from the buffer using the built-in DMA engine and record the data status information; The status polling and judgment module 23 is used to synchronously write the data to be transmitted and the data status information into the shared memory, so that the user real-time task of the Linux system reads the data status information in the shared memory at a preset polling period and judges whether the data has been successfully delivered based on the data status information. The data reading module 24 is used to read the data to be transmitted from the shared memory if the arrival is determined to be successful; wherein, the shared memory is a physical contiguous memory pre-allocated by the Linux host and accessible in user space.

[0072] In one optional implementation, the PCIe fiber optic card has a built-in SRIO IP core, which is divided into three protocol processing units: physical layer, transport layer, and logical layer. Therefore, parsing and reordering the data to be transmitted includes: Based on the physical layer, transport layer and logic layer of the SRIO IP core, the protocol parsing of the data to be transmitted is completed layer by layer; Based on the sequence number and timestamp carried in the parsed data packet, the data to be transmitted is reordered.

[0073] In one optional implementation, the shared memory is mapped to the virtual address space of the process to which the user's real-time task belongs through a memory mapping mechanism, so that the user's real-time task can directly read and write the shared memory based on the mapped virtual address pointer, thereby achieving zero-copy data access.

[0074] In one optional implementation, the data status information includes at least a data arrival flag, a memory write pointer, a buffer rollback count, a data packet length, a data packet sequence number, and a timestamp.

[0075] In one optional implementation, the polling logic for the user's real-time task is as follows: Read the memory write pointer stored in the shared memory and compare the memory write pointer with the locally maintained consumption offset; If the memory write pointer moves forward relative to the consumption offset, it is determined that there is newly arrived data to be transmitted in the shared memory that has not yet been read.

[0076] In an optional implementation, the device is further used for a hard real-time environment configuration step before the user's real-time task runs, including: Set the user's real-time task to the SCHED_FIFO real-time scheduling policy and set the system's highest real-time priority; The user's real-time task is bound to a dedicated CPU core that is isolated by the kernel, and the CPU idle sleep power-saving state of that core is disabled.

[0077] In one optional implementation, the FPGA PCIe fiber optic card is electrically connected to the PCIe slot of the Linux host via a PCIe gold finger connector, thereby enabling PCIe bus data interaction between the FPGA PCIe fiber optic card and the Linux host.

[0078] It should be noted that the low-latency data transmission device provided in this embodiment of the invention is used to execute all the process steps of the low-latency data transmission method in the above embodiment. The working principle and beneficial effects of the two are one-to-one, so they will not be described again.

[0079] Thirdly, embodiments of the present invention provide an electronic device, see [link to previous document]. Figure 5 The diagram shown is a structural schematic of an electronic device provided in an embodiment of the present invention.

[0080] like Figure 5 As shown, the device includes: Memory 31 is used to store computer programs; Processor 32 is used to execute the computer program; When the processor 32 executes the computer program, it implements the low-latency data transmission method as described in any of the above embodiments.

[0081] For example, the computer program may be divided into one or more modules / units, which are stored in the memory 31 and executed by the processor 32 to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the electronic device.

[0082] The processor 32 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0083] The memory 31 can be used to store the computer programs and / or modules. The processor 32 implements various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory 31 and calling the data stored in the memory 31. The memory 31 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory 31 may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital card (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0084] It should be noted that the aforementioned electronic devices include, but are not limited to, processors and memory, as will be understood by those skilled in the art. Figure 5 The structural diagram is merely an example of the electronic device described above and does not constitute a limitation on the electronic device. It may include more components than shown in the diagram, or combine certain components, or use different components.

[0085] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed, implements the low-latency data transmission method described in any of the above embodiments.

[0086] It should be understood that all or part of the processes in the above-described low-latency data transmission method can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the above-described low-latency data transmission method. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0087] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. It should be noted that, for those skilled in the art, several equivalent obvious modifications and / or equivalent substitutions can be made without departing from the technical principles of the present invention, and these obvious modifications and / or equivalent substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A low-latency data transmission method, applied to a scenario of collaborative interaction between an FPGA PCIe fiber optic card and a Linux system, characterized in that, include: The PCIe fiber optic card receives data to be transmitted from external devices via its fiber optic transceiver interface, parses the data to be transmitted and reorders it, and writes the reordered data into the buffer. The built-in DMA engine is used to extract the data to be transferred from the buffer and record the data status information. The data to be transmitted and the data status information are synchronously written into the shared memory so that the user real-time task of the Linux system reads the data status information in the shared memory at a preset polling period and determines whether the data has been successfully delivered based on the data status information. If the arrival is determined to be successful, the data to be transmitted is read from the shared memory; wherein, the shared memory is a pre-allocated, user-accessible physical contiguous memory on the Linux host.

2. The low-latency data transmission method as described in claim 1, characterized in that, The PCIe fiber optic card has a built-in SRIO IP core. This SRIO IP core is divided into three protocol processing units: physical layer, transport layer, and logical layer. Therefore, parsing and reordering the data to be transmitted includes: Based on the physical layer, transport layer and logic layer of the SRIO IP core, the protocol parsing of the data to be transmitted is completed layer by layer; Based on the sequence number and timestamp carried in the parsed data packet, the data to be transmitted is reordered.

3. The low-latency data transmission method as described in claim 1, characterized in that, The shared memory is mapped to the virtual address space of the process to which the user's real-time task belongs through a memory mapping mechanism, so that the user's real-time task can directly read and write the shared memory based on the mapped virtual address pointer, thereby achieving zero-copy data access.

4. The low-latency data transmission method as described in claim 1, characterized in that, The data status information includes at least the data arrival flag, memory write pointer, buffer rollback count, data packet length, data packet sequence number, and timestamp.

5. The low-latency data transmission method as described in claim 4, characterized in that, The polling logic for the user's real-time tasks is as follows: Read the memory write pointer stored in the shared memory and compare the memory write pointer with the locally maintained consumption offset; If the memory write pointer moves forward relative to the consumption offset, it is determined that there is newly arrived data to be transmitted in the shared memory that has not yet been read.

6. The low-latency data transmission method as described in claim 1, characterized in that, The method also includes a hard real-time environment configuration step before the user's real-time task runs, including: Set the user's real-time task to the SCHED_FIFO real-time scheduling policy and set the system's highest real-time priority; The user's real-time task is bound to a dedicated CPU core that is isolated by the kernel, and the CPU idle sleep power-saving state of that core is disabled.

7. The low-latency data transmission method as described in claim 1, characterized in that, The FPGA PCIe fiber optic card is electrically connected to the PCIe slot of the Linux host through a PCIe gold finger connector, enabling PCIe bus data interaction between the FPGA PCIe fiber optic card and the Linux host.

8. A low-latency data transmission device, characterized in that, include: The fiber optic receiving module is used to receive data to be transmitted from external devices through the fiber optic transceiver interface of the PCIe fiber optic card, parse the data to be transmitted and reorder it, and write the reordered data into the buffer area. The DMA engine module is used to extract the data to be transferred from the buffer using the built-in DMA engine and record the data status information. The status polling and judgment module is used to synchronously write the data to be transmitted and the data status information into the shared memory, so that the user real-time task of the Linux system reads the data status information in the shared memory at a preset polling period and judges whether the data has been successfully delivered based on the data status information. The data reading module is used to read the data to be transmitted from the shared memory if the arrival is determined to be successful; wherein, the shared memory is a physical contiguous memory pre-allocated by the Linux host and accessible in user space.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program; The processor executes the computer program to implement the low-latency data transmission method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the low-latency data transmission method as described in any one of claims 1 to 7.

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