Method, interface circuit, chip, electronic device for data transmission

Abstract

The present disclosure relates to a method, an interface circuit, a chip, and an electronic device for data transmission. The method is performed by a first interface circuit. The method comprises sending a first request to a second interface circuit. The method further comprises receiving a first acknowledgement from the second interface circuit for the first request. The method further comprises determining a transmission interval according to a time difference between a time of sending the first request and a time of receiving the first acknowledgement. The method further comprises sending a plurality of sub-frames to the second interface circuit in the determined transmission interval. The method divides a transmission time of a data frame into a latency measurement phase and a data transmission phase. A handshake operation is performed in the latency measurement phase, and no handshake operation is performed in the data transmission phase. The method implements both a handshake manner and a no-handshake manner to ensure the accuracy of the transmission interval and not to lose the data transmission performance.

Description

Technical Field

[0001] This disclosure generally relates to the field of circuit technology, and more specifically to methods, interface circuits, chips, and electronic devices for data transmission. Background Technology

[0002] As chip size increases, the number of circuit units on the chip also gradually increases. Correspondingly, the number of on-chip units that need to interact is increasing, and these units are becoming more and more dispersed. In some cases, such as in sequential logic circuits, circuit units require clock signals to operate.

[0003] Different circuit units may require different clock signals, and therefore their respective clock domains may differ. Long-distance transmission across clock domains may be necessary. In the case of long-distance transmission across clock domains, timing convergence at the back end of the transmission chain is more difficult, and transmission errors may occur. Summary of the Invention

[0004] This disclosure provides a method for data transmission, a first interface circuit, a second interface circuit, a chip, and an electronic device.

[0005] According to a first aspect of this disclosure, a method for data transmission is provided. The method is performed by a first interface circuit. The method includes sending a first request to a second interface circuit. The method further includes receiving a first acknowledgment from the second interface circuit in response to the first request. The method further includes determining a transmission interval based on a time difference between the time the first request was sent and the time the first acknowledgment was received. The method further includes sending a plurality of subframes to the second interface circuit according to the determined transmission interval.

[0006] This method employs an asynchronous, clockless transmission scheme, dividing the data frame transmission period into two phases. In the first phase (also referred to as the "delay measurement phase" in this context), a handshake is used to determine the transmission delay (the aforementioned time difference) between the sender (first interface circuit) and the receiver (second interface circuit), and the transmission interval is determined based on this delay. This ensures the accuracy of the transmission interval. In the second phase following the first phase (also referred to as the "data transmission phase" in this context), individual data packets (subframes) are sent according to the determined transmission interval. This method does not perform a handshake during the data transmission phase, thus not affecting the data packet transmission speed. This method achieves both accurate transmission intervals and no data transmission performance by using a hybrid handshake and no-handshake approach.

[0007] In some implementations of the first aspect, adjacent subframes within the plurality of subframes are encoded using an M-bit flipped encoding scheme. M is greater than or equal to one and less than the total number of bits encoding a single subframe. The first request and the plurality of subframes are transmitted via multiple data lines. The first request is represented by flipping the signals on all of the plurality of data lines. This implementation uses an M-bit flipped encoding scheme to define the encoded values ​​of adjacent data packets. Under this encoding scheme, the first request can be characterized by a full bit flip. Since the data packets and the first request are encoded differently, no additional information is needed to distinguish the first request from the data packets, thus achieving a simple representation of the first request. On the other hand, in some scenarios, the transmission delays on the plurality of data lines may differ. By flipping the signals on all data lines, the longest transmission delay on the plurality of data lines can be measured based on the signal that was flipped last. This allows the transmission interval to be determined based on the longest transmission delay, thereby ensuring the accuracy of the transmission interval.

[0008] In some implementations of the first aspect, the method further includes sending a second request to the second interface circuit if a first acknowledgment is received. This allows the second interface circuit to determine a transmission interval based on the time difference between sending the first acknowledgment and receiving the second request. With the transmission interval determined by the second interface circuit, the second interface circuit can receive data packets according to the transmission interval and determine whether the reception of data packets has timed out.

[0009] In some implementations of the first aspect, the method further includes sending a frame end marker to the second interface circuit. The frame end marker indicates the end of the data frame. In some further implementations, adjacent subframes in the plurality of subframes are encoded using an M-bit flipped encoding scheme. M is greater than or equal to one and less than the total number of bits encoding a single subframe. The frame end marker is transmitted via a plurality of data lines. The frame end marker is represented by flipping the signals on all of the plurality of data lines. This implementation uses an M-bit flipped encoding scheme to define the encoded values ​​of adjacent data packets. Under this encoding scheme, the frame end marker can be characterized by a full bit flip. Since the data packets and the frame end marker are encoded differently, no additional information is needed to distinguish the frame end marker from the data packets, thus achieving a simple representation of the frame end marker. This implementation uses the frame end marker to indicate the end of the data frame, which helps the receiver to understand the transmission status of the data frame in order to process downstream tasks (e.g., forwarding the data frame to other interface circuits after receiving a complete data frame).

[0010] In some alternative implementations of the first aspect, the method further includes determining the number of transmitted subframes. The method also includes determining the end of the data frame if the number of transmitted subframes reaches the data length of the data frame and an acknowledgment is received from the second interface circuit for the tail subframe (last subframe) among the transmitted subframes. The acknowledgment for the tail subframe indicates that the tail subframe has been received. In some further implementations, counters may be provided in both the first and second interface circuits. The counter in the first interface circuit is used to count the number of transmitted subframes. This allows the first interface circuit to determine the end of the data frame in a simple manner, preparing for the transmission of the next data frame. The counter in the second interface circuit is used to count the number of received subframes. This allows the second interface circuit to determine the end of the data frame in a simple manner, facilitating its understanding of the data frame transmission status for processing downstream tasks (e.g., forwarding the data frame to other interface circuits after receiving a complete data frame).

[0011] In some implementations of the first aspect, the transmission interval is determined separately during the transmission of different data frames. For example, the transmission interval can be redefined for the transmission of each data frame. This facilitates flexible control of the transmission rate and better adapts to ever-changing environments (such as delay changes caused by temperature variations) and scenarios (such as clock frequency conversion).

[0012] In some implementations of the first aspect, the first acknowledgment is received via at least one feedback line. The first acknowledgment indicates whether the signal received by the second interface circuit is in a normal or abnormal reception state. Since the first acknowledgment indicates the state of the signal received by the second interface circuit, the first interface circuit can take corresponding measures when the signal received by the second interface circuit is in an abnormal reception state, such as stopping the transmission of the current data frame and directly transmitting the next data frame, or retransmitting the current data frame, etc.

[0013] In some implementations of the first aspect, the at least one feedback line includes a first feedback line and a second feedback line. When the signal on the first feedback line flips, a first confirmation indicates a normal reception state of the signal received by the second interface circuit. When the signal on the second feedback line flips, the first confirmation indicates an abnormal reception state of the signal received by the second interface circuit. In this implementation, the transmission delay is measured when the signal received by the second interface circuit is in a normal reception state. When the signal received by the second interface circuit is in an abnormal reception state, it is not necessary to measure the transmission delay. Since the transmission delays on different feedback lines may differ, this implementation restricts the information of the correct feedback signal to a single feedback line, maintaining the consistency of the measured delay. This is beneficial for accurately determining the transmission interval.

[0014] In some implementations of the first aspect, the at least one feedback line includes a first feedback line, a second feedback line, and a third feedback line. When the signal on the first feedback line flips, a first confirmation indicates the normal reception state of the signal received by the second interface circuit. When the signal on the second feedback line flips, the first confirmation indicates first information indicating an abnormal reception state of the signal received by the second interface circuit. When the signal on the third feedback line flips, the first confirmation indicates second information indicating an abnormal reception state of the signal received by the second interface circuit. In this implementation, the transmission delay is measured when the signal received by the second interface circuit is in a normal reception state. When the signal received by the second interface circuit is in an abnormal reception state, it is not necessary to measure the transmission delay. Since the transmission delays on different feedback lines may differ, this implementation restricts the information of the correct signal feedback to a single feedback line, maintaining the consistency of the measured delay. This is beneficial for accurately determining the transmission interval. By setting multiple feedback lines to feedback error information, richer error information can be indicated by the combination of signals on multiple feedback lines, thereby helping the first interface circuit to grasp more transmission states.

[0015] In some implementations of the first aspect, the at least one feedback line is multiplexed with multiple data lines. The at least one feedback line can be connected to the bidirectional input / output (I / O) interfaces of the first and second interface circuits. This reduces the number of I / O lines in the first and second interface circuits.

[0016] In some implementations of the first aspect, the method further includes, if the first acknowledgment indicates a normal or abnormal reception state of the signal received by the second interface circuit, determining, at least in part, the number of errors that occurred during the transmission of the first request in the first data frame and the plurality of subframes, based on the first acknowledgment. The method also includes retransmitting the first data frame if the number of errors does not reach a threshold. It should be noted that, in this context, "first data frame" refers to any single data frame. Through the above implementation, the first interface circuit can promptly detect transmission errors in the first data frame and determine the timing for retransmitting the first data frame based on the number of errors that occurred.

[0017] In some implementations of the first aspect, the method further includes determining the number of receivers for data transmission. The method also includes sending multiple subframes to each receiver according to a configured transmission interval if the number of receivers is greater than one. This implementation considers a one-to-many broadcast scenario. In such scenarios, the transmission delays between the sender and each receiver may differ, making it unsuitable to determine the transmission delay separately for each receiver. This implementation can switch the data transmission method to an asynchronous, handshake-free method and set the configured transmission interval to meet the acceptable transmission delays for each receiver. This ensures that the transmission interval is consistent for each receiver, simplifying the sender's operation and guaranteeing the accuracy of transmission between the sender and each receiver.

[0018] According to a second aspect of this disclosure, a method for data transmission is provided. The method is performed by a second interface circuit. The method includes receiving a first request from a first interface circuit. The method further includes, if the first request is received, sending a first acknowledgment to the first interface circuit in response to the first request. The method further includes receiving a second request from the first interface circuit. The method further includes determining a transmission interval based on the time difference between sending the first acknowledgment and receiving the second request. The method further includes receiving a plurality of subframes from the first interface circuit according to the determined transmission interval.

[0019] This method employs an asynchronous, clockless transmission scheme, dividing the data frame transmission period into two phases. In the first phase (also referred to as the "delay measurement phase" in this context), a handshake is used to determine the transmission delay (the aforementioned time difference) between the sender (first interface circuit) and the receiver (second interface circuit), and the transmission interval is determined based on this delay. This ensures the accuracy of the transmission interval. In the second phase following the first phase (also referred to as the "data transmission phase" in this context), individual data packets (subframes) are received according to the determined transmission interval. This method does not perform a handshake during the data transmission phase, thus not affecting the data packet transmission speed. This method achieves both accurate transmission intervals and no data transmission performance by using a hybrid handshake and no-handshake approach. Furthermore, since the second interface circuit determines the transmission interval, it can determine whether the reception of data packets has timed out.

[0020] In some implementations of the second aspect, adjacent subframes within the plurality of subframes are encoded using an M-bit flipped encoding scheme. M is greater than or equal to one and less than the total number of bits encoding a single subframe. The first request, the second request, and the plurality of subframes are received via multiple data lines. The first request and the second request are represented by flipping the signals on all of the plurality of data lines. This implementation uses an M-bit flipped encoding scheme to define the encoded values ​​of adjacent data packets. Under this encoding scheme, the first request and the second request can be characterized by a full bit flip. Since the data packets are encoded differently from the first and second requests, no additional information is needed to distinguish the first and second requests from the data packets, thus achieving a simple representation of the first and second requests. On the other hand, in some scenarios, the transmission delays on the plurality of data lines may differ. By flipping the signals on all data lines, the longest transmission delay on the plurality of data lines can be measured based on the signal that was flipped last. This allows the transmission interval to be determined based on the longest transmission delay, thereby ensuring the accuracy of the transmission interval.

[0021] In some implementations of the second aspect, the method further includes determining the end of the data frame if a frame end marker is received from the first interface circuit. In some further implementations, adjacent subframes among the plurality of subframes are encoded using an M-bit flip-coded scheme. M is greater than or equal to one and less than the total number of bits encoding a single subframe. The frame end marker is received via the plurality of data lines. The frame end marker is represented by flipping the signals on all of the plurality of data lines. This implementation uses an M-bit flip-coded scheme to define the encoded values ​​of adjacent data packets. Under this encoding scheme, the frame end marker can be characterized by a full bit flip. Since the data packets and the frame end marker are encoded differently, no additional information is needed to distinguish the frame end marker from the data packets, thus achieving a simple representation of the frame end marker. This implementation uses the frame end marker to indicate the end of the data frame, which helps the second interface circuit (the receiver) to grasp the transmission status of the data frame in order to process downstream tasks (e.g., forwarding the data frame to other interface circuits after receiving a complete data frame).

[0022] In some alternative implementations of the second aspect, the method further includes determining the number of received subframes. The method also includes determining the end of a data frame if the number of received subframes reaches the data length of the data frame. In some further implementations, counters may be provided in both the first and second interface circuits. The counter in the first interface circuit is used to count the number of transmitted subframes. This allows the first interface circuit to easily determine the end of a data frame in preparation for sending the next data frame. The counter in the second interface circuit is used to count the number of received subframes. This allows the second interface circuit to easily determine the end of a data frame, facilitating its understanding of the data frame's transmission status for handling downstream tasks (e.g., forwarding the data frame to other interface circuits after receiving a complete data frame).

[0023] In some implementations of the second aspect, the transmission interval is determined separately during the transmission of different data frames. For example, the transmission interval can be redefined for the transmission of each data frame. This facilitates flexible control of the transmission rate and better adapts to ever-changing environments (such as delay changes caused by temperature variations) and scenarios (such as clock frequency conversion).

[0024] In some implementations of the second aspect, the first acknowledgment is sent via at least one feedback line. The first acknowledgment indicates whether the signal received by the second interface circuit is in a normal or abnormal reception state. Since the first acknowledgment indicates the state of the signal received by the second interface circuit, the first interface circuit can take corresponding measures when the signal received by the second interface circuit is in an abnormal reception state, such as stopping the transmission of the current data frame and directly transmitting the next data frame, or retransmitting the current data frame, etc.

[0025] In some implementations of the second aspect, the at least one feedback line includes a first feedback line and a second feedback line. When the signal on the first feedback line flips, a first confirmation indicates a normal reception state of the signal received by the second interface circuit. When the signal on the second feedback line flips, the first confirmation indicates an abnormal reception state of the signal received by the second interface circuit. In this implementation, the transmission delay is measured when the signal received by the second interface circuit is in a normal reception state. When the signal received by the second interface circuit is in an abnormal reception state, it is not necessary to measure the transmission delay. Since the transmission delays on different feedback lines may differ, this implementation restricts the information of the correct feedback signal to a single feedback line, maintaining the consistency of the measured delay. This is beneficial for accurately determining the transmission interval.

[0026] In some implementations of the second aspect, the at least one feedback line includes a first feedback line, a second feedback line, and a third feedback line. When the signal on the first feedback line flips, a first confirmation indicates the normal reception state of the signal received by the second interface circuit. When the signal on the second feedback line flips, the first confirmation indicates first information indicating an abnormal reception state of the signal received by the second interface circuit. When the signal on the third feedback line flips, the first confirmation indicates second information indicating an abnormal reception state of the signal received by the second interface circuit. In this implementation, the transmission delay is measured when the signal received by the second interface circuit is in a normal reception state. When the signal received by the second interface circuit is in an abnormal reception state, it is not necessary to measure the transmission delay. Since the transmission delays on different feedback lines may differ, this implementation restricts the information of the correct feedback signal to a single feedback line, maintaining the consistency of the measured delay. This is beneficial for accurately determining the transmission interval. By setting multiple feedback lines to feedback error information, richer error information can be indicated by the combination of signals on multiple feedback lines, thereby helping the first interface circuit to grasp more transmission states.

[0027] In some implementations of the second aspect, the at least one feedback line is multiplexed with multiple data lines. The at least one feedback line can be connected to the bidirectional input / output (I / O) interfaces of the first and second interface circuits. This reduces the number of I / O lines in the first and second interface circuits.

[0028] According to a third aspect of this disclosure, a first interface circuit is provided. The first interface circuit includes a transmitting circuit, a receiving circuit, and an interval determining circuit. The transmitting circuit is configured to transmit a first request to the second interface circuit. The receiving circuit is configured to receive a first acknowledgment from the second interface circuit in response to the first request. The interval determining circuit is configured to determine a transmission interval based on the time difference between transmitting the first request and receiving the first acknowledgment. The transmitting circuit is further configured to transmit a plurality of subframes to the second interface circuit according to the determined transmission interval.

[0029] According to a fourth aspect of this disclosure, a second interface circuit is provided. The second interface circuit includes a receiving circuit, a transmitting circuit, and an interval determining circuit. The receiving circuit is configured to receive a first request from a first interface circuit. The transmitting circuit is configured to send a first acknowledgment to the first interface circuit in response to the first request if the first request is received. The receiving circuit is also configured to receive a second request from the first interface circuit. The interval determining circuit is configured to determine a transmission interval based on the time difference between sending the first acknowledgment and receiving the second request. The transmitting circuit is further configured to receive a plurality of subframes from the first interface circuit according to the determined transmission interval.

[0030] According to a fifth aspect of this disclosure, a chip is provided. The chip includes at least one of a first interface circuit according to a third aspect of this disclosure or a second interface circuit according to a fourth aspect of this disclosure; and a package structure. The package structure surrounds at least one of the first interface circuit or the second interface circuit.

[0031] According to a sixth aspect of this disclosure, an electronic device is provided. The electronic device includes at least one of a first interface circuit according to a third aspect of this disclosure or a second interface circuit according to a fourth aspect of this disclosure; and a power supply circuit. The power supply circuit is configured to supply power to the at least one of the first interface circuit or the second interface circuit.

[0032] It is understood that the first interface circuit of the third aspect, the second interface circuit of the fourth aspect, the chip of the fifth aspect, and the electronic device of the sixth aspect provided above have the same beneficial effects as the methods for data transmission of the first and second aspects. Therefore, the explanations or descriptions of the first and second aspects also apply to the third, fourth, fifth, and sixth aspects. Attached Figure Description

[0033] The above and other objects, features and advantages of this disclosure will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0034] Figure 1A A schematic diagram of an example environment in which interface circuitry and / or methods for data transmission, embodiments of the present disclosure may be implemented, is shown.

[0035] Figure 1B A schematic diagram of another example environment in which interface circuitry and / or methods for data transmission, embodiments of the present disclosure may be implemented, is shown.

[0036] Figure 1C A schematic diagram of yet another example environment in which interface circuitry and / or methods for data transmission, embodiments of the present disclosure may be implemented, is shown.

[0037] Figure 2A An exemplary flowchart illustrating communication between a first interface circuit and a second interface circuit according to an embodiment of this disclosure is shown.

[0038] Figure 2B Another exemplary flowchart illustrating communication between a first interface circuit and a second interface circuit according to an embodiment of the present disclosure is shown.

[0039] Figure 2CAnother exemplary flowchart illustrating communication between a first interface circuit and a second interface circuit according to an embodiment of the present disclosure is shown.

[0040] Figure 3 A timing diagram of communication between a first interface circuit and a second interface circuit according to an embodiment of the present disclosure is shown.

[0041] Figure 4 An exemplary flowchart of a method for data transmission performed by a first interface circuit according to an embodiment of the present disclosure is shown.

[0042] Figure 5 An exemplary flowchart of a method for data transmission performed by a second interface circuit according to an embodiment of the present disclosure is shown.

[0043] Figure 6A An exemplary schematic diagram illustrating the encoding method of feedback information according to embodiments of the present disclosure is shown.

[0044] Figure 6B An exemplary schematic diagram illustrating another encoding scheme for feedback information according to embodiments of the present disclosure is shown.

[0045] Figure 7 Another timing diagram of communication between a first interface circuit and a second interface circuit according to an embodiment of the present disclosure is shown.

[0046] Figure 8 Another exemplary flowchart of a method for data transmission performed by a first interface circuit according to an embodiment of the present disclosure is shown.

[0047] Figure 9 An exemplary block diagram of a first interface circuit and a second interface circuit according to an embodiment of the present disclosure is shown.

[0048] Figure 10 An exemplary schematic diagram of the connection method between the first interface circuit and the second interface circuit according to an embodiment of the present disclosure is shown.

[0049] Figure 11 An exemplary schematic diagram of the connection method between a first interface circuit and a plurality of second interface circuits according to an embodiment of the present disclosure is shown.

[0050] Figure 12 An exemplary schematic diagram of multiple circuits cascaded according to embodiments of the present disclosure is shown.

[0051] Figure 13 Another exemplary schematic diagram showing multiple circuits cascaded according to embodiments of the present disclosure is shown.

[0052] In the various accompanying figures, the same or corresponding reference numerals indicate the same or corresponding parts. The elements in the accompanying figures are schematic and not drawn to scale. Detailed Implementation

[0053] The technical solutions of this disclosure will now be described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments.

[0054] The technical solutions of the embodiments of this disclosure will now be described with reference to the accompanying drawings. In the description of the embodiments of this disclosure, unless otherwise stated, " / " signifies "and / or," for example, A / B can mean A or B, or A and B. "And / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, in the description of the embodiments of this disclosure, "plural" or "multiple" refers to two or more than two.

[0055] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0056] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used in the specification and appended claims of this disclosure, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this disclosure, “at least one,” “one or more” means one, two, or more than two.

[0057] References to "one embodiment" or "some embodiments" as used in this specification mean that one or more embodiments of this disclosure include a particular feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "one embodiment," "some embodiments," "another embodiment," "other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0058] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement of “connecting” or “coupling” two or more parts together shall mean that these parts are directly joined together or joined through at least one intermediate component.

[0059] For ease of description, spatial relative terms such as “above,” “below,” “left,” “right,” “top,” and “bottom” are used here to describe the spatial positional relationship of a device or element to other devices or elements, as shown in the figures. For example, the terms “on,” “above,” “above,” “on the upper surface of,” “above,” “positioned on,” or “positioned on top of” mean that a first element, such as a first structure, exists on a second element, such as a second structure, where an intermediate element may or may not be present between the first and second elements. The term “contact” means connecting a first element, such as a first structure, and a second element, such as a second structure, where there may or may not be other elements at the interface between the two elements. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation in addition to the orientation of the device as described in the figures. For example, if the device in the figures is inverted, a device described as “above” or “on top of” other devices or structures will subsequently be positioned “below” or “under” other devices or structures. Thus, the exemplary term “above” can include both orientations of “above” and “below”. The device can also be positioned in other different ways, rotated 90 degrees, or in other orientations, and the spatial relative descriptions used here are explained accordingly.

[0060] The numbers or values ​​used in this specification are illustrative and are intended only to facilitate understanding of the techniques of the embodiments of this disclosure, and are by no means intended to limit the scope of this disclosure.

[0061] The apparatus and / or methods provided in this disclosure can be applied to mobile phones, tablets, wearable devices, in-vehicle devices, augmented reality (AR) / virtual reality (VR) devices, laptops, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), or other electronic devices. This disclosure does not limit the specific type of electronic device.

[0062] The following section will first provide a detailed description of some terms that may be involved in the embodiments of this disclosure.

[0063] 1. Asynchronous circuit

[0064] Asynchronous circuits, also known as clockless or self-timed circuits, are distinguished from synchronous circuits. These circuits lack a global clock; each unit is driven by a local clock, and synchronization between units is achieved through a handshake process.

[0065] 2.Handshake

[0066] In asynchronous circuits, since there is no clock signal, a handshake is required to complete the effective transmission of information. During the handshake process, the sender sends a request (req) signal, and the receiver, upon receiving the request signal, sends an acknowledgment (ack) signal. After receiving the acknowledgment signal, the sender proceeds with the next transmission. This is called completing one valid handshake.

[0067] 3. Dual Rail (DR) Encoding: A one-hot, delay-insensitive dual rail encoding scheme. In this scheme, each data point is controlled via two lines.

[0068] 4. One-of-four (1-of-4) encoding: Another one-hot delay-insensitive encoding scheme. This scheme uses 4 data lines to encode 2 bits of raw data, and only one valid "1" appears in each transmitted data.

[0069] 5. Level Encoded Transition Signaling (LETS) encoding: This is a two-phase multitrack encoding scheme. It uses four data lines to encode 2 bits of raw data. Its characteristic is that adjacent codewords have different phases, and each transmitted data bit is only flipped once.

[0070] 6. Level-encoded dual rail (LEDR) encoding: This is a special form of LETS encoding that uses two data lines to encode one bit of raw data. This encoding scheme samples level transitions on the data lines and stipulates that only one bit of the two-bit encoding is changed in each transmission.

[0071] 7. m-of-n (m-of-n) encoding: For k bits of valid data, m-of-n redundancy encoding can be used, where m represents the number of occurrences of 1 and n represents the number of data lines. When k=4, it represents 4 bits of valid data, and 2-of-7 and 3-of-6 encoding are generally used.

[0072] As mentioned above, in long-distance transmission across clock domains, timing convergence at the back end of the transmission chain is challenging, potentially leading to transmission errors. To address this, an asynchronous clockless transmission scheme has been proposed. This scheme employs asynchronous coding for transmission. It achieves data alignment without clock synchronization through redundant coding. Asynchronous clockless transmission schemes can include those using a handshake and those without. In the handshake method, a handshake is performed before each data packet transmission to ensure reliability. However, this method requires waiting for acknowledgment feedback, and frequent handshakes significantly reduce transmission speed. In the non-handshake method, the sender transmits data at fixed time intervals without waiting for acknowledgment feedback, resulting in faster transmission speeds compared to the handshake method. However, the non-handshake method cannot adapt to constantly changing environments (such as latency variations caused by temperature changes) and scenarios (such as clock frequency variations).

[0073] Therefore, this disclosure proposes a method for data transmission performed by a first interface circuit. The method includes sending a first request to a second interface circuit. The method also includes receiving a first acknowledgment from the second interface circuit in response to the first request. The method further includes determining a transmission interval based on the time difference between sending the first request and receiving the first acknowledgment. The method also includes sending a plurality of subframes to the second interface circuit according to the determined transmission interval.

[0074] This method employs an asynchronous, clockless transmission scheme, dividing the data frame transmission period into two phases. In the first phase (also referred to as the "delay measurement phase" in this context), a handshake is used to determine the transmission delay (the aforementioned time difference) between the sender (first interface circuit) and the receiver (second interface circuit), and the transmission interval is determined based on this delay. This ensures the accuracy of the transmission interval. In the second phase following the first phase (also referred to as the "data transmission phase" in this context), individual data packets (subframes) are sent according to the determined transmission interval. This method does not perform a handshake during the data transmission phase, thus not affecting the data packet transmission speed. This method achieves both accurate transmission intervals and no data transmission performance by using a hybrid handshake and no-handshake approach.

[0075] This disclosure also proposes a method for data transmission performed by a second interface circuit. The method includes receiving a first request from a first interface circuit. The method further includes, if the first request is received, sending a first acknowledgment to the first interface circuit in response to the first request. The method also includes receiving a second request from the first interface circuit. The method further includes determining a transmission interval based on the time difference between sending the first acknowledgment and receiving the second request. The method further includes receiving a plurality of subframes from the first interface circuit according to the determined transmission interval.

[0076] This method employs an asynchronous, clockless transmission scheme, dividing the data frame transmission period into two phases. In the first phase (also referred to as the "delay measurement phase" in this context), a handshake is used to determine the transmission delay (the aforementioned time difference) between the sender (first interface circuit) and the receiver (second interface circuit), and the transmission interval is determined based on this delay. This ensures the accuracy of the transmission interval. In the second phase following the first phase (also referred to as the "data transmission phase" in this context), individual data packets (subframes) are received according to the determined transmission interval. This method does not perform a handshake during the data transmission phase, thus not affecting the data packet transmission speed. This method achieves both accurate transmission intervals and no data transmission performance by using a hybrid handshake and no-handshake approach. Furthermore, since the second interface circuit determines the transmission interval, it can determine whether the reception of data packets has timed out.

[0077] Figure 1A A schematic diagram of an example environment in which interface circuitry and / or methods for data transmission, embodiments of the present disclosure may be implemented, is shown. Figure 1A The chip 100 may include multiple units. These units may correspond to multiple clock domains. Figure 1AThe diagram shows the first interface circuit 110-1 in clock domain 1, the second interface circuit 110-2 in clock domain 2, the third interface circuit 110-3 in clock domain 3, the fourth interface circuit 110-4 in clock domain 4, the fifth interface circuit 110-5 in clock domain 5, and the Nth interface circuit 110-N in clock domain N. Figure 1A The example may also include other interface circuits in other clock domains (not shown). The first interface circuit 110-1 can communicate across clock domains with the second interface circuit 110-2, the third interface circuit 110-3, the fourth interface circuit 110-4, the fifth interface circuit 110-5, and the Nth interface circuit 110-N, respectively. Although in Figure 1A Only one line is shown, but it should be understood that the first interface circuit 110-1 and the second interface circuit 110-2 can be directly connected by multiple lines. The communication path between the first interface circuit 110-1 and the second interface circuit 110-2 may be relatively long, and therefore transmission errors may occur.

[0078] Figure 1B A schematic diagram of another example environment in which interface circuitry and / or methods for data transmission, embodiments of this disclosure, may be implemented, is shown. Figure 1B In the example, the first interface circuit 110-1 and the second interface circuit 110-2 are located in different chips. The first interface circuit 110-1 is located in clock domain 1 of the first chip 100A. The second interface circuit 110-2 is located in clock domain 2 of the second chip 100B. The first chip 100A and the second chip 100B can be located on the same circuit board. Although in Figure 1B Only one line is shown, but it should be understood that the first interface circuit 110-1 and the second interface circuit 110-2 can be directly connected by multiple lines. The communication path between the first interface circuit 110-1 and the second interface circuit 110-2 may be relatively long, and therefore transmission errors may occur.

[0079] Figure 1C A schematic diagram illustrates yet another example environment in which interface circuitry and / or methods for data transmission, embodiments of this disclosure, can be implemented. Figure 1C In the example, the first interface circuit 110-1 and the second interface circuit 110-2 can be directly connected via multiple lines. For example, the first interface circuit 110-1 can send data (e.g., a request in a handshake and a data packet) to the second interface circuit 110-2 via at least two data lines. The second interface circuit 110-2 can send feedback information (e.g., an acknowledgment in a handshake) to the first interface circuit 110-1 via at least one feedback line.

[0080] Figure 2AAn exemplary flowchart illustrating communication between a first interface circuit 110-1 and a second interface circuit 110-2 according to embodiments of the present disclosure is shown. In this context, the first interface circuit 110-1 may be alternatively referred to as the sender, and the second interface circuit 110-2 may be alternatively referred to as the receiver. The sender may send data to the receiver in the form of data frames. In some embodiments of the present disclosure, a single data frame may include a frame header for handshaking and subframes. Subframes may include supplementary information of the data frame and / or a data payload. In some embodiments of the present disclosure, a single data frame may also include a frame trailer. The following is in conjunction with… Figure 2A The example illustrates an exemplary transmission process for a single data frame.

[0081] At position 202, the first interface circuit 110-1 sends a first request 204 to the second interface circuit 110-2. The first request 204 can be considered the header of the current data frame. The second interface circuit 110-2 receives the first request 204 from the first interface circuit 110-1 at position 206. After receiving the first request 204, the second interface circuit 110-2 sends a first acknowledgment 210 for the first request 204 to the first interface circuit 110-1 at position 208. The first interface circuit 110-1 receives the first acknowledgment 210 for the first request 204 from the second interface circuit 110-2 at position 212. Thus, the first interface circuit 110-1 and the second interface circuit 110-2 complete a valid handshake. At position 214, the first interface circuit 110-1 determines the transmission interval based on the time difference between sending the first request 204 and receiving the first acknowledgment 210. In one example, the transmission interval is greater than or equal to half of the aforementioned time difference. The first interface circuit 110-1 transmits multiple subframes 232 to the second interface circuit 110-2 at a predetermined transmission interval at 230. The second interface circuit 110-2 receives the multiple subframes 232 from the first interface circuit 110-1 at 234.

[0082] Figure 2A The method employs an asynchronous, clockless transmission scheme and divides the transmission period of a single data frame into two phases. In the delay measurement phase (corresponding to...) Figure 2A In section 202-214), a handshake is used to determine the transmission delay (the aforementioned time difference) between the sender (first interface circuit 110-1) and the receiver (second interface circuit 110-2), and the transmission interval is determined based on the transmission delay. This ensures the accuracy of the transmission interval. During the data transmission phase (corresponding to...), Figure 2A(230-234 in the diagram) Each data packet (subframe) is sent according to the determined transmission interval. This method does not perform a handshake during the data transmission phase, thus not affecting the data packet transmission speed. This method achieves both accurate transmission intervals and no data transmission performance by combining handshake and no-handshake methods.

[0083] In some embodiments of this disclosure, adjacent subframes within the plurality of subframes are encoded using an M-bit flipped encoding scheme. In this context, M is greater than or equal to one and less than the total number of bits encoding a single subframe. The first request and the plurality of subframes are transmitted via a plurality of data lines. The first request is represented by flipping the signals on all of the plurality of data lines. This embodiment defines the encoded values ​​of adjacent data packets using an M-bit flipped encoding scheme. Under this encoding scheme, the first request can be characterized by a full bit flip. Since the data packets and the first request are encoded differently, no additional information is needed to distinguish the first request from the data packets, thus achieving a simple representation of the first request. On the other hand, in some scenarios, the transmission delays on the plurality of data lines may differ. By flipping the signals on all data lines, the longest transmission delay on the plurality of data lines can be measured based on the signal that was flipped last. This allows the transmission interval to be determined based on the longest transmission delay, thereby ensuring the accuracy of the transmission interval.

[0084] Figure 2B Another exemplary flowchart illustrating communication between a first interface circuit and a second interface circuit according to an embodiment of this disclosure is shown. Figure 2B In the example, the first interface circuit 110-1 and the second interface circuit 110-2 perform a handshake twice. The following section will combine... Figure 2B The example illustrates an exemplary transmission process for a single data frame.

[0085] At position 202, the first interface circuit 110-1 sends a first request 204 to the second interface circuit 110-2. The first request 204 can be considered the header of the current data frame. The second interface circuit 110-2 receives the first request 204 from the first interface circuit 110-1 at position 206. After receiving the first request 204, the second interface circuit 110-2 sends a first acknowledgment 210 for the first request 204 to the first interface circuit 110-1 at position 208. The first interface circuit 110-1 receives the first acknowledgment 210 for the first request 204 from the second interface circuit 110-2 at position 212. Thus, the first interface circuit 110-1 and the second interface circuit 110-2 complete their first valid handshake. At position 214, the first interface circuit 110-1 determines the transmission interval based on the time difference between sending the first request 204 and receiving the first acknowledgment 210. In one example, the transmission interval is greater than or equal to half of this time difference.

[0086] At point 216, the first interface circuit 110-1 sends a second request 218 to the second interface circuit 110-2. The second interface circuit 110-2 receives the second request 218 from the first interface circuit 110-1 at point 220. After receiving the second request 218, the second interface circuit 110-2 may send a second acknowledgment 224 for the second request 218 to the first interface circuit 110-1 at point 222. The first interface circuit 110-1 receives the second acknowledgment 224 for the second request 218 from the second interface circuit 110-2 at point 226. Thus, the first interface circuit 110-1 and the second interface circuit 110-2 complete the second valid handshake. In some embodiments of this disclosure, the second interface circuit 110-2 may not send the second acknowledgment 224, allowing the first interface circuit 110-1 to begin subsequent operations at a predetermined time after sending the second request 218.

[0087] At 228, the second interface circuit 110-2 determines a transmission interval based on the time difference between sending the first acknowledgment 210 and receiving the second request 218. In one example, the transmission interval is greater than or equal to half of the aforementioned time difference. At 230, the first interface circuit 110-1 sends multiple subframes 232 to the second interface circuit 110-2 according to the determined transmission interval. At 234, the second interface circuit 110-2 receives multiple subframes 232 from the first interface circuit 110-1 according to the determined transmission interval.

[0088] It should be noted that the operation at position 214 can be executed in parallel with the operation at position 216, or after the operation at position 216. Embodiments of this disclosure do not limit the execution order of the operations at positions 214 and 216. The operation at position 222 can be executed in parallel with the operation at position 228, or after the operation at position 228. Embodiments of this disclosure do not limit the execution order of the operations at positions 222 and 228.

[0089] Figure 2B The method in Figure 2A Based on the method, a two-way handshake is performed. The first interface circuit 110-1 determines the transmission interval at 214 based on the time difference between sending the first request 204 and receiving the first acknowledgment 210. The second interface circuit 110-2 determines the transmission interval at 228 based on the time difference between sending the first acknowledgment 210 and receiving the second request 218. Thus, the transmission intervals of the second interface circuit 110-2 and the first interface circuit 110-1 can be considered aligned, allowing the second interface circuit 110-2 to promptly determine whether its data packet reception has timed out.

[0090] In some embodiments of this disclosure, during the process of the first interface circuit 110-1 sending multiple subframes 232 to the second interface circuit 110-2, the first interface circuit 110-1 can determine the number of subframes 232 sent. If the number of subframes 232 sent reaches the data length of a data frame, the first interface circuit 110-1 can determine that the current data frame has ended. Similarly, during the process of the second interface circuit 110-2 receiving multiple subframes 232 from the first interface circuit 110-1, the second interface circuit 110-2 can determine the number of subframes 232 received. If the number of subframes 232 received reaches the data length of a data frame, the second interface circuit 110-2 can determine that the current data frame has ended.

[0091] In one example, counters can be configured in both the first interface circuit 110-1 and the second interface circuit 110-2. The counter in the first interface circuit 110-1 is used to count the number of transmitted subframes. This allows the first interface circuit 110-1 to easily determine the end of a data frame and prepare for the transmission of the next data frame. The counter in the second interface circuit 110-2 is used to count the number of received subframes. This allows the second interface circuit 110-2 to easily determine the end of a data frame, facilitating its understanding of the data frame transmission status for handling downstream tasks (e.g., forwarding the data frame to other interface circuits after receiving a complete data frame).

[0092] Instead of using a counter, some embodiments of this disclosure propose using a frame end marker to indicate the end of a data frame. In these embodiments, after the first interface circuit 110-1 sends all subframes 232 to the second interface circuit 110-2, the first interface circuit 110-1 may send a frame end marker to the second interface circuit 110-2. Figure 2C An exemplary flowchart illustrating communication between a first interface circuit and a second interface circuit according to these embodiments is shown. Figure 2B Based on the example, Figure 2C In the example, the first interface circuit 110-1 and the second interface circuit 110-2 also performed a frame end handshake (three-way handshake). The following section combines... Figure 2C The example illustrates an exemplary transmission process for a single data frame.

[0093] At position 202, the first interface circuit 110-1 sends a first request 204 to the second interface circuit 110-2. The first request 204 can be considered the header of the current data frame. The second interface circuit 110-2 receives the first request 204 from the first interface circuit 110-1 at position 206. After receiving the first request 204, the second interface circuit 110-2 sends a first acknowledgment 210 for the first request 204 to the first interface circuit 110-1 at position 208. The first interface circuit 110-1 receives the first acknowledgment 210 for the first request 204 from the second interface circuit 110-2 at position 212. Thus, the first interface circuit 110-1 and the second interface circuit 110-2 complete their first valid handshake. At position 214, the first interface circuit 110-1 determines the transmission interval based on the time difference between sending the first request 204 and receiving the first acknowledgment 210. In one example, the transmission interval is greater than or equal to half of this time difference.

[0094] At position 216, the first interface circuit 110-1 sends a second request 218 to the second interface circuit 110-2. The second interface circuit 110-2 receives the second request 218 from the first interface circuit 110-1 at position 220. After receiving the second request 218, the second interface circuit 110-2 sends a second acknowledgment 224 for the second request 218 to the first interface circuit 110-1 at position 222. The first interface circuit 110-1 receives the second acknowledgment 224 for the second request 218 from the second interface circuit 110-2 at position 226. Thus, the first interface circuit 110-1 and the second interface circuit 110-2 complete the second valid handshake. In some embodiments of this disclosure, the second interface circuit 110-2 may not send the second acknowledgment 224, allowing the first interface circuit 110-1 to begin subsequent operations at a predetermined time after sending the second request 218.

[0095] At 228, the second interface circuit 110-2 determines a transmission interval based on the time difference between sending the first acknowledgment 210 and receiving the second request 218. In one example, the transmission interval is greater than or equal to half of the aforementioned time difference. At 230, the first interface circuit 110-1 sends multiple subframes 232 to the second interface circuit 110-2 according to the determined transmission interval. At 234, the second interface circuit 110-2 receives multiple subframes 232 from the first interface circuit 110-1 according to the determined transmission interval.

[0096] After the first interface circuit 110-1 sends all subframes 232 to the second interface circuit 110-2, the first interface circuit 110-1 can send a frame end marker 238 to the second interface circuit 110-2 at position 236. The frame end marker 238 indicates the end of the data frame. The second interface circuit 110-2 receives the frame end marker 238 at position 240. Then, the second interface circuit 110-2 sends a frame end acknowledgment 244 to the first interface circuit 110-1 at position 242. The first interface circuit 110-1 receives the frame end acknowledgment 244 at position 246, thus confirming the end of the current data frame. In this way, the first interface circuit 110-1 can begin the transmission of the next data frame.

[0097] It should be noted that the operation at position 214 can be executed in parallel with the operation at position 216, or after the operation at position 216. Embodiments of this disclosure do not limit the execution order of the operations at positions 214 and 216. The operation at position 222 can be executed in parallel with the operation at position 228, or after the operation at position 228. Embodiments of this disclosure do not limit the execution order of the operations at positions 222 and 228.

[0098] In some embodiments of this disclosure, the end-of-frame marker is transmitted via multiple data lines. The end-of-frame marker is represented by inverting the signals on all of these multiple data lines. In embodiments where the encoded values ​​of adjacent data packets are defined using an M-bit inversion encoding method, the end-of-frame marker can be characterized by a full-bit inversion. Since the data packets and the end-of-frame marker are encoded differently, no additional information is needed to distinguish the end-of-frame marker from the data packets, thus achieving a simple representation of the end-of-frame marker. This embodiment uses the end-of-frame marker to indicate the end of a data frame, which helps the receiver understand the transmission status of the data frame in order to process downstream tasks (e.g., forwarding the data frame to other interface circuits after receiving a complete data frame).

[0099] In some further embodiments of this disclosure, the encoding method of the frame end marker can be the same as that of the frame header (the request in the handshake). This allows the receiver to use a unified parsing method to parse the frame header and frame end, and to easily identify signals that do not conform to the above encoding method as abnormal signals.

[0100] The following is combined with Figure 3 The timing diagram shown illustrates a normal communication process between the first interface circuit 110-1 (sender) and the second interface circuit 110-2 (receiver). The first interface circuit 110-1 is controlled by a first master control circuit (not shown). The first master control circuit can use a first reset signal rst_1 to reset the state of each signal of the first interface circuit 110-1. The second interface circuit 110-2 is controlled by a second master control circuit (not shown). The second master control circuit can use a second reset signal rst_2 to reset the state of each signal of the second interface circuit 110-2.

[0101] Before time T1, the first interface circuit 110-1 receives command input indication cmd_in (representing command in the diagram), data input indication data_in (representing data in the diagram), and transmission activation indication tx_in_vld from the first master control circuit. These signals indicate that the first master control circuit will send data tx_data to the first interface circuit 110-1 and instruct the first interface circuit 110-1 to forward the data tx_data to the receiver (second interface circuit 110-2). At time T1, the first interface circuit 110-1 begins sending a first request. The first request can be sent using the four data lines for sending data tx_data. Figure 3 In the example, the first request is represented by toggling all the signals on the four data lines. Since before time T1, the signals on the four data lines are 4-bit binary numbers 0000 (in... Figure 3 In binary, this is represented by 4'b0000), so after flipping these 4 bits, we get the 4-bit binary number 1111 (in...). Figure 3 (represented by 4'b1111 in Chinese), as the first request.

[0102] Because of the transmission path delay between the first interface circuit 110-1 and the second interface circuit 110-2, the second interface circuit 110-2 receives the first request (4'b1111) at time T2, after time T1. For the second interface circuit 110-2, the first request can be received using the four data lines of the received data rx_data. These four data lines of the received data rx_data are the same four data lines of the first interface circuit 110-1 that transmit the data tx_data. The second interface circuit 110-2 sends a first acknowledgment to the first interface circuit 110-1 in the next clock cycle (time T3) after receiving the first request. Figure 3 In the example, the first acknowledgment is indicated by 2 bits, including rx_data_ack[0] and rx_data_ack[1]. rx_data_ack[0] and rx_data_ack[1] can represent the low-order and high-order bits of the first acknowledgment, respectively.

[0103] At time T4, the first interface circuit 110-1 receives the first acknowledgment. The first acknowledgment is indicated to the first interface circuit 110-1 via tx_data_ack[0] and tx_data_ack[1]. Here, tx_data_ack[0] corresponds to rx_data_ack[0]. tx_data_ack[1] corresponds to rx_data_ack[1]. The first interface circuit 110-1 can determine the transmission interval based on the time difference between the time of sending the first request (time T1) and the time of receiving the first acknowledgment (time T4). In one example, the transmission interval can be half the length of time between time T1 and time T4. To provide appropriate redundancy, the transmission interval can be greater than half the length of time between time T1 and time T4.

[0104] The first interface circuit 110-1 sends a second request to the second interface circuit 110-2 in the next clock cycle (at time T5) after receiving the first confirmation. Figure 3 (Represented as 4'b0000 in the original text). The second request is obtained by completely reversing the 4-bit value of the first request. At time T6, after time T5, the second interface circuit 110-2 receives the second request (4'b0000). The second interface circuit 110-2 can determine the transmission interval based on the time difference between sending the first acknowledgment (time T3) and receiving the second request (time T6). In one example, the transmission interval can be half the length of the time between time T3 and time T6. To provide appropriate redundancy, the transmission interval can be greater than half the length of the time between time T3 and time T6.

[0105] In some embodiments of this disclosure, the first interface circuit 110-1 may begin transmitting subframes at a predetermined time (e.g., time T7) after sending the second request. Alternatively, the first interface circuit 110-1 may begin transmitting subframes after receiving the second acknowledgment (assuming the second acknowledgment is received before time T7). Subframes may include ancillary information of a data frame, or a data payload, or both. Ancillary information may include the type of the data payload, or the address of the receiver, or both. Figure 3 In the example, A1:A0 represents the first subframe, A3:A2 represents the second subframe, D1:D0 represents the third subframe, and so on. A1:A0 and A3:A2 represent supplementary information. D1:D0, ..., D9:D8 and D11:D10 represent the data payload. The first interface circuit 110-1 can transmit subframes according to a determined transmission interval. For example, timing begins from the transmission of the first subframe; when the determined transmission interval is reached, the second subframe is transmitted, and so on.

[0106] The following is combined with Figure 4 and Figure 5 The operations of the sender and receiver are described separately. Figure 4 An exemplary flowchart of a method 400 for data transmission performed by a first interface circuit 110-1 according to an embodiment of the present disclosure is shown. At block 402, the first interface circuit 110-1 sends a first request to a second interface circuit 110-2. At block 404, the first interface circuit 110-1 receives a first acknowledgment from the second interface circuit 110-2 in response to the first request. Thus, the first interface circuit 110-1 and the second interface circuit 110-2 complete a valid handshake. At block 406, the first interface circuit 110-1 determines a transmission interval based on the time difference between sending the first request and receiving the first acknowledgment. At block 408, the first interface circuit 110-1 sends a plurality of subframes to the second interface circuit 110-2 according to the determined transmission interval.

[0107] Method 400 employs an asynchronous, clockless transmission scheme and divides the transmission period of a single data frame into two phases. In the delay measurement phase (corresponding to...) Figure 4 In boxes 402 to 406, a handshake is used to determine the transmission delay (the aforementioned time difference) between the sender (first interface circuit 110-1) and the receiver (second interface circuit 110-2), and the transmission interval is determined based on the transmission delay. This ensures the accuracy of the transmission interval. During the data transmission phase (corresponding to...), Figure 4In box 408, each data packet (subframe) is sent according to the determined transmission interval. Method 400 does not perform a handshake during the data transmission phase, thus not affecting the data packet transmission speed. Method 400 achieves both accurate transmission intervals and no data transmission performance by combining handshake and no-handshake methods.

[0108] Figure 5 An exemplary flowchart of a method 500 for data transmission performed by a second interface circuit 110-2 according to an embodiment of the present disclosure is shown. At block 502, the second interface circuit 110-2 receives a first request from a first interface circuit 110-1. At block 504, the second interface circuit 110-2 determines whether the first request has been received. If the second interface circuit 110-2 has received the first request ("yes" at block 504), then the second interface circuit 110-2 sends a first acknowledgment for the first request to the first interface circuit 110-1 at block 506. At block 508, the second interface circuit 110-2 may receive a second request from the first interface circuit 110-1. At block 510, the second interface circuit 110-2 determines a transmission interval based on the time difference between sending the first acknowledgment and receiving the second request. At block 512, the second interface circuit 110-2 receives a plurality of subframes from the first interface circuit 110-1 according to the determined transmission interval.

[0109] Method 500 employs an asynchronous, clockless transmission scheme and divides the transmission period of a single data frame into two phases. In the delay measurement phase (corresponding to...) Figure 5 In boxes 502 to 510, a handshake is used to determine the transmission delay (the aforementioned time difference) between the sender (first interface circuit 110-1) and the receiver (second interface circuit 110-2), and the transmission interval is determined based on the transmission delay. This ensures the accuracy of the transmission interval. During the data transmission phase (corresponding to...), Figure 5 In box 512), each data packet (subframe) is received according to the determined transmission interval. Method 500 does not perform a handshake during the data transmission phase, thus not affecting the data packet transmission speed. Method 500 achieves both accurate transmission intervals and no loss of data transmission performance by combining handshake and no-handshake methods.

[0110] In some embodiments of this disclosure, the transmission interval is determined separately during the transmission of different data frames. For example, the transmission of each data frame can employ... Figures 3 to 5 The process shown is used to redetermine the transmission interval. This allows for flexible control of the transmission rate and better adaptability to ever-changing environments (such as delay changes caused by temperature variations) and scenarios (such as clock frequency conversion).

[0111] In some embodiments of this disclosure, the first acknowledgment is received via at least one feedback line. The first acknowledgment indicates whether the signal received by the second interface circuit is in a normal or abnormal reception state. In one example, the first acknowledgment is transmitted via a single feedback line. In this case, the first acknowledgment can be encoded using a serial encoding method. Such encoding can be based on, for example, a Universal Asynchronous Receiver / Transmitter (UART) communication protocol or other serial communication protocols. In another example, the first acknowledgment is transmitted via multiple feedback lines. In this case, the first acknowledgment is encoded using a single-bit flipping encoding method (e.g., LETS encoding or LEDR encoding). Because the first acknowledgment indicates the state of the signal received by the second interface circuit, the first interface circuit can take appropriate measures when the signal received by the second interface circuit is in an abnormal reception state, such as stopping the transmission of the current data frame and directly transmitting the next data frame, or retransmitting the current data frame, etc.

[0112] In some embodiments of this disclosure, the at least one feedback line includes a first feedback line and a second feedback line. When the signal on the first feedback line flips, a first confirmation indicates a normal reception state of the signal received by the second interface circuit. When the signal on the second feedback line flips, the first confirmation indicates an abnormal reception state of the signal received by the second interface circuit. Figure 6A An exemplary schematic diagram of this encoding method is shown. The low-order bits of the first confirmed value are indicated by a first feedback line, and the high-order bits of the first confirmed value are indicated by a second feedback line. When the first confirmed value transitions between 00 and 10, and between 01 and 11, the first confirmed value represents a logic value "1". When the first confirmed value transitions between 00 and 01, and between 10 and 11, the first confirmed value represents a logic value "0". A logic value "1" indicates an abnormal reception state of the signal received by the second interface circuit. A logic value "0" indicates a normal reception state of the signal received by the second interface circuit. Thus, when the signal on the first feedback line toggles, the first confirmed value represents a logic value "0", thereby indicating a normal reception state of the signal received by the second interface circuit. When the signal on the second feedback line toggles, the first confirmed value represents a logic value "1", thereby indicating an abnormal reception state of the signal received by the second interface circuit.

[0113] In some embodiments of this disclosure, if the signal received by the second interface circuit conforms to a predetermined data encoding rule, the signal received by the second interface circuit can be considered to be in a normal reception state. If the signal received by the second interface circuit does not conform to the predetermined data encoding rule, the signal received by the second interface circuit can be considered to be in an abnormal reception state. For example, if the subframe uses an M-bit flip encoding method and the frame header and frame tail use a full-bit flip encoding method, if the signal received by the second interface circuit is not an M-bit flip or a full-bit flip, it indicates that the signal received by the second interface circuit is in an abnormal reception state. The above-mentioned abnormal situations may occur when a transmission error (incorrect data content) occurs on the data line or a transmission timeout occurs.

[0114] In this type of embodiment, the transmission delay is measured when the signal received by the second interface circuit is in a normal reception state. When the signal received by the second interface circuit is in an abnormal reception state, it is not necessary to measure the transmission delay. Since the transmission delays on different feedback lines may differ, this type of embodiment restricts the information of the correct feedback signal to a single feedback line, maintaining the consistency of the measured delay. This is beneficial for accurately determining the transmission interval. Figure 6A In the example, it is only necessary to measure the delay on the first feedback line.

[0115] In other embodiments of this disclosure, the at least one feedback line includes a first feedback line, a second feedback line, and a third feedback line. When the signal on the first feedback line flips, a first confirmation indicates a normal reception state of the signal received by the second interface circuit. When the signal on the second feedback line flips, the first confirmation indicates first information indicating an abnormal reception state of the signal received by the second interface circuit. When the signal on the third feedback line flips, the first confirmation indicates second information indicating an abnormal reception state of the signal received by the second interface circuit. Figure 6BAn exemplary schematic diagram of this encoding method is shown. The least significant bit of the first confirmed value is indicated by a first feedback line, the middle bit of the first confirmed value is indicated by a second feedback line, and the most significant bit of the first confirmed value is indicated by a third feedback line. The first confirmed value represents the logic value "2" in the following four cases: (i) the first confirmed value transitions between 000 and 100; (ii) the first confirmed value transitions between 001 and 101; (iii) the first confirmed value transitions between 011 and 111; and (iv) the first confirmed value transitions between 010 and 110. The first confirmed value represents the logic value "1" in the following four cases: (i) the first confirmed value transitions between 000 and 010; (ii) the first confirmed value transitions between 001 and 011; (iii) the first confirmed value transitions between 101 and 111; and (iv) the first confirmed value transitions between 100 and 110. The first acknowledgment represents a logic value "0" in the following four cases: (i) the value of the first acknowledgment changes between 000 and 001; (ii) the value of the first acknowledgment changes between 011 and 010; (iii) the value of the first acknowledgment changes between 100 and 101; and (iv) the value of the first acknowledgment changes between 111 and 110. A logic value "0" indicates a normal reception state of the signal received by the second interface circuit. A logic value "1" indicates a first indication of an abnormal reception state of the signal received by the second interface circuit. A logic value "2" indicates a second indication of an abnormal reception state of the signal received by the second interface circuit. The first and second information can be combined to indicate various error types in the abnormal reception state, including data content errors, receive frame header timeout errors, or receive data timeout errors. Thus, when the signal on the first feedback line flips, the first acknowledgment represents a logic value "0," thereby indicating a normal reception state of the signal received by the second interface circuit. When the signal on the second feedback line flips, the first acknowledgment indicates a logic value of "1", thus indicating first information about an abnormal reception state of the signal received by the second interface circuit. When the signal on the third feedback line flips, the first acknowledgment indicates a logic value of "2", thus indicating second information about an abnormal reception state of the signal received by the second interface circuit.

[0116] In this type of embodiment, transmission delay is measured when the signal received by the second interface circuit is in a normal reception state. When the signal received by the second interface circuit is in an abnormal reception state, transmission delay does not need to be measured. Since the transmission delays on different feedback lines may differ, this embodiment restricts the information of the correct feedback signal to a single feedback line, maintaining the consistency of the measured delay. This is beneficial for accurately determining the transmission interval. By setting multiple feedback lines to report error information, richer error information can be indicated by the combination of signals on multiple feedback lines, thus allowing the first interface circuit to grasp more transmission states. Figure 6B In the example, it is only necessary to measure the delay on the first feedback line.

[0117] It should be understood that, although Figure 6A and Figure 6B The least significant bit of the first confirmation is used to indicate a normal reception state, but in other variations of the embodiments of this disclosure, other bits of the first confirmation may also be used to indicate a normal reception state. Although Figure 6A An example with two feedback lines is shown. Figure 6B An example with three feedback lines is shown, but embodiments of this disclosure can support more feedback lines. The number of feedback lines can be set according to the specific application scenario. In some embodiments of this disclosure, the at least one feedback line can be multiplexed with multiple data lines. For example, the at least one feedback line can be connected to the bidirectional input / output (I / O) interfaces of the first interface circuit and the second interface circuit. This can save on the number of I / O lines in the first interface circuit and the second interface circuit.

[0118] Figure 7 An exemplary timing diagram is shown in the event of an abnormal communication between a first interface circuit and a second interface circuit according to an embodiment of the present disclosure. The first interface circuit 110-1 is controllable by a first master control circuit (not shown). The first master control circuit can reset the state of each signal of the first interface circuit 110-1 using a first reset signal rst_1. The second interface circuit 110-2 is controllable by a second master control circuit (not shown). The second master control circuit can reset the state of each signal of the second interface circuit 110-2 using a second reset signal rst_2.

[0119] Before time t1, the first interface circuit 110-1 receives command input indication cmd_in, data input indication data_in, and transmission activation indication tx_in_vld from the first master control circuit. These signals indicate that the first master control circuit will send data tx_data to the first interface circuit 110-1, and instruct the first interface circuit 110-1 to forward the data tx_data to the receiver (second interface circuit 110-2). At time t1, the first interface circuit 110-1 begins sending a first request. The first request can be sent using the four data lines for sending data tx_data. Figure 7 In the example, the first request is represented by toggling all the signals on the four data lines. Since before time t1, the signals on the four data lines are 4-bit binary numbers 0000 (in... Figure 7 In binary, this is represented by 4'b0000), so after flipping these 4 bits, we get the 4-bit binary number 1111 (in...). Figure 7 (represented by 4'b1111 in Chinese), as the first request.

[0120] Because of the transmission path delay between the first interface circuit 110-1 and the second interface circuit 110-2, the second interface circuit 110-2 receives the first request (4'b1111) at time t2, after time t1. For the second interface circuit 110-2, the first request can be received using the four data lines of the received data rx_data. These four data lines of the received data rx_data are the same four data lines of the first interface circuit 110-1 that transmit the data tx_data. The second interface circuit 110-2 sends a first acknowledgment to the first interface circuit 110-1 in the next clock cycle (time t3) after receiving the first request. Figure 7 In the example, the first acknowledgment is indicated by 2 bits, including rx_data_ack[0] and rx_data_ack[1]. rx_data_ack[0] and rx_data_ack[1] can represent the low-order and high-order bits of the first acknowledgment, respectively.

[0121] At time t4, the first interface circuit 110-1 receives the first acknowledgment. The first acknowledgment is indicated to the first interface circuit 110-1 via tx_data_ack[0] and tx_data_ack[1]. Here, tx_data_ack[0] corresponds to rx_data_ack[0]. tx_data_ack[1] corresponds to rx_data_ack[1]. The first interface circuit 110-1 can determine the transmission interval based on the time difference between the time of sending the first request (time t1) and the time of receiving the first acknowledgment (time t4). In one example, the transmission interval can be half the length of the time between time t1 and time t4. To provide appropriate redundancy, the transmission interval can be greater than half the length of the time between time t1 and time t4.

[0122] The first interface circuit 110-1 sends a second request to the second interface circuit 110-2 in the next clock cycle (at time t5) after receiving the first confirmation. Figure 3 (Represented as 4'b0000 in the original text). The second request is obtained by completely reversing the 4-bit value of the first request. At time t6, after time t5, the second interface circuit 110-2 receives the second request (4'b0000). The second interface circuit 110-2 can determine the transmission interval based on the time difference between sending the first acknowledgment (time t3) and receiving the second request (time t6). In one example, the transmission interval can be half the length of the time between time t3 and time t6. To provide appropriate redundancy, the transmission interval can be greater than half the length of the time between time t3 and time t6.

[0123] In some embodiments of this disclosure, the first interface circuit 110-1 may begin transmitting subframes at a predetermined time after sending the second request. Alternatively, the first interface circuit 110-1 may begin transmitting subframes after receiving the second acknowledgment. Subframes may include ancillary information of a data frame, or a data payload, or both. Ancillary information may include the type of the data payload, or the address of the recipient, or both. Figure 7 In the example, A1:A0 represents the first subframe, A3:A2 represents the second subframe, D1:D0 represents the third subframe, and so on. A1:A0 and A3:A2 represent supplementary information. D1:D0, ..., D9:D8 and D11:D10 represent the data payload. The first interface circuit 110-1 can transmit subframes according to a determined transmission interval. For example, timing begins from the transmission of the first subframe; when the determined transmission interval is reached, the second subframe is transmitted, and so on.

[0124] If the second interface circuit 110-2 detects an error during data reception (e.g., frame header timeout error, data reception timeout error, data content error, etc.), it can indicate the abnormal reception status to the first interface circuit 110-1 via the feedback line. Figure 7 In the example, at time t7, rx_data_ack[1] toggles to a high level. At time t8, the first interface circuit 110-1 receives an indication of an abnormal reception state (tx_data_ack[1] toggles to a high level). The first interface circuit 110-1 can retransmit the current data frame.

[0125] Before time t9, the signals on the four data lines were 4-bit binary numbers 0100 (in...). Figure 7 (Represented as 4'b0100). At time t9, the first interface circuit 110-1 flips these 4 bits to obtain the 4-bit binary number 1011 (in...). Figure 7 (represented by 4'b1011 in Chinese), as the first request.

[0126] At time t10, after time t9, the second interface circuit 110-2 receives the first request (4'b1011). In the next clock cycle after receiving the first request (time t11), the second interface circuit 110-2 sends a first acknowledgment to the first interface circuit 110-1 (rx_data_ack[0] toggles to high level).

[0127] At time t12, the first interface circuit 110-1 receives the first acknowledgment (tx_data_ack[0] toggles high). The first interface circuit 110-1 can determine the transmission interval based on the time difference between the time the first request was sent (time t9) and the time the first acknowledgment was received (time t12). In one example, the transmission interval can be half the length of the time between time t9 and time t12. To provide appropriate redundancy, the transmission interval can be greater than half the length of the time between time t9 and time t12.

[0128] The first interface circuit 110-1 sends a second request to the second interface circuit 110-2 in the next clock cycle (at time t13) after receiving the first confirmation. Figure 7(Represented as 4'b0100 in the original text). The second request is obtained by completely reversing the 4-bit value of the first request. At time t14, after time t13, the second interface circuit 110-2 receives the second request (4'b0100). The second interface circuit 110-2 can determine the transmission interval based on the time difference between sending the first acknowledgment (time t11) and receiving the second request (time t14). In one example, the transmission interval can be half the length of the time between time t11 and time t14. To provide appropriate redundancy, the transmission interval can be greater than half the length of the time between time t11 and time t14.

[0129] In some embodiments of this disclosure, the first interface circuit 110-1 may begin transmitting subframes at a predetermined time after sending the second request. Alternatively, the first interface circuit 110-1 may begin transmitting subframes after receiving the second acknowledgment. The first interface circuit 110-1 may transmit subframes according to a determined transmission interval. For example, timing may begin from the transmission of the first subframe, and when the timing reaches the determined transmission interval, the second subframe is transmitted, and so on.

[0130] Figure 8 Another exemplary flowchart illustrates a method for data transmission performed by a first interface circuit according to an embodiment of this disclosure. Figure 8 The examples illustrate how to handle abnormal reception states. In some embodiments of this disclosure, if the signal received by the second interface circuit conforms to predetermined data encoding rules, the signal received by the second interface circuit can be considered to be in a normal reception state. If the signal received by the second interface circuit does not conform to predetermined data encoding rules, the signal received by the second interface circuit can be considered to be in an abnormal reception state. For example, if the subframe uses an M-bit flip encoding method and the frame header and frame tail use a full-bit flip encoding method, if the signal received by the second interface circuit is not an M-bit flip or a full-bit flip, it indicates that the signal received by the second interface circuit is in an abnormal reception state. The above-mentioned abnormal situations may occur when a transmission error (incorrect data content) occurs on the data line, a transmission error (incorrect acknowledgment content) occurs on the feedback line, or a transmission timeout occurs.

[0131] At block 802, the first interface circuit 110-1 sends a first request to the second interface circuit 110-2. At block 804, the first interface circuit 110-1 receives a first acknowledgment from the second interface circuit 110-2 in response to the first request. This completes a valid handshake between the first interface circuit 110-1 and the second interface circuit 110-2. At block 806, the first interface circuit 110-1 determines whether the first acknowledgment indicates an abnormal reception state. In one example, the first acknowledgment can indicate an abnormal reception state by toggling the second feedback line without toggling the first feedback line. In another example, if the value of the first acknowledgment does not conform to the data encoding rules (e.g., it is not an M-bit toggle), the first acknowledgment itself is considered erroneous. In this case, an abnormal reception state is also considered to have occurred.

[0132] If the first acknowledgment does not indicate an abnormal reception state ("No" at block 806), then at block 808, the first interface circuit 110-1 sends a second request to the second interface circuit. At block 810, the first interface circuit 110-1 determines the transmission interval based on the time difference between sending the first request and receiving the first acknowledgment. At block 812, the first interface circuit 110-1 sends multiple subframes to the second interface circuit 110-2 according to the determined transmission interval.

[0133] At box 814, the first interface circuit 110-1 determines whether the receiving end (second interface circuit 110-2) indicates an abnormal reception state during the transmission of multiple subframes. If the receiving end does not indicate an abnormal reception state during the transmission of multiple subframes ("No" at box 814), then at box 816, the first interface circuit 110-1 can determine whether the frame tail confirmation indicates an abnormal reception state. If the frame tail confirmation does not indicate an abnormal reception state ("No" at box 816), it indicates that the current data frame has been completely transmitted, and the transmission process of the current data frame can be terminated at box 824.

[0134] exist Figure 8 In the example, if the first acknowledgment indicates an abnormal reception state ("Yes" at box 806), then at box 818, the first interface circuit 110-1 determines whether the number of errors (abnormal reception state) has reached a threshold. If the number of errors has not reached the threshold ("No" at box 818), the process returns to box 802, and the current data frame is retransmitted. If the number of errors has reached the threshold ("Yes" at box 818), the process proceeds to box 820, the first interface circuit 110-1 cancels the transmission of the current data frame, and reports the error.

[0135] If, during the transmission of multiple subframes, the receiver indicates an abnormal reception status ("Yes" in box 814), then at box 818, the first interface circuit 110-1 can determine whether the number of errors has reached a threshold. If the number of errors has not reached the threshold ("No" in box 818), the process returns to box 802, and the current data frame is retransmitted. If the number of errors has reached the threshold ("Yes" in box 818), the process proceeds to box 820, the first interface circuit 110-1 cancels the transmission of the current data frame, and reports the error.

[0136] If the frame end confirmation indicates an abnormal reception status at box 816 (marked as "Yes" at box 816), then at box 818, the first interface circuit 110-1 can determine whether the number of errors has reached a threshold. If the number of errors has not reached the threshold (marked as "No" at box 818), the process returns to box 802, and the current data frame is retransmitted. If the number of errors has reached the threshold (marked as "Yes" at box 818), the process proceeds to box 820, the first interface circuit 110-1 cancels the transmission of the current data frame, and reports the error.

[0137] It should be noted that the operation at box 808 can be performed in parallel with the operation at box 810, or after the operation at box 810. The embodiments of this disclosure do not limit the execution order of the operations at box 808 and box 810. The operation at box 814 can be performed in parallel with the operation at box 812. In one example, the threshold count at box 818 can be equal to 1. In another example, the threshold count can be greater than 1.

[0138] In some embodiments of this disclosure, the first interface circuit may include a transmitting circuit, a receiving circuit, and an interval determination circuit. The transmitting circuit may be configured to send a first request to the second interface circuit. The receiving circuit may be configured to receive a first acknowledgment from the second interface circuit in response to the first request. The interval determination circuit may be configured to determine a transmission interval based on the time difference between sending the first request and receiving the first acknowledgment. The transmitting circuit may also be configured to send multiple subframes to the second interface circuit according to the determined transmission interval. The second interface circuit may include a receiving circuit, a transmitting circuit, and an interval determination circuit. The receiving circuit may be configured to receive a first request from the first interface circuit. The transmitting circuit may be configured to send a first acknowledgment to the first interface circuit in response to the first request if it receives the first request. The receiving circuit may also be configured to receive a second request from the first interface circuit. The interval determination circuit may be configured to determine a transmission interval based on the time difference between sending the first acknowledgment and receiving the second request. The transmitting circuit may also be configured to receive multiple subframes from the first interface circuit according to the determined transmission interval.

[0139] Figure 9 A more detailed exemplary structure of the first and second interface circuits according to embodiments of this disclosure is shown. The first interface circuit, acting as the transmitter 901, can use a local clock signal TX_CLK. The second interface circuit, acting as the receiver 902, can use a local clock signal RX_CLK.

[0140] The sender 901 may include a depacketizing circuit, a transmission interval configuration circuit, a data encoding circuit, an asynchronous-to-synchronous conversion circuit, a feedback decoding circuit, and a retransmission and reporting circuit. In one example, the sender 901 may also include the counter described above. The depacketizing circuit may be configured to depacket data packets from the first master control circuit to extract the data from the data packets. The data encoding circuit may be configured to encode the extracted data for transmission as data frames. The transmission interval configuration circuit may be configured to determine the transmission interval of the data frames. Alternatively or additionally, the transmission interval configuration circuit may also be configured to receive a default value of TX_PARA_TIMEOUT for the transmission interval. Thus, if the sender 901 transmits data asynchronously without a handshake, the value of TX_PARA_TIMEOUT can be used as the transmission interval. The asynchronous-to-synchronous conversion circuit may be configured to convert asynchronous signals (signals with out-of-sync clocks) into synchronous signals (signals with synchronized clocks) for use by downstream circuits of the sender 901. The feedback decoding circuit may be configured to decode feedback signals (e.g., first acknowledgment, second acknowledgment) from the receiver 902. The retransmission and reporting circuit can be configured to retransmit the current data frame if the number of errors has not reached a threshold, and to report an error to the first master control circuit if the number of errors has reached a threshold.

[0141] Receiver 902 may include packet assembly circuitry, transmission interval configuration circuitry, data decoding circuitry, asynchronous-to-synchronous conversion circuitry, feedback encoding circuitry, and error feedback circuitry. In one example, receiver 902 may also include the counter described above. The data decoding circuitry may be configured to decode data (e.g., a first request, a second request, multiple subframes) from sender 901. The transmission interval configuration circuitry may be configured to determine the transmission interval of data frames. Alternatively or additionally, the transmission interval configuration circuitry may also be configured to receive a default value of RX_PARA_TIMEOUT for the transmission interval. Thus, if sender 901 receives data asynchronously without a handshake, receiver 902 can use the value of RX_PARA_TIMEOUT as the transmission interval. The packet assembly circuitry may be configured to assemble the data decoded by the data decoding circuitry into packets for use by downstream circuitry. The asynchronous-to-synchronous conversion circuitry may be configured to convert asynchronous signals (signals with out-of-clock timing) into synchronous signals (signals with synchronized timing) for use by downstream circuitry of receiver 902. The feedback encoding circuit can be configured to encode feedback signals (e.g., first acknowledgment, second acknowledgment) for transmission to sender 901. The error feedback circuit can be configured to report an error to the second master control circuit associated with receiver 902 if the number of errors reaches a threshold number.

[0142] In some embodiments of this disclosure, the feedback line may be multiplexed with at least a portion of a plurality of data lines. Figure 10 An exemplary schematic diagram of such an embodiment is shown. Figure 10 In the example, the feedback line can be connected to the bidirectional input / output (I / O) interfaces (e.g., ...) of the transmitter 901 (first interface circuit) and the receiver 902 (second interface circuit). Figure 10 (As shown by the bidirectional arrows in the diagram). This saves on the number of I / O operations in the first and second interface circuits.

[0143] Some embodiments of this disclosure also support broadcast scenarios. Figure 11An exemplary schematic diagram of the connection between a sender 901 and multiple receivers 902-1, ..., 902-N in such embodiments is shown. In these embodiments, the sender 901 determines the number of receivers for data transmission. If the number of receivers is greater than one, the sender 901 sends multiple subframes to each receiver according to a configured transmission interval. This type of embodiment considers a one-to-many broadcast scenario. In such a scenario, the transmission delay between the sender and each receiver may differ, making it unsuitable to determine the transmission delay separately for each receiver. This type of embodiment can switch the data transmission mode to an asynchronous, handshake-free mode and set the configured transmission interval to meet the acceptable transmission delay for each receiver. This ensures that the transmission interval is consistent for each receiver, simplifying the sender's operation and guaranteeing the accuracy of the transmission between the sender and each receiver.

[0144] Some embodiments of this disclosure are also applicable to scenarios where multiple circuits are cascaded. Figure 12 An exemplary schematic diagram of multiple cascaded circuits according to embodiments of the present disclosure is shown. Figure 12 In the example, the first-stage circuit 1210, the second-stage circuit 1220, and the third-stage circuit 1230 are cascaded. The first-stage circuit 1210 is intended to transmit data to the third-stage circuit 1230 via the second-stage circuit 1220. The first-stage circuit 1210 may include a transmitting interface circuit (denoted as SD1 in the figure). The second-stage circuit 1220 may include a receiving interface circuit (denoted as RE2 in the figure) and a transmitting interface circuit (denoted as SD2 in the figure). In the second-stage circuit 1220, RE2 may pass received data to SD2 via an intermediate processing circuit (not shown). The intermediate processing circuit may perform adaptive processing on the data. The third-stage circuit 1230 may include a receiving interface circuit (denoted as RE3 in the figure). In this context, the transmitting interface circuit refers to the circuit used to transmit data, and the receiving interface circuit refers to the circuit used to receive data. To avoid obscuring the focus of this disclosure with unnecessary details, Figure 12 Other circuit units in the first-level circuit 1210, the second-level circuit 1220, and the third-level circuit 1230 are not shown.

[0145] The second-level circuit 1220 can receive data frames from the first-level circuit 1210 via RE2 from SD1. The additional information in the data frame includes a first distribution address. The first distribution address includes the address of the second-level circuit 1220 and the address of the third-level circuit 1230. RE2 or SD2 in the second-level circuit 1220 can remove the address of the second-level circuit 1220 from the first distribution address to obtain a second distribution address. Then, the second-level circuit 1220 can send the second distribution address to RE3 of the third-level circuit 1230 via SD2. In this way, during the step-by-step forwarding of data frames, the length of the distribution address can gradually shorten, thereby saving transmission bandwidth.

[0146] Some embodiments of this disclosure also propose a multi-level reverse pressure mechanism for write commands. The first-level circuit 1210 may include a first-level reverse pressure control circuit 1211. The second-level circuit 1220 may include a second-level reverse pressure control circuit 1221. The second-level circuit 1220 can receive write commands from the first-level circuit 1210 via RE2. The write command from the first-level circuit 1210 can be passed from RE2 to SD2. Then, the second-level circuit 1220 can send the write command to RE3 of the third-level circuit 1230 via SD2. Before receiving a completion acknowledgment for the write command from the third-level circuit 1230, SD2 of the second-level circuit 1220 can enable the second-level reverse pressure signal via the second-level reverse pressure control circuit 1221. During the period when the second-level reverse pressure signal is valid, RE2 of the second-level circuit 1220 is prohibited from sending completion acknowledgments to the first-level circuit 1210. After receiving a completion acknowledgment for the write command from the third-level circuit 1230, the SD2 of the second-level circuit 1220 sends a completion acknowledgment to the first-level circuit 1210 via RE2. The first-level reverse voltage control circuit 1211 in the first-level circuit 1210 is configured to activate the first-level reverse voltage signal before receiving the completion acknowledgment from the second-level circuit 1220. During the period when the first-level reverse voltage signal is active, the first-level circuit 1210 is prohibited from sending new commands to the second-level circuit 1220. Thus, through the multi-level reverse voltage mechanism, the first-level circuit 1210 can send a new write command only after confirming that the third-level circuit 1230 has successfully received the current write command, avoiding data write errors caused by time delay errors between the multi-level circuits.

[0147] It should be noted that, Figure 12 In the example, since RE2 receives data and then passes it to SD2, "RE2 receives data" can also be expressed as "SD2 receives data" (equivalent to SD2 receiving data through RE2). Similarly, "SD2 sends data" can also be expressed as "RE2 sends data" (equivalent to RE2 sending data through SD2). Thus, Figure 12The cascaded circuits shown can perform the following operations: RE2 receives a first distribution address from SD1. The first distribution address includes the address of the second-stage circuit 1220 (which can be considered the address of RE2 or SD2) and the address of the third-stage circuit 1230 (which can be considered the address of RE3). RE2 or SD2 removes the address of the second-stage circuit 1220 from the first distribution address to obtain a second distribution address. RE2 (via SD2) sends the second distribution address to RE3. RE2 receives a write instruction from SD1. RE2 (via SD2) sends a write instruction to RE3. RE2 (via SD2) receives a completion acknowledgment from RE3 for the write instruction. RE2 sends a completion acknowledgment to SD1. SD1 is prohibited from sending new instructions to RE3 until it receives the completion acknowledgment.

[0148] Figure 13 Another exemplary schematic diagram showing multiple circuits cascaded according to embodiments of this disclosure is illustrated. Figure 13 In the example, the second circuit 1320 is cascaded with the first circuit 1310. The third circuit 1330 and the fourth circuit 1340 are cascaded with the second circuit 1320, respectively. The fifth circuit 1350 and the sixth circuit 1360 are cascaded with the third circuit 1330, respectively. The seventh circuit 1370 and the eighth circuit 1380 are cascaded with the fourth circuit 1340, respectively. Note that... Figure 13 The cascading relationships shown are merely illustrative; individual circuits can be cascaded with more or fewer circuits.

[0149] The transmitting interface circuit in the first circuit 1310 is represented by SD12 in the figure. The receiving interface circuit in the first circuit 1310 is represented by RE12 in the figure. In the second circuit 1320, the receiving interface circuit RE21 receives data from SD12, and the transmitting interface circuit SD21 transmits data to RE12. Thus, SD12 in the first circuit 1310 and RE21 in the second circuit 1320 form a corresponding transmitter and receiver pair, enabling the first circuit 1310 to transmit data to the second circuit 1320. SD21 in the second circuit 1320 and RE12 in the first circuit 1310 form a corresponding transmitter and receiver pair, enabling the second circuit 1320 to transmit data to the first circuit 1310. To more clearly represent the transmitter and receiver, in... Figure 13 In this game, blank squares represent the sender, and shaded squares represent the receiver.

[0150] When the second circuit 1320 is connected to multiple circuits (e.g., the third circuit 1330 and the fourth circuit 1340), the second circuit 1320 can be configured with a transmitting interface circuit and a receiving interface circuit for each connected circuit. For example, the transmitting interface circuit SD23 can transmit data to a corresponding receiving interface circuit in the third circuit 1330. The receiving interface circuit RE23 can receive data from a corresponding transmitting interface circuit in the third circuit 1330. The transmitting interface circuit SD24 can transmit data to a corresponding receiving interface circuit in the fourth circuit 1340. The receiving interface circuit RE24 can receive data from a corresponding transmitting interface circuit in the fourth circuit 1340.

[0151] By providing both a transmitting interface circuit and a receiving interface circuit in both the first circuit 1310 and the second circuit 1320, bidirectional communication between the first circuit 1310 and the second circuit 1320 can be achieved. Similarly, both a transmitting interface circuit and a receiving interface circuit can be provided in any two connected circuits to achieve bidirectional communication between them. It should be noted that if bidirectional communication is not required between the two circuits, only one of the transmitting interface circuit and the receiving interface circuit can be provided as needed.

[0152] In summary, the data transmission method according to embodiments of this disclosure employs an asynchronous, clockless transmission scheme and divides the data frame transmission period into two phases. In the first phase (also referred to in this context as the "delay measurement phase"), the transmission delay (the aforementioned time difference) between the sender (first interface circuit) and the receiver (second interface circuit) is determined through a handshake, and the transmission interval is determined based on this delay. This ensures the accuracy of the transmission interval. In the second phase following the first phase (also referred to in this context as the "data transmission phase"), individual data packets (subframes) are sent according to the determined transmission interval. This method does not perform a handshake during the data transmission phase, thus not affecting the data packet transmission speed. This method achieves both accurate transmission intervals and no data transmission performance by combining a handshake approach with a no-handshake approach.

[0153] Furthermore, the data transmission method according to embodiments of this disclosure can provide feedback on abnormal signal reception status. This allows the sender to take timely countermeasures when the signal received by the receiver is in an abnormal reception state, thereby saving communication time between the two parties.

[0154] This disclosure can be a method, apparatus, system, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of this disclosure.

[0155] A computer-readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer-readable storage medium can be, for example—but not limited to—an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), and any suitable combination thereof. The computer-readable storage medium as used herein is not to be construed as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0156] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0157] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0158] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0159] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0160] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0161] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0162] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or pervasive.

[0163] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with at least one other aspect. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0164] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for data transmission, performed by a first interface circuit, the method comprising: Send the first request to the second interface circuit; Receive a first acknowledgment from the second interface circuit in response to the first request; The transmission interval is determined based on the time difference between sending the first request and receiving the first confirmation; and Multiple subframes are sent to the second interface circuit according to the determined transmission interval.

2. The method according to claim 1, wherein adjacent subframes in the plurality of subframes are encoded in an M-bit flipped encoding scheme, where M is greater than or equal to one and less than the total number of bits encoding a single subframe, the first request and the plurality of subframes are transmitted via a plurality of data lines, and the first request is represented by flipping the signals on all of the plurality of data lines.

3. The method according to claim 1 or 2, further comprising: In response to receiving the first confirmation, a second request is sent to the second interface circuit.

4. The method according to claim 1 or 2, further comprising: A frame end marker is sent to the second interface circuit, the frame end marker indicating the end of the data frame.

5. The method of claim 4, wherein adjacent subframes in the plurality of subframes are encoded in an M-bit flipped encoding scheme, where M is greater than or equal to one and less than the total number of bits encoding a single subframe, the frame end marker is transmitted via a plurality of data lines, and the frame end marker is represented by flipping the signals on all of the plurality of data lines.

6. The method according to claim 1 or 2, further comprising: Determine the number of subframes to be sent; as well as In response to the number of sent subframes reaching the data length of the data frame and receiving an acknowledgment from the second interface circuit for the tail subframe among the multiple subframes, the data frame is determined to have ended.

7. The method according to claim 1 or 2, wherein the transmission interval is determined separately during the transmission of different data frames.

8. The method according to claim 1 or 2, wherein the first confirmation is received via at least one feedback line, and the first confirmation indicates a normal or abnormal reception state of the signal received by the second interface circuit.

9. The method of claim 8, wherein the at least one feedback line includes a first feedback line and a second feedback line, wherein when the signal on the first feedback line flips, the first confirmation indicates the normal reception state of the signal received by the second interface circuit, and when the signal on the second feedback line flips, the first confirmation indicates the abnormal reception state of the signal received by the second interface circuit.

10. The method of claim 8, wherein the at least one feedback line includes a first feedback line, a second feedback line, and a third feedback line, wherein when the signal on the first feedback line flips, the first confirmation indicates the normal reception state of the signal received by the second interface circuit; when the signal on the second feedback line flips, the first confirmation indicates first information of the abnormal reception state of the signal received by the second interface circuit; and when the signal on the third feedback line flips, the first confirmation indicates second information of the abnormal reception state of the signal received by the second interface circuit.

11. The method of claim 8, further comprising: The number of errors that occurred during the transmission of the first request in the first data frame and the plurality of subframes is determined at least in part based on the first confirmation; as well as In response to the number of times the threshold is not reached, the first data frame is retransmitted.

12. The method according to claim 1 or 2, further comprising: Determine the number of recipients for the data transmission; as well as In response to the fact that the number of receivers is greater than one, the plurality of subframes are sent to each receiver according to the configured transmission interval.

13. A method for data transmission, performed by a second interface circuit, the method comprising: Receive a first request from the first interface circuit; In response to receiving the first request, a first acknowledgment for the first request is sent to the first interface circuit; Receive a second request from the first interface circuit; The transmission interval is determined based on the time difference between the time of sending the first confirmation and the time of receiving the second request; as well as Multiple subframes from the first interface circuit are received according to the determined transmission interval.

14. The method of claim 13, wherein adjacent subframes in the plurality of subframes are encoded in an M-bit flipped encoding scheme, where M is greater than or equal to one and less than the total number of bits encoding a single subframe, the first request, the second request, and the plurality of subframes are received via a plurality of data lines, and the first request and the second request are represented by flipping the signals on all of the plurality of data lines.

15. The method according to claim 13 or 14, further comprising: In response to receiving a frame end marker from the first interface circuit, the end of the data frame is determined.

16. The method of claim 15, wherein adjacent subframes in the plurality of subframes are encoded in an M-bit flipped encoding scheme, where M is greater than or equal to one and less than the total number of bits encoding a single subframe, the frame end marker is received via a plurality of data lines, and the frame end marker is represented by flipping the signals on all of the plurality of data lines.

17. The method according to claim 13 or 14, further comprising: Determine the number of received subframes; as well as When the number of received subframes reaches the data length of the data frame, the data frame is determined to be terminated.

18. The method according to claim 13 or 14, wherein the transmission interval is determined separately during the transmission of different data frames.

19. The method of claim 13 or 14, wherein the first acknowledgment is transmitted via at least one feedback line, and the first acknowledgment indicates a normal or abnormal reception state of the signal received by the second interface circuit.

20. The method of claim 19, wherein the at least one feedback line includes a first feedback line and a second feedback line, wherein when the signal on the first feedback line flips, the first confirmation indicates the normal reception state of the signal received by the second interface circuit, and when the signal on the second feedback line flips, the first confirmation indicates the abnormal reception state of the signal received by the second interface circuit.

21. The method of claim 19, wherein the at least one feedback line includes a first feedback line, a second feedback line, and a third feedback line, wherein when the signal on the first feedback line flips, the first confirmation indicates the normal reception state of the signal received by the second interface circuit; when the signal on the second feedback line flips, the first confirmation indicates first information of the abnormal reception state of the signal received by the second interface circuit; and when the signal on the third feedback line flips, the first confirmation indicates second information of the abnormal reception state of the signal received by the second interface circuit.

22. A first interface circuit, comprising: The transmitting circuit is configured to send a first request to the second interface circuit; The receiving circuit is configured to receive a first acknowledgment from the second interface circuit in response to the first request; as well as An interval determination circuit is configured to determine a transmission interval based on the time difference between the time when the first request is sent and the time when the first acknowledgment is received. The transmitting circuit is further configured to transmit multiple subframes to the second interface circuit at determined transmission intervals.

23. A second interface circuit, comprising: The receiving circuit is configured to receive a first request from the first interface circuit. as well as The transmitting circuit is configured to send a first acknowledgment to the first interface circuit in response to receiving the first request; The receiving circuit is further configured to receive a second request from the first interface circuit; The second interface circuit further includes an interval determination circuit, which is configured to determine a transmission interval based on the time difference between sending the first acknowledgment and receiving the second request; The transmitting circuit is also configured to receive multiple subframes from the first interface circuit at determined transmission intervals.

24. A chip, comprising: At least one of the first interface circuit according to claim 22 or the second interface circuit according to claim 23; as well as An encapsulation structure that surrounds at least one of the first interface circuit or the second interface circuit.

25. An electronic device, comprising: At least one of the first interface circuit according to claim 22 or the second interface circuit according to claim 23; as well as The power supply circuit is configured to supply power to at least one of the first interface circuit or the second interface circuit.

Images