Method and system for write transaction processing of multi-chip interconnect

Abstract

Embodiments of the present application provide a multi-chip interconnection write transaction processing method and system. A first chip receiving side proxy pre-allocates write request message credits and write data message credits to a second chip sending side proxy. The number of write request message credits is equal to the number of request processing tracker entries, and the number of write data message credits is equal to the number of write data tracker entries. The second chip sending side proxy allocates a unique write transaction identifier for a write transaction, and independently sends a write request and write data carrying the identifier when there are available credits, and the sending order of the two is not restricted. The first chip receiving side proxy performs content address comparison with the write transaction identifier, forwards the matched write request and write data to an internal bus for processing, and returns the corresponding credit when the request processing tracker or write data tracker entry is released. The credit pre-allocation mechanism replaces the transaction-by-transaction DBIDResp handshake mechanism in the standard CHI protocol, eliminates cross-chip round-trip delay, and decouples write request and write data transmission.

Description

Technical Field

[0001] This application relates to the field of multi-chip interconnect communication technology, and in particular to a write transaction processing method and system for multi-chip interconnect. Background Technology

[0002] The CHI (Coherent Hub Interface) protocol is a standard protocol for system-on-chip interconnection under the ARM AMBA framework, defining consistent transactional interactions between the requesting node (RN) and the home node (HN). In the standard CHI write transaction flow, after the RN sends a write request to the HN, the HN must return a DBIDResp (write buffer number response) to the RN, carrying a dynamically assigned DBID (write buffer number). The RN can only send write data after receiving the DBIDResp. The HN then associates the write data with the corresponding write request using the DBID and completes the processing. This mechanism works well in on-chip interconnect scenarios, with round-trip latency at the nanosecond level, and its impact on overall performance is negligible.

[0003] With the continuous growth in computing power demands from high-performance computing and artificial intelligence applications, the computing power and storage capacity of a single chip can no longer meet application requirements. Chip-to-chip (CHIP2CHIP) architecture has become the mainstream solution to overcome the resource limitations of a single chip, while also extending the CHI protocol to inter-chip interconnect scenarios. In the CHIP2CHIP architecture, chips are connected via high-speed serial links. Each chip deploys a Home Agent (HA) and a Request Agent (RA) at the interface to complete cross-chip transaction forwarding. However, the physical latency of inter-chip links is much higher than that of intra-chip interconnects. For example, serialization, encoding, signal equalization, and deserialization processes introduce round-trip delays of tens or even hundreds of nanoseconds.

[0004] In inter-chip interconnect scenarios, the DBIDResp mechanism in the standard CHI write transaction process introduces a fundamental efficiency flaw: each write transaction must wait for DBIDResp to return from the peer HA across the chip before the RN can send the write data. This introduces at least one complete inter-chip round-trip delay, forcibly serializing the write request channel and the write data channel, which should be independent, forming a structural bottleneck in the write transaction path. Under write-intensive loads, this bottleneck directly restricts the upper limit of effective write bandwidth, urgently requiring an optimization scheme that can eliminate the DBIDResp cross-chip round trip while maintaining compatibility with the CHI protocol. Summary of the Invention

[0005] This application provides a write transaction processing method and system for multi-chip interconnection, which replaces the DBIDResp handshake mechanism of per-transaction allocation in the standard CHI protocol with a message credit pre-allocation mechanism, eliminating cross-chip round-trip latency on the write transaction processing path, and decoupling the sending order of the write request channel and the write data channel through independent message credit management, releasing the scheduling freedom of the sending side, while the receiving side uses the write transaction identifier to perform content addressing comparison to achieve out-of-order matching of write requests and write data, thereby significantly reducing the processing latency of write transactions in multi-chip interconnection scenarios, improving effective write bandwidth, and having good compatibility and ecosystem reuse capabilities with the standard CHI protocol.

[0006] In a first aspect, embodiments of this application provide a write transaction processing method for multi-chip interconnection, applied to a receiving-side proxy of a first chip, wherein the first chip is connected to a second chip via an inter-chip link, and the method includes: Write request message credits and write data message credits are allocated to the sending-side agent of the second chip. The number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip. The second chip's sending test agent receives a write request sent when it determines that a local write request message credit exists, or write data sent when it determines that a local write data message credit exists; the second chip's sending test agent consumes one write request message credit for each write request sent, and consumes one write data message credit for each write data sent. Content addressing comparison is performed based on the write transaction identifier carried by the received write request to determine the write data with the same write transaction identifier as the received write request; content addressing comparison is performed based on the write transaction identifier carried by the received write data to determine the write request with the same write transaction identifier as the received write data; wherein, the write request and write data with the same write transaction identifier are forwarded to the internal bus of the first chip for corresponding write transaction processing. In response to the release of the request processing tracker entry of the first chip, a write request message credit is returned to the sending-side agent of the second chip; in response to the release of the write data tracker entry of the first chip, a write data message credit is returned to the sending-side agent of the second chip.

[0007] Secondly, embodiments of this application provide a write transaction processing method for multi-chip interconnection, applied to a sending-side proxy of a second chip, wherein the second chip is connected to the first chip via an inter-chip link, and the method includes: The first chip receives write request message credits and write data message credits allocated by the receiving-side agent. The number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip. Assign a write transaction identifier to the write transaction to be sent, the write transaction identifier being used to uniquely identify the write transaction; If it is determined that a write request message credit is available locally, then one write request message credit is consumed and a write request carrying the write transaction identifier is sent to the receiving agent of the first chip. If it is determined that a write data message credit is available locally, one write data message credit is consumed and write data carrying the write transaction identifier is sent to the receiving agent of the first chip. The write request and the write data are sent independently and in no particular order. The receiving agent of the first chip performs association matching through the write transaction identifier after receiving the write request and the write data.

[0008] Thirdly, embodiments of this application provide a write transaction processing method for multi-chip interconnection, applied to a multi-chip interconnection system including a first chip and a second chip, wherein the first chip and the second chip are connected via an inter-chip link, and the method includes: The receiving agent of the first chip allocates write request message credits and write data message credits to the sending agent of the second chip. The number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip. The sending-side agent of the second chip assigns a write transaction identifier to the write transaction to be sent, and the write transaction identifier is used to uniquely identify the write transaction; When the sending agent of the second chip determines that there is a usable write request message credit locally, it consumes one write request message credit and sends a write request carrying the write transaction identifier to the receiving agent of the first chip; when it determines that there is a usable write data message credit locally, it consumes one write data message credit and sends write data carrying the write transaction identifier to the receiving agent of the first chip; wherein, the write request and the write data are sent independently and the sending order is not restricted. The receiving agent of the first chip performs content addressing comparison based on the write transaction identifier carried by the received write request to determine the write data with the same write transaction identifier as the received write request; performs content addressing comparison based on the write transaction identifier carried by the received write data to determine the write request with the same write transaction identifier as the received write data; the write request and write data with the same write transaction identifier are forwarded to the internal bus of the first chip for corresponding write transaction processing. In response to the release of a request processing tracker entry, the receiving agent of the first chip returns a write request message credit to the sending agent of the second chip; in response to the release of a write data tracker entry, it returns a write data message credit to the sending agent of the second chip. The sending agent of the second chip receives the credit repayment notification and increases the number of message credits held locally for the corresponding channel according to the credit repayment notification.

[0009] Fourthly, embodiments of this application provide a multi-chip interconnect system, including a first chip and a second chip, wherein the first chip and the second chip are connected via an inter-chip link; The first chip includes a receiving-side agent for executing the write transaction processing method for multi-chip interconnection as described in the first aspect; The second chip includes a send-side agent for performing a write transaction processing method for multi-chip interconnect as described in the second aspect; The first chip and the second chip are used in conjunction to implement the multi-chip interconnection write transaction processing method as described in the third aspect.

[0010] Fifthly, embodiments of this application provide an electronic device, including: a memory, a processor, and a communication interface; wherein, the memory stores a computer program, and when the computer program is executed by the processor, the processor is able to implement at least the multi-chip interconnect write transaction processing method as described in the first or second aspect.

[0011] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor of an electronic device, enables the processor to at least implement the multi-chip interconnect write transaction processing method as described in the first or second aspect.

[0012] In a seventh aspect, embodiments of this application provide a computer program product, including: a computer program or instructions that, when executed by a processor of an electronic device, enable the processor to at least implement the multi-chip interconnect write transaction processing method as described in the first or second aspect.

[0013] This application provides a write transaction processing method for multi-chip interconnection, which is executed by a receiving agent of a first chip and a sending agent of a second chip. First, the receiving agent of the first chip pre-allocates write request message credits and write data message credits to the sending agent of the second chip. The number of write request message credits equals the number of locally available request processing tracker entries on the first chip, and the number of write data message credits equals the number of locally available write data tracker entries on the first chip. The sending agent of the second chip assigns a unique write transaction identifier to each write transaction to be sent. When it determines that a locally available write request message credit exists, it consumes the credit and sends a write request carrying the write transaction identifier. When it determines that a locally available write data message credit exists, it consumes the credit and sends write data carrying the write transaction identifier. The write request and write data are sent independently, and the sending order is not restricted. After receiving a write request or write data, the receiving agent of the first chip performs content addressing comparison using the write transaction identifier as the key, determines write requests and write data with the same write transaction identifier, and forwards them to the internal bus of the first chip to complete the write transaction processing. Subsequently, the receiving agent of the first chip returns a write request message credit to the sending agent of the second chip in response to the release of the request processing tracker entry, and returns a write data message credit in response to the release of the write data tracker entry; the sending agent of the second chip receives the credit return notification and increases the number of message credits held locally for the corresponding channel accordingly.

[0014] In this scheme, the aforementioned credit pre-allocation mechanism replaces the per-transaction DBIDResp handshake mechanism in the standard CHI protocol, eliminating cross-chip round-trip latency in the write transaction processing path; write requests and write data are decoupled based on independent credits, releasing the scheduling freedom of the sending side; the receiving side achieves out-of-order matching of write requests and write data through content addressing comparison, without imposing sending order constraints at the link layer, thereby significantly reducing the processing latency of write transactions and improving the effective write bandwidth in multi-chip interconnection scenarios. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 An interactive flowchart of a write transaction processing method for multi-chip interconnection provided in an embodiment of this application; Figure 2 This application provides a schematic diagram of the transmission of write transaction processing for multi-chip interconnection. Figure 3 A matching diagram illustrating a write request arriving one clock cycle later than the write data, provided as an embodiment of this application; Figure 4 A matching diagram provided for an embodiment of this application when a write request arrives at least two clock cycles later than the write data; Figure 5 A schematic diagram illustrating the matching of write data and write request arriving simultaneously, provided as an embodiment of this application; Figure 6 A matching diagram provided for an embodiment of this application when write data arrives one clock cycle later than the write request; Figure 7 A matching diagram provided for an embodiment of this application when write data arrives at least two clock cycles later than the write request; Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] It should be noted that, in the cases involving user information in the embodiments of this application, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse. In addition, the various models involved in this application (including but not limited to language models or large models) comply with relevant laws and standards.

[0019] Furthermore, the timing of the steps in the following method embodiments is merely an example and not a strict limitation.

[0020] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0021] In this embodiment, the first chip and the second chip are connected via an inter-chip link to form a multi-chip interconnect system. The first chip acts as the receiver, and the second chip acts as the transmitter. Both the first and second chips deploy a receiver-side agent (HA) and a transmitter-side agent (RA) at the inter-chip interface. The HA is responsible for receiving requests and data from the peer chip, converting them into transactions according to its internal bus protocol, and forwarding them to the local memory subsystem for processing. The RA is responsible for converting its internal transactions into the inter-chip interface protocol and initiating requests to the peer HA. The HA and RA are deployed in pairs, together forming a complete protocol stack for the inter-chip interface.

[0022] Figure 1 An interactive flowchart of a write transaction processing method for multi-chip interconnection provided in this application embodiment is shown below. Figure 1 As shown, taking the receiving-side agent of the first chip and the transmitting-side agent of the second chip as examples, the write transaction processing method for multi-chip interconnection provided in this application embodiment may include the following steps: 101. The receiving agent of the first chip pre-allocates write request message credits and write data message credits to the sending agent of the second chip, wherein the number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip.

[0023] 102. The sending agent of the second chip assigns a unique write transaction identifier to the write transaction to be sent, and consumes a write request message credit when it determines that there is a usable write request message credit locally, and sends a write request carrying the write transaction identifier; when it determines that there is a usable write data message credit locally, it consumes a write data credit, and sends write data carrying the write transaction identifier; wherein, the write request and the write data are sent independently, and the sending order is not restricted.

[0024] 103. The receiving agent of the first chip performs content addressing comparison based on the write transaction identifier carried by the received write request to determine the write data with the same write transaction identifier as the received write request; performs content addressing comparison based on the write transaction identifier carried by the received write data to determine the write request with the same write transaction identifier as the received write data; wherein, the write request and write data with the same write transaction identifier are forwarded to the internal bus of the first chip for corresponding write transaction processing.

[0025] 104. The receiving agent of the first chip returns a write request message credit to the sending agent of the second chip in response to the release of the request processing tracker entry, and returns a write data message credit in response to the release of the write data tracker entry.

[0026] 105. The sending agent of the second chip receives the write request message credit return notification sent by the receiving agent of the first chip, and increases the number of write request message credits held locally according to the write request message credit return notification; it also receives the write data message credit return notification sent by the receiving agent of the first chip, and increases the number of write data message credits held locally according to the write data message credit return notification.

[0027] In practical applications, the DBIDResp mechanism in the standard CHI protocol write transaction process is the root cause of inter-chip write transaction delays. Its essence lies in the fact that the receiving side dynamically allocates write data buffer resources in a transaction-by-transaction handshake manner, and requires the sending side to wait for the handshake to be completed before sending write data. This forms a serialization bottleneck in inter-chip long-latency link scenarios.

[0028] To address at least one of the aforementioned technical problems, the design concept of the multi-chip interconnect write transaction processing scheme provided in this application is as follows: The write request message credits and write data message credits pre-allocated in batches during the initialization phase on the receiving side replace the per-transaction allocation of DBIDResp, allowing credit pre-allocation to replace the buffer flow control function carried by DBIDResp; the write transaction identifier statically allocated on the sending side replaces the dynamically allocated DBID on the receiving side, enabling write requests and write data to be associated and matched through the write transaction identifier; and the message credits of the write request channel and the write data channel are managed independently, completely decoupling the sending order of the two channels, that is, decoupling the write request and write data corresponding to the write transaction. Based on the above concept, this application embodiment supports the arrival of write requests and write data in any order through a bidirectional content addressing comparison mechanism on the receiving side, thereby eliminating cross-chip round-trip latency while releasing the scheduling freedom on the sending side.

[0029] To facilitate understanding of the above design concept of the embodiments of this application, a specific transmission example will be used for illustration below.

[0030] Figure 2 This is a schematic diagram illustrating the transmission of write transaction processing for a multi-chip interconnection embodiment of this application. For example... Figure 2 As shown, assume the RA side has three write transactions to send, with write transaction identifiers (Transaction IDs, or TxnIDs) of 0, 1, and 2 respectively. After the RA and HA complete initialization, the HA pre-allocates write request message credits and write data message credits to the RA. Since the write request channel and the write data channel each hold independent credits, the RA side can send the message as long as it has the corresponding channel's credit, without waiting for the other channel to be ready.

[0031] like Figure 2As shown, the packet assembler on the RA side schedules the data for two independent channels, causing write requests and write data to be sent to different channels, and their arrival order on the HA side differs—for example, write data with TxnID=1 arrives before write requests with TxnID=1, and write data with TxnID=2 arrives before write requests with TxnID=1. Upon receiving the write requests and write data, the HA side does not process them serially according to their arrival order. Instead, it uses the write transaction identifier as a key for content addressing comparison, pairing write requests with the same write transaction identifier with the write data. After matching, it forwards the data to the internal bus of the first chip for corresponding write transaction processing. Therefore, in this embodiment, the transmission of write requests and write data is completely independent, and the receiving side can complete the correct association without relying on the transmission order.

[0032] The above provides a general overview of the write transaction processing scheme for multi-chip interconnection provided in the embodiments of this application. Next, the specific implementation process of steps 101 to 106 will be described in detail.

[0033] 101. The receiving agent of the first chip pre-allocates write request message credits and write data message credits to the sending agent of the second chip, wherein the number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip.

[0034] In practical applications, the receiving-side agent of the first chip maintains a Request Handling Tracker (RHT) and a Write Data Tracker (WDT). The RHT records the request attributes and current processing status of each ongoing write transaction. Each entry in the RHT corresponds to a writing transaction in progress, and the number of RHT entries represents the upper limit of the number of write transactions the first chip can track simultaneously. The WDT temporarily stores the control field of the write data and its corresponding write data buffer index when write data arrives before the write request. The number of WDT entries represents the upper limit of the amount of first-arriving write data the first chip can temporarily store simultaneously. The WDT and the Write Data Buffer (WDB) have a one-to-one entry binding relationship and share entry allocation and release logic. The WDB stores the payload (DATA), data check (DATACHECK), and byte enable (BE) fields of the write data and is the buffer structure that actually stores the write data content.

[0035] During step 101, in the system initialization phase, the receiving agent of the first chip pre-allocates two types of message credits to the sending agent of the second chip through an initialization handshake process: one type is write request message credits, the number of which is equal to the number of RHT entries available locally on the first chip; the other type is write data message credits, the number of which is equal to the number of WDT entries available locally on the first chip. The sending agent of the second chip receives and records the available quantity of the above two types of credits, which serves as the basis for flow control when sending write requests and write data.

[0036] By binding the number of write request message credits to the number of RHT entries and the number of write data message credits to the number of WDT entries, it is ensured that the total amount of credits held by the sending agent of the second chip at any time will not exceed the actual receiving and processing capacity of the first chip, thus guaranteeing at the protocol level that the receiving buffer of the first chip will not overflow. Since the pre-allocation of credits is completed during the initialization phase, the sending agent of the second chip does not need to request buffer resources from the first chip through the per-transaction DBIDResp handshake mechanism when sending write requests and write data. It can directly decide whether to send based on the amount of credits held locally, fundamentally eliminating cross-chip round-trip latency.

[0037] 102. The sending agent of the second chip assigns a unique write transaction identifier to the write transaction to be sent, and consumes a write request message credit when it determines that there is a usable write request message credit locally, and sends a write request carrying the write transaction identifier; when it determines that there is a usable write data message credit locally, it consumes a write data credit, and sends write data carrying the write transaction identifier; wherein, the write request and the write data are sent independently, and the sending order is not restricted.

[0038] In step 102, the sending agent of the second chip assigns a unique write transaction identifier TxnID to the write transaction to be sent. This write transaction identifier is used to uniquely identify the write transaction within the scope of all incomplete transactions currently in the second chip.

[0039] Before sending the write request for the write transaction, the sending agent of the second chip first determines whether there is an available write request message credit locally. If so, it consumes one write request message credit and sends a write request carrying the write transaction identifier to the receiving agent of the first chip. The consumption of the write request message credit means that the RHT entry resource corresponding to the credit has been reserved. After the receiving agent of the first chip receives the write request subsequently, it will allocate an RHT entry for transaction tracking.

[0040] Similarly, before sending the write data for this write transaction, the sending agent of the second chip first determines whether there is an available write data message credit locally. If so, it consumes one write data message credit and sends the write data carrying the write transaction identifier to the receiving agent of the first chip. The consumption of the write data message credit means that the WDT / WDB entry resource corresponding to the credit has been reserved. After the receiving agent of the first chip receives the write data subsequently, it will allocate a WDB entry to store the data payload and, if necessary, allocate a WDT entry to temporarily store control information.

[0041] It should be noted that this solution does not require sending a write request before sending write data. In this embodiment, the sending of write requests and the sending of write data are independent of each other. In short, the sending-side agent of the second chip only needs to check the write request message credit when sending a write request, and only needs to check the write data message credit when sending write data. The checking and consumption of the two types of credit do not affect each other. Therefore, the sending order of write requests and write data is not constrained in any way: write data can be sent before write requests, and write requests can also be sent before write data, and the two can also be sent independently at the same time. This decoupling characteristic allows the packet assembler, arbitrator, and scheduling logic in the sending-side agent of the second chip to make independent scheduling decisions based on the respective states of the write request channel and the write data channel (such as link congestion, service quality priority, buffer occupancy, etc.), without maintaining cross-channel order dependencies.

[0042] Furthermore, the write transaction identifier corresponding to the write transaction is statically held by the sending agent of the second chip throughout the entire lifecycle of the write transaction and does not change with the progress of the transaction processing. The write transaction identifier is included in the message field of the write request, and the same write transaction identifier is also included in the message field of the write data. This write transaction identifier replaces the write data buffer number (DBID) dynamically allocated by the receiving side in the standard CHI protocol, serving as a unique association identifier for the receiving agent of the first chip to match write requests and write data. Since this identifier can be determined by the sending side when the transaction is initiated, without waiting for any response from the receiving side, write requests and write data can be independently encapsulated and sent under their respective credit-permitted conditions, without being constrained by the real-time allocation of identifiers by the receiving side.

[0043] 103. The receiving agent of the first chip performs content addressing comparison based on the write transaction identifier carried by the received write request to determine the write data with the same write transaction identifier as the received write request; performs content addressing comparison based on the write transaction identifier carried by the received write data to determine the write request with the same write transaction identifier as the received write data; wherein, the write request and write data with the same write transaction identifier are forwarded to the internal bus of the first chip for corresponding write transaction processing.

[0044] In summary, after the receiving agent of the first chip receives the write request or write data sent by the sending agent of the second chip, it performs content addressing comparison using the write transaction identifier as the key to determine the write data with the same write transaction identifier as the received write request, or the write request with the same write transaction identifier as the received write data.

[0045] In step 102, the sending agent of the second chip has sent the write request and write data independently. Since the sending order between the two is unrestricted, there may be several possible order scenarios when the write request and write data arrive at the receiving agent of the first chip: the write request arrives before the write data, the write data arrives before the write request, or the write request and write data arrive in the same clock cycle. To support any of these arrival orders, the receiving agent of the first chip is equipped with a Content-Addressable Memory (CAM) comparison circuit, which can perform parallel comparison of multiple memory entries in a single clock cycle using the write transaction identifier as the key.

[0046] In this embodiment, a "beat" (or "cycle") refers to one clock cycle. The receiver processing pipeline of the first chip's receiver-side agent comprises two stages: the first stage is the input latch stage (R1 stage), which registers the arriving write requests and write data respectively; the second stage is the decision and allocation stage (R2 stage), which determines the RHT allocation and attribute writing based on the CAM matching result. The write request channel and the write data channel flow through the pipeline independently without blocking each other. Under this pipeline architecture, the arrival time difference between the write request and the write data can be specifically quantified as an integer multiple of a "beat," thus corresponding to different matching paths.

[0047] Next, the two write request and write data matching processing schemes provided by the receiving-side agent of the first chip in the embodiments of this application will be described in detail.

[0048] When the receiving agent of the first chip receives a write request, it can optionally perform keyword matching on the following two types of write data, using the write transaction identifier carried in the received write request as the keyword: one type is write data that arrived in the previous cycle, i.e., write data that arrived one clock cycle earlier than the current write request and is still in the pipeline register; the other type is temporarily stored write data, i.e., write data that arrived before the previous cycle and has not yet been matched with a corresponding write request. The write data control information and the corresponding write data buffer index of the temporarily stored write data are temporarily stored in the write data tracker.

[0049] If the keyword match is successful, it means that the write data corresponding to the write request has arrived in advance. Then, the write data control information and write data buffer index corresponding to the matched write data are obtained, a request processing tracker entry is assigned to the received write request, and the write data control information and write data buffer index are written to the request processing tracker entry.

[0050] If the keyword match fails, it means that the write data corresponding to the write request has not yet arrived. In this case, a request processing tracker entry is assigned to the received write request, and the write data corresponding to the write request is marked as not having arrived in the request processing tracker entry (for example, the RCVDWDAT flag is set to invalid). The request processing tracker entry then waits for the corresponding write data to arrive before being filled with data information.

[0051] In practice, the keyword matching process when a write request arrives can be divided into two parallel content addressing comparisons: In the first path, the write transaction identifier carried by the received write request is compared with the write transaction identifier carried by the write data received in the previous cycle. If they match, it means the write data arrived one cycle earlier than the write request, and the write data is still in the pipeline register (R2 stage) and has not yet been written to the write data tracker. At this time, the receiver-side agent of the first chip can directly read the write data control information and the corresponding write data buffer index of the write data from the current pipeline register without accessing the write data tracker, thus realizing pipeline bypass reading, such as... Figure 3 As shown. Figure 3 This application provides a matching diagram for a write request arriving one clock cycle later than the write data, as shown in the embodiments of this application. Figure 3 In the scenario shown, the write data is located in the R2 stage pipeline register, and the write request is located in the R1 stage; the two are directly matched through a bypass.

[0052] The second step involves comparing the write transaction identifier carried in the received write request with the write transaction identifiers stored in all valid write data tracker entries. If a target write data tracker entry exists that matches the write transaction identifier carried in the received write request, it indicates that the write data arrived at least two clock cycles earlier than the write request, and the write data has been stored in the write data buffer. Its control information and the corresponding write data buffer index have been temporarily stored in the write data tracker. At this point, the receiving agent reads the temporarily stored write data control information and the corresponding WDB index from the target write data tracker entry, such as... Figure 4 As shown. Figure 4 This application provides a matching diagram illustrating a write request arriving at least two clock cycles after the write data. Figure 4 As shown, in this case, the write data has been temporarily stored in the write data tracker. When a write request arrives, the write data tracker is queried through CAM to complete the matching.

[0053] The two comparisons described above are completed in parallel within the same clock cycle, without the need for serial waiting.

[0054] Optionally, the keyword matching process upon the arrival of a write request can be supplemented with an additional step: comparing the write transaction identifier carried in the received write request with the write transaction identifier carried in the write data received in the current cycle. If they match, it indicates that the write request and the write data arrived in the same cycle, both at level R1. At this point, the receiving agent of the first chip directly assigns a request processing tracker entry to the write request received in the current cycle and writes the write data control information and the corresponding write data buffer index of the write data in the current cycle into the request processing tracker entry.

[0055] With the above scheme, write requests can be matched within a single cycle, regardless of whether they arrive in the same cycle as the write data, arrive one cycle later, or arrive at least two cycles later.

[0056] Next, we will elaborate on the matching process when write data arrives.

[0057] When the receiving agent of the first chip receives write data, it uses the write transaction identifier carried by the received write data as the key to perform keyword matching on the following three types of write requests: the first type is the write request that arrives in the current cycle, that is, the write request that arrives at R1 level in the same clock cycle as the write data; the second type is the write request that arrives in the previous cycle, that is, the write request that arrives one clock cycle earlier than the write data and is still in the pipeline register; the third type is the allocated write request, that is, the write request that arrives two cycles or more in advance and has been allocated a request processing tracker entry in the above write request matching process.

[0058] If a keyword match is successful, it indicates that the write request corresponding to the write data has arrived (it may have arrived in the same period, one clock cycle earlier, or even earlier and is already in the RHT). The received write data is then stored in the write data buffer, the corresponding write data buffer index is obtained, and the write data control information and write data buffer index are written into the request processing tracker entry corresponding to the matched write request. At this point, the write request attributes and write data control information in the request processing tracker entry are complete, and the write transaction is ready to be forwarded to the first chip's internal bus.

[0059] If the keyword match fails, it means that the corresponding write request has not yet arrived. The received write data is then stored in the write data buffer, and the write data control information and the corresponding write data buffer index are temporarily stored in the write data tracker, waiting for the corresponding write request to arrive later to claim it through the above-mentioned write request side matching process.

[0060] In practice, the keyword matching process when write data arrives can be divided into three parallel content addressing comparisons: The first step involves comparing the write transaction identifier carried by the received write data with the write transaction identifier carried by the write request received in the current cycle. If they match, it is determined that the received write data and the write request received in the current cycle have successfully matched. A request processing tracker entry is then assigned to the write request received in the current cycle, and the write data control information and the corresponding write data buffer index are written to that request processing tracker entry. Figure 5 As shown. Figure 5 This application provides a schematic diagram illustrating the matching of write data and write requests arriving simultaneously, as shown in the embodiments of this application. Figure 5 In the scenario shown, both the write request and the write data are at level R1, and they are matched in the same timeframe.

[0061] The second step involves comparing the write transaction identifier carried in the received write data with the write transaction identifier carried in the write request received in the previous cycle. If they match, it is determined that the received write data and the write request received in the previous cycle have successfully matched. At this time, the write request is still in the R2-level pipeline register. The receiving agent directly obtains the allocation result of the request processing tracker corresponding to the write request, and writes the write data control information and the corresponding write data buffer index into the corresponding request processing tracker entry, such as... Figure 6 As shown. Figure 6 This application provides a matching diagram for when write data arrives one clock cycle later than the write request, as shown in the embodiments of this application. Figure 6 In the scenario shown, the write request is located in the R2 stage pipeline register, and the write data is located in the R1 stage; the two are matched via a bypass.

[0062] The third step involves comparing the write transaction identifier carried in the received write data with the write transaction identifiers stored in all allocated request processing tracker entries. If a target request processing tracker entry exists that matches the write transaction identifier carried in the received write data, it is determined that the received write data successfully matches the write request corresponding to that target request processing tracker entry. The receiving agent then writes the write data control information and the corresponding write data buffer index of the write data into that target request processing tracker entry. Figure 7 As shown. Figure 7 This application provides a matching diagram illustrating a scenario where write data arrives at least two clock cycles later than the write request. Figure 7 In the scenario shown, the write request has been assigned a request processing tracker entry, and after the write data arrives, the CAM query is used to complete the matching of the request processing tracker.

[0063] The three comparisons mentioned above are completed in parallel within the same clock cycle, without the need for serial waiting.

[0064] Once the write request attributes and write data control information of a write transaction have been written to the same request processing tracker entry, the information in that request processing tracker entry is complete. The receiving agent of the first chip reads the corresponding data payload from the write data buffer based on the request attributes (such as target address, data length, quality of service requirements, etc.) and the write data buffer index recorded in the request processing tracker entry, assembles the data payload, and forwards it to the internal bus of the first chip. The local memory subsystem then completes the final write transaction processing.

[0065] 104. The receiving agent of the first chip returns a write request message credit to the sending agent of the second chip in response to the release of the request processing tracker entry, and returns a write data message credit in response to the release of the write data tracker entry.

[0066] 105. The sending agent of the second chip receives the write request message credit return notification sent by the receiving agent of the first chip, and increases the number of write request message credits held locally according to the write request message credit return notification; it also receives the write data message credit return notification sent by the receiving agent of the first chip, and increases the number of write data message credits held locally according to the write data message credit return notification.

[0067] In this embodiment, after the receiving agent of the first chip completes the forwarding processing of the write request or write data, it returns the message credit of the corresponding channel to the sending agent of the second chip; the sending agent of the second chip receives the credit return notification and updates the amount of credit held locally accordingly.

[0068] Specifically, when the write transaction corresponding to an RHT entry in the receiving agent of the first chip is completed—that is, when the write request attributes and write data control information of the write transaction are complete, and the write transaction has been successfully forwarded to the internal bus of the first chip and a completion response has been received—the RHT entry is released. The release of the RHT entry means that the tracking resources occupied by the write transaction in the receiving agent of the first chip have been reclaimed and can be used to track new write transactions. In response to the release of the RHT entry, the receiving agent of the first chip sends a write request message credit return notification to the sending agent of the second chip, returning one write request message credit.

[0069] After receiving the write request message credit return notification, the sending agent of the second chip increases the number of write request message credits held locally by one.

[0070] Similarly, once the data payload stored in a WDB entry in the receiving agent of the first chip has been read and forwarded to the internal bus of the first chip, the WDB entry is released, and the WDT entry corresponding to that WDB entry is released synchronously. The release of the WDB entry means that the data storage resources occupied by the written data in the receiving agent of the first chip have been reclaimed and can be used to store new written data. In response to the release of the WDT entry, the receiving agent of the first chip sends a write data message credit return notification to the sending agent of the second chip, returning one write data message credit.

[0071] After receiving the write data message credit return notification, the sending agent of the second chip increases the number of write data message credits held locally by one.

[0072] It's important to note that the return of write request message credits and write data message credits are independent of each other. The release of RHT entries triggers the return of write request message credits, while the release of WDT entries triggers the return of write data message credits. Their release conditions differ—RHT entries must wait for the write transaction to complete before being released, while WDT entries are released after the data payload is read and forwarded to the internal bus, with their bound WDT entries released synchronously. Therefore, the return of these two types of credits does not affect or block each other. Through this credit return mechanism, the pre-allocation, consumption, and return of credits form a complete closed loop, ensuring that the number of credits held by the sending agent of the second chip at any given time always accurately reflects the current available resource capacity of the receiving agent of the first chip, thus ensuring the continuous and effective operation of the flow control mechanism throughout the entire write transaction processing flow.

[0073] In summary, the multi-chip interconnected write transaction processing method provided in this application pre-allocates write request message credits and write data message credits to the sending agent of the second chip during the initialization phase through the receiving agent of the first chip. The number of credits is bound to the number of request processing tracker entries and the number of write data tracker entries, respectively. This credit pre-allocation mechanism replaces the per-transaction DBIDResp handshake mechanism in the standard CHI protocol, eliminating cross-chip round-trip latency in the write transaction processing path. The sending agent of the second chip assigns a unique write transaction identifier to each write transaction and independently sends write requests and write data based on the availability of write request message credits and write data message credits, ensuring that the sending order of write requests and write data is not affected by the transaction's status. The constraints free up optimization space for the sending-side packet assembler, arbitrator, and scheduling logic. Upon receiving a write request or write data, the receiving-side agent of the first chip performs multi-path parallel content addressing comparison using the write transaction identifier as the key. This enables single-cycle matching in various out-of-order arrival scenarios, including simultaneous arrival of write requests and write data, arrivals one beat earlier, and arrivals at least two beats later. Combined with the one-to-one binding relationship between WDT and WDB and the shared entry allocation and release logic, it supports arbitrary arrival order with low hardware overhead. Subsequently, the receiving-side agent releases and returns write request message credits in response to RHT entries and write data message credits in response to WDT entries. The sending-side agent receives credit return notifications and updates its local credit count, forming a complete credit closed loop. Through the above scheme, this application eliminates the cross-chip round-trip latency introduced by DBIDResp in standard CHI write transactions in multi-chip interconnection scenarios, reduces the average processing latency of write transactions, improves effective write bandwidth, and maintains compatibility with the standard CHI protocol and the reusability of standard ecosystem resources.

[0074] In an optional embodiment, this application also provides a write transaction processing method for multi-chip interconnection, applied to a receiving-side proxy of a first chip, wherein the first chip is connected to a second chip via an inter-chip link, comprising: Write request message credits and write data message credits are allocated to the sending-side agent of the second chip. The number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip. The second chip's sending agent sends a write request when it determines that a write request message credit exists locally, or sends write data when it determines that a write data message credit exists locally; the second chip's sending agent consumes one write request message credit for each write request sent, and consumes one write data message credit for each write data sent. Content addressing is compared based on the write transaction identifier carried by the received write request to determine the write data with the same write transaction identifier as the received write request; content addressing is compared based on the write transaction identifier carried by the received write data to determine the write request with the same write transaction identifier as the received write data; wherein, the write request and write data with the same write transaction identifier are forwarded to the internal bus of the first chip for corresponding write transaction processing. In response to the release of the request processing tracker entry of the first chip, a write request message credit is returned to the sending-side agent of the second chip; in response to the release of the write data tracker entry of the first chip, a write data message credit is returned to the sending-side agent of the second chip.

[0075] This application also provides a write transaction processing method for multi-chip interconnection, applied to the sending-side proxy of a second chip, wherein the second chip is connected to the first chip via an inter-chip link, including: The first chip receives write request message credits and write data message credits allocated by the receiving-side agent. The number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip. Assign a write transaction identifier to the write transaction to be sent. The write transaction identifier is used to uniquely identify the write transaction. If it is determined that a write request message credit is available locally, one write request message credit is consumed and a write request carrying a write transaction identifier is sent to the receiving agent of the first chip. If it is determined that a write data message credit is available locally, one write data message credit is consumed and write data carrying the write transaction identifier is sent to the receiving agent of the first chip. The write request and the write data are sent independently and in no particular order. The receiving agent of the first chip performs association matching through the write transaction identifier after receiving the write request and the write data.

[0076] In an optional embodiment, this application also provides a write transaction processing method for multi-chip interconnect, applied to a multi-chip interconnect system including a first chip and a second chip, wherein the first chip and the second chip are connected via an inter-chip link, including: The receiving agent of the first chip allocates write request message credits and write data message credits to the sending agent of the second chip. The number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip. The sending-side agent of the second chip assigns a write transaction identifier to the write transaction to be sent. The write transaction identifier is used to uniquely identify the write transaction. When the sending agent of the second chip determines that there is a usable write request message credit locally, it consumes one write request message credit and sends a write request carrying a write transaction identifier to the receiving agent of the first chip; when it determines that there is a usable write data message credit locally, it consumes one write data message credit and sends write data carrying a write transaction identifier to the receiving agent of the first chip; wherein, the write request and the write data are sent independently and the sending order is not restricted. The receiving agent of the first chip performs content addressing comparison based on the write transaction identifier carried by the received write request to determine the write data with the same write transaction identifier as the received write request; performs content addressing comparison based on the write transaction identifier carried by the received write data to determine the write request with the same write transaction identifier as the received write data; the write request and write data with the same write transaction identifier are forwarded to the internal bus of the first chip for corresponding write transaction processing. In response to the release of the request processing tracker entry, the receiving agent of the first chip returns a write request message credit to the sending agent of the second chip; in response to the release of the write data tracker entry, it returns a write data message credit to the sending agent of the second chip. The sending agent of the second chip receives the credit return notification and increases the number of message credits held locally for the corresponding channel according to the credit return notification.

[0077] In an optional embodiment, this application also provides a multi-chip interconnect system, characterized in that it includes a first chip and a second chip, the first chip and the second chip being connected via an inter-chip link; The first chip includes a receiving-side agent for executing the multi-chip interconnect write transaction processing method executed by the receiving-side agent of the first chip. The second chip includes a sending-side agent for executing the multi-chip interconnect write transaction processing method executed by the sending-side agent of the second chip. The first chip and the second chip are used together to implement a write transaction processing method for a multi-chip interconnect system that includes the first chip and the second chip.

[0078] The specific implementation process can be referred to the aforementioned process, and will not be repeated in this embodiment.

[0079] The following describes in detail one or more embodiments of the multi-chip interconnect write transaction processing apparatus of this application. Those skilled in the art will understand that these apparatuses can be configured using commercially available hardware components through the steps taught in this solution.

[0080] In one possible design, embodiments of this application also provide an electronic device, such as... Figure 8As shown, the electronic device may include: a memory 11, a processor 12, and a communication interface 13. The memory 11 stores a computer program, which, when executed by the processor 12, enables the processor 12 to at least implement the multi-chip interconnect write transaction processing method provided in the foregoing embodiments.

[0081] The aforementioned memory 11 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random-Access Memory (SRAM), Electrically Erasable Programmable Read Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0082] Accordingly, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, enables the processor to implement the steps in the above-described method embodiments. The computer-readable storage medium includes volatile or non-volatile components, or a combination thereof, and can be removable or non-removable. Examples of computer-readable storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), flash memory or other memory technologies, CD-ROM, Digital Video Disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium.

[0083] Accordingly, this application also provides a computer program product, which includes a computer program or instructions that, when executed by a processor, cause the processor to implement the steps in the above method embodiments. It should be understood that each step or combination of steps in the above method flow can be implemented by the computer program or instructions. Furthermore, these computer programs or instructions can be applied to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable multi-chip interconnected write transaction processing device, enabling the processor of such a device to function as an apparatus for implementing the corresponding functions in the above method embodiments.

[0084] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0085] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of a necessary general-purpose hardware platform, or by a combination of hardware and software. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a computer product. This application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0086] Finally, it should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0087] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A write transaction processing method for multi-chip interconnection, characterized in that, A receiver-side proxy applied to a first chip, which is connected to a second chip via an inter-chip link, includes: Write request message credits and write data message credits are allocated to the sending-side agent of the second chip. The number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip. The second chip's sending test agent receives a write request sent when it determines that a local write request message credit exists, or write data sent when it determines that a local write data message credit exists; the second chip's sending test agent consumes one write request message credit for each write request sent, and consumes one write data message credit for each write data sent. Content addressing comparison is performed based on the write transaction identifier carried by the received write request to determine the write data with the same write transaction identifier as the received write request; content addressing comparison is performed based on the write transaction identifier carried by the received write data to determine the write request with the same write transaction identifier as the received write data; wherein, the write request and write data with the same write transaction identifier are forwarded to the internal bus of the first chip for corresponding write transaction processing. In response to the release of the request processing tracker entry of the first chip, a write request message credit is returned to the sending-side agent of the second chip; in response to the release of the write data tracker entry of the first chip, a write data message credit is returned to the sending-side agent of the second chip.

2. The method according to claim 1, characterized in that, The step of performing content addressing comparison based on the write transaction identifier carried in the received write request to determine the write data with the same write transaction identifier as the received write request includes: Using the write transaction identifier carried by the received write request as the key, the write data that arrived in the previous cycle and the temporarily stored write data are matched by the key; the temporarily stored write data is the write data that arrived before the previous cycle and did not match the corresponding write request. The write data control information of the temporarily stored write data and the corresponding write data buffer index are temporarily stored in the write data tracker. If the keyword match is successful, the write data control information and write data buffer index corresponding to the matched write data are obtained, a request processing tracker entry is assigned to the received write request, and the write data control information and the write data buffer index are written into the request processing tracker entry. If the keyword match fails, a request processing tracker entry is assigned to the received write request, and the write data corresponding to the write request is marked as not yet arrived.

3. The method according to claim 2, characterized in that, Using the write transaction identifier carried in the received write request as the key, perform key matching on the write data that arrived in the previous cycle and the write data that has been temporarily stored, including: The write transaction identifier carried by the received write request is compared with the write transaction identifier carried by the write data received in the previous cycle; if they match, the write data control information and the corresponding write data buffer index of the write data received in the previous cycle are directly read from the current pipeline register. The write transaction identifier carried by the received write request is compared with the write transaction identifier stored in the valid write data tracker entry; if there is a target write data tracker entry that matches the write transaction identifier carried by the received write request, the temporarily stored write data control information and the corresponding write data buffer index are read from the write data tracker entry.

4. The method according to claim 1, characterized in that, The step of performing content addressing comparison based on the write transaction identifier carried in the received write data to determine the write request with the same write transaction identifier as the received write data includes: Using the write transaction identifier carried by the received write data as the key, perform keyword matching on the request processing tracker entries of the write requests that arrive in the current period, the write requests that arrive in the previous period, and the allocated write requests. If the keyword match is successful, the received write data is stored in the write data buffer, the corresponding write data buffer index is obtained, and the write data control information of the received write data and the write data buffer index are written into the request processing tracker entry corresponding to the matched write request. If the keyword match fails, the received write data is stored in the write data buffer, and the write data control information of the received write data and the corresponding write data buffer index are temporarily stored in the write data tracker.

5. The method according to claim 4, characterized in that, The step of matching the write transaction identifier carried in the received write data with the key to the request processing tracker entries of write requests arriving in the current period, write requests arriving in the previous period, and allocated write requests includes: The write transaction identifier carried by the received write data is compared with the write transaction identifier carried by the write request received in the current period; if they match, it is determined that the received write data and the write request received in the current period are successfully matched, and a request processing tracker entry is assigned to the write request received in the current period. The write transaction identifier carried in the received write data is compared with the write transaction identifier carried in the write request received in the previous cycle; if they match, it is determined that the received write data and the write request received in the previous cycle have been successfully matched. The write transaction identifier carried by the received write data is compared with the write transaction identifier stored in the allocated request processing tracker entry; if there is a target request processing tracker entry that matches the write transaction identifier carried by the received write request, it is determined that the received write data and the write request corresponding to the target request processing tracker entry are successfully matched.

6. The method according to any one of claims 1 to 5, characterized in that, There is a one-to-one entry binding relationship between the write data tracker and the write data buffer, and they share the same entry allocation and release logic.

7. A write transaction processing method for multi-chip interconnection, characterized in that, A transmitting-side proxy applied to a second chip, which is connected to the first chip via an inter-chip link, includes: The first chip receives write request message credits and write data message credits allocated by the receiving-side agent. The number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip. Assign a write transaction identifier to the write transaction to be sent, the write transaction identifier being used to uniquely identify the write transaction; If it is determined that a write request message credit is available locally, then one write request message credit is consumed and a write request carrying the write transaction identifier is sent to the receiving agent of the first chip. If it is determined that a write data message credit is available locally, one write data message credit is consumed and write data carrying the write transaction identifier is sent to the receiving agent of the first chip. The write request and the write data are sent independently and in no particular order. The receiving agent of the first chip performs association matching through the write transaction identifier after receiving the write request and the write data.

8. The method according to claim 7, characterized in that, The method further includes: Receive the write request message credit return notification sent by the receiving agent of the first chip when the request processing tracker entry of the first chip is released; Increase the number of write request message credits held locally according to the write request message credit return notification; Receive the write data message credit return notification sent by the receiving-side agent of the first chip when the write data tracker entry of the first chip is released; The number of locally held write data message credits is increased according to the write data message credit return notification.

9. A write transaction processing method for multi-chip interconnection, characterized in that, An application to a multi-chip interconnect system comprising a first chip and a second chip, wherein the first chip and the second chip are connected via an inter-chip link, comprising: The receiving agent of the first chip allocates write request message credits and write data message credits to the sending agent of the second chip. The number of write request message credits is equal to the number of request processing tracker entries available locally on the first chip, and the number of write data message credits is equal to the number of write data tracker entries available locally on the first chip. The sending-side agent of the second chip assigns a write transaction identifier to the write transaction to be sent, and the write transaction identifier is used to uniquely identify the write transaction; When the sending agent of the second chip determines that there is a usable write request message credit locally, it consumes one write request message credit and sends a write request carrying the write transaction identifier to the receiving agent of the first chip; when it determines that there is a usable write data message credit locally, it consumes one write data message credit and sends write data carrying the write transaction identifier to the receiving agent of the first chip; wherein, the write request and the write data are sent independently and the sending order is not restricted. The receiving agent of the first chip performs content addressing comparison based on the write transaction identifier carried by the received write request to determine the write data with the same write transaction identifier as the received write request; performs content addressing comparison based on the write transaction identifier carried by the received write data to determine the write request with the same write transaction identifier as the received write data; the write request and write data with the same write transaction identifier are forwarded to the internal bus of the first chip for corresponding write transaction processing. In response to the release of a request processing tracker entry, the receiving agent of the first chip returns a write request message credit to the sending agent of the second chip; in response to the release of a write data tracker entry, it returns a write data message credit to the sending agent of the second chip. The sending agent of the second chip receives the credit repayment notification and increases the number of message credits held locally for the corresponding channel according to the credit repayment notification.

10. A multi-chip interconnect system, characterized in that, It includes a first chip and a second chip, which are connected to each other via an inter-chip link; The first chip includes a receiving-side agent for performing the method as described in any one of claims 1 to 6; The second chip includes a transmitting-side agent for performing the method as described in any one of claims 7 to 8; The first chip and the second chip are used in conjunction to implement the method as described in claim 9.

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