A multi-interface data real-time acquisition and storage system based on a PCIe bus

Abstract

The application discloses a kind of multi-interface data real-time acquisition and storage system based on PCIe bus, it is related to data acquisition technical field, including: control module, running record control software and management data storage;High-speed optical signal acquisition module, parallel data stream is written into first dynamic random access memory cache;Low-speed differential signal acquisition module, generate standardized data frame;Data convergence and bus transmission module, read the data in first dynamic random access memory and are encapsulated as bus transmission data packet according to channel number;Disk array storage module, extract bus transmission data packet from system memory and shunt write in disk array according to interface type and channel number;Instruction analysis and channel configuration module, configure the acquisition enable state, transmission rate and trigger condition of corresponding channel;The application improves the data transmission bandwidth when multiple types of signals are collected in parallel, real-time disk persistence and channel configuration flexibility.

Description

Technical Field

[0001] This invention relates to the field of data acquisition technology, and more specifically to a multi-interface real-time data acquisition and storage system based on the PCIe bus. Background Technology

[0002] With the rapid development of aerospace, radar detection, electronic warfare, and high-speed communication, test and measurement systems need to simultaneously acquire multiple types and rates of external signals, and perform high-bandwidth, low-latency real-time storage and offline playback analysis of the acquired data. In typical application scenarios, the device under test often simultaneously outputs multiple heterogeneous interface signals such as high-speed fiber optic serial signals, differential serial communication signals, low-voltage differential signals, and controller area network bus messages, requiring the acquisition system to have the ability to access multiple interfaces in parallel, unify protocol parsing, and write large-capacity data to disk. Existing data acquisition systems typically adopt the following solutions: First, design dedicated acquisition boards for a single interface type, with each interface corresponding to independent hardware. Firstly, when the platform and host computer software collaboratively acquire data across multiple interfaces, multiple boards and software sets are required, resulting in high system complexity, poor synchronization, and high cost. Secondly, using a general-purpose data acquisition card with an external protocol converter box to convert various signals into standard interfaces before connecting them to the acquisition card introduces additional latency, making it difficult to meet the real-time requirements of high-speed fiber optic signals. Furthermore, the converter box has a limited number of channels and insufficient scalability. Thirdly, although some systems use field-programmable gate array chips to achieve parallel acquisition across multiple interfaces, the data is transmitted to the host computer via a low-speed bus or a universal serial bus, making bus bandwidth a bottleneck. When high-speed optical signals and multiple low-speed signals are acquired simultaneously at full load, data frame loss or transmission blockage occurs.

[0003] Regarding data storage, existing solutions mostly use a single solid-state drive (SSD) or hard disk drive (HDD) for sequential writing. When multiple channels of data are written to the disk simultaneously, the write bandwidth of a single storage medium is insufficient to support a continuous high-speed data stream, leading to write interruptions or data overwriting. Furthermore, existing systems lack flexibility in channel configuration. Parameters such as acquisition rate, trigger conditions, and channel enable often need to be fixed during the hardware design phase and cannot be dynamically adjusted via software during operation, limiting the system's adaptability to different testing scenarios. In terms of data playback and retrieval, most systems only support simple sequential file reading, lacking the ability to search frame-by-frame based on trigger conditions and display waveform overlays, which is inconvenient for post-event data analysis and fault location.

[0004] Therefore, there is an urgent need for a multi-interface real-time data acquisition and storage system that can simultaneously access high-speed fiber optic signals and multiple low-speed heterogeneous interface signals, achieve high-bandwidth data transfer through a high-speed serial bus, support continuous writing to disk arrays, and has flexible channel configuration and offline playback capabilities. Summary of the Invention

[0005] To address the aforementioned technical problems, a multi-interface real-time data acquisition and storage system based on the PCIe bus is provided. This technical solution solves the problems mentioned above.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A multi-interface real-time data acquisition and storage system based on PCIe bus includes:

[0008] The control module, with its built-in central processing unit and system memory, is used to run the recording control software and manage data storage;

[0009] The high-speed optical signal acquisition module includes a first field-programmable gate array chip and a first dynamic random access memory, which is used to receive high-speed optical signals from an external optical fiber link and perform photoelectric conversion and serial deserialization processing to generate a parallel data stream, and write the parallel data stream into the first dynamic random access memory buffer.

[0010] The low-speed differential signal acquisition module includes a second field-programmable gate array chip and a second dynamic random access memory, which is used to receive multiple external low-speed signals and perform protocol parsing to generate standardized data frames, and forward the standardized data frames to the high-speed optical signal acquisition module via a high-speed serial link between boards.

[0011] The data aggregation and bus transmission module has a built-in direct memory access controller, which is used to read data from the first dynamic random access memory and encapsulate it into bus transmission data packets according to the channel number, and then transport it to the system memory through the direct memory access controller.

[0012] The disk array storage module is used to extract bus transmission data packets from system memory and write them to the disk array according to interface type and channel number.

[0013] The instruction parsing and channel configuration module is used to receive control instructions issued by the control module through the bus base address register space, and to configure the acquisition enable status, transmission rate and trigger conditions of the corresponding channel.

[0014] Furthermore, it receives high-speed optical signals from an external fiber optic link and performs photoelectric conversion and serial-to-deserialization processing to generate a parallel data stream, including:

[0015] The first high-speed optical signal input from the external fiber optic link is received through a four-channel small pluggable optical module.

[0016] The second high-speed optical signal input from an external fiber optic link is received via a micro-socket type optical module;

[0017] The first high-speed optical signal and the second high-speed optical signal are respectively converted into electrical signals by photoelectric conversion.

[0018] The electrical signal is input into the serial deserializer circuit module of the first field-programmable gate array chip to perform serial-to-parallel conversion;

[0019] Perform 8-bit and 10-bit decoding and word alignment operations on the serial-to-parallel converted data to generate a parallel data stream.

[0020] Furthermore, it receives multiple external low-speed signals and performs protocol parsing to generate standardized data frames, including:

[0021] The differential signal input from the external differential serial communication interface is received through the differential serial communication receiving chip; level decision and start bit detection are performed on the differential signal to extract valid data bytes;

[0022] The differential pair signal input from the external low-voltage differential signal interface is received by the low-voltage differential signal receiving chip; clock data recovery processing is performed on the differential pair signal to extract the serial bit stream; and serial-to-parallel conversion is performed on the serial bit stream to generate parallel data words.

[0023] The system receives bus messages from the external Controller Area Network (CAN) interface via the CAN transceiver chip; performs identifier filtering and cyclic redundancy check on the bus messages; and extracts the data field bytes that pass the check.

[0024] A standardized data frame is generated by uniformly adding timestamps and channel numbers to the valid data bytes, parallel data words, and data field bytes.

[0025] Furthermore, the standardized data frames are forwarded to the high-speed optical signal acquisition module via a high-speed inter-board serial link, including:

[0026] Multiple standardized data frames are spliced ​​and assembled according to a preset frame length to generate an aggregated data packet;

[0027] Write the source board identifier and frame count value in the frame header of the aggregated data packet;

[0028] The aggregated data packet is written to the second dynamic random access memory for temporary buffering;

[0029] Aggregated data packets are transmitted from the second field-programmable gate array chip to the first field-programmable gate array chip via a high-speed serial link between boards.

[0030] After receiving the aggregated data packet, the first field-programmable gate array chip strips the frame header and merges the standardized data frame with the parallel data stream into the first dynamic random access memory.

[0031] Furthermore, the data is moved to system memory via the direct memory access controller, including:

[0032] The first field-programmable gate array chip sends a write address channel request to the direct memory access controller, carrying the target memory start address and transmission length;

[0033] The direct memory access controller writes bus transmission data packets from the internal buffer memory of the first field-programmable gate array chip to the system memory clock cycle by clock cycle through the write data channel;

[0034] After the system memory completes data reception, it returns a write completion acknowledgment signal through the write response channel.

[0035] The direct memory access controller sends an interrupt signal to the central processing unit after all data has been transferred.

[0036] The central processing unit responds to the interrupt signal, confirms the completion of the data transfer, and updates the transfer status register.

[0037] Furthermore, the data is written to the disk array in a split-processing manner based on interface type and channel number, including:

[0038] Read the interface type identifier and channel number fields from the header of the bus transmission data packet;

[0039] The interface type identifier determines the interface category to which the current data packet belongs;

[0040] In response to the interface category being low-speed differential signal, all channel data of the same group of signals are written to the same storage file;

[0041] In response to whether the interface type is fiber optic signal or serializer signal, the data of each channel is written independently to the corresponding storage file.

[0042] Data is appended to the end of the corresponding storage file in the disk array in binary format.

[0043] Furthermore, configure the acquisition enable status, transmission rate, and trigger conditions for the corresponding channel, including:

[0044] Read the instruction word written by the control module from the bus base address register space;

[0045] The instruction word is split into fields to extract the operation code, data type identifier, target channel number, and configuration parameters;

[0046] The current instruction is determined to be a channel enable instruction, a rate configuration instruction, or a trigger condition setting instruction based on the opcode.

[0047] In response to the channel enable command, the acquisition enable register corresponding to the target channel number is set to the valid state;

[0048] In response to the rate configuration command, the configuration parameters are written to the transmission rate divider register or clock divider register of the target channel;

[0049] In response to the trigger condition setting command, the configuration parameters are written to the trigger level register and trigger edge selection register of the target channel.

[0050] Furthermore, before performing photoelectric conversion and serial-to-deserialization processing on the high-speed optical signal, the following steps are also included:

[0051] A first reference clock signal is generated by an onboard crystal oscillator and input into the global clock network of the first field-programmable gate array chip as a logic working clock.

[0052] A second reference clock signal is generated by an onboard crystal oscillator and input to the reference clock input port of the serializer / deserializer circuit module.

[0053] A serial transmission rate clock is generated by multiplying and dividing the second reference clock signal using a phase-locked loop chip.

[0054] The serial transmission rate clock is fed back to the transmitter and receiver of the serial deserializer circuit module to complete clock locking.

[0055] Furthermore, after writing the storage file to the disk array, the process also includes:

[0056] Receive offline playback instructions from the control module; the offline playback instructions carry the target file path and playback rate parameters.

[0057] Read the corresponding storage file from the disk array based on the target file path;

[0058] The data reading rhythm is controlled according to the playback rate parameter, and the data is sent to the waveform drawing module frame by frame.

[0059] In the waveform display window, plot the waveform curves of each signal with the time axis on the horizontal axis and the signal amplitude on the vertical axis;

[0060] In response to user-defined trigger search conditions, a frame-by-frame matching scan is performed in the stored file; data frames that meet the trigger conditions are located and marked for display in the waveform display window.

[0061] Furthermore, after the direct memory access controller triggers an interrupt signal to the central processing unit, it also includes:

[0062] After responding to the interrupt signal, the central processing unit reads the status register of the direct memory access controller;

[0063] Extract the actual number of bytes transmitted and the error flag from the status register;

[0064] In response to the error flag being in an abnormal state, a new direct memory access write request is initiated to retransmit the data segment that was not successfully transmitted.

[0065] In response to the error flag being in a normal state, the actual number of bytes is incremented into the global transfer counter;

[0066] Determine if the global transfer counter has reached the preset storage fragmentation threshold; in response to reaching the storage fragmentation threshold, close the current storage file and create a new storage file to continue writing.

[0067] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0068] 1. This invention, through the collaborative design of a high-speed optical signal acquisition module and a low-speed differential signal acquisition module, enables the simultaneous access of multiple heterogeneous interface signals within the same system, including fiber optic serial signals, differential serial communication signals, low-voltage differential signals, and controller area network bus messages. This eliminates the need for separate acquisition platforms and host computer software for each interface, significantly reducing the number of system hardware components, connection complexity, and overall cost. The low-speed differential signal acquisition module forwards the parsed standardized data frames to the high-speed optical signal acquisition module via a high-speed inter-board serial link. The data frames are then uniformly aggregated by a first field-programmable gate array chip and written into the same first dynamic random access memory, ensuring that high-speed and low-speed signals enter the same data path after timestamp alignment. This avoids the channel synchronization deviation caused by independent clock domains in multi-board solutions.

[0069] 2. The data aggregation and bus transmission module directly moves the packaged bus transmission data packets from the internal buffer memory of the field-programmable gate array chip to the system memory through the direct memory access controller. This eliminates the need for the central processing unit to handle data transfer byte-by-byte, fully utilizing the bandwidth resources of the high-speed serial bus. Even when high-speed optical signals and multiple low-speed signals are simultaneously acquired at full load, it ensures real-time data transmission without frame loss or blockage. The disk array storage module distributes data packets according to interface type and channel number, writing them to corresponding storage files. These storage files are then distributed across a disk array composed of multiple non-volatile storage media. Parallel writing across multiple disks increases the overall write bandwidth, meeting the continuous disk write requirements of multi-channel high-speed data streams and avoiding data interruption or overwriting due to insufficient write bandwidth on a single disk. The instruction parsing and channel configuration module allows the control module to dynamically issue control instructions through the bus base address register space during system operation. This enables real-time adjustment of the acquisition enable status, transmission rate, and trigger conditions of each channel without requiring system downtime and hardware reconfiguration. This allows the same system to flexibly adapt to the acquisition needs of different test scenarios and signal types.

[0070] 3. After data transfer is complete, the Direct Memory Access Controller (DMI) triggers an interrupt signal to the Central Processing Unit (CPU). The CPU reads the status register to determine whether the transfer was successful, retransmits abnormal data segments, and automatically manages the storage file through a global transfer counter, ensuring the integrity and traceability of data during long-term continuous acquisition. The system supports reading storage files from the disk array according to the target file path and playback rate parameters, sending them frame by frame to the waveform drawing module for visualization, and allows users to set trigger search conditions to perform frame-by-frame matching scans in the storage file, quickly locating abnormal data frames and significantly improving the efficiency of post-event data analysis and troubleshooting. Attached Figure Description

[0071] Figure 1 This is a system architecture diagram of the present invention. Detailed Implementation

[0072] The following description is intended to disclose the invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art.

[0073] Example 1: Refer to Figure 1 As shown, a multi-interface real-time data acquisition and storage system based on the PCIe bus includes:

[0074] The control module, with its built-in central processing unit and system memory, is used to run the recording control software and manage data storage;

[0075] The high-speed optical signal acquisition module includes a first field-programmable gate array chip and a first dynamic random access memory, which is used to receive high-speed optical signals from an external optical fiber link and perform photoelectric conversion and serial deserialization processing to generate a parallel data stream, and write the parallel data stream into the first dynamic random access memory buffer.

[0076] The low-speed differential signal acquisition module includes a second field-programmable gate array chip and a second dynamic random access memory, which is used to receive multiple external low-speed signals and perform protocol parsing to generate standardized data frames, and forward the standardized data frames to the high-speed optical signal acquisition module via a high-speed serial link between boards.

[0077] The data aggregation and bus transmission module has a built-in direct memory access controller, which is used to read data from the first dynamic random access memory and encapsulate it into bus transmission data packets according to the channel number, and then transport it to the system memory through the direct memory access controller.

[0078] The disk array storage module is used to extract bus transmission data packets from system memory and write them to the disk array according to interface type and channel number.

[0079] The instruction parsing and channel configuration module is used to receive control instructions issued by the control module through the bus base address register space, and to configure the acquisition enable status, transmission rate and trigger conditions of the corresponding channel.

[0080] Through the above scheme, the collaborative design of the high-speed optical signal acquisition module and the low-speed differential signal acquisition module enables the simultaneous access of various heterogeneous interface signals within the same system, including fiber optic serial signals, differential serial communication signals, low-voltage differential signals, and controller area network bus messages. The low-speed differential signal acquisition module forwards the parsed standardized data frames to the high-speed optical signal acquisition module via a high-speed inter-board serial link for unified aggregation, ensuring that multiple signals are time-aligned in the same data path. The data aggregation and bus transmission module achieves high-bandwidth zero-copy transmission through the direct memory access controller, eliminating bus bottlenecks. The disk array storage module performs write operations according to interface type and channel number, ensuring continuous high-speed disk writing capability. The instruction parsing and channel configuration module supports dynamic adjustment of channel parameters during runtime, improving the system's adaptability to different test scenarios.

[0081] In some embodiments, receiving a high-speed optical signal from an external fiber optic link and performing photoelectric conversion and serial-to-deserialization processing to generate a parallel data stream includes:

[0082] The first high-speed optical signal input from the external fiber optic link is received through a four-channel small pluggable optical module.

[0083] The second high-speed optical signal input from an external fiber optic link is received via a micro-socket type optical module;

[0084] The first high-speed optical signal and the second high-speed optical signal are respectively converted into electrical signals by photoelectric conversion.

[0085] The electrical signal is input into the serial deserializer circuit module of the first field-programmable gate array chip to perform serial-to-parallel conversion;

[0086] Perform 8-bit and 10-bit decoding and word alignment operations on the serial-to-parallel converted data to generate a parallel data stream.

[0087] Specifically, the high-speed optical signal acquisition module receives high-speed optical signals from external fiber optic links through two different packaged optical modules. The four-channel small pluggable optical module (QSFP) is a miniaturized optical interface device supporting four parallel optical signal transmissions and receptions, with each signal reaching a rate of up to 10Gbps, for a total bandwidth of 40Gbps. This module connects to the external fiber optic link via a standard LC fiber optic connector to receive the first high-speed optical signal transmitted by the external device. The micro-socket type optical module (MicroPOD) is an ultra-miniaturized optical transceiver module suitable for onboard high-density optical interconnect scenarios. It connects to fiber optic patch cords via onboard micro-sockets to receive the second high-speed optical signal transmitted by the external device. The micro-socket type optical module is smaller than the four-channel small pluggable optical module, making it suitable for arranging multiple optical receiving channels within limited board space.

[0088] The first and second high-speed optical signals are converted into electrical signals by photoelectric conversion. Photoelectric conversion means that the photodiode inside the optical module converts the received optical pulse signal into a corresponding current pulse signal, and then the current signal is converted into a voltage signal by the transimpedance amplifier, and finally outputs a differential electrical signal that conforms to the electrical interface standard. The amplitude of the differential electrical signal is proportional to the intensity of the optical signal, and the frequency is consistent with the modulation rate of the optical signal.

[0089] The electrical signal is input into the serial deserializer circuit module of the first field-programmable gate array (FPGA) chip to perform serial-to-parallel conversion. The serial deserializer, or SerDes circuit module, is a high-speed serial interface circuit integrated inside the FPGA chip, which includes a transmitter (Serializer) and a receiver (Deserializer). The receiver receives the externally input serial differential electrical signal, samples the serial bit stream bit by bit through the internal high-speed sampling clock, and converts the serial bit stream into parallel data according to a preset parallel bit width, such as 32 bits or 64 bits, and outputs parallel data words.

[0090] After serial-to-parallel conversion, the data undergoes 8-bit / 10-bit decoding and word alignment to generate a parallel data stream. 8-bit / 10-bit decoding is a common line encoding and decoding method in serial communication. The transmitting end encodes every 8 bits of data into 10-bit symbols for transmission, and the receiving end decodes the 10-bit symbols back into 8 bits of original data. At the same time, special characters in the encoding, namely the K character, are used to achieve word boundary alignment. The word alignment operation refers to identifying alignment characters such as K28.5 during the decoding process to determine the starting boundary of the parallel data word and ensure the correctness of subsequent data parsing. After decoding and word alignment are completed, a parallel data stream with a bit width of 32 bits or 64 bits is generated and written to the first dynamic random access memory, i.e., DDR, for caching.

[0091] In some embodiments, receiving multiple external low-speed signals and performing protocol parsing to generate standardized data frames includes:

[0092] The differential signal input from the external differential serial communication interface is received through the differential serial communication receiving chip; level decision and start bit detection are performed on the differential signal to extract valid data bytes;

[0093] The differential pair signal input from the external low-voltage differential signal interface is received by the low-voltage differential signal receiving chip; clock data recovery processing is performed on the differential pair signal to extract the serial bit stream; and serial-to-parallel conversion is performed on the serial bit stream to generate parallel data words.

[0094] The system receives bus messages from the external Controller Area Network (CAN) interface via the CAN transceiver chip; performs identifier filtering and cyclic redundancy check on the bus messages; and extracts the data field bytes that pass the check.

[0095] A standardized data frame is generated by uniformly adding timestamps and channel numbers to the valid data bytes, parallel data words, and data field bytes.

[0096] Specifically, the low-speed differential signal acquisition module simultaneously connects to three different low-speed signal interfaces of different protocol types. The first is a differential serial communication interface such as RS-422 or RS-485, which receives differential signals sent by external devices through a differential serial communication receiving chip such as MAX3088. The differential signal is carried by a pair of complementary voltage lines, namely line A and line B. The receiving chip determines the logic level by comparing the voltage difference between line A and line B: when the voltage of line A is higher than the voltage of line B, it is determined to be logic 1, otherwise it is logic 0. After the level determination is completed, the start bit detection is performed, that is, the falling edge is detected in the continuous high level, i.e., the idle state, as the start mark of a frame of data. Then, the data bits are sampled bit by bit according to the preset baud rate clock to extract the valid data bytes, which are usually 8 data bits.

[0097] The second type is the Low Voltage Differential Signal Interface (LVDS). It receives differential pair signals from external devices through a low voltage differential signal receiving chip such as the DS90LV048. LVDS signals use a low voltage swing, typically 350mV, differential transmission, which features low power consumption, low radiation, and high anti-interference capability. Clock data recovery (CDR) is performed on the differential pair signals, extracting the embedded clock information from the differential signals and using the recovered clock to synchronously sample the serial bit stream, eliminating clock offset and jitter during transmission. The recovered serial bit stream is then converted from serial to parallel, generating parallel data words according to a preset parallel bit width, such as 8 bits, 16 bits, or 32 bits.

[0098] The third type is the Controller Area Network (CAN) interface, which receives differential message signals from the external CAN bus through a CAN transceiver chip such as the TJA1050. The CAN bus adopts a multi-master peer-to-peer network structure, and messages are transmitted in frames. Each frame contains a frame start, an arbitration field with an 11-bit or 29-bit identifier, a control field, a data field of 0-8 bytes, a CRC check field, and a frame end field. Identifier filtering is performed on the bus messages, that is, according to the preset receive identifier list, only message frames with matching identifiers are received, and irrelevant messages are discarded. Cyclic redundancy check (CRC) is performed on messages that pass the identifier filtering. The CRC check field in the message is compared with the locally calculated CRC value. If the check passes, up to 8 bytes of data field are extracted. If the check fails, the frame is discarded and the error count is recorded.

[0099] The effective data bytes, parallel data bytes, and data field bytes extracted from the above three interfaces are uniformly timestamped and channel numbers are added to generate standardized data frames. The timestamp is generated by the free-running counter inside the second field-programmable gate array chip, recording the precise time of data arrival with a resolution of up to nanoseconds, and is used for time alignment of subsequent multi-channel data. The channel number is a unique identifier assigned to each signal interface, such as 0x01~0xFF, used to distinguish data from different physical channels. The frame format of the standardized data frame is as follows: the frame header contains a frame synchronization word, an 8-byte timestamp, a 2-byte channel number, a 2-byte data length, N bytes of effective data, and a 2-byte frame tail checksum. The unified frame format ensures that data of different protocol types have a unified data structure in subsequent processing.

[0100] In some embodiments, forwarding standardized data frames to a high-speed optical signal acquisition module via a high-speed inter-board serial link includes:

[0101] Multiple standardized data frames are spliced ​​and assembled according to a preset frame length to generate an aggregated data packet;

[0102] Write the source board identifier and frame count value in the frame header of the aggregated data packet;

[0103] The aggregated data packet is written to the second dynamic random access memory for temporary buffering;

[0104] Aggregated data packets are transmitted from the second field-programmable gate array chip to the first field-programmable gate array chip via a high-speed serial link between boards.

[0105] After receiving the aggregated data packet, the first field-programmable gate array chip strips the frame header and merges the standardized data frame with the parallel data stream into the first dynamic random access memory.

[0106] Specifically, after parsing the protocols of multiple low-speed signals, the second field-programmable gate array chip in the low-speed differential signal acquisition module aggregates and packages the generated standardized data frames. The multiple standardized data frames are spliced ​​and assembled according to a preset frame length, such as 4096 bytes, to generate an aggregated data packet. During the splicing process, the standardized data frames of each low-speed signal within the same acquisition cycle are arranged sequentially according to channel number and filled to the preset frame length. If the total data volume in the current cycle is less than the preset frame length, idle bytes (0xFF) are padded at the end to complete the length.

[0107] The source board identifier and frame count value are written in the frame header of the aggregated data packet. The source board identifier is the unique hardware number of the low-speed differential signal acquisition module, such as 0x02, which is used to distinguish the data source at the receiving end of the high-speed optical signal acquisition module. The frame count value is an incrementing counter, ranging from 0 to 0xFFFF in a loop. It increments once for each aggregated data packet sent. The receiving end determines whether there is packet loss by detecting the continuity of the frame count value.

[0108] The aggregated data packets are written to the second dynamic random access memory (DDR) for temporary buffering. The second DDR serves as a transmission buffer, temporarily storing the aggregated data packets to be sent. When the inter-board link is idle, the transmission state machine of the second field-programmable gate array chip reads and sends the data packets.

[0109] Aggregated data packets are transmitted from the second FPGA chip to the first FPGA chip via a high-speed serial link between the boards. The high-speed serial link between the boards is implemented using a high-speed serial transceiver such as a GTX or GTH transceiver, with a single-channel rate of up to 6.6Gbps or 10.3125Gbps. The two boards are connected by a differential pair cable. The transmitting end encodes the aggregated data packets into 8B / 10B and then transmits them serially. The receiving end performs decoding and word alignment to recover the original data.

[0110] After receiving the aggregated data packet, the first field-programmable gate array chip strips the frame header, that is, removes the source board identifier and frame count value fields, and merges the restored standardized data frame with the parallel data stream generated by the local high-speed optical signal acquisition module and writes it into the first dynamic random access memory. During the merging and writing, the data of each channel is allocated to the corresponding storage area in the first dynamic random access memory according to the channel number, so as to prepare for the unified reading of the subsequent data aggregation and bus transmission module.

[0111] In some embodiments, moving data to system memory via a direct memory access controller includes:

[0112] The first field-programmable gate array chip sends a write address channel request to the direct memory access controller, carrying the target memory start address and transmission length;

[0113] The direct memory access controller writes bus transmission data packets from the internal buffer memory of the first field-programmable gate array chip to the system memory clock cycle by clock cycle through the write data channel;

[0114] After the system memory completes data reception, it returns a write completion acknowledgment signal through the write response channel.

[0115] The direct memory access controller sends an interrupt signal to the central processing unit after all data has been transferred.

[0116] The central processing unit responds to the interrupt signal, confirms the completion of the data transfer, and updates the transfer status register.

[0117] Specifically, the data aggregation and bus transmission module realizes high-bandwidth data transfer from the FPGA to system memory through the Direct Memory Access (DMA) controller on the PCIe bus. After completing data aggregation and frame header encapsulation, the first field-programmable gate array chip initiates a write address channel (AW channel) request to the PCIe bus DMA controller. This request carries the target memory start address, which is the first address of the DMA buffer pre-allocated by the control module, and the transmission length, which is the total number of bytes of the data packet to be transferred. The write address channel request is encapsulated in the transaction layer data packet (TLP) format of the PCIe bus and sent to the PCIe root complex.

[0118] After receiving a write address request, the Direct Memory Access Controller (DMI) writes the bus transmission data packet from the internal buffer memory (BlockRAM or FIFO) of the first Field Programmable Gate Array (FPGA) chip to the system memory clock cycle via the write data channel (W channel). The write data channel divides the data into multiple TLP write requests according to the maximum effective payload size of the PCIe bus, such as 256 bytes or 512 bytes. Each TLP carries the corresponding memory offset address and data payload. After receiving the TLP, the system memory controller writes the data to the corresponding physical memory address.

[0119] After the system memory completes the data reception, it returns a write completion acknowledgment signal (BRESP) through the write response channel (B channel) to confirm that the data has been successfully written. If the write response carries an error status such as address decoding error or slave device error, the direct memory access controller records the error information and marks this transmission as abnormal.

[0120] After all data has been transferred, the Direct Memory Access Controller (DMI) triggers an interrupt signal to the CPU via the PCIe bus interrupt mechanism, such as MSI or MSI-X interrupt. After responding to the interrupt signal, the CPU enters the interrupt service routine, reads the transfer completion status bit of the DMI, and confirms that the data transfer is complete. Subsequently, it updates the transfer count value, the last completion timestamp, and other fields in the transfer status register for the control software to query the transfer progress.

[0121] In some embodiments, writing to the disk array is split according to interface type and channel number, including:

[0122] Read the interface type identifier and channel number fields from the header of the bus transmission data packet;

[0123] The interface type identifier determines the interface category to which the current data packet belongs;

[0124] In response to the interface category being low-speed differential signal, all channel data of the same group of signals are written to the same storage file;

[0125] In response to whether the interface type is fiber optic signal or serializer signal, the data of each channel is written independently to the corresponding storage file.

[0126] Data is appended to the end of the corresponding storage file in the disk array in binary format.

[0127] Specifically, after the disk array storage module extracts the bus transmission data packet from the DMA buffer in the system memory, it first reads the interface type identifier in the data packet frame header, such as 0x01 for fiber optic signal, 0x02 for LVDS signal, 0x03 for RS-422 signal, and 0x04 for CAN signal, as well as the channel number field, such as 0x0001~0x00FF.

[0128] After determining the interface category to which the current data packet belongs based on the interface type identifier, a differentiated file writing strategy is executed. For low-speed differential signal classes, such as LVDS, RS-422, and CAN signals, since the multiple channels of the same group of signals are strictly synchronized in time and the data volume is relatively small, all channel data of the same group of signals are written to the same storage file to facilitate subsequent synchronous playback analysis by group. The file naming format is "interface class group number date and time.bin".

[0129] For fiber optic signals or serial-to-deserializer signals, since the data rate of each fiber optic channel is extremely high, reaching 10Gbps per channel, the data of each channel is written independently to the corresponding storage file to avoid bandwidth contention caused by interleaving of data from multiple channels; the file naming format is "interface type channel number date and time.bin".

[0130] Data is appended to the end of the corresponding storage file in the disk array in binary format. The disk array consists of multiple non-volatile storage media such as NVMe solid-state drives, and is configured as RAID0 (striping mode) through the RAID controller to distribute the data across multiple hard drives to improve the overall write bandwidth. The write operation adopts asynchronous I / O and is executed in parallel by the write thread pool of the disk array storage module to ensure that no write blocking occurs when multiple channels of data are written to the disk at the same time.

[0131] In some embodiments, configuring the acquisition enable state, transmission rate, and triggering conditions for the corresponding channel includes:

[0132] Read the instruction word written by the control module from the bus base address register space;

[0133] The instruction word is split into fields to extract the operation code, data type identifier, target channel number, and configuration parameters;

[0134] The current instruction is determined to be a channel enable instruction, a rate configuration instruction, or a trigger condition setting instruction based on the opcode.

[0135] In response to the channel enable command, the acquisition enable register corresponding to the target channel number is set to the valid state;

[0136] In response to the rate configuration command, the configuration parameters are written to the transmission rate divider register or clock divider register of the target channel;

[0137] In response to the trigger condition setting command, the configuration parameters are written to the trigger level register and trigger edge selection register of the target channel.

[0138] Specifically, the instruction parsing and channel configuration module uses the base address register (BAR) space of the PCIe bus to enable instruction interaction between the control module and the field-programmable gate array (FPGA) chip. The control module, i.e., the central processing unit, writes instruction words to the bus base address register space via the PCIe configuration space or memory-mapped I / O (MMIO). The instruction word has a fixed 32-bit or 64-bit format, containing the opcode in the high 8 bits, the data type identifier in the second high 8 bits, the target channel number in the middle 16 bits, and configuration parameters in the low 32 bits or low 16 bits.

[0139] The register access control logic in the instruction parsing and channel configuration module reads the instruction word written by the control module from the bus base address register space; it splits the instruction word into fields to extract the opcode, data type identifier, target channel number, and configuration parameters; and it determines the current instruction type based on the opcode: opcode 0x01 is a channel enable instruction, 0x02 is a rate configuration instruction, and 0x03 is a trigger condition setting instruction.

[0140] In response to the channel enable instruction, i.e. opcode 0x01, the acquisition enable register corresponding to the target channel number is set to the valid state, i.e. logic 1. The acquisition enable register is a bitmap register where each bit corresponds to one physical channel. After being set, the channel starts receiving and processing external signals. After being cleared, the channel stops acquiring data and sets the output data to the idle state.

[0141] In response to the rate configuration command, i.e. opcode 0x02, the configuration parameters are written to the transmission rate divider register or clock divider register of the target channel. The transmission rate divider register is used to adjust the sampling division ratio of the low-speed signal channel, such as dividing a 100MHz reference clock into a sampling clock of 1MHz to 50MHz. The clock divider register is used to adjust the SerDes reference clock division coefficient of the high-speed optical signal channel, thereby adapting to external signal sources of different rates.

[0142] In response to the trigger condition setting instruction, i.e. opcode 0x03, the configuration parameters are written to the trigger level register and trigger edge selection register of the target channel. The trigger level register stores the threshold voltage value of the trigger decision in the form of DAC codewords. The trigger edge selection register stores the trigger mode, including rising edge trigger, falling edge trigger, or dual edge trigger. When the amplitude of the data acquired by the channel meets the trigger condition, the acquisition is started or a trigger flag is inserted.

[0143] In some embodiments, before performing photoelectric conversion and serial-to-deserialization processing on the high-speed optical signal, the method further includes:

[0144] A first reference clock signal is generated by an onboard crystal oscillator and input into the global clock network of the first field-programmable gate array chip as a logic working clock.

[0145] A second reference clock signal is generated by an onboard crystal oscillator and input to the reference clock input port of the serializer / deserializer circuit module.

[0146] A serial transmission rate clock is generated by multiplying and dividing the second reference clock signal using a phase-locked loop chip.

[0147] The serial transmission rate clock is fed back to the transmitter and receiver of the serial deserializer circuit module to complete clock locking.

[0148] Specifically, the normal operation of the high-speed optical signal acquisition module depends on a precise clock system. A first reference clock signal is generated by an onboard crystal oscillator, such as a 100MHz active crystal oscillator. After being fanned out by a clock buffer, the first reference clock signal is input to the global clock network of the first field-programmable gate array chip. The global clock network is a dedicated low-skew clock distribution network inside the FPGA, which distributes the reference clock to all logic units inside the chip with a very small clock skew, usually less than 100ps, as the working clock for logic circuits such as the FPGA's internal state machine, counters, and FIFO read / write control.

[0149] A second reference clock signal is generated by another onboard crystal oscillator, such as a 156.25MHz or 161.13MHz active crystal oscillator. The second reference clock signal is input to the reference clock input port, i.e., the REFCLK port, of the serializer / deserializer circuit module. The frequency of this reference clock is directly related to the SerDes line rate. For example, a SerDes line rate of 10.3125Gbps corresponds to a reference clock of 161.13MHz, which is obtained by internal frequency multiplication by 64.

[0150] The second reference clock signal is multiplied and divided by a phase-locked loop (PLL) chip, such as the SI5341, to generate a serial transmission rate clock. The PLL chip contains a phase detector, a loop filter, a voltage-controlled oscillator, and a frequency divider. The input reference clock is multiplied to the high-frequency clock required by SerDes, such as 644.53MHz or 1289.06MHz, through the PLL, and then divided to obtain the working clock required by each submodule.

[0151] The serial transmission rate clock is fed back to the transmitting and receiving ends of the serial deserializer circuit module to complete clock locking. The transmitting end uses this clock to serialize parallel data into a serial bit stream, and the receiving end uses this clock to oversample the input serial bit stream and recover the clock data, ensuring that the clock frequency and phase of the transmitting and receiving ends are strictly synchronized, thereby ensuring that the bit error rate of serial data transmission meets the system requirements, which is usually less than 10⁻¹².

[0152] In some embodiments, after writing the storage file to the disk array, the method further includes:

[0153] Receive offline playback instructions from the control module; the offline playback instructions carry the target file path and playback rate parameters.

[0154] Read the corresponding storage file from the disk array based on the target file path;

[0155] The data reading rhythm is controlled according to the playback rate parameter, and the data is sent to the waveform drawing module frame by frame.

[0156] In the waveform display window, plot the waveform curves of each signal with the time axis on the horizontal axis and the signal amplitude on the vertical axis;

[0157] In response to user-defined trigger search conditions, a frame-by-frame matching scan is performed in the stored file; data frames that meet the trigger conditions are located and marked for display in the waveform display window.

[0158] Specifically, after the real-time data acquisition and storage tasks are completed, users can issue offline playback commands through the control module, i.e., the host computer software interface, to replay, view, and search the stored historical data. The offline playback command includes the target file path, such as / data / LVDS_GRP01_20260724.bin, and playback rate parameters such as 1×, 2×, 4×, 8×, or a custom speed.

[0159] The corresponding storage file is read from the disk array according to the target file path. The read operation uses memory-mapped file (mmap) or asynchronous pre-fetching method to preload the data blocks of the storage file into the read buffer of the system memory to avoid playback stuttering caused by random disk reads.

[0160] The playback rate parameter controls the data reading rhythm, sending data frame by frame to the waveform drawing module. The playback rate parameter determines the number of data frames read from the storage file per second. For example, 1× rate corresponds to the original data rate during real-time acquisition, while 2× rate doubles the reading rhythm. After receiving each frame of data, the waveform drawing module parses the timestamp and channel number in the frame header and allocates the data to the corresponding waveform display channel according to the channel.

[0161] In the waveform display window, the waveform curves of each signal are plotted with the time axis as the horizontal axis and the signal amplitude as the vertical axis. The waveform display window supports interactive operations such as multi-channel overlay display, zooming, panning, and cursor measurement. For digital signals such as CAN messages, they are displayed in the form of logic level square waves. For analog signals such as LVDS differential signals, they are displayed in the form of continuous waveform curves.

[0162] In response to user-defined trigger search conditions, such as the amplitude of channel 03 exceeding 2.5V and lasting for more than 10 sampling points, a frame-by-frame matching scan is performed in the stored file. During the scan, data is read frame by frame and it is determined whether the trigger conditions are met. After locating the data frame that meets the trigger conditions, the trigger position is displayed in the waveform display window with a highlighted mark or a vertical line. Users can quickly jump to the abnormal data segment for detailed analysis.

[0163] In some embodiments, after the direct memory access controller triggers an interrupt signal to the central processing unit, the method further includes:

[0164] After responding to the interrupt signal, the central processing unit reads the status register of the direct memory access controller;

[0165] Extract the actual number of bytes transmitted and the error flag from the status register;

[0166] In response to the error flag being in an abnormal state, a new direct memory access write request is initiated to retransmit the data segment that was not successfully transmitted.

[0167] In response to the error flag being in a normal state, the actual number of bytes is incremented into the global transfer counter;

[0168] Determine if the global transfer counter has reached the preset storage fragmentation threshold; in response to reaching the storage fragmentation threshold, close the current storage file and create a new storage file to continue writing.

[0169] Specifically, after the central processing unit responds to the interrupt signal triggered by the direct memory access controller, it enters the interrupt service routine and reads the status register of the direct memory access controller through the MMIO mode of the PCIe bus. The status register is a 32-bit register, in which the lower 24 bits record the actual number of bytes transferred this time, the 24th bit is the error flag bit where 0 indicates normal and 1 indicates abnormal, the 25th bit is the transfer completion flag bit, and the 26th bit is the address out of bounds flag bit.

[0170] After extracting the actual number of bytes transmitted and the error flag from the status register, different processing branches are executed based on the state of the error flag. In response to an abnormal error flag state, such as PCIe link training failure, memory address decoding error, or write timeout, the CPU records an error log containing the error type, occurrence time, and target address. Subsequently, it re-initiates a direct memory access write request, carrying the starting address and remaining length of the unsuccessfully transmitted data segment, and retransmits the unsuccessfully transmitted data segment. The maximum number of retransmissions is 3. If the limit is exceeded, a fatal error is reported to the recording control software, and acquisition on the corresponding channel is suspended.

[0171] In response to the error flag being in a normal state, the actual number of bytes is incremented into the global transmission counter. The global transmission counter is a 64-bit software variable that records the total number of bytes transmitted since the start of acquisition, and is used to calculate statistical information such as acquisition rate, remaining storage space, and estimated acquisition duration.

[0172] The system determines whether the global transfer counter has reached the preset storage fragmentation threshold, such as one fragment per 4GB. In response to reaching the storage fragmentation threshold, the system closes the current storage file, writes the file end identifier, and refreshes the file system cache. When a new storage file is created, the fragmentation number is updated in the file name and writing continues. Through automatic fragmentation management, the system avoids the problem of file system performance degradation and excessive memory consumption during subsequent playback caused by excessively large single storage files. At the same time, it facilitates data retrieval and archiving management by time period.

[0173] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0174] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention. The scope of protection claimed by the appended claims and their equivalents is defined.

Claims

1. A multi-interface real-time data acquisition and storage system based on a PCIe bus, characterized in that, The system includes: The control module, with its built-in central processing unit and system memory, is used to run the recording control software and manage data storage; The high-speed optical signal acquisition module includes a first field-programmable gate array chip and a first dynamic random access memory, which is used to receive high-speed optical signals from an external optical fiber link and perform photoelectric conversion and serial deserialization processing to generate a parallel data stream, and write the parallel data stream into the first dynamic random access memory buffer. The low-speed differential signal acquisition module includes a second field-programmable gate array chip and a second dynamic random access memory, which is used to receive multiple external low-speed signals and perform protocol parsing to generate standardized data frames, and forward the standardized data frames to the high-speed optical signal acquisition module via a high-speed serial link between boards. The data aggregation and bus transmission module has a built-in direct memory access controller, which is used to read data from the first dynamic random access memory and encapsulate it into bus transmission data packets according to the channel number, and then transport it to the system memory through the direct memory access controller; The disk array storage module is used to extract bus transmission data packets from system memory and write them to the disk array according to interface type and channel number. The instruction parsing and channel configuration module is used to receive control instructions issued by the control module through the bus base address register space, and to configure the acquisition enable status, transmission rate and trigger conditions of the corresponding channel.

2. The real-time data acquisition and storage system based on a PCIe bus according to claim 1, characterized in that, It receives high-speed optical signals from an external fiber optic link and performs photoelectric conversion and serial-to-deserialization processing to generate a parallel data stream, including: The first high-speed optical signal input from the external fiber optic link is received through a four-channel small pluggable optical module. The second high-speed optical signal input from an external fiber optic link is received via a micro-socket type optical module; The first high-speed optical signal and the second high-speed optical signal are respectively converted into electrical signals by photoelectric conversion. The electrical signal is input into the serial deserializer circuit module of the first field-programmable gate array chip to perform serial-to-parallel conversion; Perform 8-bit and 10-bit decoding and word alignment operations on the serial-to-parallel converted data to generate a parallel data stream.

3. The real-time data acquisition and storage system based on a PCIe bus according to claim 1, characterized in that, Receive multiple external low-speed signals and perform protocol parsing to generate standardized data frames, including: The differential signal input from the external differential serial communication interface is received through the differential serial communication receiving chip; level decision and start bit detection are performed on the differential signal to extract valid data bytes; The differential pair signal input from the external low-voltage differential signal interface is received by the low-voltage differential signal receiving chip; clock data recovery processing is performed on the differential pair signal to extract the serial bit stream; and serial-to-parallel conversion is performed on the serial bit stream to generate parallel data words. The system receives bus messages from the external Controller Area Network (CAN) interface via the CAN transceiver chip; performs identifier filtering and cyclic redundancy check on the bus messages; and extracts the data field bytes that pass the check. A standardized data frame is generated by uniformly adding timestamps and channel numbers to the valid data bytes, parallel data words, and data field bytes.

4. The real-time data acquisition and storage system based on a PCIe bus according to claim 1, characterized in that, The standardized data frames are forwarded to the high-speed optical signal acquisition module via a high-speed inter-board serial link, including: Multiple standardized data frames are spliced ​​and assembled according to a preset frame length to generate an aggregated data packet; Write the source board identifier and frame count value in the frame header of the aggregated data packet; The aggregated data packet is written to the second dynamic random access memory for temporary buffering; Aggregated data packets are transmitted from the second field-programmable gate array chip to the first field-programmable gate array chip via a high-speed serial link between boards. After receiving the aggregated data packet, the first field-programmable gate array chip strips the frame header and merges the standardized data frame with the parallel data stream into the first dynamic random access memory.

5. The real-time data acquisition and storage system based on a PCIe bus according to claim 1, characterized in that, Transporting data to system memory via the direct memory access controller includes: The first field programmable gate array chip sends a write address channel request to the direct memory access controller, carrying the target memory start address and transmission length; The direct memory access controller writes bus transmission data packets from the internal buffer memory of the first field-programmable gate array chip to the system memory clock cycle by clock cycle through the write data channel; After the system memory completes data reception, it returns a write completion acknowledgment signal through the write response channel. The direct memory access controller sends an interrupt signal to the central processing unit after all data has been transferred. The central processing unit responds to the interrupt signal, confirms the completion of the data transfer, and updates the transfer status register.

6. The real-time data acquisition and storage system based on a PCIe bus according to claim 1, characterized in that, Writes to the disk array are routed according to interface type and channel number, including: Read the interface type identifier and channel number fields from the header of the bus transmission data packet; The interface type identifier determines the interface category to which the current data packet belongs; In response to the interface category being low-speed differential signal, all channel data of the same group of signals are written to the same storage file; In response to whether the interface type is fiber optic signal or serializer signal, the data of each channel is written independently to the corresponding storage file. Data is appended to the end of the corresponding storage file in the disk array in binary format.

7. The real-time data acquisition and storage system based on a PCIe bus according to claim 1, characterized in that, Configure the acquisition enable status, transmission rate, and trigger conditions for the corresponding channel, including: Read the instruction word written by the control module from the bus base address register space; The instruction word is split into fields to extract the operation code, data type identifier, target channel number, and configuration parameters; The current instruction is determined to be a channel enable instruction, a rate configuration instruction, or a trigger condition setting instruction based on the opcode. In response to the channel enable command, the acquisition enable register corresponding to the target channel number is set to the valid state; In response to the rate configuration command, the configuration parameters are written to the transmission rate divider register or clock divider register of the target channel; In response to the trigger condition setting command, the configuration parameters are written to the trigger level register and trigger edge selection register of the target channel.

8. A multi-interface real-time data acquisition and storage system based on a PCIe bus according to claim 2, characterized in that, Before performing photoelectric conversion and serial-to-deserialization processing on high-speed optical signals, the process also includes: A first reference clock signal is generated by an onboard crystal oscillator and input into the global clock network of the first field-programmable gate array chip as a logic working clock. A second reference clock signal is generated by an onboard crystal oscillator and input to the reference clock input port of the serializer / deserializer circuit module. A serial transmission rate clock is generated by multiplying and dividing the second reference clock signal using a phase-locked loop chip. The serial transmission rate clock is fed back to the transmitter and receiver of the serial deserializer circuit module to complete clock locking.

9. A multi-interface real-time data acquisition and storage system based on a PCIe bus according to claim 1, characterized in that, After writing the storage file to the disk array, the process also includes: Receive offline playback instructions from the control module; the offline playback instructions carry the target file path and playback rate parameters. Read the corresponding storage file from the disk array based on the target file path; The data reading rhythm is controlled according to the playback rate parameter, and the data is sent to the waveform drawing module frame by frame. In the waveform display window, plot the waveform curves of each signal with the time axis on the horizontal axis and the signal amplitude on the vertical axis; In response to user-defined trigger search conditions, a frame-by-frame matching scan is performed in the stored file; data frames that meet the trigger conditions are located and marked for display in the waveform display window.

10. A multi-interface real-time data acquisition and storage system based on a PCIe bus according to claim 5, characterized in that, After the direct memory access controller triggers an interrupt signal to the central processing unit, the following is also included: After responding to the interrupt signal, the central processing unit reads the status register of the direct memory access controller; Extract the actual number of bytes transmitted and the error flag from the status register; In response to the error flag being in an abnormal state, a new direct memory access write request is initiated to retransmit the data segment that was not successfully transmitted. In response to the error flag being in a normal state, the actual number of bytes is incremented into the global transfer counter; Determine if the global transfer counter has reached the preset storage fragmentation threshold; in response to reaching the storage fragmentation threshold, close the current storage file and create a new storage file to continue writing.

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